6aae58151300b1619ef9e988dcec0f663f78d527
[sfrench/cifs-2.6.git] / drivers / gpu / drm / bridge / synopsys / dw-hdmi.c
1 /*
2  * DesignWare High-Definition Multimedia Interface (HDMI) driver
3  *
4  * Copyright (C) 2013-2015 Mentor Graphics Inc.
5  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
6  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  */
14 #include <linux/module.h>
15 #include <linux/irq.h>
16 #include <linux/delay.h>
17 #include <linux/err.h>
18 #include <linux/clk.h>
19 #include <linux/hdmi.h>
20 #include <linux/mutex.h>
21 #include <linux/of_device.h>
22 #include <linux/regmap.h>
23 #include <linux/spinlock.h>
24
25 #include <drm/drm_of.h>
26 #include <drm/drmP.h>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_crtc_helper.h>
29 #include <drm/drm_edid.h>
30 #include <drm/drm_encoder_slave.h>
31 #include <drm/bridge/dw_hdmi.h>
32
33 #include <uapi/linux/media-bus-format.h>
34 #include <uapi/linux/videodev2.h>
35
36 #include "dw-hdmi.h"
37 #include "dw-hdmi-audio.h"
38 #include "dw-hdmi-cec.h"
39
40 #include <media/cec-notifier.h>
41
42 #define DDC_SEGMENT_ADDR        0x30
43
44 #define HDMI_EDID_LEN           512
45
46 enum hdmi_datamap {
47         RGB444_8B = 0x01,
48         RGB444_10B = 0x03,
49         RGB444_12B = 0x05,
50         RGB444_16B = 0x07,
51         YCbCr444_8B = 0x09,
52         YCbCr444_10B = 0x0B,
53         YCbCr444_12B = 0x0D,
54         YCbCr444_16B = 0x0F,
55         YCbCr422_8B = 0x16,
56         YCbCr422_10B = 0x14,
57         YCbCr422_12B = 0x12,
58 };
59
60 static const u16 csc_coeff_default[3][4] = {
61         { 0x2000, 0x0000, 0x0000, 0x0000 },
62         { 0x0000, 0x2000, 0x0000, 0x0000 },
63         { 0x0000, 0x0000, 0x2000, 0x0000 }
64 };
65
66 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
67         { 0x2000, 0x6926, 0x74fd, 0x010e },
68         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
69         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
70 };
71
72 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
73         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
74         { 0x2000, 0x3264, 0x0000, 0x7e6d },
75         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
76 };
77
78 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
79         { 0x2591, 0x1322, 0x074b, 0x0000 },
80         { 0x6535, 0x2000, 0x7acc, 0x0200 },
81         { 0x6acd, 0x7534, 0x2000, 0x0200 }
82 };
83
84 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
85         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
86         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
87         { 0x6756, 0x78ab, 0x2000, 0x0200 }
88 };
89
90 struct hdmi_vmode {
91         bool mdataenablepolarity;
92
93         unsigned int mpixelclock;
94         unsigned int mpixelrepetitioninput;
95         unsigned int mpixelrepetitionoutput;
96 };
97
98 struct hdmi_data_info {
99         unsigned int enc_in_bus_format;
100         unsigned int enc_out_bus_format;
101         unsigned int enc_in_encoding;
102         unsigned int enc_out_encoding;
103         unsigned int pix_repet_factor;
104         unsigned int hdcp_enable;
105         struct hdmi_vmode video_mode;
106 };
107
108 struct dw_hdmi_i2c {
109         struct i2c_adapter      adap;
110
111         struct mutex            lock;   /* used to serialize data transfers */
112         struct completion       cmp;
113         u8                      stat;
114
115         u8                      slave_reg;
116         bool                    is_regaddr;
117         bool                    is_segment;
118 };
119
120 struct dw_hdmi_phy_data {
121         enum dw_hdmi_phy_type type;
122         const char *name;
123         unsigned int gen;
124         bool has_svsret;
125         int (*configure)(struct dw_hdmi *hdmi,
126                          const struct dw_hdmi_plat_data *pdata,
127                          unsigned long mpixelclock);
128 };
129
130 struct dw_hdmi {
131         struct drm_connector connector;
132         struct drm_bridge bridge;
133
134         unsigned int version;
135
136         struct platform_device *audio;
137         struct platform_device *cec;
138         struct device *dev;
139         struct clk *isfr_clk;
140         struct clk *iahb_clk;
141         struct dw_hdmi_i2c *i2c;
142
143         struct hdmi_data_info hdmi_data;
144         const struct dw_hdmi_plat_data *plat_data;
145
146         int vic;
147
148         u8 edid[HDMI_EDID_LEN];
149         bool cable_plugin;
150
151         struct {
152                 const struct dw_hdmi_phy_ops *ops;
153                 const char *name;
154                 void *data;
155                 bool enabled;
156         } phy;
157
158         struct drm_display_mode previous_mode;
159
160         struct i2c_adapter *ddc;
161         void __iomem *regs;
162         bool sink_is_hdmi;
163         bool sink_has_audio;
164
165         struct mutex mutex;             /* for state below and previous_mode */
166         enum drm_connector_force force; /* mutex-protected force state */
167         bool disabled;                  /* DRM has disabled our bridge */
168         bool bridge_is_on;              /* indicates the bridge is on */
169         bool rxsense;                   /* rxsense state */
170         u8 phy_mask;                    /* desired phy int mask settings */
171         u8 mc_clkdis;                   /* clock disable register */
172
173         spinlock_t audio_lock;
174         struct mutex audio_mutex;
175         unsigned int sample_rate;
176         unsigned int audio_cts;
177         unsigned int audio_n;
178         bool audio_enable;
179
180         unsigned int reg_shift;
181         struct regmap *regm;
182         void (*enable_audio)(struct dw_hdmi *hdmi);
183         void (*disable_audio)(struct dw_hdmi *hdmi);
184
185         struct cec_notifier *cec_notifier;
186 };
187
188 #define HDMI_IH_PHY_STAT0_RX_SENSE \
189         (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
190          HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
191
192 #define HDMI_PHY_RX_SENSE \
193         (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
194          HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
195
196 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
197 {
198         regmap_write(hdmi->regm, offset << hdmi->reg_shift, val);
199 }
200
201 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
202 {
203         unsigned int val = 0;
204
205         regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val);
206
207         return val;
208 }
209
210 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
211 {
212         regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data);
213 }
214
215 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
216                              u8 shift, u8 mask)
217 {
218         hdmi_modb(hdmi, data << shift, mask, reg);
219 }
220
221 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
222 {
223         /* Software reset */
224         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
225
226         /* Set Standard Mode speed (determined to be 100KHz on iMX6) */
227         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
228
229         /* Set done, not acknowledged and arbitration interrupt polarities */
230         hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
231         hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
232                     HDMI_I2CM_CTLINT);
233
234         /* Clear DONE and ERROR interrupts */
235         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
236                     HDMI_IH_I2CM_STAT0);
237
238         /* Mute DONE and ERROR interrupts */
239         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
240                     HDMI_IH_MUTE_I2CM_STAT0);
241 }
242
243 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
244                             unsigned char *buf, unsigned int length)
245 {
246         struct dw_hdmi_i2c *i2c = hdmi->i2c;
247         int stat;
248
249         if (!i2c->is_regaddr) {
250                 dev_dbg(hdmi->dev, "set read register address to 0\n");
251                 i2c->slave_reg = 0x00;
252                 i2c->is_regaddr = true;
253         }
254
255         while (length--) {
256                 reinit_completion(&i2c->cmp);
257
258                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
259                 if (i2c->is_segment)
260                         hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
261                                     HDMI_I2CM_OPERATION);
262                 else
263                         hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
264                                     HDMI_I2CM_OPERATION);
265
266                 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
267                 if (!stat)
268                         return -EAGAIN;
269
270                 /* Check for error condition on the bus */
271                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
272                         return -EIO;
273
274                 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
275         }
276         i2c->is_segment = false;
277
278         return 0;
279 }
280
281 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
282                              unsigned char *buf, unsigned int length)
283 {
284         struct dw_hdmi_i2c *i2c = hdmi->i2c;
285         int stat;
286
287         if (!i2c->is_regaddr) {
288                 /* Use the first write byte as register address */
289                 i2c->slave_reg = buf[0];
290                 length--;
291                 buf++;
292                 i2c->is_regaddr = true;
293         }
294
295         while (length--) {
296                 reinit_completion(&i2c->cmp);
297
298                 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
299                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
300                 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
301                             HDMI_I2CM_OPERATION);
302
303                 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
304                 if (!stat)
305                         return -EAGAIN;
306
307                 /* Check for error condition on the bus */
308                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
309                         return -EIO;
310         }
311
312         return 0;
313 }
314
315 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
316                             struct i2c_msg *msgs, int num)
317 {
318         struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
319         struct dw_hdmi_i2c *i2c = hdmi->i2c;
320         u8 addr = msgs[0].addr;
321         int i, ret = 0;
322
323         dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
324
325         for (i = 0; i < num; i++) {
326                 if (msgs[i].len == 0) {
327                         dev_dbg(hdmi->dev,
328                                 "unsupported transfer %d/%d, no data\n",
329                                 i + 1, num);
330                         return -EOPNOTSUPP;
331                 }
332         }
333
334         mutex_lock(&i2c->lock);
335
336         /* Unmute DONE and ERROR interrupts */
337         hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
338
339         /* Set slave device address taken from the first I2C message */
340         hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
341
342         /* Set slave device register address on transfer */
343         i2c->is_regaddr = false;
344
345         /* Set segment pointer for I2C extended read mode operation */
346         i2c->is_segment = false;
347
348         for (i = 0; i < num; i++) {
349                 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
350                         i + 1, num, msgs[i].len, msgs[i].flags);
351                 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
352                         i2c->is_segment = true;
353                         hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
354                         hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
355                 } else {
356                         if (msgs[i].flags & I2C_M_RD)
357                                 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
358                                                        msgs[i].len);
359                         else
360                                 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
361                                                         msgs[i].len);
362                 }
363                 if (ret < 0)
364                         break;
365         }
366
367         if (!ret)
368                 ret = num;
369
370         /* Mute DONE and ERROR interrupts */
371         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
372                     HDMI_IH_MUTE_I2CM_STAT0);
373
374         mutex_unlock(&i2c->lock);
375
376         return ret;
377 }
378
379 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
380 {
381         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
382 }
383
384 static const struct i2c_algorithm dw_hdmi_algorithm = {
385         .master_xfer    = dw_hdmi_i2c_xfer,
386         .functionality  = dw_hdmi_i2c_func,
387 };
388
389 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
390 {
391         struct i2c_adapter *adap;
392         struct dw_hdmi_i2c *i2c;
393         int ret;
394
395         i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
396         if (!i2c)
397                 return ERR_PTR(-ENOMEM);
398
399         mutex_init(&i2c->lock);
400         init_completion(&i2c->cmp);
401
402         adap = &i2c->adap;
403         adap->class = I2C_CLASS_DDC;
404         adap->owner = THIS_MODULE;
405         adap->dev.parent = hdmi->dev;
406         adap->algo = &dw_hdmi_algorithm;
407         strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
408         i2c_set_adapdata(adap, hdmi);
409
410         ret = i2c_add_adapter(adap);
411         if (ret) {
412                 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
413                 devm_kfree(hdmi->dev, i2c);
414                 return ERR_PTR(ret);
415         }
416
417         hdmi->i2c = i2c;
418
419         dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
420
421         return adap;
422 }
423
424 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
425                            unsigned int n)
426 {
427         /* Must be set/cleared first */
428         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
429
430         /* nshift factor = 0 */
431         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
432
433         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
434                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
435         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
436         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
437
438         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
439         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
440         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
441 }
442
443 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
444 {
445         unsigned int n = (128 * freq) / 1000;
446         unsigned int mult = 1;
447
448         while (freq > 48000) {
449                 mult *= 2;
450                 freq /= 2;
451         }
452
453         switch (freq) {
454         case 32000:
455                 if (pixel_clk == 25175000)
456                         n = 4576;
457                 else if (pixel_clk == 27027000)
458                         n = 4096;
459                 else if (pixel_clk == 74176000 || pixel_clk == 148352000)
460                         n = 11648;
461                 else
462                         n = 4096;
463                 n *= mult;
464                 break;
465
466         case 44100:
467                 if (pixel_clk == 25175000)
468                         n = 7007;
469                 else if (pixel_clk == 74176000)
470                         n = 17836;
471                 else if (pixel_clk == 148352000)
472                         n = 8918;
473                 else
474                         n = 6272;
475                 n *= mult;
476                 break;
477
478         case 48000:
479                 if (pixel_clk == 25175000)
480                         n = 6864;
481                 else if (pixel_clk == 27027000)
482                         n = 6144;
483                 else if (pixel_clk == 74176000)
484                         n = 11648;
485                 else if (pixel_clk == 148352000)
486                         n = 5824;
487                 else
488                         n = 6144;
489                 n *= mult;
490                 break;
491
492         default:
493                 break;
494         }
495
496         return n;
497 }
498
499 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
500         unsigned long pixel_clk, unsigned int sample_rate)
501 {
502         unsigned long ftdms = pixel_clk;
503         unsigned int n, cts;
504         u64 tmp;
505
506         n = hdmi_compute_n(sample_rate, pixel_clk);
507
508         /*
509          * Compute the CTS value from the N value.  Note that CTS and N
510          * can be up to 20 bits in total, so we need 64-bit math.  Also
511          * note that our TDMS clock is not fully accurate; it is accurate
512          * to kHz.  This can introduce an unnecessary remainder in the
513          * calculation below, so we don't try to warn about that.
514          */
515         tmp = (u64)ftdms * n;
516         do_div(tmp, 128 * sample_rate);
517         cts = tmp;
518
519         dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
520                 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
521                 n, cts);
522
523         spin_lock_irq(&hdmi->audio_lock);
524         hdmi->audio_n = n;
525         hdmi->audio_cts = cts;
526         hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
527         spin_unlock_irq(&hdmi->audio_lock);
528 }
529
530 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
531 {
532         mutex_lock(&hdmi->audio_mutex);
533         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
534         mutex_unlock(&hdmi->audio_mutex);
535 }
536
537 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
538 {
539         mutex_lock(&hdmi->audio_mutex);
540         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
541                                  hdmi->sample_rate);
542         mutex_unlock(&hdmi->audio_mutex);
543 }
544
545 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
546 {
547         mutex_lock(&hdmi->audio_mutex);
548         hdmi->sample_rate = rate;
549         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
550                                  hdmi->sample_rate);
551         mutex_unlock(&hdmi->audio_mutex);
552 }
553 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
554
555 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
556 {
557         if (enable)
558                 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
559         else
560                 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
561         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
562 }
563
564 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
565 {
566         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
567 }
568
569 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi)
570 {
571         hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
572 }
573
574 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi)
575 {
576         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
577         hdmi_enable_audio_clk(hdmi, true);
578 }
579
580 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi)
581 {
582         hdmi_enable_audio_clk(hdmi, false);
583 }
584
585 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
586 {
587         unsigned long flags;
588
589         spin_lock_irqsave(&hdmi->audio_lock, flags);
590         hdmi->audio_enable = true;
591         if (hdmi->enable_audio)
592                 hdmi->enable_audio(hdmi);
593         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
594 }
595 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
596
597 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
598 {
599         unsigned long flags;
600
601         spin_lock_irqsave(&hdmi->audio_lock, flags);
602         hdmi->audio_enable = false;
603         if (hdmi->disable_audio)
604                 hdmi->disable_audio(hdmi);
605         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
606 }
607 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
608
609 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
610 {
611         switch (bus_format) {
612         case MEDIA_BUS_FMT_RGB888_1X24:
613         case MEDIA_BUS_FMT_RGB101010_1X30:
614         case MEDIA_BUS_FMT_RGB121212_1X36:
615         case MEDIA_BUS_FMT_RGB161616_1X48:
616                 return true;
617
618         default:
619                 return false;
620         }
621 }
622
623 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
624 {
625         switch (bus_format) {
626         case MEDIA_BUS_FMT_YUV8_1X24:
627         case MEDIA_BUS_FMT_YUV10_1X30:
628         case MEDIA_BUS_FMT_YUV12_1X36:
629         case MEDIA_BUS_FMT_YUV16_1X48:
630                 return true;
631
632         default:
633                 return false;
634         }
635 }
636
637 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
638 {
639         switch (bus_format) {
640         case MEDIA_BUS_FMT_UYVY8_1X16:
641         case MEDIA_BUS_FMT_UYVY10_1X20:
642         case MEDIA_BUS_FMT_UYVY12_1X24:
643                 return true;
644
645         default:
646                 return false;
647         }
648 }
649
650 static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
651 {
652         switch (bus_format) {
653         case MEDIA_BUS_FMT_RGB888_1X24:
654         case MEDIA_BUS_FMT_YUV8_1X24:
655         case MEDIA_BUS_FMT_UYVY8_1X16:
656         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
657                 return 8;
658
659         case MEDIA_BUS_FMT_RGB101010_1X30:
660         case MEDIA_BUS_FMT_YUV10_1X30:
661         case MEDIA_BUS_FMT_UYVY10_1X20:
662         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
663                 return 10;
664
665         case MEDIA_BUS_FMT_RGB121212_1X36:
666         case MEDIA_BUS_FMT_YUV12_1X36:
667         case MEDIA_BUS_FMT_UYVY12_1X24:
668         case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
669                 return 12;
670
671         case MEDIA_BUS_FMT_RGB161616_1X48:
672         case MEDIA_BUS_FMT_YUV16_1X48:
673         case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
674                 return 16;
675
676         default:
677                 return 0;
678         }
679 }
680
681 /*
682  * this submodule is responsible for the video data synchronization.
683  * for example, for RGB 4:4:4 input, the data map is defined as
684  *                      pin{47~40} <==> R[7:0]
685  *                      pin{31~24} <==> G[7:0]
686  *                      pin{15~8}  <==> B[7:0]
687  */
688 static void hdmi_video_sample(struct dw_hdmi *hdmi)
689 {
690         int color_format = 0;
691         u8 val;
692
693         switch (hdmi->hdmi_data.enc_in_bus_format) {
694         case MEDIA_BUS_FMT_RGB888_1X24:
695                 color_format = 0x01;
696                 break;
697         case MEDIA_BUS_FMT_RGB101010_1X30:
698                 color_format = 0x03;
699                 break;
700         case MEDIA_BUS_FMT_RGB121212_1X36:
701                 color_format = 0x05;
702                 break;
703         case MEDIA_BUS_FMT_RGB161616_1X48:
704                 color_format = 0x07;
705                 break;
706
707         case MEDIA_BUS_FMT_YUV8_1X24:
708         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
709                 color_format = 0x09;
710                 break;
711         case MEDIA_BUS_FMT_YUV10_1X30:
712         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
713                 color_format = 0x0B;
714                 break;
715         case MEDIA_BUS_FMT_YUV12_1X36:
716         case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
717                 color_format = 0x0D;
718                 break;
719         case MEDIA_BUS_FMT_YUV16_1X48:
720         case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
721                 color_format = 0x0F;
722                 break;
723
724         case MEDIA_BUS_FMT_UYVY8_1X16:
725                 color_format = 0x16;
726                 break;
727         case MEDIA_BUS_FMT_UYVY10_1X20:
728                 color_format = 0x14;
729                 break;
730         case MEDIA_BUS_FMT_UYVY12_1X24:
731                 color_format = 0x12;
732                 break;
733
734         default:
735                 return;
736         }
737
738         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
739                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
740                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
741         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
742
743         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
744         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
745                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
746                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
747         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
748         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
749         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
750         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
751         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
752         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
753         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
754 }
755
756 static int is_color_space_conversion(struct dw_hdmi *hdmi)
757 {
758         return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format;
759 }
760
761 static int is_color_space_decimation(struct dw_hdmi *hdmi)
762 {
763         if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
764                 return 0;
765
766         if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
767             hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
768                 return 1;
769
770         return 0;
771 }
772
773 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
774 {
775         if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
776                 return 0;
777
778         if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
779             hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
780                 return 1;
781
782         return 0;
783 }
784
785 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
786 {
787         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
788         unsigned i;
789         u32 csc_scale = 1;
790
791         if (is_color_space_conversion(hdmi)) {
792                 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
793                         if (hdmi->hdmi_data.enc_out_encoding ==
794                                                 V4L2_YCBCR_ENC_601)
795                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
796                         else
797                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
798                 } else if (hdmi_bus_fmt_is_rgb(
799                                         hdmi->hdmi_data.enc_in_bus_format)) {
800                         if (hdmi->hdmi_data.enc_out_encoding ==
801                                                 V4L2_YCBCR_ENC_601)
802                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
803                         else
804                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
805                         csc_scale = 0;
806                 }
807         }
808
809         /* The CSC registers are sequential, alternating MSB then LSB */
810         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
811                 u16 coeff_a = (*csc_coeff)[0][i];
812                 u16 coeff_b = (*csc_coeff)[1][i];
813                 u16 coeff_c = (*csc_coeff)[2][i];
814
815                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
816                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
817                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
818                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
819                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
820                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
821         }
822
823         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
824                   HDMI_CSC_SCALE);
825 }
826
827 static void hdmi_video_csc(struct dw_hdmi *hdmi)
828 {
829         int color_depth = 0;
830         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
831         int decimation = 0;
832
833         /* YCC422 interpolation to 444 mode */
834         if (is_color_space_interpolation(hdmi))
835                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
836         else if (is_color_space_decimation(hdmi))
837                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
838
839         switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
840         case 8:
841                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
842                 break;
843         case 10:
844                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
845                 break;
846         case 12:
847                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
848                 break;
849         case 16:
850                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
851                 break;
852
853         default:
854                 return;
855         }
856
857         /* Configure the CSC registers */
858         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
859         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
860                   HDMI_CSC_SCALE);
861
862         dw_hdmi_update_csc_coeffs(hdmi);
863 }
864
865 /*
866  * HDMI video packetizer is used to packetize the data.
867  * for example, if input is YCC422 mode or repeater is used,
868  * data should be repacked this module can be bypassed.
869  */
870 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
871 {
872         unsigned int color_depth = 0;
873         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
874         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
875         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
876         u8 val, vp_conf;
877
878         if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
879             hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) {
880                 switch (hdmi_bus_fmt_color_depth(
881                                         hdmi->hdmi_data.enc_out_bus_format)) {
882                 case 8:
883                         color_depth = 4;
884                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
885                         break;
886                 case 10:
887                         color_depth = 5;
888                         break;
889                 case 12:
890                         color_depth = 6;
891                         break;
892                 case 16:
893                         color_depth = 7;
894                         break;
895                 default:
896                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
897                 }
898         } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
899                 switch (hdmi_bus_fmt_color_depth(
900                                         hdmi->hdmi_data.enc_out_bus_format)) {
901                 case 0:
902                 case 8:
903                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
904                         break;
905                 case 10:
906                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
907                         break;
908                 case 12:
909                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
910                         break;
911
912                 default:
913                         return;
914                 }
915                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
916         } else {
917                 return;
918         }
919
920         /* set the packetizer registers */
921         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
922                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
923                 ((hdmi_data->pix_repet_factor <<
924                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
925                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
926         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
927
928         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
929                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
930
931         /* Data from pixel repeater block */
932         if (hdmi_data->pix_repet_factor > 1) {
933                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
934                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
935         } else { /* data from packetizer block */
936                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
937                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
938         }
939
940         hdmi_modb(hdmi, vp_conf,
941                   HDMI_VP_CONF_PR_EN_MASK |
942                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
943
944         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
945                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
946
947         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
948
949         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
950                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
951                           HDMI_VP_CONF_PP_EN_ENABLE |
952                           HDMI_VP_CONF_YCC422_EN_DISABLE;
953         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
954                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
955                           HDMI_VP_CONF_PP_EN_DISABLE |
956                           HDMI_VP_CONF_YCC422_EN_ENABLE;
957         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
958                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
959                           HDMI_VP_CONF_PP_EN_DISABLE |
960                           HDMI_VP_CONF_YCC422_EN_DISABLE;
961         } else {
962                 return;
963         }
964
965         hdmi_modb(hdmi, vp_conf,
966                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
967                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
968
969         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
970                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
971                   HDMI_VP_STUFF_PP_STUFFING_MASK |
972                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
973
974         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
975                   HDMI_VP_CONF);
976 }
977
978 /* -----------------------------------------------------------------------------
979  * Synopsys PHY Handling
980  */
981
982 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
983                                        unsigned char bit)
984 {
985         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
986                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
987 }
988
989 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
990 {
991         u32 val;
992
993         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
994                 if (msec-- == 0)
995                         return false;
996                 udelay(1000);
997         }
998         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
999
1000         return true;
1001 }
1002
1003 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1004                            unsigned char addr)
1005 {
1006         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1007         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1008         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1009                     HDMI_PHY_I2CM_DATAO_1_ADDR);
1010         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1011                     HDMI_PHY_I2CM_DATAO_0_ADDR);
1012         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1013                     HDMI_PHY_I2CM_OPERATION_ADDR);
1014         hdmi_phy_wait_i2c_done(hdmi, 1000);
1015 }
1016 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
1017
1018 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1019 {
1020         hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1021                          HDMI_PHY_CONF0_PDZ_OFFSET,
1022                          HDMI_PHY_CONF0_PDZ_MASK);
1023 }
1024
1025 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1026 {
1027         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1028                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
1029                          HDMI_PHY_CONF0_ENTMDS_MASK);
1030 }
1031
1032 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
1033 {
1034         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1035                          HDMI_PHY_CONF0_SVSRET_OFFSET,
1036                          HDMI_PHY_CONF0_SVSRET_MASK);
1037 }
1038
1039 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1040 {
1041         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1042                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1043                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1044 }
1045
1046 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1047 {
1048         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1049                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1050                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1051 }
1052
1053 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1054 {
1055         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1056                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1057                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1058 }
1059
1060 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1061 {
1062         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1063                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1064                          HDMI_PHY_CONF0_SELDIPIF_MASK);
1065 }
1066
1067 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
1068 {
1069         const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1070         unsigned int i;
1071         u16 val;
1072
1073         if (phy->gen == 1) {
1074                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1075                 dw_hdmi_phy_enable_powerdown(hdmi, true);
1076                 return;
1077         }
1078
1079         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1080
1081         /*
1082          * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went
1083          * to low power mode.
1084          */
1085         for (i = 0; i < 5; ++i) {
1086                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1087                 if (!(val & HDMI_PHY_TX_PHY_LOCK))
1088                         break;
1089
1090                 usleep_range(1000, 2000);
1091         }
1092
1093         if (val & HDMI_PHY_TX_PHY_LOCK)
1094                 dev_warn(hdmi->dev, "PHY failed to power down\n");
1095         else
1096                 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);
1097
1098         dw_hdmi_phy_gen2_pddq(hdmi, 1);
1099 }
1100
1101 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
1102 {
1103         const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1104         unsigned int i;
1105         u8 val;
1106
1107         if (phy->gen == 1) {
1108                 dw_hdmi_phy_enable_powerdown(hdmi, false);
1109
1110                 /* Toggle TMDS enable. */
1111                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1112                 dw_hdmi_phy_enable_tmds(hdmi, 1);
1113                 return 0;
1114         }
1115
1116         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1117         dw_hdmi_phy_gen2_pddq(hdmi, 0);
1118
1119         /* Wait for PHY PLL lock */
1120         for (i = 0; i < 5; ++i) {
1121                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1122                 if (val)
1123                         break;
1124
1125                 usleep_range(1000, 2000);
1126         }
1127
1128         if (!val) {
1129                 dev_err(hdmi->dev, "PHY PLL failed to lock\n");
1130                 return -ETIMEDOUT;
1131         }
1132
1133         dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);
1134         return 0;
1135 }
1136
1137 /*
1138  * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
1139  * information the DWC MHL PHY has the same register layout and is thus also
1140  * supported by this function.
1141  */
1142 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
1143                 const struct dw_hdmi_plat_data *pdata,
1144                 unsigned long mpixelclock)
1145 {
1146         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1147         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1148         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1149
1150         /* PLL/MPLL Cfg - always match on final entry */
1151         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1152                 if (mpixelclock <= mpll_config->mpixelclock)
1153                         break;
1154
1155         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1156                 if (mpixelclock <= curr_ctrl->mpixelclock)
1157                         break;
1158
1159         for (; phy_config->mpixelclock != ~0UL; phy_config++)
1160                 if (mpixelclock <= phy_config->mpixelclock)
1161                         break;
1162
1163         if (mpll_config->mpixelclock == ~0UL ||
1164             curr_ctrl->mpixelclock == ~0UL ||
1165             phy_config->mpixelclock == ~0UL)
1166                 return -EINVAL;
1167
1168         dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
1169                               HDMI_3D_TX_PHY_CPCE_CTRL);
1170         dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
1171                               HDMI_3D_TX_PHY_GMPCTRL);
1172         dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
1173                               HDMI_3D_TX_PHY_CURRCTRL);
1174
1175         dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
1176         dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
1177                               HDMI_3D_TX_PHY_MSM_CTRL);
1178
1179         dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
1180         dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
1181                               HDMI_3D_TX_PHY_CKSYMTXCTRL);
1182         dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
1183                               HDMI_3D_TX_PHY_VLEVCTRL);
1184
1185         /* Override and disable clock termination. */
1186         dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
1187                               HDMI_3D_TX_PHY_CKCALCTRL);
1188
1189         return 0;
1190 }
1191
1192 static int hdmi_phy_configure(struct dw_hdmi *hdmi)
1193 {
1194         const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1195         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1196         unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
1197         int ret;
1198
1199         dw_hdmi_phy_power_off(hdmi);
1200
1201         /* Leave low power consumption mode by asserting SVSRET. */
1202         if (phy->has_svsret)
1203                 dw_hdmi_phy_enable_svsret(hdmi, 1);
1204
1205         /* PHY reset. The reset signal is active high on Gen2 PHYs. */
1206         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1207         hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
1208
1209         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1210
1211         hdmi_phy_test_clear(hdmi, 1);
1212         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
1213                     HDMI_PHY_I2CM_SLAVE_ADDR);
1214         hdmi_phy_test_clear(hdmi, 0);
1215
1216         /* Write to the PHY as configured by the platform */
1217         if (pdata->configure_phy)
1218                 ret = pdata->configure_phy(hdmi, pdata, mpixelclock);
1219         else
1220                 ret = phy->configure(hdmi, pdata, mpixelclock);
1221         if (ret) {
1222                 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
1223                         mpixelclock);
1224                 return ret;
1225         }
1226
1227         return dw_hdmi_phy_power_on(hdmi);
1228 }
1229
1230 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
1231                             struct drm_display_mode *mode)
1232 {
1233         int i, ret;
1234
1235         /* HDMI Phy spec says to do the phy initialization sequence twice */
1236         for (i = 0; i < 2; i++) {
1237                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1238                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1239
1240                 ret = hdmi_phy_configure(hdmi);
1241                 if (ret)
1242                         return ret;
1243         }
1244
1245         return 0;
1246 }
1247
1248 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
1249 {
1250         dw_hdmi_phy_power_off(hdmi);
1251 }
1252
1253 static enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
1254                                                       void *data)
1255 {
1256         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1257                 connector_status_connected : connector_status_disconnected;
1258 }
1259
1260 static void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
1261                                    bool force, bool disabled, bool rxsense)
1262 {
1263         u8 old_mask = hdmi->phy_mask;
1264
1265         if (force || disabled || !rxsense)
1266                 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1267         else
1268                 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1269
1270         if (old_mask != hdmi->phy_mask)
1271                 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1272 }
1273
1274 static void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
1275 {
1276         /*
1277          * Configure the PHY RX SENSE and HPD interrupts polarities and clear
1278          * any pending interrupt.
1279          */
1280         hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1281         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1282                     HDMI_IH_PHY_STAT0);
1283
1284         /* Enable cable hot plug irq. */
1285         hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1286
1287         /* Clear and unmute interrupts. */
1288         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1289                     HDMI_IH_PHY_STAT0);
1290         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1291                     HDMI_IH_MUTE_PHY_STAT0);
1292 }
1293
1294 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
1295         .init = dw_hdmi_phy_init,
1296         .disable = dw_hdmi_phy_disable,
1297         .read_hpd = dw_hdmi_phy_read_hpd,
1298         .update_hpd = dw_hdmi_phy_update_hpd,
1299         .setup_hpd = dw_hdmi_phy_setup_hpd,
1300 };
1301
1302 /* -----------------------------------------------------------------------------
1303  * HDMI TX Setup
1304  */
1305
1306 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1307 {
1308         u8 de;
1309
1310         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1311                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1312         else
1313                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1314
1315         /* disable rx detect */
1316         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1317                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1318
1319         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1320
1321         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1322                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1323 }
1324
1325 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1326 {
1327         struct hdmi_avi_infoframe frame;
1328         u8 val;
1329
1330         /* Initialise info frame from DRM mode */
1331         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
1332
1333         if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1334                 frame.colorspace = HDMI_COLORSPACE_YUV444;
1335         else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
1336                 frame.colorspace = HDMI_COLORSPACE_YUV422;
1337         else
1338                 frame.colorspace = HDMI_COLORSPACE_RGB;
1339
1340         /* Set up colorimetry */
1341         switch (hdmi->hdmi_data.enc_out_encoding) {
1342         case V4L2_YCBCR_ENC_601:
1343                 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1344                         frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1345                 else
1346                         frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1347                 frame.extended_colorimetry =
1348                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1349                 break;
1350         case V4L2_YCBCR_ENC_709:
1351                 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1352                         frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1353                 else
1354                         frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1355                 frame.extended_colorimetry =
1356                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1357                 break;
1358         default: /* Carries no data */
1359                 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1360                 frame.extended_colorimetry =
1361                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1362                 break;
1363         }
1364
1365         frame.scan_mode = HDMI_SCAN_MODE_NONE;
1366
1367         /*
1368          * The Designware IP uses a different byte format from standard
1369          * AVI info frames, though generally the bits are in the correct
1370          * bytes.
1371          */
1372
1373         /*
1374          * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,
1375          * scan info in bits 4,5 rather than 0,1 and active aspect present in
1376          * bit 6 rather than 4.
1377          */
1378         val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3);
1379         if (frame.active_aspect & 15)
1380                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1381         if (frame.top_bar || frame.bottom_bar)
1382                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1383         if (frame.left_bar || frame.right_bar)
1384                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1385         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1386
1387         /* AVI data byte 2 differences: none */
1388         val = ((frame.colorimetry & 0x3) << 6) |
1389               ((frame.picture_aspect & 0x3) << 4) |
1390               (frame.active_aspect & 0xf);
1391         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1392
1393         /* AVI data byte 3 differences: none */
1394         val = ((frame.extended_colorimetry & 0x7) << 4) |
1395               ((frame.quantization_range & 0x3) << 2) |
1396               (frame.nups & 0x3);
1397         if (frame.itc)
1398                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1399         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1400
1401         /* AVI data byte 4 differences: none */
1402         val = frame.video_code & 0x7f;
1403         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1404
1405         /* AVI Data Byte 5- set up input and output pixel repetition */
1406         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1407                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1408                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1409                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1410                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1411                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1412         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1413
1414         /*
1415          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1416          * ycc range in bits 2,3 rather than 6,7
1417          */
1418         val = ((frame.ycc_quantization_range & 0x3) << 2) |
1419               (frame.content_type & 0x3);
1420         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1421
1422         /* AVI Data Bytes 6-13 */
1423         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1424         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1425         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1426         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1427         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1428         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1429         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1430         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1431 }
1432
1433 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1434                                                  struct drm_display_mode *mode)
1435 {
1436         struct hdmi_vendor_infoframe frame;
1437         u8 buffer[10];
1438         ssize_t err;
1439
1440         err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode);
1441         if (err < 0)
1442                 /*
1443                  * Going into that statement does not means vendor infoframe
1444                  * fails. It just informed us that vendor infoframe is not
1445                  * needed for the selected mode. Only 4k or stereoscopic 3D
1446                  * mode requires vendor infoframe. So just simply return.
1447                  */
1448                 return;
1449
1450         err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1451         if (err < 0) {
1452                 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1453                         err);
1454                 return;
1455         }
1456         hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1457                         HDMI_FC_DATAUTO0_VSD_MASK);
1458
1459         /* Set the length of HDMI vendor specific InfoFrame payload */
1460         hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1461
1462         /* Set 24bit IEEE Registration Identifier */
1463         hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1464         hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1465         hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1466
1467         /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
1468         hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1469         hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1470
1471         if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
1472                 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1473
1474         /* Packet frame interpolation */
1475         hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1476
1477         /* Auto packets per frame and line spacing */
1478         hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1479
1480         /* Configures the Frame Composer On RDRB mode */
1481         hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1482                         HDMI_FC_DATAUTO0_VSD_MASK);
1483 }
1484
1485 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1486                              const struct drm_display_mode *mode)
1487 {
1488         u8 inv_val;
1489         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1490         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1491         unsigned int vdisplay;
1492
1493         vmode->mpixelclock = mode->clock * 1000;
1494
1495         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1496
1497         /* Set up HDMI_FC_INVIDCONF */
1498         inv_val = (hdmi->hdmi_data.hdcp_enable ?
1499                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1500                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1501
1502         inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1503                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1504                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1505
1506         inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1507                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1508                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1509
1510         inv_val |= (vmode->mdataenablepolarity ?
1511                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1512                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1513
1514         if (hdmi->vic == 39)
1515                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1516         else
1517                 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1518                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1519                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1520
1521         inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1522                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1523                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1524
1525         inv_val |= hdmi->sink_is_hdmi ?
1526                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1527                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1528
1529         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1530
1531         vdisplay = mode->vdisplay;
1532         vblank = mode->vtotal - mode->vdisplay;
1533         v_de_vs = mode->vsync_start - mode->vdisplay;
1534         vsync_len = mode->vsync_end - mode->vsync_start;
1535
1536         /*
1537          * When we're setting an interlaced mode, we need
1538          * to adjust the vertical timing to suit.
1539          */
1540         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1541                 vdisplay /= 2;
1542                 vblank /= 2;
1543                 v_de_vs /= 2;
1544                 vsync_len /= 2;
1545         }
1546
1547         /* Set up horizontal active pixel width */
1548         hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1549         hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1550
1551         /* Set up vertical active lines */
1552         hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1553         hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1554
1555         /* Set up horizontal blanking pixel region width */
1556         hblank = mode->htotal - mode->hdisplay;
1557         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1558         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1559
1560         /* Set up vertical blanking pixel region width */
1561         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1562
1563         /* Set up HSYNC active edge delay width (in pixel clks) */
1564         h_de_hs = mode->hsync_start - mode->hdisplay;
1565         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1566         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1567
1568         /* Set up VSYNC active edge delay (in lines) */
1569         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1570
1571         /* Set up HSYNC active pulse width (in pixel clks) */
1572         hsync_len = mode->hsync_end - mode->hsync_start;
1573         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1574         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1575
1576         /* Set up VSYNC active edge delay (in lines) */
1577         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1578 }
1579
1580 /* HDMI Initialization Step B.4 */
1581 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1582 {
1583         /* control period minimum duration */
1584         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1585         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1586         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1587
1588         /* Set to fill TMDS data channels */
1589         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1590         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1591         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1592
1593         /* Enable pixel clock and tmds data path */
1594         hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE |
1595                            HDMI_MC_CLKDIS_CSCCLK_DISABLE |
1596                            HDMI_MC_CLKDIS_AUDCLK_DISABLE |
1597                            HDMI_MC_CLKDIS_PREPCLK_DISABLE |
1598                            HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1599         hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1600         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1601
1602         hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1603         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1604
1605         /* Enable csc path */
1606         if (is_color_space_conversion(hdmi)) {
1607                 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1608                 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1609         }
1610
1611         /* Enable color space conversion if needed */
1612         if (is_color_space_conversion(hdmi))
1613                 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
1614                             HDMI_MC_FLOWCTRL);
1615         else
1616                 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
1617                             HDMI_MC_FLOWCTRL);
1618 }
1619
1620 /* Workaround to clear the overflow condition */
1621 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1622 {
1623         unsigned int count;
1624         unsigned int i;
1625         u8 val;
1626
1627         /*
1628          * Under some circumstances the Frame Composer arithmetic unit can miss
1629          * an FC register write due to being busy processing the previous one.
1630          * The issue can be worked around by issuing a TMDS software reset and
1631          * then write one of the FC registers several times.
1632          *
1633          * The number of iterations matters and depends on the HDMI TX revision
1634          * (and possibly on the platform). So far only i.MX6Q (v1.30a) and
1635          * i.MX6DL (v1.31a) have been identified as needing the workaround, with
1636          * 4 and 1 iterations respectively.
1637          */
1638
1639         switch (hdmi->version) {
1640         case 0x130a:
1641                 count = 4;
1642                 break;
1643         case 0x131a:
1644                 count = 1;
1645                 break;
1646         default:
1647                 return;
1648         }
1649
1650         /* TMDS software reset */
1651         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1652
1653         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1654         for (i = 0; i < count; i++)
1655                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1656 }
1657
1658 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1659 {
1660         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1661         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1662 }
1663
1664 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1665 {
1666         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1667                     HDMI_IH_MUTE_FC_STAT2);
1668 }
1669
1670 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1671 {
1672         int ret;
1673
1674         hdmi_disable_overflow_interrupts(hdmi);
1675
1676         hdmi->vic = drm_match_cea_mode(mode);
1677
1678         if (!hdmi->vic) {
1679                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1680         } else {
1681                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1682         }
1683
1684         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1685             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1686             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1687             (hdmi->vic == 17) || (hdmi->vic == 18))
1688                 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
1689         else
1690                 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
1691
1692         hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1693         hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1694
1695         /* TOFIX: Get input format from plat data or fallback to RGB888 */
1696         if (hdmi->plat_data->input_bus_format)
1697                 hdmi->hdmi_data.enc_in_bus_format =
1698                         hdmi->plat_data->input_bus_format;
1699         else
1700                 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1701
1702         /* TOFIX: Get input encoding from plat data or fallback to none */
1703         if (hdmi->plat_data->input_bus_encoding)
1704                 hdmi->hdmi_data.enc_in_encoding =
1705                         hdmi->plat_data->input_bus_encoding;
1706         else
1707                 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
1708
1709         /* TOFIX: Default to RGB888 output format */
1710         hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1711
1712         hdmi->hdmi_data.pix_repet_factor = 0;
1713         hdmi->hdmi_data.hdcp_enable = 0;
1714         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1715
1716         /* HDMI Initialization Step B.1 */
1717         hdmi_av_composer(hdmi, mode);
1718
1719         /* HDMI Initializateion Step B.2 */
1720         ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode);
1721         if (ret)
1722                 return ret;
1723         hdmi->phy.enabled = true;
1724
1725         /* HDMI Initialization Step B.3 */
1726         dw_hdmi_enable_video_path(hdmi);
1727
1728         if (hdmi->sink_has_audio) {
1729                 dev_dbg(hdmi->dev, "sink has audio support\n");
1730
1731                 /* HDMI Initialization Step E - Configure audio */
1732                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1733                 hdmi_enable_audio_clk(hdmi, true);
1734         }
1735
1736         /* not for DVI mode */
1737         if (hdmi->sink_is_hdmi) {
1738                 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1739
1740                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1741                 hdmi_config_AVI(hdmi, mode);
1742                 hdmi_config_vendor_specific_infoframe(hdmi, mode);
1743         } else {
1744                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1745         }
1746
1747         hdmi_video_packetize(hdmi);
1748         hdmi_video_csc(hdmi);
1749         hdmi_video_sample(hdmi);
1750         hdmi_tx_hdcp_config(hdmi);
1751
1752         dw_hdmi_clear_overflow(hdmi);
1753         if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
1754                 hdmi_enable_overflow_interrupts(hdmi);
1755
1756         return 0;
1757 }
1758
1759 static void dw_hdmi_setup_i2c(struct dw_hdmi *hdmi)
1760 {
1761         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1762                     HDMI_PHY_I2CM_INT_ADDR);
1763
1764         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1765                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1766                     HDMI_PHY_I2CM_CTLINT_ADDR);
1767 }
1768
1769 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1770 {
1771         u8 ih_mute;
1772
1773         /*
1774          * Boot up defaults are:
1775          * HDMI_IH_MUTE   = 0x03 (disabled)
1776          * HDMI_IH_MUTE_* = 0x00 (enabled)
1777          *
1778          * Disable top level interrupt bits in HDMI block
1779          */
1780         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1781                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1782                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1783
1784         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1785
1786         /* by default mask all interrupts */
1787         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1788         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1789         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1790         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1791         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1792         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1793         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1794         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1795         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1796         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1797         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1798         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1799         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1800         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1801
1802         /* Disable interrupts in the IH_MUTE_* registers */
1803         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1804         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1805         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1806         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1807         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1808         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1809         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1810         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1811         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1812         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1813
1814         /* Enable top level interrupt bits in HDMI block */
1815         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1816                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1817         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1818 }
1819
1820 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1821 {
1822         hdmi->bridge_is_on = true;
1823         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1824 }
1825
1826 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1827 {
1828         if (hdmi->phy.enabled) {
1829                 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
1830                 hdmi->phy.enabled = false;
1831         }
1832
1833         hdmi->bridge_is_on = false;
1834 }
1835
1836 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1837 {
1838         int force = hdmi->force;
1839
1840         if (hdmi->disabled) {
1841                 force = DRM_FORCE_OFF;
1842         } else if (force == DRM_FORCE_UNSPECIFIED) {
1843                 if (hdmi->rxsense)
1844                         force = DRM_FORCE_ON;
1845                 else
1846                         force = DRM_FORCE_OFF;
1847         }
1848
1849         if (force == DRM_FORCE_OFF) {
1850                 if (hdmi->bridge_is_on)
1851                         dw_hdmi_poweroff(hdmi);
1852         } else {
1853                 if (!hdmi->bridge_is_on)
1854                         dw_hdmi_poweron(hdmi);
1855         }
1856 }
1857
1858 /*
1859  * Adjust the detection of RXSENSE according to whether we have a forced
1860  * connection mode enabled, or whether we have been disabled.  There is
1861  * no point processing RXSENSE interrupts if we have a forced connection
1862  * state, or DRM has us disabled.
1863  *
1864  * We also disable rxsense interrupts when we think we're disconnected
1865  * to avoid floating TDMS signals giving false rxsense interrupts.
1866  *
1867  * Note: we still need to listen for HPD interrupts even when DRM has us
1868  * disabled so that we can detect a connect event.
1869  */
1870 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1871 {
1872         if (hdmi->phy.ops->update_hpd)
1873                 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data,
1874                                           hdmi->force, hdmi->disabled,
1875                                           hdmi->rxsense);
1876 }
1877
1878 static enum drm_connector_status
1879 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1880 {
1881         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1882                                              connector);
1883
1884         mutex_lock(&hdmi->mutex);
1885         hdmi->force = DRM_FORCE_UNSPECIFIED;
1886         dw_hdmi_update_power(hdmi);
1887         dw_hdmi_update_phy_mask(hdmi);
1888         mutex_unlock(&hdmi->mutex);
1889
1890         return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
1891 }
1892
1893 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1894 {
1895         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1896                                              connector);
1897         struct edid *edid;
1898         int ret = 0;
1899
1900         if (!hdmi->ddc)
1901                 return 0;
1902
1903         edid = drm_get_edid(connector, hdmi->ddc);
1904         if (edid) {
1905                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1906                         edid->width_cm, edid->height_cm);
1907
1908                 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1909                 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1910                 drm_mode_connector_update_edid_property(connector, edid);
1911                 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
1912                 ret = drm_add_edid_modes(connector, edid);
1913                 /* Store the ELD */
1914                 drm_edid_to_eld(connector, edid);
1915                 kfree(edid);
1916         } else {
1917                 dev_dbg(hdmi->dev, "failed to get edid\n");
1918         }
1919
1920         return ret;
1921 }
1922
1923 static void dw_hdmi_connector_force(struct drm_connector *connector)
1924 {
1925         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1926                                              connector);
1927
1928         mutex_lock(&hdmi->mutex);
1929         hdmi->force = connector->force;
1930         dw_hdmi_update_power(hdmi);
1931         dw_hdmi_update_phy_mask(hdmi);
1932         mutex_unlock(&hdmi->mutex);
1933 }
1934
1935 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
1936         .dpms = drm_atomic_helper_connector_dpms,
1937         .fill_modes = drm_helper_probe_single_connector_modes,
1938         .detect = dw_hdmi_connector_detect,
1939         .destroy = drm_connector_cleanup,
1940         .force = dw_hdmi_connector_force,
1941         .reset = drm_atomic_helper_connector_reset,
1942         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1943         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1944 };
1945
1946 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1947         .get_modes = dw_hdmi_connector_get_modes,
1948         .best_encoder = drm_atomic_helper_best_encoder,
1949 };
1950
1951 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge)
1952 {
1953         struct dw_hdmi *hdmi = bridge->driver_private;
1954         struct drm_encoder *encoder = bridge->encoder;
1955         struct drm_connector *connector = &hdmi->connector;
1956
1957         connector->interlace_allowed = 1;
1958         connector->polled = DRM_CONNECTOR_POLL_HPD;
1959
1960         drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
1961
1962         drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs,
1963                            DRM_MODE_CONNECTOR_HDMIA);
1964
1965         drm_mode_connector_attach_encoder(connector, encoder);
1966
1967         return 0;
1968 }
1969
1970 static enum drm_mode_status
1971 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
1972                           const struct drm_display_mode *mode)
1973 {
1974         struct dw_hdmi *hdmi = bridge->driver_private;
1975         struct drm_connector *connector = &hdmi->connector;
1976         enum drm_mode_status mode_status = MODE_OK;
1977
1978         /* We don't support double-clocked modes */
1979         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1980                 return MODE_BAD;
1981
1982         if (hdmi->plat_data->mode_valid)
1983                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1984
1985         return mode_status;
1986 }
1987
1988 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1989                                     struct drm_display_mode *orig_mode,
1990                                     struct drm_display_mode *mode)
1991 {
1992         struct dw_hdmi *hdmi = bridge->driver_private;
1993
1994         mutex_lock(&hdmi->mutex);
1995
1996         /* Store the display mode for plugin/DKMS poweron events */
1997         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1998
1999         mutex_unlock(&hdmi->mutex);
2000 }
2001
2002 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
2003 {
2004         struct dw_hdmi *hdmi = bridge->driver_private;
2005
2006         mutex_lock(&hdmi->mutex);
2007         hdmi->disabled = true;
2008         dw_hdmi_update_power(hdmi);
2009         dw_hdmi_update_phy_mask(hdmi);
2010         mutex_unlock(&hdmi->mutex);
2011 }
2012
2013 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
2014 {
2015         struct dw_hdmi *hdmi = bridge->driver_private;
2016
2017         mutex_lock(&hdmi->mutex);
2018         hdmi->disabled = false;
2019         dw_hdmi_update_power(hdmi);
2020         dw_hdmi_update_phy_mask(hdmi);
2021         mutex_unlock(&hdmi->mutex);
2022 }
2023
2024 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
2025         .attach = dw_hdmi_bridge_attach,
2026         .enable = dw_hdmi_bridge_enable,
2027         .disable = dw_hdmi_bridge_disable,
2028         .mode_set = dw_hdmi_bridge_mode_set,
2029         .mode_valid = dw_hdmi_bridge_mode_valid,
2030 };
2031
2032 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
2033 {
2034         struct dw_hdmi_i2c *i2c = hdmi->i2c;
2035         unsigned int stat;
2036
2037         stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
2038         if (!stat)
2039                 return IRQ_NONE;
2040
2041         hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
2042
2043         i2c->stat = stat;
2044
2045         complete(&i2c->cmp);
2046
2047         return IRQ_HANDLED;
2048 }
2049
2050 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
2051 {
2052         struct dw_hdmi *hdmi = dev_id;
2053         u8 intr_stat;
2054         irqreturn_t ret = IRQ_NONE;
2055
2056         if (hdmi->i2c)
2057                 ret = dw_hdmi_i2c_irq(hdmi);
2058
2059         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2060         if (intr_stat) {
2061                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2062                 return IRQ_WAKE_THREAD;
2063         }
2064
2065         return ret;
2066 }
2067
2068 void __dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)
2069 {
2070         mutex_lock(&hdmi->mutex);
2071
2072         if (!hdmi->force) {
2073                 /*
2074                  * If the RX sense status indicates we're disconnected,
2075                  * clear the software rxsense status.
2076                  */
2077                 if (!rx_sense)
2078                         hdmi->rxsense = false;
2079
2080                 /*
2081                  * Only set the software rxsense status when both
2082                  * rxsense and hpd indicates we're connected.
2083                  * This avoids what seems to be bad behaviour in
2084                  * at least iMX6S versions of the phy.
2085                  */
2086                 if (hpd)
2087                         hdmi->rxsense = true;
2088
2089                 dw_hdmi_update_power(hdmi);
2090                 dw_hdmi_update_phy_mask(hdmi);
2091         }
2092         mutex_unlock(&hdmi->mutex);
2093 }
2094
2095 void dw_hdmi_setup_rx_sense(struct device *dev, bool hpd, bool rx_sense)
2096 {
2097         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2098
2099         __dw_hdmi_setup_rx_sense(hdmi, hpd, rx_sense);
2100 }
2101 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense);
2102
2103 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
2104 {
2105         struct dw_hdmi *hdmi = dev_id;
2106         u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
2107
2108         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2109         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
2110         phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
2111
2112         phy_pol_mask = 0;
2113         if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
2114                 phy_pol_mask |= HDMI_PHY_HPD;
2115         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
2116                 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
2117         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
2118                 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
2119         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
2120                 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
2121         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
2122                 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
2123
2124         if (phy_pol_mask)
2125                 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
2126
2127         /*
2128          * RX sense tells us whether the TDMS transmitters are detecting
2129          * load - in other words, there's something listening on the
2130          * other end of the link.  Use this to decide whether we should
2131          * power on the phy as HPD may be toggled by the sink to merely
2132          * ask the source to re-read the EDID.
2133          */
2134         if (intr_stat &
2135             (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
2136                 __dw_hdmi_setup_rx_sense(hdmi,
2137                                          phy_stat & HDMI_PHY_HPD,
2138                                          phy_stat & HDMI_PHY_RX_SENSE);
2139
2140                 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0)
2141                         cec_notifier_set_phys_addr(hdmi->cec_notifier,
2142                                                    CEC_PHYS_ADDR_INVALID);
2143         }
2144
2145         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
2146                 dev_dbg(hdmi->dev, "EVENT=%s\n",
2147                         phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
2148                 if (hdmi->bridge.dev)
2149                         drm_helper_hpd_irq_event(hdmi->bridge.dev);
2150         }
2151
2152         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
2153         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2154                     HDMI_IH_MUTE_PHY_STAT0);
2155
2156         return IRQ_HANDLED;
2157 }
2158
2159 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {
2160         {
2161                 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,
2162                 .name = "DWC HDMI TX PHY",
2163                 .gen = 1,
2164         }, {
2165                 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,
2166                 .name = "DWC MHL PHY + HEAC PHY",
2167                 .gen = 2,
2168                 .has_svsret = true,
2169                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2170         }, {
2171                 .type = DW_HDMI_PHY_DWC_MHL_PHY,
2172                 .name = "DWC MHL PHY",
2173                 .gen = 2,
2174                 .has_svsret = true,
2175                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2176         }, {
2177                 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,
2178                 .name = "DWC HDMI 3D TX PHY + HEAC PHY",
2179                 .gen = 2,
2180                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2181         }, {
2182                 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,
2183                 .name = "DWC HDMI 3D TX PHY",
2184                 .gen = 2,
2185                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2186         }, {
2187                 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
2188                 .name = "DWC HDMI 2.0 TX PHY",
2189                 .gen = 2,
2190                 .has_svsret = true,
2191         }, {
2192                 .type = DW_HDMI_PHY_VENDOR_PHY,
2193                 .name = "Vendor PHY",
2194         }
2195 };
2196
2197 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
2198 {
2199         unsigned int i;
2200         u8 phy_type;
2201
2202         phy_type = hdmi_readb(hdmi, HDMI_CONFIG2_ID);
2203
2204         if (phy_type == DW_HDMI_PHY_VENDOR_PHY) {
2205                 /* Vendor PHYs require support from the glue layer. */
2206                 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
2207                         dev_err(hdmi->dev,
2208                                 "Vendor HDMI PHY not supported by glue layer\n");
2209                         return -ENODEV;
2210                 }
2211
2212                 hdmi->phy.ops = hdmi->plat_data->phy_ops;
2213                 hdmi->phy.data = hdmi->plat_data->phy_data;
2214                 hdmi->phy.name = hdmi->plat_data->phy_name;
2215                 return 0;
2216         }
2217
2218         /* Synopsys PHYs are handled internally. */
2219         for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {
2220                 if (dw_hdmi_phys[i].type == phy_type) {
2221                         hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
2222                         hdmi->phy.name = dw_hdmi_phys[i].name;
2223                         hdmi->phy.data = (void *)&dw_hdmi_phys[i];
2224
2225                         if (!dw_hdmi_phys[i].configure &&
2226                             !hdmi->plat_data->configure_phy) {
2227                                 dev_err(hdmi->dev, "%s requires platform support\n",
2228                                         hdmi->phy.name);
2229                                 return -ENODEV;
2230                         }
2231
2232                         return 0;
2233                 }
2234         }
2235
2236         dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type);
2237         return -ENODEV;
2238 }
2239
2240 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi)
2241 {
2242         mutex_lock(&hdmi->mutex);
2243         hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
2244         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2245         mutex_unlock(&hdmi->mutex);
2246 }
2247
2248 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi)
2249 {
2250         mutex_lock(&hdmi->mutex);
2251         hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
2252         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2253         mutex_unlock(&hdmi->mutex);
2254 }
2255
2256 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = {
2257         .write = hdmi_writeb,
2258         .read = hdmi_readb,
2259         .enable = dw_hdmi_cec_enable,
2260         .disable = dw_hdmi_cec_disable,
2261 };
2262
2263 static const struct regmap_config hdmi_regmap_8bit_config = {
2264         .reg_bits       = 32,
2265         .val_bits       = 8,
2266         .reg_stride     = 1,
2267         .max_register   = HDMI_I2CM_FS_SCL_LCNT_0_ADDR,
2268 };
2269
2270 static const struct regmap_config hdmi_regmap_32bit_config = {
2271         .reg_bits       = 32,
2272         .val_bits       = 32,
2273         .reg_stride     = 4,
2274         .max_register   = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2,
2275 };
2276
2277 static struct dw_hdmi *
2278 __dw_hdmi_probe(struct platform_device *pdev,
2279                 const struct dw_hdmi_plat_data *plat_data)
2280 {
2281         struct device *dev = &pdev->dev;
2282         struct device_node *np = dev->of_node;
2283         struct platform_device_info pdevinfo;
2284         struct device_node *ddc_node;
2285         struct dw_hdmi_cec_data cec;
2286         struct dw_hdmi *hdmi;
2287         struct resource *iores = NULL;
2288         int irq;
2289         int ret;
2290         u32 val = 1;
2291         u8 prod_id0;
2292         u8 prod_id1;
2293         u8 config0;
2294         u8 config3;
2295
2296         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2297         if (!hdmi)
2298                 return ERR_PTR(-ENOMEM);
2299
2300         hdmi->plat_data = plat_data;
2301         hdmi->dev = dev;
2302         hdmi->sample_rate = 48000;
2303         hdmi->disabled = true;
2304         hdmi->rxsense = true;
2305         hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
2306         hdmi->mc_clkdis = 0x7f;
2307
2308         mutex_init(&hdmi->mutex);
2309         mutex_init(&hdmi->audio_mutex);
2310         spin_lock_init(&hdmi->audio_lock);
2311
2312         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2313         if (ddc_node) {
2314                 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
2315                 of_node_put(ddc_node);
2316                 if (!hdmi->ddc) {
2317                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
2318                         return ERR_PTR(-EPROBE_DEFER);
2319                 }
2320
2321         } else {
2322                 dev_dbg(hdmi->dev, "no ddc property found\n");
2323         }
2324
2325         if (!plat_data->regm) {
2326                 const struct regmap_config *reg_config;
2327
2328                 of_property_read_u32(np, "reg-io-width", &val);
2329                 switch (val) {
2330                 case 4:
2331                         reg_config = &hdmi_regmap_32bit_config;
2332                         hdmi->reg_shift = 2;
2333                         break;
2334                 case 1:
2335                         reg_config = &hdmi_regmap_8bit_config;
2336                         break;
2337                 default:
2338                         dev_err(dev, "reg-io-width must be 1 or 4\n");
2339                         return ERR_PTR(-EINVAL);
2340                 }
2341
2342                 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2343                 hdmi->regs = devm_ioremap_resource(dev, iores);
2344                 if (IS_ERR(hdmi->regs)) {
2345                         ret = PTR_ERR(hdmi->regs);
2346                         goto err_res;
2347                 }
2348
2349                 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
2350                 if (IS_ERR(hdmi->regm)) {
2351                         dev_err(dev, "Failed to configure regmap\n");
2352                         ret = PTR_ERR(hdmi->regm);
2353                         goto err_res;
2354                 }
2355         } else {
2356                 hdmi->regm = plat_data->regm;
2357         }
2358
2359         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2360         if (IS_ERR(hdmi->isfr_clk)) {
2361                 ret = PTR_ERR(hdmi->isfr_clk);
2362                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
2363                 goto err_res;
2364         }
2365
2366         ret = clk_prepare_enable(hdmi->isfr_clk);
2367         if (ret) {
2368                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
2369                 goto err_res;
2370         }
2371
2372         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2373         if (IS_ERR(hdmi->iahb_clk)) {
2374                 ret = PTR_ERR(hdmi->iahb_clk);
2375                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
2376                 goto err_isfr;
2377         }
2378
2379         ret = clk_prepare_enable(hdmi->iahb_clk);
2380         if (ret) {
2381                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
2382                 goto err_isfr;
2383         }
2384
2385         /* Product and revision IDs */
2386         hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
2387                       | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
2388         prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);
2389         prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);
2390
2391         if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX ||
2392             (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) {
2393                 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
2394                         hdmi->version, prod_id0, prod_id1);
2395                 ret = -ENODEV;
2396                 goto err_iahb;
2397         }
2398
2399         ret = dw_hdmi_detect_phy(hdmi);
2400         if (ret < 0)
2401                 goto err_iahb;
2402
2403         dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
2404                  hdmi->version >> 12, hdmi->version & 0xfff,
2405                  prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without",
2406                  hdmi->phy.name);
2407
2408         initialize_hdmi_ih_mutes(hdmi);
2409
2410         irq = platform_get_irq(pdev, 0);
2411         if (irq < 0) {
2412                 ret = irq;
2413                 goto err_iahb;
2414         }
2415
2416         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2417                                         dw_hdmi_irq, IRQF_SHARED,
2418                                         dev_name(dev), hdmi);
2419         if (ret)
2420                 goto err_iahb;
2421
2422         hdmi->cec_notifier = cec_notifier_get(dev);
2423         if (!hdmi->cec_notifier) {
2424                 ret = -ENOMEM;
2425                 goto err_iahb;
2426         }
2427
2428         /*
2429          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2430          * N and cts values before enabling phy
2431          */
2432         hdmi_init_clk_regenerator(hdmi);
2433
2434         /* If DDC bus is not specified, try to register HDMI I2C bus */
2435         if (!hdmi->ddc) {
2436                 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2437                 if (IS_ERR(hdmi->ddc))
2438                         hdmi->ddc = NULL;
2439         }
2440
2441         hdmi->bridge.driver_private = hdmi;
2442         hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
2443 #ifdef CONFIG_OF
2444         hdmi->bridge.of_node = pdev->dev.of_node;
2445 #endif
2446
2447         dw_hdmi_setup_i2c(hdmi);
2448         if (hdmi->phy.ops->setup_hpd)
2449                 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
2450
2451         memset(&pdevinfo, 0, sizeof(pdevinfo));
2452         pdevinfo.parent = dev;
2453         pdevinfo.id = PLATFORM_DEVID_AUTO;
2454
2455         config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
2456         config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
2457
2458         if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) {
2459                 struct dw_hdmi_audio_data audio;
2460
2461                 audio.phys = iores->start;
2462                 audio.base = hdmi->regs;
2463                 audio.irq = irq;
2464                 audio.hdmi = hdmi;
2465                 audio.eld = hdmi->connector.eld;
2466                 hdmi->enable_audio = dw_hdmi_ahb_audio_enable;
2467                 hdmi->disable_audio = dw_hdmi_ahb_audio_disable;
2468
2469                 pdevinfo.name = "dw-hdmi-ahb-audio";
2470                 pdevinfo.data = &audio;
2471                 pdevinfo.size_data = sizeof(audio);
2472                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2473                 hdmi->audio = platform_device_register_full(&pdevinfo);
2474         } else if (config0 & HDMI_CONFIG0_I2S) {
2475                 struct dw_hdmi_i2s_audio_data audio;
2476
2477                 audio.hdmi      = hdmi;
2478                 audio.write     = hdmi_writeb;
2479                 audio.read      = hdmi_readb;
2480                 hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
2481                 hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
2482
2483                 pdevinfo.name = "dw-hdmi-i2s-audio";
2484                 pdevinfo.data = &audio;
2485                 pdevinfo.size_data = sizeof(audio);
2486                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2487                 hdmi->audio = platform_device_register_full(&pdevinfo);
2488         }
2489
2490         if (config0 & HDMI_CONFIG0_CEC) {
2491                 cec.hdmi = hdmi;
2492                 cec.ops = &dw_hdmi_cec_ops;
2493                 cec.irq = irq;
2494
2495                 pdevinfo.name = "dw-hdmi-cec";
2496                 pdevinfo.data = &cec;
2497                 pdevinfo.size_data = sizeof(cec);
2498                 pdevinfo.dma_mask = 0;
2499
2500                 hdmi->cec = platform_device_register_full(&pdevinfo);
2501         }
2502
2503         /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */
2504         if (hdmi->i2c)
2505                 dw_hdmi_i2c_init(hdmi);
2506
2507         platform_set_drvdata(pdev, hdmi);
2508
2509         return hdmi;
2510
2511 err_iahb:
2512         if (hdmi->i2c) {
2513                 i2c_del_adapter(&hdmi->i2c->adap);
2514                 hdmi->ddc = NULL;
2515         }
2516
2517         if (hdmi->cec_notifier)
2518                 cec_notifier_put(hdmi->cec_notifier);
2519
2520         clk_disable_unprepare(hdmi->iahb_clk);
2521 err_isfr:
2522         clk_disable_unprepare(hdmi->isfr_clk);
2523 err_res:
2524         i2c_put_adapter(hdmi->ddc);
2525
2526         return ERR_PTR(ret);
2527 }
2528
2529 static void __dw_hdmi_remove(struct dw_hdmi *hdmi)
2530 {
2531         if (hdmi->audio && !IS_ERR(hdmi->audio))
2532                 platform_device_unregister(hdmi->audio);
2533         if (!IS_ERR(hdmi->cec))
2534                 platform_device_unregister(hdmi->cec);
2535
2536         /* Disable all interrupts */
2537         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2538
2539         if (hdmi->cec_notifier)
2540                 cec_notifier_put(hdmi->cec_notifier);
2541
2542         clk_disable_unprepare(hdmi->iahb_clk);
2543         clk_disable_unprepare(hdmi->isfr_clk);
2544
2545         if (hdmi->i2c)
2546                 i2c_del_adapter(&hdmi->i2c->adap);
2547         else
2548                 i2c_put_adapter(hdmi->ddc);
2549 }
2550
2551 /* -----------------------------------------------------------------------------
2552  * Probe/remove API, used from platforms based on the DRM bridge API.
2553  */
2554 int dw_hdmi_probe(struct platform_device *pdev,
2555                   const struct dw_hdmi_plat_data *plat_data)
2556 {
2557         struct dw_hdmi *hdmi;
2558
2559         hdmi = __dw_hdmi_probe(pdev, plat_data);
2560         if (IS_ERR(hdmi))
2561                 return PTR_ERR(hdmi);
2562
2563         drm_bridge_add(&hdmi->bridge);
2564
2565         return 0;
2566 }
2567 EXPORT_SYMBOL_GPL(dw_hdmi_probe);
2568
2569 void dw_hdmi_remove(struct platform_device *pdev)
2570 {
2571         struct dw_hdmi *hdmi = platform_get_drvdata(pdev);
2572
2573         drm_bridge_remove(&hdmi->bridge);
2574
2575         __dw_hdmi_remove(hdmi);
2576 }
2577 EXPORT_SYMBOL_GPL(dw_hdmi_remove);
2578
2579 /* -----------------------------------------------------------------------------
2580  * Bind/unbind API, used from platforms based on the component framework.
2581  */
2582 int dw_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
2583                  const struct dw_hdmi_plat_data *plat_data)
2584 {
2585         struct dw_hdmi *hdmi;
2586         int ret;
2587
2588         hdmi = __dw_hdmi_probe(pdev, plat_data);
2589         if (IS_ERR(hdmi))
2590                 return PTR_ERR(hdmi);
2591
2592         ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL);
2593         if (ret) {
2594                 dw_hdmi_remove(pdev);
2595                 DRM_ERROR("Failed to initialize bridge with drm\n");
2596                 return ret;
2597         }
2598
2599         return 0;
2600 }
2601 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2602
2603 void dw_hdmi_unbind(struct device *dev)
2604 {
2605         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2606
2607         __dw_hdmi_remove(hdmi);
2608 }
2609 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
2610
2611 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
2612 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2613 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
2614 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
2615 MODULE_DESCRIPTION("DW HDMI transmitter driver");
2616 MODULE_LICENSE("GPL");
2617 MODULE_ALIAS("platform:dw-hdmi");