drivers/gpu/drm/arm/malidp_drv.c

   1 /*
   2  * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
   3  * Author: Liviu Dudau <Liviu.Dudau@arm.com>
   4  *
   5  * This program is free software and is provided to you under the terms of the
   6  * GNU General Public License version 2 as published by the Free Software
   7  * Foundation, and any use by you of this program is subject to the terms
   8  * of such GNU licence.
   9  *
  10  * ARM Mali DP500/DP550/DP650 KMS/DRM driver
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/clk.h>
  15 #include <linux/component.h>
  16 #include <linux/console.h>
  17 #include <linux/of_device.h>
  18 #include <linux/of_graph.h>
  19 #include <linux/of_reserved_mem.h>
  20 #include <linux/pm_runtime.h>
  21
  22 #include <drm/drmP.h>
  23 #include <drm/drm_atomic.h>
  24 #include <drm/drm_atomic_helper.h>
  25 #include <drm/drm_crtc.h>
  26 #include <drm/drm_crtc_helper.h>
  27 #include <drm/drm_fb_cma_helper.h>
  28 #include <drm/drm_gem_cma_helper.h>
  29 #include <drm/drm_gem_framebuffer_helper.h>
  30 #include <drm/drm_of.h>
  31
  32 #include "malidp_drv.h"
  33 #include "malidp_regs.h"
  34 #include "malidp_hw.h"
  35
  36 #define MALIDP_CONF_VALID_TIMEOUT       250
  37
  38 static void malidp_write_gamma_table(struct malidp_hw_device *hwdev,
  39                                      u32 data[MALIDP_COEFFTAB_NUM_COEFFS])
  40 {
  41         int i;
  42         /* Update all channels with a single gamma curve. */
  43         const u32 gamma_write_mask = GENMASK(18, 16);
  44         /*
  45          * Always write an entire table, so the address field in
  46          * DE_COEFFTAB_ADDR is 0 and we can use the gamma_write_mask bitmask
  47          * directly.
  48          */
  49         malidp_hw_write(hwdev, gamma_write_mask,
  50                         hwdev->map.coeffs_base + MALIDP_COEF_TABLE_ADDR);
  51         for (i = 0; i < MALIDP_COEFFTAB_NUM_COEFFS; ++i)
  52                 malidp_hw_write(hwdev, data[i],
  53                                 hwdev->map.coeffs_base +
  54                                 MALIDP_COEF_TABLE_DATA);
  55 }
  56
  57 static void malidp_atomic_commit_update_gamma(struct drm_crtc *crtc,
  58                                               struct drm_crtc_state *old_state)
  59 {
  60         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  61         struct malidp_hw_device *hwdev = malidp->dev;
  62
  63         if (!crtc->state->color_mgmt_changed)
  64                 return;
  65
  66         if (!crtc->state->gamma_lut) {
  67                 malidp_hw_clearbits(hwdev,
  68                                     MALIDP_DISP_FUNC_GAMMA,
  69                                     MALIDP_DE_DISPLAY_FUNC);
  70         } else {
  71                 struct malidp_crtc_state *mc =
  72                         to_malidp_crtc_state(crtc->state);
  73
  74                 if (!old_state->gamma_lut || (crtc->state->gamma_lut->base.id !=
  75                                               old_state->gamma_lut->base.id))
  76                         malidp_write_gamma_table(hwdev, mc->gamma_coeffs);
  77
  78                 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_GAMMA,
  79                                   MALIDP_DE_DISPLAY_FUNC);
  80         }
  81 }
  82
  83 static
  84 void malidp_atomic_commit_update_coloradj(struct drm_crtc *crtc,
  85                                           struct drm_crtc_state *old_state)
  86 {
  87         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  88         struct malidp_hw_device *hwdev = malidp->dev;
  89         int i;
  90
  91         if (!crtc->state->color_mgmt_changed)
  92                 return;
  93
  94         if (!crtc->state->ctm) {
  95                 malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_CADJ,
  96                                     MALIDP_DE_DISPLAY_FUNC);
  97         } else {
  98                 struct malidp_crtc_state *mc =
  99                         to_malidp_crtc_state(crtc->state);
 100
 101                 if (!old_state->ctm || (crtc->state->ctm->base.id !=
 102                                         old_state->ctm->base.id))
 103                         for (i = 0; i < MALIDP_COLORADJ_NUM_COEFFS; ++i)
 104                                 malidp_hw_write(hwdev,
 105                                                 mc->coloradj_coeffs[i],
 106                                                 hwdev->map.coeffs_base +
 107                                                 MALIDP_COLOR_ADJ_COEF + 4 * i);
 108
 109                 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_CADJ,
 110                                   MALIDP_DE_DISPLAY_FUNC);
 111         }
 112 }
 113
 114 static void malidp_atomic_commit_se_config(struct drm_crtc *crtc,
 115                                            struct drm_crtc_state *old_state)
 116 {
 117         struct malidp_crtc_state *cs = to_malidp_crtc_state(crtc->state);
 118         struct malidp_crtc_state *old_cs = to_malidp_crtc_state(old_state);
 119         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
 120         struct malidp_hw_device *hwdev = malidp->dev;
 121         struct malidp_se_config *s = &cs->scaler_config;
 122         struct malidp_se_config *old_s = &old_cs->scaler_config;
 123         u32 se_control = hwdev->map.se_base +
 124                          ((hwdev->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ?
 125                          0x10 : 0xC);
 126         u32 layer_control = se_control + MALIDP_SE_LAYER_CONTROL;
 127         u32 scr = se_control + MALIDP_SE_SCALING_CONTROL;
 128         u32 val;
 129
 130         /* Set SE_CONTROL */
 131         if (!s->scale_enable) {
 132                 val = malidp_hw_read(hwdev, se_control);
 133                 val &= ~MALIDP_SE_SCALING_EN;
 134                 malidp_hw_write(hwdev, val, se_control);
 135                 return;
 136         }
 137
 138         hwdev->se_set_scaling_coeffs(hwdev, s, old_s);
 139         val = malidp_hw_read(hwdev, se_control);
 140         val |= MALIDP_SE_SCALING_EN | MALIDP_SE_ALPHA_EN;
 141
 142         val &= ~MALIDP_SE_ENH(MALIDP_SE_ENH_MASK);
 143         val |= s->enhancer_enable ? MALIDP_SE_ENH(3) : 0;
 144
 145         val |= MALIDP_SE_RGBO_IF_EN;
 146         malidp_hw_write(hwdev, val, se_control);
 147
 148         /* Set IN_SIZE & OUT_SIZE. */
 149         val = MALIDP_SE_SET_V_SIZE(s->input_h) |
 150               MALIDP_SE_SET_H_SIZE(s->input_w);
 151         malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_IN_SIZE);
 152         val = MALIDP_SE_SET_V_SIZE(s->output_h) |
 153               MALIDP_SE_SET_H_SIZE(s->output_w);
 154         malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_OUT_SIZE);
 155
 156         /* Set phase regs. */
 157         malidp_hw_write(hwdev, s->h_init_phase, scr + MALIDP_SE_H_INIT_PH);
 158         malidp_hw_write(hwdev, s->h_delta_phase, scr + MALIDP_SE_H_DELTA_PH);
 159         malidp_hw_write(hwdev, s->v_init_phase, scr + MALIDP_SE_V_INIT_PH);
 160         malidp_hw_write(hwdev, s->v_delta_phase, scr + MALIDP_SE_V_DELTA_PH);
 161 }
 162
 163 /*
 164  * set the "config valid" bit and wait until the hardware acts on it
 165  */
 166 static int malidp_set_and_wait_config_valid(struct drm_device *drm)
 167 {
 168         struct malidp_drm *malidp = drm->dev_private;
 169         struct malidp_hw_device *hwdev = malidp->dev;
 170         int ret;
 171
 172         atomic_set(&malidp->config_valid, 0);
 173         hwdev->set_config_valid(hwdev);
 174         /* don't wait for config_valid flag if we are in config mode */
 175         if (hwdev->in_config_mode(hwdev))
 176                 return 0;
 177
 178         ret = wait_event_interruptible_timeout(malidp->wq,
 179                         atomic_read(&malidp->config_valid) == 1,
 180                         msecs_to_jiffies(MALIDP_CONF_VALID_TIMEOUT));
 181
 182         return (ret > 0) ? 0 : -ETIMEDOUT;
 183 }
 184
 185 static void malidp_output_poll_changed(struct drm_device *drm)
 186 {
 187         struct malidp_drm *malidp = drm->dev_private;
 188
 189         drm_fbdev_cma_hotplug_event(malidp->fbdev);
 190 }
 191
 192 static void malidp_atomic_commit_hw_done(struct drm_atomic_state *state)
 193 {
 194         struct drm_pending_vblank_event *event;
 195         struct drm_device *drm = state->dev;
 196         struct malidp_drm *malidp = drm->dev_private;
 197
 198         if (malidp->crtc.enabled) {
 199                 /* only set config_valid if the CRTC is enabled */
 200                 if (malidp_set_and_wait_config_valid(drm))
 201                         DRM_DEBUG_DRIVER("timed out waiting for updated configuration\n");
 202         }
 203
 204         event = malidp->crtc.state->event;
 205         if (event) {
 206                 malidp->crtc.state->event = NULL;
 207
 208                 spin_lock_irq(&drm->event_lock);
 209                 if (drm_crtc_vblank_get(&malidp->crtc) == 0)
 210                         drm_crtc_arm_vblank_event(&malidp->crtc, event);
 211                 else
 212                         drm_crtc_send_vblank_event(&malidp->crtc, event);
 213                 spin_unlock_irq(&drm->event_lock);
 214         }
 215         drm_atomic_helper_commit_hw_done(state);
 216 }
 217
 218 static void malidp_atomic_commit_tail(struct drm_atomic_state *state)
 219 {
 220         struct drm_device *drm = state->dev;
 221         struct drm_crtc *crtc;
 222         struct drm_crtc_state *old_crtc_state;
 223         int i;
 224
 225         pm_runtime_get_sync(drm->dev);
 226
 227         drm_atomic_helper_commit_modeset_disables(drm, state);
 228
 229         for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
 230                 malidp_atomic_commit_update_gamma(crtc, old_crtc_state);
 231                 malidp_atomic_commit_update_coloradj(crtc, old_crtc_state);
 232                 malidp_atomic_commit_se_config(crtc, old_crtc_state);
 233         }
 234
 235         drm_atomic_helper_commit_planes(drm, state, 0);
 236
 237         drm_atomic_helper_commit_modeset_enables(drm, state);
 238
 239         malidp_atomic_commit_hw_done(state);
 240
 241         drm_atomic_helper_wait_for_vblanks(drm, state);
 242
 243         pm_runtime_put(drm->dev);
 244
 245         drm_atomic_helper_cleanup_planes(drm, state);
 246 }
 247
 248 static const struct drm_mode_config_helper_funcs malidp_mode_config_helpers = {
 249         .atomic_commit_tail = malidp_atomic_commit_tail,
 250 };
 251
 252 static const struct drm_mode_config_funcs malidp_mode_config_funcs = {
 253         .fb_create = drm_gem_fb_create,
 254         .output_poll_changed = malidp_output_poll_changed,
 255         .atomic_check = drm_atomic_helper_check,
 256         .atomic_commit = drm_atomic_helper_commit,
 257 };
 258
 259 static int malidp_init(struct drm_device *drm)
 260 {
 261         int ret;
 262         struct malidp_drm *malidp = drm->dev_private;
 263         struct malidp_hw_device *hwdev = malidp->dev;
 264
 265         drm_mode_config_init(drm);
 266
 267         drm->mode_config.min_width = hwdev->min_line_size;
 268         drm->mode_config.min_height = hwdev->min_line_size;
 269         drm->mode_config.max_width = hwdev->max_line_size;
 270         drm->mode_config.max_height = hwdev->max_line_size;
 271         drm->mode_config.funcs = &malidp_mode_config_funcs;
 272         drm->mode_config.helper_private = &malidp_mode_config_helpers;
 273
 274         ret = malidp_crtc_init(drm);
 275         if (ret) {
 276                 drm_mode_config_cleanup(drm);
 277                 return ret;
 278         }
 279
 280         return 0;
 281 }
 282
 283 static void malidp_fini(struct drm_device *drm)
 284 {
 285         malidp_de_planes_destroy(drm);
 286         drm_mode_config_cleanup(drm);
 287 }
 288
 289 static int malidp_irq_init(struct platform_device *pdev)
 290 {
 291         int irq_de, irq_se, ret = 0;
 292         struct drm_device *drm = dev_get_drvdata(&pdev->dev);
 293
 294         /* fetch the interrupts from DT */
 295         irq_de = platform_get_irq_byname(pdev, "DE");
 296         if (irq_de < 0) {
 297                 DRM_ERROR("no 'DE' IRQ specified!\n");
 298                 return irq_de;
 299         }
 300         irq_se = platform_get_irq_byname(pdev, "SE");
 301         if (irq_se < 0) {
 302                 DRM_ERROR("no 'SE' IRQ specified!\n");
 303                 return irq_se;
 304         }
 305
 306         ret = malidp_de_irq_init(drm, irq_de);
 307         if (ret)
 308                 return ret;
 309
 310         ret = malidp_se_irq_init(drm, irq_se);
 311         if (ret) {
 312                 malidp_de_irq_fini(drm);
 313                 return ret;
 314         }
 315
 316         return 0;
 317 }
 318
 319 static void malidp_lastclose(struct drm_device *drm)
 320 {
 321         struct malidp_drm *malidp = drm->dev_private;
 322
 323         drm_fbdev_cma_restore_mode(malidp->fbdev);
 324 }
 325
 326 DEFINE_DRM_GEM_CMA_FOPS(fops);
 327
 328 static struct drm_driver malidp_driver = {
 329         .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC |
 330                            DRIVER_PRIME,
 331         .lastclose = malidp_lastclose,
 332         .gem_free_object_unlocked = drm_gem_cma_free_object,
 333         .gem_vm_ops = &drm_gem_cma_vm_ops,
 334         .dumb_create = drm_gem_cma_dumb_create,
 335         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 336         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 337         .gem_prime_export = drm_gem_prime_export,
 338         .gem_prime_import = drm_gem_prime_import,
 339         .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
 340         .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
 341         .gem_prime_vmap = drm_gem_cma_prime_vmap,
 342         .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
 343         .gem_prime_mmap = drm_gem_cma_prime_mmap,
 344         .fops = &fops,
 345         .name = "mali-dp",
 346         .desc = "ARM Mali Display Processor driver",
 347         .date = "20160106",
 348         .major = 1,
 349         .minor = 0,
 350 };
 351
 352 static const struct of_device_id  malidp_drm_of_match[] = {
 353         {
 354                 .compatible = "arm,mali-dp500",
 355                 .data = &malidp_device[MALIDP_500]
 356         },
 357         {
 358                 .compatible = "arm,mali-dp550",
 359                 .data = &malidp_device[MALIDP_550]
 360         },
 361         {
 362                 .compatible = "arm,mali-dp650",
 363                 .data = &malidp_device[MALIDP_650]
 364         },
 365         {},
 366 };
 367 MODULE_DEVICE_TABLE(of, malidp_drm_of_match);
 368
 369 static bool malidp_is_compatible_hw_id(struct malidp_hw_device *hwdev,
 370                                        const struct of_device_id *dev_id)
 371 {
 372         u32 core_id;
 373         const char *compatstr_dp500 = "arm,mali-dp500";
 374         bool is_dp500;
 375         bool dt_is_dp500;
 376
 377         /*
 378          * The DP500 CORE_ID register is in a different location, so check it
 379          * first. If the product id field matches, then this is DP500, otherwise
 380          * check the DP550/650 CORE_ID register.
 381          */
 382         core_id = malidp_hw_read(hwdev, MALIDP500_DC_BASE + MALIDP_DE_CORE_ID);
 383         /* Offset 0x18 will never read 0x500 on products other than DP500. */
 384         is_dp500 = (MALIDP_PRODUCT_ID(core_id) == 0x500);
 385         dt_is_dp500 = strnstr(dev_id->compatible, compatstr_dp500,
 386                               sizeof(dev_id->compatible)) != NULL;
 387         if (is_dp500 != dt_is_dp500) {
 388                 DRM_ERROR("Device-tree expects %s, but hardware %s DP500.\n",
 389                           dev_id->compatible, is_dp500 ? "is" : "is not");
 390                 return false;
 391         } else if (!dt_is_dp500) {
 392                 u16 product_id;
 393                 char buf[32];
 394
 395                 core_id = malidp_hw_read(hwdev,
 396                                          MALIDP550_DC_BASE + MALIDP_DE_CORE_ID);
 397                 product_id = MALIDP_PRODUCT_ID(core_id);
 398                 snprintf(buf, sizeof(buf), "arm,mali-dp%X", product_id);
 399                 if (!strnstr(dev_id->compatible, buf,
 400                              sizeof(dev_id->compatible))) {
 401                         DRM_ERROR("Device-tree expects %s, but hardware is DP%03X.\n",
 402                                   dev_id->compatible, product_id);
 403                         return false;
 404                 }
 405         }
 406         return true;
 407 }
 408
 409 static bool malidp_has_sufficient_address_space(const struct resource *res,
 410                                                 const struct of_device_id *dev_id)
 411 {
 412         resource_size_t res_size = resource_size(res);
 413         const char *compatstr_dp500 = "arm,mali-dp500";
 414
 415         if (!strnstr(dev_id->compatible, compatstr_dp500,
 416                      sizeof(dev_id->compatible)))
 417                 return res_size >= MALIDP550_ADDR_SPACE_SIZE;
 418         else if (res_size < MALIDP500_ADDR_SPACE_SIZE)
 419                 return false;
 420         return true;
 421 }
 422
 423 static ssize_t core_id_show(struct device *dev, struct device_attribute *attr,
 424                             char *buf)
 425 {
 426         struct drm_device *drm = dev_get_drvdata(dev);
 427         struct malidp_drm *malidp = drm->dev_private;
 428
 429         return snprintf(buf, PAGE_SIZE, "%08x\n", malidp->core_id);
 430 }
 431
 432 DEVICE_ATTR_RO(core_id);
 433
 434 static int malidp_init_sysfs(struct device *dev)
 435 {
 436         int ret = device_create_file(dev, &dev_attr_core_id);
 437
 438         if (ret)
 439                 DRM_ERROR("failed to create device file for core_id\n");
 440
 441         return ret;
 442 }
 443
 444 static void malidp_fini_sysfs(struct device *dev)
 445 {
 446         device_remove_file(dev, &dev_attr_core_id);
 447 }
 448
 449 #define MAX_OUTPUT_CHANNELS     3
 450
 451 static int malidp_runtime_pm_suspend(struct device *dev)
 452 {
 453         struct drm_device *drm = dev_get_drvdata(dev);
 454         struct malidp_drm *malidp = drm->dev_private;
 455         struct malidp_hw_device *hwdev = malidp->dev;
 456
 457         /* we can only suspend if the hardware is in config mode */
 458         WARN_ON(!hwdev->in_config_mode(hwdev));
 459
 460         hwdev->pm_suspended = true;
 461         clk_disable_unprepare(hwdev->mclk);
 462         clk_disable_unprepare(hwdev->aclk);
 463         clk_disable_unprepare(hwdev->pclk);
 464
 465         return 0;
 466 }
 467
 468 static int malidp_runtime_pm_resume(struct device *dev)
 469 {
 470         struct drm_device *drm = dev_get_drvdata(dev);
 471         struct malidp_drm *malidp = drm->dev_private;
 472         struct malidp_hw_device *hwdev = malidp->dev;
 473
 474         clk_prepare_enable(hwdev->pclk);
 475         clk_prepare_enable(hwdev->aclk);
 476         clk_prepare_enable(hwdev->mclk);
 477         hwdev->pm_suspended = false;
 478
 479         return 0;
 480 }
 481
 482 static int malidp_bind(struct device *dev)
 483 {
 484         struct resource *res;
 485         struct drm_device *drm;
 486         struct malidp_drm *malidp;
 487         struct malidp_hw_device *hwdev;
 488         struct platform_device *pdev = to_platform_device(dev);
 489         struct of_device_id const *dev_id;
 490         /* number of lines for the R, G and B output */
 491         u8 output_width[MAX_OUTPUT_CHANNELS];
 492         int ret = 0, i;
 493         u32 version, out_depth = 0;
 494
 495         malidp = devm_kzalloc(dev, sizeof(*malidp), GFP_KERNEL);
 496         if (!malidp)
 497                 return -ENOMEM;
 498
 499         hwdev = devm_kzalloc(dev, sizeof(*hwdev), GFP_KERNEL);
 500         if (!hwdev)
 501                 return -ENOMEM;
 502
 503         /*
 504          * copy the associated data from malidp_drm_of_match to avoid
 505          * having to keep a reference to the OF node after binding
 506          */
 507         memcpy(hwdev, of_device_get_match_data(dev), sizeof(*hwdev));
 508         malidp->dev = hwdev;
 509
 510         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 511         hwdev->regs = devm_ioremap_resource(dev, res);
 512         if (IS_ERR(hwdev->regs))
 513                 return PTR_ERR(hwdev->regs);
 514
 515         hwdev->pclk = devm_clk_get(dev, "pclk");
 516         if (IS_ERR(hwdev->pclk))
 517                 return PTR_ERR(hwdev->pclk);
 518
 519         hwdev->aclk = devm_clk_get(dev, "aclk");
 520         if (IS_ERR(hwdev->aclk))
 521                 return PTR_ERR(hwdev->aclk);
 522
 523         hwdev->mclk = devm_clk_get(dev, "mclk");
 524         if (IS_ERR(hwdev->mclk))
 525                 return PTR_ERR(hwdev->mclk);
 526
 527         hwdev->pxlclk = devm_clk_get(dev, "pxlclk");
 528         if (IS_ERR(hwdev->pxlclk))
 529                 return PTR_ERR(hwdev->pxlclk);
 530
 531         /* Get the optional framebuffer memory resource */
 532         ret = of_reserved_mem_device_init(dev);
 533         if (ret && ret != -ENODEV)
 534                 return ret;
 535
 536         drm = drm_dev_alloc(&malidp_driver, dev);
 537         if (IS_ERR(drm)) {
 538                 ret = PTR_ERR(drm);
 539                 goto alloc_fail;
 540         }
 541
 542         drm->dev_private = malidp;
 543         dev_set_drvdata(dev, drm);
 544
 545         /* Enable power management */
 546         pm_runtime_enable(dev);
 547
 548         /* Resume device to enable the clocks */
 549         if (pm_runtime_enabled(dev))
 550                 pm_runtime_get_sync(dev);
 551         else
 552                 malidp_runtime_pm_resume(dev);
 553
 554         dev_id = of_match_device(malidp_drm_of_match, dev);
 555         if (!dev_id) {
 556                 ret = -EINVAL;
 557                 goto query_hw_fail;
 558         }
 559
 560         if (!malidp_has_sufficient_address_space(res, dev_id)) {
 561                 DRM_ERROR("Insufficient address space in device-tree.\n");
 562                 ret = -EINVAL;
 563                 goto query_hw_fail;
 564         }
 565
 566         if (!malidp_is_compatible_hw_id(hwdev, dev_id)) {
 567                 ret = -EINVAL;
 568                 goto query_hw_fail;
 569         }
 570
 571         ret = hwdev->query_hw(hwdev);
 572         if (ret) {
 573                 DRM_ERROR("Invalid HW configuration\n");
 574                 goto query_hw_fail;
 575         }
 576
 577         version = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_DE_CORE_ID);
 578         DRM_INFO("found ARM Mali-DP%3x version r%dp%d\n", version >> 16,
 579                  (version >> 12) & 0xf, (version >> 8) & 0xf);
 580
 581         malidp->core_id = version;
 582
 583         /* set the number of lines used for output of RGB data */
 584         ret = of_property_read_u8_array(dev->of_node,
 585                                         "arm,malidp-output-port-lines",
 586                                         output_width, MAX_OUTPUT_CHANNELS);
 587         if (ret)
 588                 goto query_hw_fail;
 589
 590         for (i = 0; i < MAX_OUTPUT_CHANNELS; i++)
 591                 out_depth = (out_depth << 8) | (output_width[i] & 0xf);
 592         malidp_hw_write(hwdev, out_depth, hwdev->map.out_depth_base);
 593
 594         atomic_set(&malidp->config_valid, 0);
 595         init_waitqueue_head(&malidp->wq);
 596
 597         ret = malidp_init(drm);
 598         if (ret < 0)
 599                 goto query_hw_fail;
 600
 601         ret = malidp_init_sysfs(dev);
 602         if (ret)
 603                 goto init_fail;
 604
 605         /* Set the CRTC's port so that the encoder component can find it */
 606         malidp->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
 607
 608         ret = component_bind_all(dev, drm);
 609         if (ret) {
 610                 DRM_ERROR("Failed to bind all components\n");
 611                 goto bind_fail;
 612         }
 613
 614         ret = malidp_irq_init(pdev);
 615         if (ret < 0)
 616                 goto irq_init_fail;
 617
 618         drm->irq_enabled = true;
 619
 620         ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
 621         if (ret < 0) {
 622                 DRM_ERROR("failed to initialise vblank\n");
 623                 goto vblank_fail;
 624         }
 625         pm_runtime_put(dev);
 626
 627         drm_mode_config_reset(drm);
 628
 629         malidp->fbdev = drm_fbdev_cma_init(drm, 32,
 630                                            drm->mode_config.num_connector);
 631
 632         if (IS_ERR(malidp->fbdev)) {
 633                 ret = PTR_ERR(malidp->fbdev);
 634                 malidp->fbdev = NULL;
 635                 goto fbdev_fail;
 636         }
 637
 638         drm_kms_helper_poll_init(drm);
 639
 640         ret = drm_dev_register(drm, 0);
 641         if (ret)
 642                 goto register_fail;
 643
 644         return 0;
 645
 646 register_fail:
 647         if (malidp->fbdev) {
 648                 drm_fbdev_cma_fini(malidp->fbdev);
 649                 malidp->fbdev = NULL;
 650         }
 651         drm_kms_helper_poll_fini(drm);
 652 fbdev_fail:
 653         pm_runtime_get_sync(dev);
 654 vblank_fail:
 655         malidp_se_irq_fini(drm);
 656         malidp_de_irq_fini(drm);
 657         drm->irq_enabled = false;
 658 irq_init_fail:
 659         component_unbind_all(dev, drm);
 660 bind_fail:
 661         of_node_put(malidp->crtc.port);
 662         malidp->crtc.port = NULL;
 663 init_fail:
 664         malidp_fini_sysfs(dev);
 665         malidp_fini(drm);
 666 query_hw_fail:
 667         pm_runtime_put(dev);
 668         if (pm_runtime_enabled(dev))
 669                 pm_runtime_disable(dev);
 670         else
 671                 malidp_runtime_pm_suspend(dev);
 672         drm->dev_private = NULL;
 673         dev_set_drvdata(dev, NULL);
 674         drm_dev_unref(drm);
 675 alloc_fail:
 676         of_reserved_mem_device_release(dev);
 677
 678         return ret;
 679 }
 680
 681 static void malidp_unbind(struct device *dev)
 682 {
 683         struct drm_device *drm = dev_get_drvdata(dev);
 684         struct malidp_drm *malidp = drm->dev_private;
 685
 686         drm_dev_unregister(drm);
 687         if (malidp->fbdev) {
 688                 drm_fbdev_cma_fini(malidp->fbdev);
 689                 malidp->fbdev = NULL;
 690         }
 691         drm_kms_helper_poll_fini(drm);
 692         pm_runtime_get_sync(dev);
 693         malidp_se_irq_fini(drm);
 694         malidp_de_irq_fini(drm);
 695         component_unbind_all(dev, drm);
 696         of_node_put(malidp->crtc.port);
 697         malidp->crtc.port = NULL;
 698         malidp_fini_sysfs(dev);
 699         malidp_fini(drm);
 700         pm_runtime_put(dev);
 701         if (pm_runtime_enabled(dev))
 702                 pm_runtime_disable(dev);
 703         else
 704                 malidp_runtime_pm_suspend(dev);
 705         drm->dev_private = NULL;
 706         dev_set_drvdata(dev, NULL);
 707         drm_dev_unref(drm);
 708         of_reserved_mem_device_release(dev);
 709 }
 710
 711 static const struct component_master_ops malidp_master_ops = {
 712         .bind = malidp_bind,
 713         .unbind = malidp_unbind,
 714 };
 715
 716 static int malidp_compare_dev(struct device *dev, void *data)
 717 {
 718         struct device_node *np = data;
 719
 720         return dev->of_node == np;
 721 }
 722
 723 static int malidp_platform_probe(struct platform_device *pdev)
 724 {
 725         struct device_node *port;
 726         struct component_match *match = NULL;
 727
 728         if (!pdev->dev.of_node)
 729                 return -ENODEV;
 730
 731         /* there is only one output port inside each device, find it */
 732         port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
 733         if (!port)
 734                 return -ENODEV;
 735
 736         drm_of_component_match_add(&pdev->dev, &match, malidp_compare_dev,
 737                                    port);
 738         of_node_put(port);
 739         return component_master_add_with_match(&pdev->dev, &malidp_master_ops,
 740                                                match);
 741 }
 742
 743 static int malidp_platform_remove(struct platform_device *pdev)
 744 {
 745         component_master_del(&pdev->dev, &malidp_master_ops);
 746         return 0;
 747 }
 748
 749 static int __maybe_unused malidp_pm_suspend(struct device *dev)
 750 {
 751         struct drm_device *drm = dev_get_drvdata(dev);
 752         struct malidp_drm *malidp = drm->dev_private;
 753
 754         drm_kms_helper_poll_disable(drm);
 755         console_lock();
 756         drm_fbdev_cma_set_suspend(malidp->fbdev, 1);
 757         console_unlock();
 758         malidp->pm_state = drm_atomic_helper_suspend(drm);
 759         if (IS_ERR(malidp->pm_state)) {
 760                 console_lock();
 761                 drm_fbdev_cma_set_suspend(malidp->fbdev, 0);
 762                 console_unlock();
 763                 drm_kms_helper_poll_enable(drm);
 764                 return PTR_ERR(malidp->pm_state);
 765         }
 766
 767         return 0;
 768 }
 769
 770 static int __maybe_unused malidp_pm_resume(struct device *dev)
 771 {
 772         struct drm_device *drm = dev_get_drvdata(dev);
 773         struct malidp_drm *malidp = drm->dev_private;
 774
 775         drm_atomic_helper_resume(drm, malidp->pm_state);
 776         console_lock();
 777         drm_fbdev_cma_set_suspend(malidp->fbdev, 0);
 778         console_unlock();
 779         drm_kms_helper_poll_enable(drm);
 780
 781         return 0;
 782 }
 783
 784 static const struct dev_pm_ops malidp_pm_ops = {
 785         SET_SYSTEM_SLEEP_PM_OPS(malidp_pm_suspend, malidp_pm_resume) \
 786         SET_RUNTIME_PM_OPS(malidp_runtime_pm_suspend, malidp_runtime_pm_resume, NULL)
 787 };
 788
 789 static struct platform_driver malidp_platform_driver = {
 790         .probe          = malidp_platform_probe,
 791         .remove         = malidp_platform_remove,
 792         .driver = {
 793                 .name = "mali-dp",
 794                 .pm = &malidp_pm_ops,
 795                 .of_match_table = malidp_drm_of_match,
 796         },
 797 };
 798
 799 module_platform_driver(malidp_platform_driver);
 800
 801 MODULE_AUTHOR("Liviu Dudau <Liviu.Dudau@arm.com>");
 802 MODULE_DESCRIPTION("ARM Mali DP DRM driver");
 803 MODULE_LICENSE("GPL v2");