2 * Copyright (C) 2013-2015 ARM Limited
3 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive
12 #include <linux/module.h>
13 #include <linux/spinlock.h>
14 #include <linux/clk.h>
15 #include <linux/component.h>
16 #include <linux/list.h>
17 #include <linux/of_graph.h>
18 #include <linux/of_reserved_mem.h>
19 #include <linux/pm_runtime.h>
22 #include <drm/drm_atomic_helper.h>
23 #include <drm/drm_crtc.h>
24 #include <drm/drm_crtc_helper.h>
25 #include <drm/drm_fb_helper.h>
26 #include <drm/drm_fb_cma_helper.h>
27 #include <drm/drm_gem_cma_helper.h>
28 #include <drm/drm_of.h>
30 #include "hdlcd_drv.h"
31 #include "hdlcd_regs.h"
33 static int hdlcd_load(struct drm_device *drm, unsigned long flags)
35 struct hdlcd_drm_private *hdlcd = drm->dev_private;
36 struct platform_device *pdev = to_platform_device(drm->dev);
41 hdlcd->clk = devm_clk_get(drm->dev, "pxlclk");
42 if (IS_ERR(hdlcd->clk))
43 return PTR_ERR(hdlcd->clk);
45 #ifdef CONFIG_DEBUG_FS
46 atomic_set(&hdlcd->buffer_underrun_count, 0);
47 atomic_set(&hdlcd->bus_error_count, 0);
48 atomic_set(&hdlcd->vsync_count, 0);
49 atomic_set(&hdlcd->dma_end_count, 0);
52 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
53 hdlcd->mmio = devm_ioremap_resource(drm->dev, res);
54 if (IS_ERR(hdlcd->mmio)) {
55 DRM_ERROR("failed to map control registers area\n");
56 ret = PTR_ERR(hdlcd->mmio);
61 version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
62 if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
63 DRM_ERROR("unknown product id: 0x%x\n", version);
66 DRM_INFO("found ARM HDLCD version r%dp%d\n",
67 (version & HDLCD_VERSION_MAJOR_MASK) >> 8,
68 version & HDLCD_VERSION_MINOR_MASK);
70 /* Get the optional framebuffer memory resource */
71 ret = of_reserved_mem_device_init(drm->dev);
72 if (ret && ret != -ENODEV)
75 ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
79 ret = hdlcd_setup_crtc(drm);
81 DRM_ERROR("failed to create crtc\n");
85 ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
87 DRM_ERROR("failed to install IRQ handler\n");
94 drm_crtc_cleanup(&hdlcd->crtc);
96 of_reserved_mem_device_release(drm->dev);
101 static void hdlcd_fb_output_poll_changed(struct drm_device *drm)
103 struct hdlcd_drm_private *hdlcd = drm->dev_private;
105 drm_fbdev_cma_hotplug_event(hdlcd->fbdev);
108 static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = {
109 .fb_create = drm_fb_cma_create,
110 .output_poll_changed = hdlcd_fb_output_poll_changed,
111 .atomic_check = drm_atomic_helper_check,
112 .atomic_commit = drm_atomic_helper_commit,
115 static void hdlcd_setup_mode_config(struct drm_device *drm)
117 drm_mode_config_init(drm);
118 drm->mode_config.min_width = 0;
119 drm->mode_config.min_height = 0;
120 drm->mode_config.max_width = HDLCD_MAX_XRES;
121 drm->mode_config.max_height = HDLCD_MAX_YRES;
122 drm->mode_config.funcs = &hdlcd_mode_config_funcs;
125 static void hdlcd_lastclose(struct drm_device *drm)
127 struct hdlcd_drm_private *hdlcd = drm->dev_private;
129 drm_fbdev_cma_restore_mode(hdlcd->fbdev);
132 static irqreturn_t hdlcd_irq(int irq, void *arg)
134 struct drm_device *drm = arg;
135 struct hdlcd_drm_private *hdlcd = drm->dev_private;
136 unsigned long irq_status;
138 irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS);
140 #ifdef CONFIG_DEBUG_FS
141 if (irq_status & HDLCD_INTERRUPT_UNDERRUN)
142 atomic_inc(&hdlcd->buffer_underrun_count);
144 if (irq_status & HDLCD_INTERRUPT_DMA_END)
145 atomic_inc(&hdlcd->dma_end_count);
147 if (irq_status & HDLCD_INTERRUPT_BUS_ERROR)
148 atomic_inc(&hdlcd->bus_error_count);
150 if (irq_status & HDLCD_INTERRUPT_VSYNC)
151 atomic_inc(&hdlcd->vsync_count);
154 if (irq_status & HDLCD_INTERRUPT_VSYNC)
155 drm_crtc_handle_vblank(&hdlcd->crtc);
157 /* acknowledge interrupt(s) */
158 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
163 static void hdlcd_irq_preinstall(struct drm_device *drm)
165 struct hdlcd_drm_private *hdlcd = drm->dev_private;
166 /* Ensure interrupts are disabled */
167 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
168 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
171 static int hdlcd_irq_postinstall(struct drm_device *drm)
173 #ifdef CONFIG_DEBUG_FS
174 struct hdlcd_drm_private *hdlcd = drm->dev_private;
175 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
177 /* enable debug interrupts */
178 irq_mask |= HDLCD_DEBUG_INT_MASK;
180 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
185 static void hdlcd_irq_uninstall(struct drm_device *drm)
187 struct hdlcd_drm_private *hdlcd = drm->dev_private;
188 /* disable all the interrupts that we might have enabled */
189 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
191 #ifdef CONFIG_DEBUG_FS
192 /* disable debug interrupts */
193 irq_mask &= ~HDLCD_DEBUG_INT_MASK;
196 /* disable vsync interrupts */
197 irq_mask &= ~HDLCD_INTERRUPT_VSYNC;
199 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
202 #ifdef CONFIG_DEBUG_FS
203 static int hdlcd_show_underrun_count(struct seq_file *m, void *arg)
205 struct drm_info_node *node = (struct drm_info_node *)m->private;
206 struct drm_device *drm = node->minor->dev;
207 struct hdlcd_drm_private *hdlcd = drm->dev_private;
209 seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count));
210 seq_printf(m, "dma_end : %d\n", atomic_read(&hdlcd->dma_end_count));
211 seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count));
212 seq_printf(m, "vsync : %d\n", atomic_read(&hdlcd->vsync_count));
216 static int hdlcd_show_pxlclock(struct seq_file *m, void *arg)
218 struct drm_info_node *node = (struct drm_info_node *)m->private;
219 struct drm_device *drm = node->minor->dev;
220 struct hdlcd_drm_private *hdlcd = drm->dev_private;
221 unsigned long clkrate = clk_get_rate(hdlcd->clk);
222 unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;
224 seq_printf(m, "hw : %lu\n", clkrate);
225 seq_printf(m, "mode: %lu\n", mode_clock);
229 static struct drm_info_list hdlcd_debugfs_list[] = {
230 { "interrupt_count", hdlcd_show_underrun_count, 0 },
231 { "clocks", hdlcd_show_pxlclock, 0 },
232 { "fb", drm_fb_cma_debugfs_show, 0 },
235 static int hdlcd_debugfs_init(struct drm_minor *minor)
237 return drm_debugfs_create_files(hdlcd_debugfs_list,
238 ARRAY_SIZE(hdlcd_debugfs_list), minor->debugfs_root, minor);
242 DEFINE_DRM_GEM_CMA_FOPS(fops);
244 static struct drm_driver hdlcd_driver = {
245 .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM |
246 DRIVER_MODESET | DRIVER_PRIME |
248 .lastclose = hdlcd_lastclose,
249 .irq_handler = hdlcd_irq,
250 .irq_preinstall = hdlcd_irq_preinstall,
251 .irq_postinstall = hdlcd_irq_postinstall,
252 .irq_uninstall = hdlcd_irq_uninstall,
253 .gem_free_object_unlocked = drm_gem_cma_free_object,
254 .gem_vm_ops = &drm_gem_cma_vm_ops,
255 .dumb_create = drm_gem_cma_dumb_create,
256 .dumb_map_offset = drm_gem_cma_dumb_map_offset,
257 .dumb_destroy = drm_gem_dumb_destroy,
258 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
259 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
260 .gem_prime_export = drm_gem_prime_export,
261 .gem_prime_import = drm_gem_prime_import,
262 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
263 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
264 .gem_prime_vmap = drm_gem_cma_prime_vmap,
265 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
266 .gem_prime_mmap = drm_gem_cma_prime_mmap,
267 #ifdef CONFIG_DEBUG_FS
268 .debugfs_init = hdlcd_debugfs_init,
272 .desc = "ARM HDLCD Controller DRM",
278 static int hdlcd_drm_bind(struct device *dev)
280 struct drm_device *drm;
281 struct hdlcd_drm_private *hdlcd;
284 hdlcd = devm_kzalloc(dev, sizeof(*hdlcd), GFP_KERNEL);
288 drm = drm_dev_alloc(&hdlcd_driver, dev);
292 drm->dev_private = hdlcd;
293 dev_set_drvdata(dev, drm);
295 hdlcd_setup_mode_config(drm);
296 ret = hdlcd_load(drm, 0);
300 /* Set the CRTC's port so that the encoder component can find it */
301 hdlcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
303 ret = component_bind_all(dev, drm);
305 DRM_ERROR("Failed to bind all components\n");
309 ret = pm_runtime_set_active(dev);
313 pm_runtime_enable(dev);
315 ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
317 DRM_ERROR("failed to initialise vblank\n");
321 drm_mode_config_reset(drm);
322 drm_kms_helper_poll_init(drm);
324 hdlcd->fbdev = drm_fbdev_cma_init(drm, 32,
325 drm->mode_config.num_connector);
327 if (IS_ERR(hdlcd->fbdev)) {
328 ret = PTR_ERR(hdlcd->fbdev);
333 ret = drm_dev_register(drm, 0);
341 drm_fbdev_cma_fini(hdlcd->fbdev);
345 drm_kms_helper_poll_fini(drm);
346 drm_vblank_cleanup(drm);
348 pm_runtime_disable(drm->dev);
350 component_unbind_all(dev, drm);
352 of_node_put(hdlcd->crtc.port);
353 hdlcd->crtc.port = NULL;
354 drm_irq_uninstall(drm);
355 of_reserved_mem_device_release(drm->dev);
357 drm_mode_config_cleanup(drm);
358 dev_set_drvdata(dev, NULL);
364 static void hdlcd_drm_unbind(struct device *dev)
366 struct drm_device *drm = dev_get_drvdata(dev);
367 struct hdlcd_drm_private *hdlcd = drm->dev_private;
369 drm_dev_unregister(drm);
371 drm_fbdev_cma_fini(hdlcd->fbdev);
374 drm_kms_helper_poll_fini(drm);
375 component_unbind_all(dev, drm);
376 of_node_put(hdlcd->crtc.port);
377 hdlcd->crtc.port = NULL;
378 drm_vblank_cleanup(drm);
379 pm_runtime_get_sync(drm->dev);
380 drm_irq_uninstall(drm);
381 pm_runtime_put_sync(drm->dev);
382 pm_runtime_disable(drm->dev);
383 of_reserved_mem_device_release(drm->dev);
384 drm_mode_config_cleanup(drm);
386 drm->dev_private = NULL;
387 dev_set_drvdata(dev, NULL);
390 static const struct component_master_ops hdlcd_master_ops = {
391 .bind = hdlcd_drm_bind,
392 .unbind = hdlcd_drm_unbind,
395 static int compare_dev(struct device *dev, void *data)
397 return dev->of_node == data;
400 static int hdlcd_probe(struct platform_device *pdev)
402 struct device_node *port;
403 struct component_match *match = NULL;
405 /* there is only one output port inside each device, find it */
406 port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
410 drm_of_component_match_add(&pdev->dev, &match, compare_dev, port);
413 return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops,
417 static int hdlcd_remove(struct platform_device *pdev)
419 component_master_del(&pdev->dev, &hdlcd_master_ops);
423 static const struct of_device_id hdlcd_of_match[] = {
424 { .compatible = "arm,hdlcd" },
427 MODULE_DEVICE_TABLE(of, hdlcd_of_match);
429 static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
431 struct drm_device *drm = dev_get_drvdata(dev);
432 struct hdlcd_drm_private *hdlcd = drm ? drm->dev_private : NULL;
437 drm_kms_helper_poll_disable(drm);
439 hdlcd->state = drm_atomic_helper_suspend(drm);
440 if (IS_ERR(hdlcd->state)) {
441 drm_kms_helper_poll_enable(drm);
442 return PTR_ERR(hdlcd->state);
448 static int __maybe_unused hdlcd_pm_resume(struct device *dev)
450 struct drm_device *drm = dev_get_drvdata(dev);
451 struct hdlcd_drm_private *hdlcd = drm ? drm->dev_private : NULL;
456 drm_atomic_helper_resume(drm, hdlcd->state);
457 drm_kms_helper_poll_enable(drm);
458 pm_runtime_set_active(dev);
463 static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume);
465 static struct platform_driver hdlcd_platform_driver = {
466 .probe = hdlcd_probe,
467 .remove = hdlcd_remove,
471 .of_match_table = hdlcd_of_match,
475 module_platform_driver(hdlcd_platform_driver);
477 MODULE_AUTHOR("Liviu Dudau");
478 MODULE_DESCRIPTION("ARM HDLCD DRM driver");
479 MODULE_LICENSE("GPL v2");