drm: arcpgu: Use crtc->mode_valid() callback
[sfrench/cifs-2.6.git] / drivers / gpu / drm / arc / arcpgu_crtc.c
1 /*
2  * ARC PGU DRM driver.
3  *
4  * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <drm/drm_atomic_helper.h>
18 #include <drm/drm_crtc_helper.h>
19 #include <drm/drm_fb_cma_helper.h>
20 #include <drm/drm_gem_cma_helper.h>
21 #include <drm/drm_plane_helper.h>
22 #include <linux/clk.h>
23 #include <linux/platform_data/simplefb.h>
24
25 #include "arcpgu.h"
26 #include "arcpgu_regs.h"
27
28 #define ENCODE_PGU_XY(x, y)     ((((x) - 1) << 16) | ((y) - 1))
29
30 static struct simplefb_format supported_formats[] = {
31         { "r5g6b5", 16, {11, 5}, {5, 6}, {0, 5}, {0, 0}, DRM_FORMAT_RGB565 },
32         { "r8g8b8", 24, {16, 8}, {8, 8}, {0, 8}, {0, 0}, DRM_FORMAT_RGB888 },
33 };
34
35 static void arc_pgu_set_pxl_fmt(struct drm_crtc *crtc)
36 {
37         struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
38         const struct drm_framebuffer *fb = crtc->primary->state->fb;
39         uint32_t pixel_format = fb->format->format;
40         struct simplefb_format *format = NULL;
41         int i;
42
43         for (i = 0; i < ARRAY_SIZE(supported_formats); i++) {
44                 if (supported_formats[i].fourcc == pixel_format)
45                         format = &supported_formats[i];
46         }
47
48         if (WARN_ON(!format))
49                 return;
50
51         if (format->fourcc == DRM_FORMAT_RGB888)
52                 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
53                               arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
54                                            ARCPGU_MODE_RGB888_MASK);
55
56 }
57
58 static const struct drm_crtc_funcs arc_pgu_crtc_funcs = {
59         .destroy = drm_crtc_cleanup,
60         .set_config = drm_atomic_helper_set_config,
61         .page_flip = drm_atomic_helper_page_flip,
62         .reset = drm_atomic_helper_crtc_reset,
63         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
64         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
65 };
66
67 enum drm_mode_status arc_pgu_crtc_mode_valid(struct drm_crtc *crtc,
68                                              const struct drm_display_mode *mode)
69 {
70         struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
71         long rate, clk_rate = mode->clock * 1000;
72
73         rate = clk_round_rate(arcpgu->clk, clk_rate);
74         if (rate != clk_rate)
75                 return MODE_NOCLOCK;
76
77         return MODE_OK;
78 }
79
80 static void arc_pgu_crtc_mode_set_nofb(struct drm_crtc *crtc)
81 {
82         struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
83         struct drm_display_mode *m = &crtc->state->adjusted_mode;
84         u32 val;
85
86         arc_pgu_write(arcpgu, ARCPGU_REG_FMT,
87                       ENCODE_PGU_XY(m->crtc_htotal, m->crtc_vtotal));
88
89         arc_pgu_write(arcpgu, ARCPGU_REG_HSYNC,
90                       ENCODE_PGU_XY(m->crtc_hsync_start - m->crtc_hdisplay,
91                                     m->crtc_hsync_end - m->crtc_hdisplay));
92
93         arc_pgu_write(arcpgu, ARCPGU_REG_VSYNC,
94                       ENCODE_PGU_XY(m->crtc_vsync_start - m->crtc_vdisplay,
95                                     m->crtc_vsync_end - m->crtc_vdisplay));
96
97         arc_pgu_write(arcpgu, ARCPGU_REG_ACTIVE,
98                       ENCODE_PGU_XY(m->crtc_hblank_end - m->crtc_hblank_start,
99                                     m->crtc_vblank_end - m->crtc_vblank_start));
100
101         val = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL);
102
103         if (m->flags & DRM_MODE_FLAG_PVSYNC)
104                 val |= ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST;
105         else
106                 val &= ~(ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST);
107
108         if (m->flags & DRM_MODE_FLAG_PHSYNC)
109                 val |= ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST;
110         else
111                 val &= ~(ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST);
112
113         arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, val);
114         arc_pgu_write(arcpgu, ARCPGU_REG_STRIDE, 0);
115         arc_pgu_write(arcpgu, ARCPGU_REG_START_SET, 1);
116
117         arc_pgu_set_pxl_fmt(crtc);
118
119         clk_set_rate(arcpgu->clk, m->crtc_clock * 1000);
120 }
121
122 static void arc_pgu_crtc_enable(struct drm_crtc *crtc)
123 {
124         struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
125
126         clk_prepare_enable(arcpgu->clk);
127         arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
128                       arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
129                       ARCPGU_CTRL_ENABLE_MASK);
130 }
131
132 static void arc_pgu_crtc_disable(struct drm_crtc *crtc)
133 {
134         struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
135
136         if (!crtc->primary->fb)
137                 return;
138
139         clk_disable_unprepare(arcpgu->clk);
140         arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
141                               arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) &
142                               ~ARCPGU_CTRL_ENABLE_MASK);
143 }
144
145 static void arc_pgu_crtc_atomic_begin(struct drm_crtc *crtc,
146                                       struct drm_crtc_state *state)
147 {
148         struct drm_pending_vblank_event *event = crtc->state->event;
149
150         if (event) {
151                 crtc->state->event = NULL;
152
153                 spin_lock_irq(&crtc->dev->event_lock);
154                 drm_crtc_send_vblank_event(crtc, event);
155                 spin_unlock_irq(&crtc->dev->event_lock);
156         }
157 }
158
159 static const struct drm_crtc_helper_funcs arc_pgu_crtc_helper_funcs = {
160         .mode_valid     = arc_pgu_crtc_mode_valid,
161         .mode_set       = drm_helper_crtc_mode_set,
162         .mode_set_base  = drm_helper_crtc_mode_set_base,
163         .mode_set_nofb  = arc_pgu_crtc_mode_set_nofb,
164         .enable         = arc_pgu_crtc_enable,
165         .disable        = arc_pgu_crtc_disable,
166         .prepare        = arc_pgu_crtc_disable,
167         .commit         = arc_pgu_crtc_enable,
168         .atomic_begin   = arc_pgu_crtc_atomic_begin,
169 };
170
171 static void arc_pgu_plane_atomic_update(struct drm_plane *plane,
172                                         struct drm_plane_state *state)
173 {
174         struct arcpgu_drm_private *arcpgu;
175         struct drm_gem_cma_object *gem;
176
177         if (!plane->state->crtc || !plane->state->fb)
178                 return;
179
180         arcpgu = crtc_to_arcpgu_priv(plane->state->crtc);
181         gem = drm_fb_cma_get_gem_obj(plane->state->fb, 0);
182         arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->paddr);
183 }
184
185 static const struct drm_plane_helper_funcs arc_pgu_plane_helper_funcs = {
186         .atomic_update = arc_pgu_plane_atomic_update,
187 };
188
189 static void arc_pgu_plane_destroy(struct drm_plane *plane)
190 {
191         drm_plane_helper_disable(plane);
192         drm_plane_cleanup(plane);
193 }
194
195 static const struct drm_plane_funcs arc_pgu_plane_funcs = {
196         .update_plane           = drm_atomic_helper_update_plane,
197         .disable_plane          = drm_atomic_helper_disable_plane,
198         .destroy                = arc_pgu_plane_destroy,
199         .reset                  = drm_atomic_helper_plane_reset,
200         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
201         .atomic_destroy_state   = drm_atomic_helper_plane_destroy_state,
202 };
203
204 static struct drm_plane *arc_pgu_plane_init(struct drm_device *drm)
205 {
206         struct arcpgu_drm_private *arcpgu = drm->dev_private;
207         struct drm_plane *plane = NULL;
208         u32 formats[ARRAY_SIZE(supported_formats)], i;
209         int ret;
210
211         plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
212         if (!plane)
213                 return ERR_PTR(-ENOMEM);
214
215         for (i = 0; i < ARRAY_SIZE(supported_formats); i++)
216                 formats[i] = supported_formats[i].fourcc;
217
218         ret = drm_universal_plane_init(drm, plane, 0xff, &arc_pgu_plane_funcs,
219                                        formats, ARRAY_SIZE(formats),
220                                        DRM_PLANE_TYPE_PRIMARY, NULL);
221         if (ret)
222                 return ERR_PTR(ret);
223
224         drm_plane_helper_add(plane, &arc_pgu_plane_helper_funcs);
225         arcpgu->plane = plane;
226
227         return plane;
228 }
229
230 int arc_pgu_setup_crtc(struct drm_device *drm)
231 {
232         struct arcpgu_drm_private *arcpgu = drm->dev_private;
233         struct drm_plane *primary;
234         int ret;
235
236         primary = arc_pgu_plane_init(drm);
237         if (IS_ERR(primary))
238                 return PTR_ERR(primary);
239
240         ret = drm_crtc_init_with_planes(drm, &arcpgu->crtc, primary, NULL,
241                                         &arc_pgu_crtc_funcs, NULL);
242         if (ret) {
243                 arc_pgu_plane_destroy(primary);
244                 return ret;
245         }
246
247         drm_crtc_helper_add(&arcpgu->crtc, &arc_pgu_crtc_helper_funcs);
248         return 0;
249 }