2 * Copyright 2015 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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24 #ifndef _GPU_SCHEDULER_H_
25 #define _GPU_SCHEDULER_H_
27 #include <linux/kfifo.h>
28 #include <linux/dma-fence.h>
30 struct amd_gpu_scheduler;
34 * A scheduler entity is a wrapper around a job queue or a group
35 * of other entities. Entities take turns emitting jobs from their
36 * job queues to corresponding hardware ring based on scheduling
39 struct amd_sched_entity {
40 struct list_head list;
41 struct amd_sched_rq *rq;
43 struct amd_gpu_scheduler *sched;
45 spinlock_t queue_lock;
46 struct kfifo job_queue;
49 uint64_t fence_context;
51 struct dma_fence *dependency;
52 struct dma_fence_cb cb;
56 * Run queue is a set of entities scheduling command submissions for
57 * one specific ring. It implements the scheduling policy that selects
58 * the next entity to emit commands from.
62 struct list_head entities;
63 struct amd_sched_entity *current_entity;
66 struct amd_sched_fence {
67 struct dma_fence scheduled;
68 struct dma_fence finished;
69 struct dma_fence_cb cb;
70 struct dma_fence *parent;
71 struct amd_gpu_scheduler *sched;
76 struct amd_sched_job {
77 struct amd_gpu_scheduler *sched;
78 struct amd_sched_entity *s_entity;
79 struct amd_sched_fence *s_fence;
80 struct dma_fence_cb finish_cb;
81 struct work_struct finish_work;
82 struct list_head node;
83 struct delayed_work work_tdr;
88 extern const struct dma_fence_ops amd_sched_fence_ops_scheduled;
89 extern const struct dma_fence_ops amd_sched_fence_ops_finished;
90 static inline struct amd_sched_fence *to_amd_sched_fence(struct dma_fence *f)
92 if (f->ops == &amd_sched_fence_ops_scheduled)
93 return container_of(f, struct amd_sched_fence, scheduled);
95 if (f->ops == &amd_sched_fence_ops_finished)
96 return container_of(f, struct amd_sched_fence, finished);
101 static inline bool amd_sched_invalidate_job(struct amd_sched_job *s_job, int threshold)
103 return (s_job && atomic_inc_return(&s_job->karma) > threshold);
107 * Define the backend operations called by the scheduler,
108 * these functions should be implemented in driver side
110 struct amd_sched_backend_ops {
111 struct dma_fence *(*dependency)(struct amd_sched_job *sched_job);
112 struct dma_fence *(*run_job)(struct amd_sched_job *sched_job);
113 void (*timedout_job)(struct amd_sched_job *sched_job);
114 void (*free_job)(struct amd_sched_job *sched_job);
117 enum amd_sched_priority {
118 AMD_SCHED_PRIORITY_MIN,
119 AMD_SCHED_PRIORITY_LOW = AMD_SCHED_PRIORITY_MIN,
120 AMD_SCHED_PRIORITY_NORMAL,
121 AMD_SCHED_PRIORITY_HIGH_SW,
122 AMD_SCHED_PRIORITY_HIGH_HW,
123 AMD_SCHED_PRIORITY_KERNEL,
124 AMD_SCHED_PRIORITY_MAX,
125 AMD_SCHED_PRIORITY_INVALID = -1,
126 AMD_SCHED_PRIORITY_UNSET = -2
130 * One scheduler is implemented for each hardware ring
132 struct amd_gpu_scheduler {
133 const struct amd_sched_backend_ops *ops;
134 uint32_t hw_submission_limit;
137 struct amd_sched_rq sched_rq[AMD_SCHED_PRIORITY_MAX];
138 wait_queue_head_t wake_up_worker;
139 wait_queue_head_t job_scheduled;
140 atomic_t hw_rq_count;
141 atomic64_t job_id_count;
142 struct task_struct *thread;
143 struct list_head ring_mirror_list;
144 spinlock_t job_list_lock;
147 int amd_sched_init(struct amd_gpu_scheduler *sched,
148 const struct amd_sched_backend_ops *ops,
149 uint32_t hw_submission, long timeout, const char *name);
150 void amd_sched_fini(struct amd_gpu_scheduler *sched);
152 int amd_sched_entity_init(struct amd_gpu_scheduler *sched,
153 struct amd_sched_entity *entity,
154 struct amd_sched_rq *rq,
156 void amd_sched_entity_fini(struct amd_gpu_scheduler *sched,
157 struct amd_sched_entity *entity);
158 void amd_sched_entity_push_job(struct amd_sched_job *sched_job);
159 void amd_sched_entity_set_rq(struct amd_sched_entity *entity,
160 struct amd_sched_rq *rq);
162 int amd_sched_fence_slab_init(void);
163 void amd_sched_fence_slab_fini(void);
165 struct amd_sched_fence *amd_sched_fence_create(
166 struct amd_sched_entity *s_entity, void *owner);
167 void amd_sched_fence_scheduled(struct amd_sched_fence *fence);
168 void amd_sched_fence_finished(struct amd_sched_fence *fence);
169 int amd_sched_job_init(struct amd_sched_job *job,
170 struct amd_gpu_scheduler *sched,
171 struct amd_sched_entity *entity,
173 void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched);
174 void amd_sched_job_recovery(struct amd_gpu_scheduler *sched);
175 bool amd_sched_dependency_optimized(struct dma_fence* fence,
176 struct amd_sched_entity *entity);
177 void amd_sched_job_kickout(struct amd_sched_job *s_job);
179 static inline enum amd_sched_priority
180 amd_sched_get_job_priority(struct amd_sched_job *job)
182 return (job->s_entity->rq - job->sched->sched_rq);