drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui <ray.huang@amd.com>
  23  *
  24  */
  25 #include "pp_debug.h"
  26 #include <linux/types.h>
  27 #include <linux/kernel.h>
  28 #include <linux/slab.h>
  29 #include <linux/gfp.h>
  30
  31 #include "smumgr.h"
  32 #include "iceland_smumgr.h"
  33
  34 #include "ppsmc.h"
  35
  36 #include "cgs_common.h"
  37
  38 #include "smu7_dyn_defaults.h"
  39 #include "smu7_hwmgr.h"
  40 #include "hardwaremanager.h"
  41 #include "ppatomctrl.h"
  42 #include "atombios.h"
  43 #include "pppcielanes.h"
  44 #include "pp_endian.h"
  45 #include "processpptables.h"
  46
  47
  48 #include "smu/smu_7_1_1_d.h"
  49 #include "smu/smu_7_1_1_sh_mask.h"
  50 #include "smu71_discrete.h"
  51
  52 #include "smu_ucode_xfer_vi.h"
  53 #include "gmc/gmc_8_1_d.h"
  54 #include "gmc/gmc_8_1_sh_mask.h"
  55 #include "bif/bif_5_0_d.h"
  56 #include "bif/bif_5_0_sh_mask.h"
  57 #include "dce/dce_10_0_d.h"
  58 #include "dce/dce_10_0_sh_mask.h"
  59
  60
  61 #define ICELAND_SMC_SIZE               0x20000
  62
  63 #define VOLTAGE_SCALE 4
  64 #define POWERTUNE_DEFAULT_SET_MAX    1
  65 #define VOLTAGE_VID_OFFSET_SCALE1   625
  66 #define VOLTAGE_VID_OFFSET_SCALE2   100
  67 #define MC_CG_ARB_FREQ_F1           0x0b
  68 #define VDDC_VDDCI_DELTA            200
  69
  70 #define DEVICE_ID_VI_ICELAND_M_6900     0x6900
  71 #define DEVICE_ID_VI_ICELAND_M_6901     0x6901
  72 #define DEVICE_ID_VI_ICELAND_M_6902     0x6902
  73 #define DEVICE_ID_VI_ICELAND_M_6903     0x6903
  74
  75 static const struct iceland_pt_defaults defaults_iceland = {
  76         /*
  77          * sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc,
  78          * TDC_MAWt, TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT
  79          */
  80         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
  81         { 0x79,  0x253, 0x25D, 0xAE,  0x72,  0x80,  0x83,  0x86,  0x6F,  0xC8,  0xC9,  0xC9,  0x2F,  0x4D,  0x61  },
  82         { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
  83 };
  84
  85 /* 35W - XT, XTL */
  86 static const struct iceland_pt_defaults defaults_icelandxt = {
  87         /*
  88          * sviLoadLIneEn, SviLoadLineVddC,
  89          * TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
  90          * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac,
  91          * BAPM_TEMP_GRADIENT
  92          */
  93         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x0,
  94         { 0xA7,  0x0, 0x0, 0xB5,  0x0, 0x0, 0x9F,  0x0, 0x0, 0xD6,  0x0, 0x0, 0xD7,  0x0, 0x0},
  95         { 0x1EA, 0x0, 0x0, 0x224, 0x0, 0x0, 0x25E, 0x0, 0x0, 0x28E, 0x0, 0x0, 0x2AB, 0x0, 0x0}
  96 };
  97
  98 /* 25W - PRO, LE */
  99 static const struct iceland_pt_defaults defaults_icelandpro = {
 100         /*
 101          * sviLoadLIneEn, SviLoadLineVddC,
 102          * TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
 103          * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac,
 104          * BAPM_TEMP_GRADIENT
 105          */
 106         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x0,
 107         { 0xB7,  0x0, 0x0, 0xC3,  0x0, 0x0, 0xB5,  0x0, 0x0, 0xEA,  0x0, 0x0, 0xE6,  0x0, 0x0},
 108         { 0x1EA, 0x0, 0x0, 0x224, 0x0, 0x0, 0x25E, 0x0, 0x0, 0x28E, 0x0, 0x0, 0x2AB, 0x0, 0x0}
 109 };
 110
 111 static int iceland_start_smc(struct pp_hwmgr *hwmgr)
 112 {
 113         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 114                                   SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 115
 116         return 0;
 117 }
 118
 119 static void iceland_reset_smc(struct pp_hwmgr *hwmgr)
 120 {
 121         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 122                                   SMC_SYSCON_RESET_CNTL,
 123                                   rst_reg, 1);
 124 }
 125
 126
 127 static void iceland_stop_smc_clock(struct pp_hwmgr *hwmgr)
 128 {
 129         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 130                                   SMC_SYSCON_CLOCK_CNTL_0,
 131                                   ck_disable, 1);
 132 }
 133
 134 static void iceland_start_smc_clock(struct pp_hwmgr *hwmgr)
 135 {
 136         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 137                                   SMC_SYSCON_CLOCK_CNTL_0,
 138                                   ck_disable, 0);
 139 }
 140
 141 static int iceland_smu_start_smc(struct pp_hwmgr *hwmgr)
 142 {
 143         /* set smc instruct start point at 0x0 */
 144         smu7_program_jump_on_start(hwmgr);
 145
 146         /* enable smc clock */
 147         iceland_start_smc_clock(hwmgr);
 148
 149         /* de-assert reset */
 150         iceland_start_smc(hwmgr);
 151
 152         PHM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS,
 153                                  INTERRUPTS_ENABLED, 1);
 154
 155         return 0;
 156 }
 157
 158
 159 static int iceland_upload_smc_firmware_data(struct pp_hwmgr *hwmgr,
 160                                         uint32_t length, const uint8_t *src,
 161                                         uint32_t limit, uint32_t start_addr)
 162 {
 163         uint32_t byte_count = length;
 164         uint32_t data;
 165
 166         PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL);
 167
 168         cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr);
 169         PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
 170
 171         while (byte_count >= 4) {
 172                 data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
 173                 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
 174                 src += 4;
 175                 byte_count -= 4;
 176         }
 177
 178         PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
 179
 180         PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be divisible by 4.", return -EINVAL);
 181
 182         return 0;
 183 }
 184
 185
 186 static int iceland_smu_upload_firmware_image(struct pp_hwmgr *hwmgr)
 187 {
 188         uint32_t val;
 189         struct cgs_firmware_info info = {0};
 190
 191         if (hwmgr == NULL || hwmgr->device == NULL)
 192                 return -EINVAL;
 193
 194         /* load SMC firmware */
 195         cgs_get_firmware_info(hwmgr->device,
 196                 smu7_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
 197
 198         if (info.image_size & 3) {
 199                 pr_err("[ powerplay ] SMC ucode is not 4 bytes aligned\n");
 200                 return -EINVAL;
 201         }
 202
 203         if (info.image_size > ICELAND_SMC_SIZE) {
 204                 pr_err("[ powerplay ] SMC address is beyond the SMC RAM area\n");
 205                 return -EINVAL;
 206         }
 207
 208         /* wait for smc boot up */
 209         PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
 210                                          RCU_UC_EVENTS, boot_seq_done, 0);
 211
 212         /* clear firmware interrupt enable flag */
 213         val = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 214                                     ixSMC_SYSCON_MISC_CNTL);
 215         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 216                                ixSMC_SYSCON_MISC_CNTL, val | 1);
 217
 218         /* stop smc clock */
 219         iceland_stop_smc_clock(hwmgr);
 220
 221         /* reset smc */
 222         iceland_reset_smc(hwmgr);
 223         iceland_upload_smc_firmware_data(hwmgr, info.image_size,
 224                                 (uint8_t *)info.kptr, ICELAND_SMC_SIZE,
 225                                 info.ucode_start_address);
 226
 227         return 0;
 228 }
 229
 230 static int iceland_request_smu_load_specific_fw(struct pp_hwmgr *hwmgr,
 231                                                 uint32_t firmwareType)
 232 {
 233         return 0;
 234 }
 235
 236 static int iceland_start_smu(struct pp_hwmgr *hwmgr)
 237 {
 238         int result;
 239
 240         result = iceland_smu_upload_firmware_image(hwmgr);
 241         if (result)
 242                 return result;
 243         result = iceland_smu_start_smc(hwmgr);
 244         if (result)
 245                 return result;
 246
 247         if (!smu7_is_smc_ram_running(hwmgr)) {
 248                 pr_info("smu not running, upload firmware again \n");
 249                 result = iceland_smu_upload_firmware_image(hwmgr);
 250                 if (result)
 251                         return result;
 252
 253                 result = iceland_smu_start_smc(hwmgr);
 254                 if (result)
 255                         return result;
 256         }
 257
 258         result = smu7_request_smu_load_fw(hwmgr);
 259
 260         return result;
 261 }
 262
 263 static int iceland_smu_init(struct pp_hwmgr *hwmgr)
 264 {
 265         int i;
 266         struct iceland_smumgr *iceland_priv = NULL;
 267
 268         iceland_priv = kzalloc(sizeof(struct iceland_smumgr), GFP_KERNEL);
 269
 270         if (iceland_priv == NULL)
 271                 return -ENOMEM;
 272
 273         hwmgr->smu_backend = iceland_priv;
 274
 275         if (smu7_init(hwmgr))
 276                 return -EINVAL;
 277
 278         for (i = 0; i < SMU71_MAX_LEVELS_GRAPHICS; i++)
 279                 iceland_priv->activity_target[i] = 30;
 280
 281         return 0;
 282 }
 283
 284
 285 static void iceland_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
 286 {
 287         struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
 288         struct cgs_system_info sys_info = {0};
 289         uint32_t dev_id;
 290
 291         sys_info.size = sizeof(struct cgs_system_info);
 292         sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
 293         cgs_query_system_info(hwmgr->device, &sys_info);
 294         dev_id = (uint32_t)sys_info.value;
 295
 296         switch (dev_id) {
 297         case DEVICE_ID_VI_ICELAND_M_6900:
 298         case DEVICE_ID_VI_ICELAND_M_6903:
 299                 smu_data->power_tune_defaults = &defaults_icelandxt;
 300                 break;
 301
 302         case DEVICE_ID_VI_ICELAND_M_6901:
 303         case DEVICE_ID_VI_ICELAND_M_6902:
 304                 smu_data->power_tune_defaults = &defaults_icelandpro;
 305                 break;
 306         default:
 307                 smu_data->power_tune_defaults = &defaults_iceland;
 308                 pr_warn("Unknown V.I. Device ID.\n");
 309                 break;
 310         }
 311         return;
 312 }
 313
 314 static int iceland_populate_svi_load_line(struct pp_hwmgr *hwmgr)
 315 {
 316         struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
 317         const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
 318
 319         smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en;
 320         smu_data->power_tune_table.SviLoadLineVddC = defaults->svi_load_line_vddc;
 321         smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
 322         smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
 323
 324         return 0;
 325 }
 326
 327 static int iceland_populate_tdc_limit(struct pp_hwmgr *hwmgr)
 328 {
 329         uint16_t tdc_limit;
 330         struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
 331         const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
 332
 333         tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256);
 334         smu_data->power_tune_table.TDC_VDDC_PkgLimit =
 335                         CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
 336         smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
 337                         defaults->tdc_vddc_throttle_release_limit_perc;
 338         smu_data->power_tune_table.TDC_MAWt = defaults->tdc_mawt;
 339
 340         return 0;
 341 }
 342
 343 static int iceland_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
 344 {
 345         struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
 346         const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
 347         uint32_t temp;
 348
 349         if (smu7_read_smc_sram_dword(hwmgr,
 350                         fuse_table_offset +
 351                         offsetof(SMU71_Discrete_PmFuses, TdcWaterfallCtl),
 352                         (uint32_t *)&temp, SMC_RAM_END))
 353                 PP_ASSERT_WITH_CODE(false,
 354                                 "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
 355                                 return -EINVAL);
 356         else
 357                 smu_data->power_tune_table.TdcWaterfallCtl = defaults->tdc_waterfall_ctl;
 358
 359         return 0;
 360 }
 361
 362 static int iceland_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
 363 {
 364         return 0;
 365 }
 366
 367 static int iceland_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
 368 {
 369         int i;
 370         struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
 371
 372         /* Currently not used. Set all to zero. */
 373         for (i = 0; i < 8; i++)
 374                 smu_data->power_tune_table.GnbLPML[i] = 0;
 375
 376         return 0;
 377 }
 378
 379 static int iceland_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
 380 {
 381         struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
 382         uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
 383         uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
 384         struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table;
 385
 386         HiSidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
 387         LoSidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
 388
 389         smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
 390                         CONVERT_FROM_HOST_TO_SMC_US(HiSidd);
 391         smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
 392                         CONVERT_FROM_HOST_TO_SMC_US(LoSidd);
 393
 394         return 0;
 395 }
 396
 397 static int iceland_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr)
 398 {
 399         int i;
 400         struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
 401         uint8_t *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd;
 402         uint8_t *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd;
 403
 404         PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table,
 405                             "The CAC Leakage table does not exist!", return -EINVAL);
 406         PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8,
 407                             "There should never be more than 8 entries for BapmVddcVid!!!", return -EINVAL);
 408         PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count,
 409                             "CACLeakageTable->count and VddcDependencyOnSCLk->count not equal", return -EINVAL);
 410
 411         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_EVV)) {
 412                 for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) {
 413                         lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1);
 414                         hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2);
 415                 }
 416         } else {
 417                 PP_ASSERT_WITH_CODE(false, "Iceland should always support EVV", return -EINVAL);
 418         }
 419
 420         return 0;
 421 }
 422
 423 static int iceland_populate_vddc_vid(struct pp_hwmgr *hwmgr)
 424 {
 425         int i;
 426         struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
 427         uint8_t *vid = smu_data->power_tune_table.VddCVid;
 428         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 429
 430         PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 8,
 431                 "There should never be more than 8 entries for VddcVid!!!",
 432                 return -EINVAL);
 433
 434         for (i = 0; i < (int)data->vddc_voltage_table.count; i++) {
 435                 vid[i] = convert_to_vid(data->vddc_voltage_table.entries[i].value);
 436         }
 437
 438         return 0;
 439 }
 440
 441
 442
 443 static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr)
 444 {
 445         struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
 446         uint32_t pm_fuse_table_offset;
 447
 448         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 449                         PHM_PlatformCaps_PowerContainment)) {
 450                 if (smu7_read_smc_sram_dword(hwmgr,
 451                                 SMU71_FIRMWARE_HEADER_LOCATION +
 452                                 offsetof(SMU71_Firmware_Header, PmFuseTable),
 453                                 &pm_fuse_table_offset, SMC_RAM_END))
 454                         PP_ASSERT_WITH_CODE(false,
 455                                         "Attempt to get pm_fuse_table_offset Failed!",
 456                                         return -EINVAL);
 457
 458                 /* DW0 - DW3 */
 459                 if (iceland_populate_bapm_vddc_vid_sidd(hwmgr))
 460                         PP_ASSERT_WITH_CODE(false,
 461                                         "Attempt to populate bapm vddc vid Failed!",
 462                                         return -EINVAL);
 463
 464                 /* DW4 - DW5 */
 465                 if (iceland_populate_vddc_vid(hwmgr))
 466                         PP_ASSERT_WITH_CODE(false,
 467                                         "Attempt to populate vddc vid Failed!",
 468                                         return -EINVAL);
 469
 470                 /* DW6 */
 471                 if (iceland_populate_svi_load_line(hwmgr))
 472                         PP_ASSERT_WITH_CODE(false,
 473                                         "Attempt to populate SviLoadLine Failed!",
 474                                         return -EINVAL);
 475                 /* DW7 */
 476                 if (iceland_populate_tdc_limit(hwmgr))
 477                         PP_ASSERT_WITH_CODE(false,
 478                                         "Attempt to populate TDCLimit Failed!", return -EINVAL);
 479                 /* DW8 */
 480                 if (iceland_populate_dw8(hwmgr, pm_fuse_table_offset))
 481                         PP_ASSERT_WITH_CODE(false,
 482                                         "Attempt to populate TdcWaterfallCtl, "
 483                                         "LPMLTemperature Min and Max Failed!",
 484                                         return -EINVAL);
 485
 486                 /* DW9-DW12 */
 487                 if (0 != iceland_populate_temperature_scaler(hwmgr))
 488                         PP_ASSERT_WITH_CODE(false,
 489                                         "Attempt to populate LPMLTemperatureScaler Failed!",
 490                                         return -EINVAL);
 491
 492                 /* DW13-DW16 */
 493                 if (iceland_populate_gnb_lpml(hwmgr))
 494                         PP_ASSERT_WITH_CODE(false,
 495                                         "Attempt to populate GnbLPML Failed!",
 496                                         return -EINVAL);
 497
 498                 /* DW18 */
 499                 if (iceland_populate_bapm_vddc_base_leakage_sidd(hwmgr))
 500                         PP_ASSERT_WITH_CODE(false,
 501                                         "Attempt to populate BapmVddCBaseLeakage Hi and Lo Sidd Failed!",
 502                                         return -EINVAL);
 503
 504                 if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
 505                                 (uint8_t *)&smu_data->power_tune_table,
 506                                 sizeof(struct SMU71_Discrete_PmFuses), SMC_RAM_END))
 507                         PP_ASSERT_WITH_CODE(false,
 508                                         "Attempt to download PmFuseTable Failed!",
 509                                         return -EINVAL);
 510         }
 511         return 0;
 512 }
 513
 514 static int iceland_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
 515         struct phm_clock_voltage_dependency_table *allowed_clock_voltage_table,
 516         uint32_t clock, uint32_t *vol)
 517 {
 518         uint32_t i = 0;
 519
 520         /* clock - voltage dependency table is empty table */
 521         if (allowed_clock_voltage_table->count == 0)
 522                 return -EINVAL;
 523
 524         for (i = 0; i < allowed_clock_voltage_table->count; i++) {
 525                 /* find first sclk bigger than request */
 526                 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
 527                         *vol = allowed_clock_voltage_table->entries[i].v;
 528                         return 0;
 529                 }
 530         }
 531
 532         /* sclk is bigger than max sclk in the dependence table */
 533         *vol = allowed_clock_voltage_table->entries[i - 1].v;
 534
 535         return 0;
 536 }
 537
 538 static int iceland_get_std_voltage_value_sidd(struct pp_hwmgr *hwmgr,
 539                 pp_atomctrl_voltage_table_entry *tab, uint16_t *hi,
 540                 uint16_t *lo)
 541 {
 542         uint16_t v_index;
 543         bool vol_found = false;
 544         *hi = tab->value * VOLTAGE_SCALE;
 545         *lo = tab->value * VOLTAGE_SCALE;
 546
 547         /* SCLK/VDDC Dependency Table has to exist. */
 548         PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk,
 549                         "The SCLK/VDDC Dependency Table does not exist.\n",
 550                         return -EINVAL);
 551
 552         if (NULL == hwmgr->dyn_state.cac_leakage_table) {
 553                 pr_warn("CAC Leakage Table does not exist, using vddc.\n");
 554                 return 0;
 555         }
 556
 557         /*
 558          * Since voltage in the sclk/vddc dependency table is not
 559          * necessarily in ascending order because of ELB voltage
 560          * patching, loop through entire list to find exact voltage.
 561          */
 562         for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {
 563                 if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
 564                         vol_found = true;
 565                         if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {
 566                                 *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
 567                                 *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage * VOLTAGE_SCALE);
 568                         } else {
 569                                 pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index, using maximum index from CAC table.\n");
 570                                 *lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE;
 571                                 *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE);
 572                         }
 573                         break;
 574                 }
 575         }
 576
 577         /*
 578          * If voltage is not found in the first pass, loop again to
 579          * find the best match, equal or higher value.
 580          */
 581         if (!vol_found) {
 582                 for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {
 583                         if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
 584                                 vol_found = true;
 585                                 if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {
 586                                         *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
 587                                         *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage) * VOLTAGE_SCALE;
 588                                 } else {
 589                                         pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index in second look up, using maximum index from CAC table.");
 590                                         *lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE;
 591                                         *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE);
 592                                 }
 593                                 break;
 594                         }
 595                 }
 596
 597                 if (!vol_found)
 598                         pr_warn("Unable to get std_vddc from SCLK/VDDC Dependency Table, using vddc.\n");
 599         }
 600
 601         return 0;
 602 }
 603
 604 static int iceland_populate_smc_voltage_table(struct pp_hwmgr *hwmgr,
 605                 pp_atomctrl_voltage_table_entry *tab,
 606                 SMU71_Discrete_VoltageLevel *smc_voltage_tab)
 607 {
 608         int result;
 609
 610         result = iceland_get_std_voltage_value_sidd(hwmgr, tab,
 611                         &smc_voltage_tab->StdVoltageHiSidd,
 612                         &smc_voltage_tab->StdVoltageLoSidd);
 613         if (0 != result) {
 614                 smc_voltage_tab->StdVoltageHiSidd = tab->value * VOLTAGE_SCALE;
 615                 smc_voltage_tab->StdVoltageLoSidd = tab->value * VOLTAGE_SCALE;
 616         }
 617
 618         smc_voltage_tab->Voltage = PP_HOST_TO_SMC_US(tab->value * VOLTAGE_SCALE);
 619         CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageHiSidd);
 620         CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageHiSidd);
 621
 622         return 0;
 623 }
 624
 625 static int iceland_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
 626                         SMU71_Discrete_DpmTable *table)
 627 {
 628         unsigned int count;
 629         int result;
 630         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 631
 632         table->VddcLevelCount = data->vddc_voltage_table.count;
 633         for (count = 0; count < table->VddcLevelCount; count++) {
 634                 result = iceland_populate_smc_voltage_table(hwmgr,
 635                                 &(data->vddc_voltage_table.entries[count]),
 636                                 &(table->VddcLevel[count]));
 637                 PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL);
 638
 639                 /* GPIO voltage control */
 640                 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control)
 641                         table->VddcLevel[count].Smio |= data->vddc_voltage_table.entries[count].smio_low;
 642                 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control)
 643                         table->VddcLevel[count].Smio = 0;
 644         }
 645
 646         CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
 647
 648         return 0;
 649 }
 650
 651 static int iceland_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
 652                         SMU71_Discrete_DpmTable *table)
 653 {
 654         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 655         uint32_t count;
 656         int result;
 657
 658         table->VddciLevelCount = data->vddci_voltage_table.count;
 659
 660         for (count = 0; count < table->VddciLevelCount; count++) {
 661                 result = iceland_populate_smc_voltage_table(hwmgr,
 662                                 &(data->vddci_voltage_table.entries[count]),
 663                                 &(table->VddciLevel[count]));
 664                 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL);
 665                 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
 666                         table->VddciLevel[count].Smio |= data->vddci_voltage_table.entries[count].smio_low;
 667                 else
 668                         table->VddciLevel[count].Smio |= 0;
 669         }
 670
 671         CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
 672
 673         return 0;
 674 }
 675
 676 static int iceland_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
 677                         SMU71_Discrete_DpmTable *table)
 678 {
 679         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 680         uint32_t count;
 681         int result;
 682
 683         table->MvddLevelCount = data->mvdd_voltage_table.count;
 684
 685         for (count = 0; count < table->VddciLevelCount; count++) {
 686                 result = iceland_populate_smc_voltage_table(hwmgr,
 687                                 &(data->mvdd_voltage_table.entries[count]),
 688                                 &table->MvddLevel[count]);
 689                 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL);
 690                 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control)
 691                         table->MvddLevel[count].Smio |= data->mvdd_voltage_table.entries[count].smio_low;
 692                 else
 693                         table->MvddLevel[count].Smio |= 0;
 694         }
 695
 696         CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
 697
 698         return 0;
 699 }
 700
 701
 702 static int iceland_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
 703         SMU71_Discrete_DpmTable *table)
 704 {
 705         int result;
 706
 707         result = iceland_populate_smc_vddc_table(hwmgr, table);
 708         PP_ASSERT_WITH_CODE(0 == result,
 709                         "can not populate VDDC voltage table to SMC", return -EINVAL);
 710
 711         result = iceland_populate_smc_vdd_ci_table(hwmgr, table);
 712         PP_ASSERT_WITH_CODE(0 == result,
 713                         "can not populate VDDCI voltage table to SMC", return -EINVAL);
 714
 715         result = iceland_populate_smc_mvdd_table(hwmgr, table);
 716         PP_ASSERT_WITH_CODE(0 == result,
 717                         "can not populate MVDD voltage table to SMC", return -EINVAL);
 718
 719         return 0;
 720 }
 721
 722 static int iceland_populate_ulv_level(struct pp_hwmgr *hwmgr,
 723                 struct SMU71_Discrete_Ulv *state)
 724 {
 725         uint32_t voltage_response_time, ulv_voltage;
 726         int result;
 727         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 728
 729         state->CcPwrDynRm = 0;
 730         state->CcPwrDynRm1 = 0;
 731
 732         result = pp_tables_get_response_times(hwmgr, &voltage_response_time, &ulv_voltage);
 733         PP_ASSERT_WITH_CODE((0 == result), "can not get ULV voltage value", return result;);
 734
 735         if (ulv_voltage == 0) {
 736                 data->ulv_supported = false;
 737                 return 0;
 738         }
 739
 740         if (data->voltage_control != SMU7_VOLTAGE_CONTROL_BY_SVID2) {
 741                 /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */
 742                 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
 743                         state->VddcOffset = 0;
 744                 else
 745                         /* used in SMIO Mode. not implemented for now. this is backup only for CI. */
 746                         state->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage);
 747         } else {
 748                 /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */
 749                 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
 750                         state->VddcOffsetVid = 0;
 751                 else  /* used in SVI2 Mode */
 752                         state->VddcOffsetVid = (uint8_t)(
 753                                         (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage)
 754                                                 * VOLTAGE_VID_OFFSET_SCALE2
 755                                                 / VOLTAGE_VID_OFFSET_SCALE1);
 756         }
 757         state->VddcPhase = 1;
 758
 759         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
 760         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
 761         CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
 762
 763         return 0;
 764 }
 765
 766 static int iceland_populate_ulv_state(struct pp_hwmgr *hwmgr,
 767                  SMU71_Discrete_Ulv *ulv_level)
 768 {
 769         return iceland_populate_ulv_level(hwmgr, ulv_level);
 770 }
 771
 772 static int iceland_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU71_Discrete_DpmTable *table)
 773 {
 774         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 775         struct smu7_dpm_table *dpm_table = &data->dpm_table;
 776         struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
 777         uint32_t i;
 778
 779         /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
 780         for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
 781                 table->LinkLevel[i].PcieGenSpeed  =
 782                         (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
 783                 table->LinkLevel[i].PcieLaneCount =
 784                         (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
 785                 table->LinkLevel[i].EnabledForActivity =
 786                         1;
 787                 table->LinkLevel[i].SPC =
 788                         (uint8_t)(data->pcie_spc_cap & 0xff);
 789                 table->LinkLevel[i].DownThreshold =
 790                         PP_HOST_TO_SMC_UL(5);
 791                 table->LinkLevel[i].UpThreshold =
 792                         PP_HOST_TO_SMC_UL(30);
 793         }
 794
 795         smu_data->smc_state_table.LinkLevelCount =
 796                 (uint8_t)dpm_table->pcie_speed_table.count;
 797         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
 798                 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
 799
 800         return 0;
 801 }
 802
 803 static int iceland_calculate_sclk_params(struct pp_hwmgr *hwmgr,
 804                 uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *sclk)
 805 {
 806         const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 807         pp_atomctrl_clock_dividers_vi dividers;
 808         uint32_t spll_func_cntl            = data->clock_registers.vCG_SPLL_FUNC_CNTL;
 809         uint32_t spll_func_cntl_3          = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
 810         uint32_t spll_func_cntl_4          = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
 811         uint32_t cg_spll_spread_spectrum   = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
 812         uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
 813         uint32_t    reference_clock;
 814         uint32_t reference_divider;
 815         uint32_t fbdiv;
 816         int result;
 817
 818         /* get the engine clock dividers for this clock value*/
 819         result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock,  &dividers);
 820
 821         PP_ASSERT_WITH_CODE(result == 0,
 822                 "Error retrieving Engine Clock dividers from VBIOS.", return result);
 823
 824         /* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/
 825         reference_clock = atomctrl_get_reference_clock(hwmgr);
 826
 827         reference_divider = 1 + dividers.uc_pll_ref_div;
 828
 829         /* low 14 bits is fraction and high 12 bits is divider*/
 830         fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
 831
 832         /* SPLL_FUNC_CNTL setup*/
 833         spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
 834                 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
 835         spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
 836                 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A,  dividers.uc_pll_post_div);
 837
 838         /* SPLL_FUNC_CNTL_3 setup*/
 839         spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
 840                 CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
 841
 842         /* set to use fractional accumulation*/
 843         spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
 844                 CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
 845
 846         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 847                         PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
 848                 pp_atomctrl_internal_ss_info ss_info;
 849
 850                 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
 851                 if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) {
 852                         /*
 853                         * ss_info.speed_spectrum_percentage -- in unit of 0.01%
 854                         * ss_info.speed_spectrum_rate -- in unit of khz
 855                         */
 856                         /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */
 857                         uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);
 858
 859                         /* clkv = 2 * D * fbdiv / NS */
 860                         uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);
 861
 862                         cg_spll_spread_spectrum =
 863                                 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS);
 864                         cg_spll_spread_spectrum =
 865                                 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
 866                         cg_spll_spread_spectrum_2 =
 867                                 PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV);
 868                 }
 869         }
 870
 871         sclk->SclkFrequency        = engine_clock;
 872         sclk->CgSpllFuncCntl3      = spll_func_cntl_3;
 873         sclk->CgSpllFuncCntl4      = spll_func_cntl_4;
 874         sclk->SpllSpreadSpectrum   = cg_spll_spread_spectrum;
 875         sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
 876         sclk->SclkDid              = (uint8_t)dividers.pll_post_divider;
 877
 878         return 0;
 879 }
 880
 881 static int iceland_populate_phase_value_based_on_sclk(struct pp_hwmgr *hwmgr,
 882                                 const struct phm_phase_shedding_limits_table *pl,
 883                                         uint32_t sclk, uint32_t *p_shed)
 884 {
 885         unsigned int i;
 886
 887         /* use the minimum phase shedding */
 888         *p_shed = 1;
 889
 890         for (i = 0; i < pl->count; i++) {
 891                 if (sclk < pl->entries[i].Sclk) {
 892                         *p_shed = i;
 893                         break;
 894                 }
 895         }
 896         return 0;
 897 }
 898
 899 static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
 900                                                 uint32_t engine_clock,
 901                                 uint16_t sclk_activity_level_threshold,
 902                                 SMU71_Discrete_GraphicsLevel *graphic_level)
 903 {
 904         int result;
 905         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 906
 907         result = iceland_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
 908
 909         /* populate graphics levels*/
 910         result = iceland_get_dependency_volt_by_clk(hwmgr,
 911                 hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock,
 912                 &graphic_level->MinVddc);
 913         PP_ASSERT_WITH_CODE((0 == result),
 914                 "can not find VDDC voltage value for VDDC       \
 915                 engine clock dependency table", return result);
 916
 917         /* SCLK frequency in units of 10KHz*/
 918         graphic_level->SclkFrequency = engine_clock;
 919         graphic_level->MinVddcPhases = 1;
 920
 921         if (data->vddc_phase_shed_control)
 922                 iceland_populate_phase_value_based_on_sclk(hwmgr,
 923                                 hwmgr->dyn_state.vddc_phase_shed_limits_table,
 924                                 engine_clock,
 925                                 &graphic_level->MinVddcPhases);
 926
 927         /* Indicates maximum activity level for this performance level. 50% for now*/
 928         graphic_level->ActivityLevel = sclk_activity_level_threshold;
 929
 930         graphic_level->CcPwrDynRm = 0;
 931         graphic_level->CcPwrDynRm1 = 0;
 932         /* this level can be used if activity is high enough.*/
 933         graphic_level->EnabledForActivity = 0;
 934         /* this level can be used for throttling.*/
 935         graphic_level->EnabledForThrottle = 1;
 936         graphic_level->UpHyst = 0;
 937         graphic_level->DownHyst = 100;
 938         graphic_level->VoltageDownHyst = 0;
 939         graphic_level->PowerThrottle = 0;
 940
 941         data->display_timing.min_clock_in_sr =
 942                         hwmgr->display_config.min_core_set_clock_in_sr;
 943
 944         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 945                         PHM_PlatformCaps_SclkDeepSleep))
 946                 graphic_level->DeepSleepDivId =
 947                                 smu7_get_sleep_divider_id_from_clock(engine_clock,
 948                                                 data->display_timing.min_clock_in_sr);
 949
 950         /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
 951         graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
 952
 953         if (0 == result) {
 954                 graphic_level->MinVddc = PP_HOST_TO_SMC_UL(graphic_level->MinVddc * VOLTAGE_SCALE);
 955                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);
 956                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency);
 957                 CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel);
 958                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3);
 959                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4);
 960                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum);
 961                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2);
 962                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm);
 963                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1);
 964         }
 965
 966         return result;
 967 }
 968
 969 static int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
 970 {
 971         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 972         struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
 973         struct smu7_dpm_table *dpm_table = &data->dpm_table;
 974         uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start +
 975                                 offsetof(SMU71_Discrete_DpmTable, GraphicsLevel);
 976
 977         uint32_t level_array_size = sizeof(SMU71_Discrete_GraphicsLevel) *
 978                                                 SMU71_MAX_LEVELS_GRAPHICS;
 979
 980         SMU71_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;
 981
 982         uint32_t i;
 983         uint8_t highest_pcie_level_enabled = 0;
 984         uint8_t lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0;
 985         uint8_t count = 0;
 986         int result = 0;
 987
 988         memset(levels, 0x00, level_array_size);
 989
 990         for (i = 0; i < dpm_table->sclk_table.count; i++) {
 991                 result = iceland_populate_single_graphic_level(hwmgr,
 992                                         dpm_table->sclk_table.dpm_levels[i].value,
 993                                         (uint16_t)smu_data->activity_target[i],
 994                                         &(smu_data->smc_state_table.GraphicsLevel[i]));
 995                 if (result != 0)
 996                         return result;
 997
 998                 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
 999                 if (i > 1)
1000                         smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
1001         }
1002
1003         /* Only enable level 0 for now. */
1004         smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1005
1006         /* set highest level watermark to high */
1007         if (dpm_table->sclk_table.count > 1)
1008                 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
1009                         PPSMC_DISPLAY_WATERMARK_HIGH;
1010
1011         smu_data->smc_state_table.GraphicsDpmLevelCount =
1012                 (uint8_t)dpm_table->sclk_table.count;
1013         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1014                 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1015
1016         while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1017                                 (1 << (highest_pcie_level_enabled + 1))) != 0) {
1018                 highest_pcie_level_enabled++;
1019         }
1020
1021         while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1022                 (1 << lowest_pcie_level_enabled)) == 0) {
1023                 lowest_pcie_level_enabled++;
1024         }
1025
1026         while ((count < highest_pcie_level_enabled) &&
1027                         ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1028                                 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0)) {
1029                 count++;
1030         }
1031
1032         mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ?
1033                 (lowest_pcie_level_enabled+1+count) : highest_pcie_level_enabled;
1034
1035
1036         /* set pcieDpmLevel to highest_pcie_level_enabled*/
1037         for (i = 2; i < dpm_table->sclk_table.count; i++) {
1038                 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
1039         }
1040
1041         /* set pcieDpmLevel to lowest_pcie_level_enabled*/
1042         smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
1043
1044         /* set pcieDpmLevel to mid_pcie_level_enabled*/
1045         smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
1046
1047         /* level count will send to smc once at init smc table and never change*/
1048         result = smu7_copy_bytes_to_smc(hwmgr, level_array_adress,
1049                                 (uint8_t *)levels, (uint32_t)level_array_size,
1050                                                                 SMC_RAM_END);
1051
1052         return result;
1053 }
1054
1055 static int iceland_calculate_mclk_params(
1056                 struct pp_hwmgr *hwmgr,
1057                 uint32_t memory_clock,
1058                 SMU71_Discrete_MemoryLevel *mclk,
1059                 bool strobe_mode,
1060                 bool dllStateOn
1061                 )
1062 {
1063         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1064
1065         uint32_t  dll_cntl = data->clock_registers.vDLL_CNTL;
1066         uint32_t  mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
1067         uint32_t  mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;
1068         uint32_t  mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;
1069         uint32_t  mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
1070         uint32_t  mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
1071         uint32_t  mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;
1072         uint32_t  mpll_ss1 = data->clock_registers.vMPLL_SS1;
1073         uint32_t  mpll_ss2 = data->clock_registers.vMPLL_SS2;
1074
1075         pp_atomctrl_memory_clock_param mpll_param;
1076         int result;
1077
1078         result = atomctrl_get_memory_pll_dividers_si(hwmgr,
1079                                 memory_clock, &mpll_param, strobe_mode);
1080         PP_ASSERT_WITH_CODE(0 == result,
1081                 "Error retrieving Memory Clock Parameters from VBIOS.", return result);
1082
1083         /* MPLL_FUNC_CNTL setup*/
1084         mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
1085
1086         /* MPLL_FUNC_CNTL_1 setup*/
1087         mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
1088                                                         MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf);
1089         mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
1090                                                         MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac);
1091         mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
1092                                                         MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode);
1093
1094         /* MPLL_AD_FUNC_CNTL setup*/
1095         mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl,
1096                                                         MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1097
1098         if (data->is_memory_gddr5) {
1099                 /* MPLL_DQ_FUNC_CNTL setup*/
1100                 mpll_dq_func_cntl  = PHM_SET_FIELD(mpll_dq_func_cntl,
1101                                                                 MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
1102                 mpll_dq_func_cntl  = PHM_SET_FIELD(mpll_dq_func_cntl,
1103                                                                 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1104         }
1105
1106         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1107                         PHM_PlatformCaps_MemorySpreadSpectrumSupport)) {
1108                 /*
1109                  ************************************
1110                  Fref = Reference Frequency
1111                  NF = Feedback divider ratio
1112                  NR = Reference divider ratio
1113                  Fnom = Nominal VCO output frequency = Fref * NF / NR
1114                  Fs = Spreading Rate
1115                  D = Percentage down-spread / 2
1116                  Fint = Reference input frequency to PFD = Fref / NR
1117                  NS = Spreading rate divider ratio = int(Fint / (2 * Fs))
1118                  CLKS = NS - 1 = ISS_STEP_NUM[11:0]
1119                  NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2)
1120                  CLKV = 65536 * NV = ISS_STEP_SIZE[25:0]
1121                  *************************************
1122                  */
1123                 pp_atomctrl_internal_ss_info ss_info;
1124                 uint32_t freq_nom;
1125                 uint32_t tmp;
1126                 uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
1127
1128                 /* for GDDR5 for all modes and DDR3 */
1129                 if (1 == mpll_param.qdr)
1130                         freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider);
1131                 else
1132                         freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider);
1133
1134                 /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2  Note: S.I. reference_divider = 1*/
1135                 tmp = (freq_nom / reference_clock);
1136                 tmp = tmp * tmp;
1137
1138                 if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
1139                         /* ss_info.speed_spectrum_percentage -- in unit of 0.01% */
1140                         /* ss.Info.speed_spectrum_rate -- in unit of khz */
1141                         /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
1142                         /*     = reference_clock * 5 / speed_spectrum_rate */
1143                         uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;
1144
1145                         /* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */
1146                         /*     = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */
1147                         uint32_t clkv =
1148                                 (uint32_t)((((131 * ss_info.speed_spectrum_percentage *
1149                                                         ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
1150
1151                         mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
1152                         mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
1153                 }
1154         }
1155
1156         /* MCLK_PWRMGT_CNTL setup */
1157         mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1158                 MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
1159         mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1160                 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
1161         mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1162                 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
1163
1164
1165         /* Save the result data to outpupt memory level structure */
1166         mclk->MclkFrequency   = memory_clock;
1167         mclk->MpllFuncCntl    = mpll_func_cntl;
1168         mclk->MpllFuncCntl_1  = mpll_func_cntl_1;
1169         mclk->MpllFuncCntl_2  = mpll_func_cntl_2;
1170         mclk->MpllAdFuncCntl  = mpll_ad_func_cntl;
1171         mclk->MpllDqFuncCntl  = mpll_dq_func_cntl;
1172         mclk->MclkPwrmgtCntl  = mclk_pwrmgt_cntl;
1173         mclk->DllCntl         = dll_cntl;
1174         mclk->MpllSs1         = mpll_ss1;
1175         mclk->MpllSs2         = mpll_ss2;
1176
1177         return 0;
1178 }
1179
1180 static uint8_t iceland_get_mclk_frequency_ratio(uint32_t memory_clock,
1181                 bool strobe_mode)
1182 {
1183         uint8_t mc_para_index;
1184
1185         if (strobe_mode) {
1186                 if (memory_clock < 12500) {
1187                         mc_para_index = 0x00;
1188                 } else if (memory_clock > 47500) {
1189                         mc_para_index = 0x0f;
1190                 } else {
1191                         mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);
1192                 }
1193         } else {
1194                 if (memory_clock < 65000) {
1195                         mc_para_index = 0x00;
1196                 } else if (memory_clock > 135000) {
1197                         mc_para_index = 0x0f;
1198                 } else {
1199                         mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);
1200                 }
1201         }
1202
1203         return mc_para_index;
1204 }
1205
1206 static uint8_t iceland_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)
1207 {
1208         uint8_t mc_para_index;
1209
1210         if (memory_clock < 10000) {
1211                 mc_para_index = 0;
1212         } else if (memory_clock >= 80000) {
1213                 mc_para_index = 0x0f;
1214         } else {
1215                 mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);
1216         }
1217
1218         return mc_para_index;
1219 }
1220
1221 static int iceland_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl,
1222                                         uint32_t memory_clock, uint32_t *p_shed)
1223 {
1224         unsigned int i;
1225
1226         *p_shed = 1;
1227
1228         for (i = 0; i < pl->count; i++) {
1229                 if (memory_clock < pl->entries[i].Mclk) {
1230                         *p_shed = i;
1231                         break;
1232                 }
1233         }
1234
1235         return 0;
1236 }
1237
1238 static int iceland_populate_single_memory_level(
1239                 struct pp_hwmgr *hwmgr,
1240                 uint32_t memory_clock,
1241                 SMU71_Discrete_MemoryLevel *memory_level
1242                 )
1243 {
1244         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1245         int result = 0;
1246         bool dll_state_on;
1247         struct cgs_display_info info = {0};
1248         uint32_t mclk_edc_wr_enable_threshold = 40000;
1249         uint32_t mclk_edc_enable_threshold = 40000;
1250         uint32_t mclk_strobe_mode_threshold = 40000;
1251
1252         if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) {
1253                 result = iceland_get_dependency_volt_by_clk(hwmgr,
1254                         hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc);
1255                 PP_ASSERT_WITH_CODE((0 == result),
1256                         "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result);
1257         }
1258
1259         if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE) {
1260                 memory_level->MinVddci = memory_level->MinVddc;
1261         } else if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) {
1262                 result = iceland_get_dependency_volt_by_clk(hwmgr,
1263                                 hwmgr->dyn_state.vddci_dependency_on_mclk,
1264                                 memory_clock,
1265                                 &memory_level->MinVddci);
1266                 PP_ASSERT_WITH_CODE((0 == result),
1267                         "can not find MinVddci voltage value from memory VDDCI voltage dependency table", return result);
1268         }
1269
1270         memory_level->MinVddcPhases = 1;
1271
1272         if (data->vddc_phase_shed_control) {
1273                 iceland_populate_phase_value_based_on_mclk(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table,
1274                                 memory_clock, &memory_level->MinVddcPhases);
1275         }
1276
1277         memory_level->EnabledForThrottle = 1;
1278         memory_level->EnabledForActivity = 0;
1279         memory_level->UpHyst = 0;
1280         memory_level->DownHyst = 100;
1281         memory_level->VoltageDownHyst = 0;
1282
1283         /* Indicates maximum activity level for this performance level.*/
1284         memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1285         memory_level->StutterEnable = 0;
1286         memory_level->StrobeEnable = 0;
1287         memory_level->EdcReadEnable = 0;
1288         memory_level->EdcWriteEnable = 0;
1289         memory_level->RttEnable = 0;
1290
1291         /* default set to low watermark. Highest level will be set to high later.*/
1292         memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1293
1294         cgs_get_active_displays_info(hwmgr->device, &info);
1295         data->display_timing.num_existing_displays = info.display_count;
1296
1297         /* stutter mode not support on iceland */
1298
1299         /* decide strobe mode*/
1300         memory_level->StrobeEnable = (mclk_strobe_mode_threshold != 0) &&
1301                 (memory_clock <= mclk_strobe_mode_threshold);
1302
1303         /* decide EDC mode and memory clock ratio*/
1304         if (data->is_memory_gddr5) {
1305                 memory_level->StrobeRatio = iceland_get_mclk_frequency_ratio(memory_clock,
1306                                         memory_level->StrobeEnable);
1307
1308                 if ((mclk_edc_enable_threshold != 0) &&
1309                                 (memory_clock > mclk_edc_enable_threshold)) {
1310                         memory_level->EdcReadEnable = 1;
1311                 }
1312
1313                 if ((mclk_edc_wr_enable_threshold != 0) &&
1314                                 (memory_clock > mclk_edc_wr_enable_threshold)) {
1315                         memory_level->EdcWriteEnable = 1;
1316                 }
1317
1318                 if (memory_level->StrobeEnable) {
1319                         if (iceland_get_mclk_frequency_ratio(memory_clock, 1) >=
1320                                         ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf))
1321                                 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
1322                         else
1323                                 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
1324                 } else
1325                         dll_state_on = data->dll_default_on;
1326         } else {
1327                 memory_level->StrobeRatio =
1328                         iceland_get_ddr3_mclk_frequency_ratio(memory_clock);
1329                 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
1330         }
1331
1332         result = iceland_calculate_mclk_params(hwmgr,
1333                 memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
1334
1335         if (0 == result) {
1336                 memory_level->MinVddc = PP_HOST_TO_SMC_UL(memory_level->MinVddc * VOLTAGE_SCALE);
1337                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinVddcPhases);
1338                 memory_level->MinVddci = PP_HOST_TO_SMC_UL(memory_level->MinVddci * VOLTAGE_SCALE);
1339                 memory_level->MinMvdd = PP_HOST_TO_SMC_UL(memory_level->MinMvdd * VOLTAGE_SCALE);
1340                 /* MCLK frequency in units of 10KHz*/
1341                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency);
1342                 /* Indicates maximum activity level for this performance level.*/
1343                 CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel);
1344                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl);
1345                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1);
1346                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2);
1347                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl);
1348                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl);
1349                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl);
1350                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl);
1351                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1);
1352                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2);
1353         }
1354
1355         return result;
1356 }
1357
1358 static int iceland_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1359 {
1360         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1361         struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1362         struct smu7_dpm_table *dpm_table = &data->dpm_table;
1363         int result;
1364
1365         /* populate MCLK dpm table to SMU7 */
1366         uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start + offsetof(SMU71_Discrete_DpmTable, MemoryLevel);
1367         uint32_t level_array_size = sizeof(SMU71_Discrete_MemoryLevel) * SMU71_MAX_LEVELS_MEMORY;
1368         SMU71_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel;
1369         uint32_t i;
1370
1371         memset(levels, 0x00, level_array_size);
1372
1373         for (i = 0; i < dpm_table->mclk_table.count; i++) {
1374                 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1375                         "can not populate memory level as memory clock is zero", return -EINVAL);
1376                 result = iceland_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value,
1377                         &(smu_data->smc_state_table.MemoryLevel[i]));
1378                 if (0 != result) {
1379                         return result;
1380                 }
1381         }
1382
1383         /* Only enable level 0 for now.*/
1384         smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
1385
1386         /*
1387         * in order to prevent MC activity from stutter mode to push DPM up.
1388         * the UVD change complements this by putting the MCLK in a higher state
1389         * by default such that we are not effected by up threshold or and MCLK DPM latency.
1390         */
1391         smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
1392         CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel);
1393
1394         smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
1395         data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1396         /* set highest level watermark to high*/
1397         smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1398
1399         /* level count will send to smc once at init smc table and never change*/
1400         result = smu7_copy_bytes_to_smc(hwmgr,
1401                 level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size,
1402                 SMC_RAM_END);
1403
1404         return result;
1405 }
1406
1407 static int iceland_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk,
1408                                         SMU71_Discrete_VoltageLevel *voltage)
1409 {
1410         const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1411
1412         uint32_t i = 0;
1413
1414         if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1415                 /* find mvdd value which clock is more than request */
1416                 for (i = 0; i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count; i++) {
1417                         if (mclk <= hwmgr->dyn_state.mvdd_dependency_on_mclk->entries[i].clk) {
1418                                 /* Always round to higher voltage. */
1419                                 voltage->Voltage = data->mvdd_voltage_table.entries[i].value;
1420                                 break;
1421                         }
1422                 }
1423
1424                 PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count,
1425                         "MVDD Voltage is outside the supported range.", return -EINVAL);
1426
1427         } else {
1428                 return -EINVAL;
1429         }
1430
1431         return 0;
1432 }
1433
1434 static int iceland_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1435         SMU71_Discrete_DpmTable *table)
1436 {
1437         int result = 0;
1438         const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1439         struct pp_atomctrl_clock_dividers_vi dividers;
1440         uint32_t vddc_phase_shed_control = 0;
1441
1442         SMU71_Discrete_VoltageLevel voltage_level;
1443         uint32_t spll_func_cntl    = data->clock_registers.vCG_SPLL_FUNC_CNTL;
1444         uint32_t spll_func_cntl_2  = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
1445         uint32_t dll_cntl          = data->clock_registers.vDLL_CNTL;
1446         uint32_t mclk_pwrmgt_cntl  = data->clock_registers.vMCLK_PWRMGT_CNTL;
1447
1448
1449         /* The ACPI state should not do DPM on DC (or ever).*/
1450         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1451
1452         if (data->acpi_vddc)
1453                 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE);
1454         else
1455                 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE);
1456
1457         table->ACPILevel.MinVddcPhases = vddc_phase_shed_control ? 0 : 1;
1458         /* assign zero for now*/
1459         table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
1460
1461         /* get the engine clock dividers for this clock value*/
1462         result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
1463                 table->ACPILevel.SclkFrequency,  &dividers);
1464
1465         PP_ASSERT_WITH_CODE(result == 0,
1466                 "Error retrieving Engine Clock dividers from VBIOS.", return result);
1467
1468         /* divider ID for required SCLK*/
1469         table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
1470         table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1471         table->ACPILevel.DeepSleepDivId = 0;
1472
1473         spll_func_cntl      = PHM_SET_FIELD(spll_func_cntl,
1474                                                         CG_SPLL_FUNC_CNTL,   SPLL_PWRON,     0);
1475         spll_func_cntl      = PHM_SET_FIELD(spll_func_cntl,
1476                                                         CG_SPLL_FUNC_CNTL,   SPLL_RESET,     1);
1477         spll_func_cntl_2    = PHM_SET_FIELD(spll_func_cntl_2,
1478                                                         CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL,   4);
1479
1480         table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
1481         table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
1482         table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
1483         table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
1484         table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
1485         table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
1486         table->ACPILevel.CcPwrDynRm = 0;
1487         table->ACPILevel.CcPwrDynRm1 = 0;
1488
1489
1490         /* For various features to be enabled/disabled while this level is active.*/
1491         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1492         /* SCLK frequency in units of 10KHz*/
1493         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
1494         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
1495         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
1496         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
1497         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
1498         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
1499         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
1500         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1501         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1502
1503         /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
1504         table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
1505         table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
1506
1507         if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
1508                 table->MemoryACPILevel.MinVddci = table->MemoryACPILevel.MinVddc;
1509         else {
1510                 if (data->acpi_vddci != 0)
1511                         table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->acpi_vddci * VOLTAGE_SCALE);
1512                 else
1513                         table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->min_vddci_in_pptable * VOLTAGE_SCALE);
1514         }
1515
1516         if (0 == iceland_populate_mvdd_value(hwmgr, 0, &voltage_level))
1517                 table->MemoryACPILevel.MinMvdd =
1518                         PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);
1519         else
1520                 table->MemoryACPILevel.MinMvdd = 0;
1521
1522         /* Force reset on DLL*/
1523         mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1524                 MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
1525         mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1526                 MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
1527
1528         /* Disable DLL in ACPIState*/
1529         mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1530                 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
1531         mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1532                 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
1533
1534         /* Enable DLL bypass signal*/
1535         dll_cntl            = PHM_SET_FIELD(dll_cntl,
1536                 DLL_CNTL, MRDCK0_BYPASS, 0);
1537         dll_cntl            = PHM_SET_FIELD(dll_cntl,
1538                 DLL_CNTL, MRDCK1_BYPASS, 0);
1539
1540         table->MemoryACPILevel.DllCntl            =
1541                 PP_HOST_TO_SMC_UL(dll_cntl);
1542         table->MemoryACPILevel.MclkPwrmgtCntl     =
1543                 PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);
1544         table->MemoryACPILevel.MpllAdFuncCntl     =
1545                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);
1546         table->MemoryACPILevel.MpllDqFuncCntl     =
1547                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);
1548         table->MemoryACPILevel.MpllFuncCntl       =
1549                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);
1550         table->MemoryACPILevel.MpllFuncCntl_1     =
1551                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);
1552         table->MemoryACPILevel.MpllFuncCntl_2     =
1553                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);
1554         table->MemoryACPILevel.MpllSs1            =
1555                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);
1556         table->MemoryACPILevel.MpllSs2            =
1557                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
1558
1559         table->MemoryACPILevel.EnabledForThrottle = 0;
1560         table->MemoryACPILevel.EnabledForActivity = 0;
1561         table->MemoryACPILevel.UpHyst = 0;
1562         table->MemoryACPILevel.DownHyst = 100;
1563         table->MemoryACPILevel.VoltageDownHyst = 0;
1564         /* Indicates maximum activity level for this performance level.*/
1565         table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
1566
1567         table->MemoryACPILevel.StutterEnable = 0;
1568         table->MemoryACPILevel.StrobeEnable = 0;
1569         table->MemoryACPILevel.EdcReadEnable = 0;
1570         table->MemoryACPILevel.EdcWriteEnable = 0;
1571         table->MemoryACPILevel.RttEnable = 0;
1572
1573         return result;
1574 }
1575
1576 static int iceland_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1577                                         SMU71_Discrete_DpmTable *table)
1578 {
1579         return 0;
1580 }
1581
1582 static int iceland_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1583                 SMU71_Discrete_DpmTable *table)
1584 {
1585         return 0;
1586 }
1587
1588 static int iceland_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
1589                 SMU71_Discrete_DpmTable *table)
1590 {
1591         return 0;
1592 }
1593
1594 static int iceland_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1595         SMU71_Discrete_DpmTable *table)
1596 {
1597         return 0;
1598 }
1599
1600 static int iceland_populate_memory_timing_parameters(
1601                 struct pp_hwmgr *hwmgr,
1602                 uint32_t engine_clock,
1603                 uint32_t memory_clock,
1604                 struct SMU71_Discrete_MCArbDramTimingTableEntry *arb_regs
1605                 )
1606 {
1607         uint32_t dramTiming;
1608         uint32_t dramTiming2;
1609         uint32_t burstTime;
1610         int result;
1611
1612         result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1613                                 engine_clock, memory_clock);
1614
1615         PP_ASSERT_WITH_CODE(result == 0,
1616                 "Error calling VBIOS to set DRAM_TIMING.", return result);
1617
1618         dramTiming  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1619         dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1620         burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1621
1622         arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dramTiming);
1623         arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
1624         arb_regs->McArbBurstTime = (uint8_t)burstTime;
1625
1626         return 0;
1627 }
1628
1629 static int iceland_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1630 {
1631         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1632         struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1633         int result = 0;
1634         SMU71_Discrete_MCArbDramTimingTable  arb_regs;
1635         uint32_t i, j;
1636
1637         memset(&arb_regs, 0x00, sizeof(SMU71_Discrete_MCArbDramTimingTable));
1638
1639         for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1640                 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1641                         result = iceland_populate_memory_timing_parameters
1642                                 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
1643                                  data->dpm_table.mclk_table.dpm_levels[j].value,
1644                                  &arb_regs.entries[i][j]);
1645
1646                         if (0 != result) {
1647                                 break;
1648                         }
1649                 }
1650         }
1651
1652         if (0 == result) {
1653                 result = smu7_copy_bytes_to_smc(
1654                                 hwmgr,
1655                                 smu_data->smu7_data.arb_table_start,
1656                                 (uint8_t *)&arb_regs,
1657                                 sizeof(SMU71_Discrete_MCArbDramTimingTable),
1658                                 SMC_RAM_END
1659                                 );
1660         }
1661
1662         return result;
1663 }
1664
1665 static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1666                         SMU71_Discrete_DpmTable *table)
1667 {
1668         int result = 0;
1669         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1670         struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1671         table->GraphicsBootLevel = 0;
1672         table->MemoryBootLevel = 0;
1673
1674         /* find boot level from dpm table*/
1675         result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1676                         data->vbios_boot_state.sclk_bootup_value,
1677                         (uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel));
1678
1679         if (0 != result) {
1680                 smu_data->smc_state_table.GraphicsBootLevel = 0;
1681                 pr_err("VBIOS did not find boot engine clock value \
1682                         in dependency table. Using Graphics DPM level 0!");
1683                 result = 0;
1684         }
1685
1686         result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1687                 data->vbios_boot_state.mclk_bootup_value,
1688                 (uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel));
1689
1690         if (0 != result) {
1691                 smu_data->smc_state_table.MemoryBootLevel = 0;
1692                 pr_err("VBIOS did not find boot engine clock value \
1693                         in dependency table. Using Memory DPM level 0!");
1694                 result = 0;
1695         }
1696
1697         table->BootVddc = data->vbios_boot_state.vddc_bootup_value;
1698         if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
1699                 table->BootVddci = table->BootVddc;
1700         else
1701                 table->BootVddci = data->vbios_boot_state.vddci_bootup_value;
1702
1703         table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
1704
1705         return result;
1706 }
1707
1708 static int iceland_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
1709                                  SMU71_Discrete_MCRegisters *mc_reg_table)
1710 {
1711         const struct iceland_smumgr *smu_data = (struct iceland_smumgr *)hwmgr->smu_backend;
1712
1713         uint32_t i, j;
1714
1715         for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) {
1716                 if (smu_data->mc_reg_table.validflag & 1<<j) {
1717                         PP_ASSERT_WITH_CODE(i < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE,
1718                                 "Index of mc_reg_table->address[] array out of boundary", return -EINVAL);
1719                         mc_reg_table->address[i].s0 =
1720                                 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0);
1721                         mc_reg_table->address[i].s1 =
1722                                 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1);
1723                         i++;
1724                 }
1725         }
1726
1727         mc_reg_table->last = (uint8_t)i;
1728
1729         return 0;
1730 }
1731
1732 /*convert register values from driver to SMC format */
1733 static void iceland_convert_mc_registers(
1734         const struct iceland_mc_reg_entry *entry,
1735         SMU71_Discrete_MCRegisterSet *data,
1736         uint32_t num_entries, uint32_t valid_flag)
1737 {
1738         uint32_t i, j;
1739
1740         for (i = 0, j = 0; j < num_entries; j++) {
1741                 if (valid_flag & 1<<j) {
1742                         data->value[i] = PP_HOST_TO_SMC_UL(entry->mc_data[j]);
1743                         i++;
1744                 }
1745         }
1746 }
1747
1748 static int iceland_convert_mc_reg_table_entry_to_smc(struct pp_hwmgr *hwmgr,
1749                 const uint32_t memory_clock,
1750                 SMU71_Discrete_MCRegisterSet *mc_reg_table_data
1751                 )
1752 {
1753         struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1754         uint32_t i = 0;
1755
1756         for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
1757                 if (memory_clock <=
1758                         smu_data->mc_reg_table.mc_reg_table_entry[i].mclk_max) {
1759                         break;
1760                 }
1761         }
1762
1763         if ((i == smu_data->mc_reg_table.num_entries) && (i > 0))
1764                 --i;
1765
1766         iceland_convert_mc_registers(&smu_data->mc_reg_table.mc_reg_table_entry[i],
1767                                 mc_reg_table_data, smu_data->mc_reg_table.last,
1768                                 smu_data->mc_reg_table.validflag);
1769
1770         return 0;
1771 }
1772
1773 static int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
1774                 SMU71_Discrete_MCRegisters *mc_regs)
1775 {
1776         int result = 0;
1777         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1778         int res;
1779         uint32_t i;
1780
1781         for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
1782                 res = iceland_convert_mc_reg_table_entry_to_smc(
1783                                 hwmgr,
1784                                 data->dpm_table.mclk_table.dpm_levels[i].value,
1785                                 &mc_regs->data[i]
1786                                 );
1787
1788                 if (0 != res)
1789                         result = res;
1790         }
1791
1792         return result;
1793 }
1794
1795 static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
1796 {
1797         struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1798         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1799         uint32_t address;
1800         int32_t result;
1801
1802         if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
1803                 return 0;
1804
1805
1806         memset(&smu_data->mc_regs, 0, sizeof(SMU71_Discrete_MCRegisters));
1807
1808         result = iceland_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs));
1809
1810         if (result != 0)
1811                 return result;
1812
1813
1814         address = smu_data->smu7_data.mc_reg_table_start + (uint32_t)offsetof(SMU71_Discrete_MCRegisters, data[0]);
1815
1816         return  smu7_copy_bytes_to_smc(hwmgr, address,
1817                                  (uint8_t *)&smu_data->mc_regs.data[0],
1818                                 sizeof(SMU71_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count,
1819                                 SMC_RAM_END);
1820 }
1821
1822 static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
1823 {
1824         int result;
1825         struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1826
1827         memset(&smu_data->mc_regs, 0x00, sizeof(SMU71_Discrete_MCRegisters));
1828         result = iceland_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
1829         PP_ASSERT_WITH_CODE(0 == result,
1830                 "Failed to initialize MCRegTable for the MC register addresses!", return result;);
1831
1832         result = iceland_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs);
1833         PP_ASSERT_WITH_CODE(0 == result,
1834                 "Failed to initialize MCRegTable for driver state!", return result;);
1835
1836         return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start,
1837                         (uint8_t *)&smu_data->mc_regs, sizeof(SMU71_Discrete_MCRegisters), SMC_RAM_END);
1838 }
1839
1840 static int iceland_populate_smc_initial_state(struct pp_hwmgr *hwmgr)
1841 {
1842         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1843         struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1844         uint8_t count, level;
1845
1846         count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count);
1847
1848         for (level = 0; level < count; level++) {
1849                 if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[level].clk
1850                          >= data->vbios_boot_state.sclk_bootup_value) {
1851                         smu_data->smc_state_table.GraphicsBootLevel = level;
1852                         break;
1853                 }
1854         }
1855
1856         count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_mclk->count);
1857
1858         for (level = 0; level < count; level++) {
1859                 if (hwmgr->dyn_state.vddc_dependency_on_mclk->entries[level].clk
1860                         >= data->vbios_boot_state.mclk_bootup_value) {
1861                         smu_data->smc_state_table.MemoryBootLevel = level;
1862                         break;
1863                 }
1864         }
1865
1866         return 0;
1867 }
1868
1869 static int iceland_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
1870 {
1871         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1872         struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1873         const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
1874         SMU71_Discrete_DpmTable  *dpm_table = &(smu_data->smc_state_table);
1875         struct phm_cac_tdp_table *cac_dtp_table = hwmgr->dyn_state.cac_dtp_table;
1876         struct phm_ppm_table *ppm = hwmgr->dyn_state.ppm_parameter_table;
1877         const uint16_t *def1, *def2;
1878         int i, j, k;
1879
1880
1881         /*
1882          * TDP number of fraction bits are changed from 8 to 7 for Iceland
1883          * as requested by SMC team
1884          */
1885
1886         dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 256));
1887         dpm_table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usConfigurableTDP * 256));
1888
1889
1890         dpm_table->DTETjOffset = 0;
1891
1892         dpm_table->GpuTjMax = (uint8_t)(data->thermal_temp_setting.temperature_high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES);
1893         dpm_table->GpuTjHyst = 8;
1894
1895         dpm_table->DTEAmbientTempBase = defaults->dte_ambient_temp_base;
1896
1897         /* The following are for new Iceland Multi-input fan/thermal control */
1898         if (NULL != ppm) {
1899                 dpm_table->PPM_PkgPwrLimit = (uint16_t)ppm->dgpu_tdp * 256 / 1000;
1900                 dpm_table->PPM_TemperatureLimit = (uint16_t)ppm->tj_max * 256;
1901         } else {
1902                 dpm_table->PPM_PkgPwrLimit = 0;
1903                 dpm_table->PPM_TemperatureLimit = 0;
1904         }
1905
1906         CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_PkgPwrLimit);
1907         CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_TemperatureLimit);
1908
1909         dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient);
1910         def1 = defaults->bapmti_r;
1911         def2 = defaults->bapmti_rc;
1912
1913         for (i = 0; i < SMU71_DTE_ITERATIONS; i++) {
1914                 for (j = 0; j < SMU71_DTE_SOURCES; j++) {
1915                         for (k = 0; k < SMU71_DTE_SINKS; k++) {
1916                                 dpm_table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*def1);
1917                                 dpm_table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*def2);
1918                                 def1++;
1919                                 def2++;
1920                         }
1921                 }
1922         }
1923
1924         return 0;
1925 }
1926
1927 static int iceland_populate_smc_svi2_config(struct pp_hwmgr *hwmgr,
1928                                             SMU71_Discrete_DpmTable *tab)
1929 {
1930         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1931
1932         if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control)
1933                 tab->SVI2Enable |= VDDC_ON_SVI2;
1934
1935         if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1936                 tab->SVI2Enable |= VDDCI_ON_SVI2;
1937         else
1938                 tab->MergedVddci = 1;
1939
1940         if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control)
1941                 tab->SVI2Enable |= MVDD_ON_SVI2;
1942
1943         PP_ASSERT_WITH_CODE(tab->SVI2Enable != (VDDC_ON_SVI2 | VDDCI_ON_SVI2 | MVDD_ON_SVI2) &&
1944                 (tab->SVI2Enable & VDDC_ON_SVI2), "SVI2 domain configuration is incorrect!", return -EINVAL);
1945
1946         return 0;
1947 }
1948
1949 static int iceland_init_smc_table(struct pp_hwmgr *hwmgr)
1950 {
1951         int result;
1952         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1953         struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1954         SMU71_Discrete_DpmTable  *table = &(smu_data->smc_state_table);
1955
1956
1957         iceland_initialize_power_tune_defaults(hwmgr);
1958         memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table));
1959
1960         if (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control) {
1961                 iceland_populate_smc_voltage_tables(hwmgr, table);
1962         }
1963
1964         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1965                         PHM_PlatformCaps_AutomaticDCTransition))
1966                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1967
1968
1969         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1970                         PHM_PlatformCaps_StepVddc))
1971                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1972
1973         if (data->is_memory_gddr5)
1974                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1975
1976
1977         if (data->ulv_supported) {
1978                 result = iceland_populate_ulv_state(hwmgr, &(smu_data->ulv_setting));
1979                 PP_ASSERT_WITH_CODE(0 == result,
1980                         "Failed to initialize ULV state!", return result;);
1981
1982                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1983                         ixCG_ULV_PARAMETER, 0x40035);
1984         }
1985
1986         result = iceland_populate_smc_link_level(hwmgr, table);
1987         PP_ASSERT_WITH_CODE(0 == result,
1988                 "Failed to initialize Link Level!", return result;);
1989
1990         result = iceland_populate_all_graphic_levels(hwmgr);
1991         PP_ASSERT_WITH_CODE(0 == result,
1992                 "Failed to initialize Graphics Level!", return result;);
1993
1994         result = iceland_populate_all_memory_levels(hwmgr);
1995         PP_ASSERT_WITH_CODE(0 == result,
1996                 "Failed to initialize Memory Level!", return result;);
1997
1998         result = iceland_populate_smc_acpi_level(hwmgr, table);
1999         PP_ASSERT_WITH_CODE(0 == result,
2000                 "Failed to initialize ACPI Level!", return result;);
2001
2002         result = iceland_populate_smc_vce_level(hwmgr, table);
2003         PP_ASSERT_WITH_CODE(0 == result,
2004                 "Failed to initialize VCE Level!", return result;);
2005
2006         result = iceland_populate_smc_acp_level(hwmgr, table);
2007         PP_ASSERT_WITH_CODE(0 == result,
2008                 "Failed to initialize ACP Level!", return result;);
2009
2010         result = iceland_populate_smc_samu_level(hwmgr, table);
2011         PP_ASSERT_WITH_CODE(0 == result,
2012                 "Failed to initialize SAMU Level!", return result;);
2013
2014         /* Since only the initial state is completely set up at this point (the other states are just copies of the boot state) we only */
2015         /* need to populate the  ARB settings for the initial state. */
2016         result = iceland_program_memory_timing_parameters(hwmgr);
2017         PP_ASSERT_WITH_CODE(0 == result,
2018                 "Failed to Write ARB settings for the initial state.", return result;);
2019
2020         result = iceland_populate_smc_uvd_level(hwmgr, table);
2021         PP_ASSERT_WITH_CODE(0 == result,
2022                 "Failed to initialize UVD Level!", return result;);
2023
2024         table->GraphicsBootLevel = 0;
2025         table->MemoryBootLevel = 0;
2026
2027         result = iceland_populate_smc_boot_level(hwmgr, table);
2028         PP_ASSERT_WITH_CODE(0 == result,
2029                 "Failed to initialize Boot Level!", return result;);
2030
2031         result = iceland_populate_smc_initial_state(hwmgr);
2032         PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Boot State!", return result);
2033
2034         result = iceland_populate_bapm_parameters_in_dpm_table(hwmgr);
2035         PP_ASSERT_WITH_CODE(0 == result, "Failed to populate BAPM Parameters!", return result);
2036
2037         table->GraphicsVoltageChangeEnable  = 1;
2038         table->GraphicsThermThrottleEnable  = 1;
2039         table->GraphicsInterval = 1;
2040         table->VoltageInterval  = 1;
2041         table->ThermalInterval  = 1;
2042
2043         table->TemperatureLimitHigh =
2044                 (data->thermal_temp_setting.temperature_high *
2045                  SMU7_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2046         table->TemperatureLimitLow =
2047                 (data->thermal_temp_setting.temperature_low *
2048                 SMU7_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2049
2050         table->MemoryVoltageChangeEnable  = 1;
2051         table->MemoryInterval  = 1;
2052         table->VoltageResponseTime  = 0;
2053         table->PhaseResponseTime  = 0;
2054         table->MemoryThermThrottleEnable  = 1;
2055         table->PCIeBootLinkLevel = 0;
2056         table->PCIeGenInterval = 1;
2057
2058         result = iceland_populate_smc_svi2_config(hwmgr, table);
2059         PP_ASSERT_WITH_CODE(0 == result,
2060                 "Failed to populate SVI2 setting!", return result);
2061
2062         table->ThermGpio  = 17;
2063         table->SclkStepSize = 0x4000;
2064
2065         CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2066         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcVid);
2067         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcPhase);
2068         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddciVid);
2069         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskMvddVid);
2070         CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2071         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2072         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2073         CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2074         CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2075
2076         table->BootVddc = PP_HOST_TO_SMC_US(table->BootVddc * VOLTAGE_SCALE);
2077         table->BootVddci = PP_HOST_TO_SMC_US(table->BootVddci * VOLTAGE_SCALE);
2078         table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE);
2079
2080         /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2081         result = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.dpm_table_start +
2082                                                                                 offsetof(SMU71_Discrete_DpmTable, SystemFlags),
2083                                                                                 (uint8_t *)&(table->SystemFlags),
2084                                                                                 sizeof(SMU71_Discrete_DpmTable)-3 * sizeof(SMU71_PIDController),
2085                                                                                 SMC_RAM_END);
2086
2087         PP_ASSERT_WITH_CODE(0 == result,
2088                 "Failed to upload dpm data to SMC memory!", return result;);
2089
2090         /* Upload all ulv setting to SMC memory.(dpm level, dpm level count etc) */
2091         result = smu7_copy_bytes_to_smc(hwmgr,
2092                         smu_data->smu7_data.ulv_setting_starts,
2093                         (uint8_t *)&(smu_data->ulv_setting),
2094                         sizeof(SMU71_Discrete_Ulv),
2095                         SMC_RAM_END);
2096
2097
2098         result = iceland_populate_initial_mc_reg_table(hwmgr);
2099         PP_ASSERT_WITH_CODE((0 == result),
2100                 "Failed to populate initialize MC Reg table!", return result);
2101
2102         result = iceland_populate_pm_fuses(hwmgr);
2103         PP_ASSERT_WITH_CODE(0 == result,
2104                         "Failed to  populate PM fuses to SMC memory!", return result);
2105
2106         return 0;
2107 }
2108
2109 int iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2110 {
2111         struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
2112         SMU71_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
2113         uint32_t duty100;
2114         uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
2115         uint16_t fdo_min, slope1, slope2;
2116         uint32_t reference_clock;
2117         int res;
2118         uint64_t tmp64;
2119
2120         if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl))
2121                 return 0;
2122
2123         if (hwmgr->thermal_controller.fanInfo.bNoFan) {
2124                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2125                         PHM_PlatformCaps_MicrocodeFanControl);
2126                 return 0;
2127         }
2128
2129         if (0 == smu7_data->fan_table_start) {
2130                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
2131                 return 0;
2132         }
2133
2134         duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL1, FMAX_DUTY100);
2135
2136         if (0 == duty100) {
2137                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
2138                 return 0;
2139         }
2140
2141         tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin * duty100;
2142         do_div(tmp64, 10000);
2143         fdo_min = (uint16_t)tmp64;
2144
2145         t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed - hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
2146         t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh - hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
2147
2148         pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
2149         pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
2150
2151         slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
2152         slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
2153
2154         fan_table.TempMin = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMin) / 100);
2155         fan_table.TempMed = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMed) / 100);
2156         fan_table.TempMax = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax) / 100);
2157
2158         fan_table.Slope1 = cpu_to_be16(slope1);
2159         fan_table.Slope2 = cpu_to_be16(slope2);
2160
2161         fan_table.FdoMin = cpu_to_be16(fdo_min);
2162
2163         fan_table.HystDown = cpu_to_be16(hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst);
2164
2165         fan_table.HystUp = cpu_to_be16(1);
2166
2167         fan_table.HystSlope = cpu_to_be16(1);
2168
2169         fan_table.TempRespLim = cpu_to_be16(5);
2170
2171         reference_clock = smu7_get_xclk(hwmgr);
2172
2173         fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay * reference_clock) / 1600);
2174
2175         fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
2176
2177         fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL);
2178
2179         /* fan_table.FanControl_GL_Flag = 1; */
2180
2181         res = smu7_copy_bytes_to_smc(hwmgr, smu7_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END);
2182
2183         return 0;
2184 }
2185
2186
2187 static int iceland_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2188 {
2189         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2190
2191         if (data->need_update_smu7_dpm_table &
2192                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
2193                 return iceland_program_memory_timing_parameters(hwmgr);
2194
2195         return 0;
2196 }
2197
2198 static int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2199 {
2200         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2201         struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
2202
2203         int result = 0;
2204         uint32_t low_sclk_interrupt_threshold = 0;
2205
2206         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2207                         PHM_PlatformCaps_SclkThrottleLowNotification)
2208                 && (hwmgr->gfx_arbiter.sclk_threshold !=
2209                                 data->low_sclk_interrupt_threshold)) {
2210                 data->low_sclk_interrupt_threshold =
2211                                 hwmgr->gfx_arbiter.sclk_threshold;
2212                 low_sclk_interrupt_threshold =
2213                                 data->low_sclk_interrupt_threshold;
2214
2215                 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
2216
2217                 result = smu7_copy_bytes_to_smc(
2218                                 hwmgr,
2219                                 smu_data->smu7_data.dpm_table_start +
2220                                 offsetof(SMU71_Discrete_DpmTable,
2221                                         LowSclkInterruptThreshold),
2222                                 (uint8_t *)&low_sclk_interrupt_threshold,
2223                                 sizeof(uint32_t),
2224                                 SMC_RAM_END);
2225         }
2226
2227         result = iceland_update_and_upload_mc_reg_table(hwmgr);
2228
2229         PP_ASSERT_WITH_CODE((0 == result), "Failed to upload MC reg table!", return result);
2230
2231         result = iceland_program_mem_timing_parameters(hwmgr);
2232         PP_ASSERT_WITH_CODE((result == 0),
2233                         "Failed to program memory timing parameters!",
2234                         );
2235
2236         return result;
2237 }
2238
2239 static uint32_t iceland_get_offsetof(uint32_t type, uint32_t member)
2240 {
2241         switch (type) {
2242         case SMU_SoftRegisters:
2243                 switch (member) {
2244                 case HandshakeDisables:
2245                         return offsetof(SMU71_SoftRegisters, HandshakeDisables);
2246                 case VoltageChangeTimeout:
2247                         return offsetof(SMU71_SoftRegisters, VoltageChangeTimeout);
2248                 case AverageGraphicsActivity:
2249                         return offsetof(SMU71_SoftRegisters, AverageGraphicsActivity);
2250                 case PreVBlankGap:
2251                         return offsetof(SMU71_SoftRegisters, PreVBlankGap);
2252                 case VBlankTimeout:
2253                         return offsetof(SMU71_SoftRegisters, VBlankTimeout);
2254                 case UcodeLoadStatus:
2255                         return offsetof(SMU71_SoftRegisters, UcodeLoadStatus);
2256                 case DRAM_LOG_ADDR_H:
2257                         return offsetof(SMU71_SoftRegisters, DRAM_LOG_ADDR_H);
2258                 case DRAM_LOG_ADDR_L:
2259                         return offsetof(SMU71_SoftRegisters, DRAM_LOG_ADDR_L);
2260                 case DRAM_LOG_PHY_ADDR_H:
2261                         return offsetof(SMU71_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
2262                 case DRAM_LOG_PHY_ADDR_L:
2263                         return offsetof(SMU71_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
2264                 case DRAM_LOG_BUFF_SIZE:
2265                         return offsetof(SMU71_SoftRegisters, DRAM_LOG_BUFF_SIZE);
2266                 }
2267         case SMU_Discrete_DpmTable:
2268                 switch (member) {
2269                 case LowSclkInterruptThreshold:
2270                         return offsetof(SMU71_Discrete_DpmTable, LowSclkInterruptThreshold);
2271                 }
2272         }
2273         pr_warn("can't get the offset of type %x member %x\n", type, member);
2274         return 0;
2275 }
2276
2277 static uint32_t iceland_get_mac_definition(uint32_t value)
2278 {
2279         switch (value) {
2280         case SMU_MAX_LEVELS_GRAPHICS:
2281                 return SMU71_MAX_LEVELS_GRAPHICS;
2282         case SMU_MAX_LEVELS_MEMORY:
2283                 return SMU71_MAX_LEVELS_MEMORY;
2284         case SMU_MAX_LEVELS_LINK:
2285                 return SMU71_MAX_LEVELS_LINK;
2286         case SMU_MAX_ENTRIES_SMIO:
2287                 return SMU71_MAX_ENTRIES_SMIO;
2288         case SMU_MAX_LEVELS_VDDC:
2289                 return SMU71_MAX_LEVELS_VDDC;
2290         case SMU_MAX_LEVELS_VDDCI:
2291                 return SMU71_MAX_LEVELS_VDDCI;
2292         case SMU_MAX_LEVELS_MVDD:
2293                 return SMU71_MAX_LEVELS_MVDD;
2294         }
2295
2296         pr_warn("can't get the mac of %x\n", value);
2297         return 0;
2298 }
2299
2300 static int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
2301 {
2302         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2303         struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
2304
2305         uint32_t tmp;
2306         int result;
2307         bool error = false;
2308
2309         result = smu7_read_smc_sram_dword(hwmgr,
2310                                 SMU71_FIRMWARE_HEADER_LOCATION +
2311                                 offsetof(SMU71_Firmware_Header, DpmTable),
2312                                 &tmp, SMC_RAM_END);
2313
2314         if (0 == result) {
2315                 smu7_data->dpm_table_start = tmp;
2316         }
2317
2318         error |= (0 != result);
2319
2320         result = smu7_read_smc_sram_dword(hwmgr,
2321                                 SMU71_FIRMWARE_HEADER_LOCATION +
2322                                 offsetof(SMU71_Firmware_Header, SoftRegisters),
2323                                 &tmp, SMC_RAM_END);
2324
2325         if (0 == result) {
2326                 data->soft_regs_start = tmp;
2327                 smu7_data->soft_regs_start = tmp;
2328         }
2329
2330         error |= (0 != result);
2331
2332
2333         result = smu7_read_smc_sram_dword(hwmgr,
2334                                 SMU71_FIRMWARE_HEADER_LOCATION +
2335                                 offsetof(SMU71_Firmware_Header, mcRegisterTable),
2336                                 &tmp, SMC_RAM_END);
2337
2338         if (0 == result) {
2339                 smu7_data->mc_reg_table_start = tmp;
2340         }
2341
2342         result = smu7_read_smc_sram_dword(hwmgr,
2343                                 SMU71_FIRMWARE_HEADER_LOCATION +
2344                                 offsetof(SMU71_Firmware_Header, FanTable),
2345                                 &tmp, SMC_RAM_END);
2346
2347         if (0 == result) {
2348                 smu7_data->fan_table_start = tmp;
2349         }
2350
2351         error |= (0 != result);
2352
2353         result = smu7_read_smc_sram_dword(hwmgr,
2354                                 SMU71_FIRMWARE_HEADER_LOCATION +
2355                                 offsetof(SMU71_Firmware_Header, mcArbDramTimingTable),
2356                                 &tmp, SMC_RAM_END);
2357
2358         if (0 == result) {
2359                 smu7_data->arb_table_start = tmp;
2360         }
2361
2362         error |= (0 != result);
2363
2364
2365         result = smu7_read_smc_sram_dword(hwmgr,
2366                                 SMU71_FIRMWARE_HEADER_LOCATION +
2367                                 offsetof(SMU71_Firmware_Header, Version),
2368                                 &tmp, SMC_RAM_END);
2369
2370         if (0 == result) {
2371                 hwmgr->microcode_version_info.SMC = tmp;
2372         }
2373
2374         error |= (0 != result);
2375
2376         result = smu7_read_smc_sram_dword(hwmgr,
2377                                 SMU71_FIRMWARE_HEADER_LOCATION +
2378                                 offsetof(SMU71_Firmware_Header, UlvSettings),
2379                                 &tmp, SMC_RAM_END);
2380
2381         if (0 == result) {
2382                 smu7_data->ulv_setting_starts = tmp;
2383         }
2384
2385         error |= (0 != result);
2386
2387         return error ? 1 : 0;
2388 }
2389
2390 /*---------------------------MC----------------------------*/
2391
2392 static uint8_t iceland_get_memory_modile_index(struct pp_hwmgr *hwmgr)
2393 {
2394         return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
2395 }
2396
2397 static bool iceland_check_s0_mc_reg_index(uint16_t in_reg, uint16_t *out_reg)
2398 {
2399         bool result = true;
2400
2401         switch (in_reg) {
2402         case  mmMC_SEQ_RAS_TIMING:
2403                 *out_reg = mmMC_SEQ_RAS_TIMING_LP;
2404                 break;
2405
2406         case  mmMC_SEQ_DLL_STBY:
2407                 *out_reg = mmMC_SEQ_DLL_STBY_LP;
2408                 break;
2409
2410         case  mmMC_SEQ_G5PDX_CMD0:
2411                 *out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
2412                 break;
2413
2414         case  mmMC_SEQ_G5PDX_CMD1:
2415                 *out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
2416                 break;
2417
2418         case  mmMC_SEQ_G5PDX_CTRL:
2419                 *out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
2420                 break;
2421
2422         case mmMC_SEQ_CAS_TIMING:
2423                 *out_reg = mmMC_SEQ_CAS_TIMING_LP;
2424                 break;
2425
2426         case mmMC_SEQ_MISC_TIMING:
2427                 *out_reg = mmMC_SEQ_MISC_TIMING_LP;
2428                 break;
2429
2430         case mmMC_SEQ_MISC_TIMING2:
2431                 *out_reg = mmMC_SEQ_MISC_TIMING2_LP;
2432                 break;
2433
2434         case mmMC_SEQ_PMG_DVS_CMD:
2435                 *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
2436                 break;
2437
2438         case mmMC_SEQ_PMG_DVS_CTL:
2439                 *out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
2440                 break;
2441
2442         case mmMC_SEQ_RD_CTL_D0:
2443                 *out_reg = mmMC_SEQ_RD_CTL_D0_LP;
2444                 break;
2445
2446         case mmMC_SEQ_RD_CTL_D1:
2447                 *out_reg = mmMC_SEQ_RD_CTL_D1_LP;
2448                 break;
2449
2450         case mmMC_SEQ_WR_CTL_D0:
2451                 *out_reg = mmMC_SEQ_WR_CTL_D0_LP;
2452                 break;
2453
2454         case mmMC_SEQ_WR_CTL_D1:
2455                 *out_reg = mmMC_SEQ_WR_CTL_D1_LP;
2456                 break;
2457
2458         case mmMC_PMG_CMD_EMRS:
2459                 *out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
2460                 break;
2461
2462         case mmMC_PMG_CMD_MRS:
2463                 *out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
2464                 break;
2465
2466         case mmMC_PMG_CMD_MRS1:
2467                 *out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
2468                 break;
2469
2470         case mmMC_SEQ_PMG_TIMING:
2471                 *out_reg = mmMC_SEQ_PMG_TIMING_LP;
2472                 break;
2473
2474         case mmMC_PMG_CMD_MRS2:
2475                 *out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
2476                 break;
2477
2478         case mmMC_SEQ_WR_CTL_2:
2479                 *out_reg = mmMC_SEQ_WR_CTL_2_LP;
2480                 break;
2481
2482         default:
2483                 result = false;
2484                 break;
2485         }
2486
2487         return result;
2488 }
2489
2490 static int iceland_set_s0_mc_reg_index(struct iceland_mc_reg_table *table)
2491 {
2492         uint32_t i;
2493         uint16_t address;
2494
2495         for (i = 0; i < table->last; i++) {
2496                 table->mc_reg_address[i].s0 =
2497                         iceland_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)
2498                         ? address : table->mc_reg_address[i].s1;
2499         }
2500         return 0;
2501 }
2502
2503 static int iceland_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table,
2504                                         struct iceland_mc_reg_table *ni_table)
2505 {
2506         uint8_t i, j;
2507
2508         PP_ASSERT_WITH_CODE((table->last <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2509                 "Invalid VramInfo table.", return -EINVAL);
2510         PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
2511                 "Invalid VramInfo table.", return -EINVAL);
2512
2513         for (i = 0; i < table->last; i++) {
2514                 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
2515         }
2516         ni_table->last = table->last;
2517
2518         for (i = 0; i < table->num_entries; i++) {
2519                 ni_table->mc_reg_table_entry[i].mclk_max =
2520                         table->mc_reg_table_entry[i].mclk_max;
2521                 for (j = 0; j < table->last; j++) {
2522                         ni_table->mc_reg_table_entry[i].mc_data[j] =
2523                                 table->mc_reg_table_entry[i].mc_data[j];
2524                 }
2525         }
2526
2527         ni_table->num_entries = table->num_entries;
2528
2529         return 0;
2530 }
2531
2532 static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr,
2533                                         struct iceland_mc_reg_table *table)
2534 {
2535         uint8_t i, j, k;
2536         uint32_t temp_reg;
2537         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2538
2539         for (i = 0, j = table->last; i < table->last; i++) {
2540                 PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2541                         "Invalid VramInfo table.", return -EINVAL);
2542
2543                 switch (table->mc_reg_address[i].s1) {
2544
2545                 case mmMC_SEQ_MISC1:
2546                         temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS);
2547                         table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
2548                         table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
2549                         for (k = 0; k < table->num_entries; k++) {
2550                                 table->mc_reg_table_entry[k].mc_data[j] =
2551                                         ((temp_reg & 0xffff0000)) |
2552                                         ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
2553                         }
2554                         j++;
2555                         PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2556                                 "Invalid VramInfo table.", return -EINVAL);
2557
2558                         temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
2559                         table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
2560                         table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
2561                         for (k = 0; k < table->num_entries; k++) {
2562                                 table->mc_reg_table_entry[k].mc_data[j] =
2563                                         (temp_reg & 0xffff0000) |
2564                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
2565
2566                                 if (!data->is_memory_gddr5) {
2567                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
2568                                 }
2569                         }
2570                         j++;
2571                         PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2572                                 "Invalid VramInfo table.", return -EINVAL);
2573
2574                         if (!data->is_memory_gddr5 && j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE) {
2575                                 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
2576                                 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
2577                                 for (k = 0; k < table->num_entries; k++) {
2578                                         table->mc_reg_table_entry[k].mc_data[j] =
2579                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
2580                                 }
2581                                 j++;
2582                                 PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2583                                         "Invalid VramInfo table.", return -EINVAL);
2584                         }
2585
2586                         break;
2587
2588                 case mmMC_SEQ_RESERVE_M:
2589                         temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
2590                         table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
2591                         table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
2592                         for (k = 0; k < table->num_entries; k++) {
2593                                 table->mc_reg_table_entry[k].mc_data[j] =
2594                                         (temp_reg & 0xffff0000) |
2595                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
2596                         }
2597                         j++;
2598                         PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2599                                 "Invalid VramInfo table.", return -EINVAL);
2600                         break;
2601
2602                 default:
2603                         break;
2604                 }
2605
2606         }
2607
2608         table->last = j;
2609
2610         return 0;
2611 }
2612
2613 static int iceland_set_valid_flag(struct iceland_mc_reg_table *table)
2614 {
2615         uint8_t i, j;
2616         for (i = 0; i < table->last; i++) {
2617                 for (j = 1; j < table->num_entries; j++) {
2618                         if (table->mc_reg_table_entry[j-1].mc_data[i] !=
2619                                 table->mc_reg_table_entry[j].mc_data[i]) {
2620                                 table->validflag |= (1<<i);
2621                                 break;
2622                         }
2623                 }
2624         }
2625
2626         return 0;
2627 }
2628
2629 static int iceland_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
2630 {
2631         int result;
2632         struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
2633         pp_atomctrl_mc_reg_table *table;
2634         struct iceland_mc_reg_table *ni_table = &smu_data->mc_reg_table;
2635         uint8_t module_index = iceland_get_memory_modile_index(hwmgr);
2636
2637         table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
2638
2639         if (NULL == table)
2640                 return -ENOMEM;
2641
2642         /* Program additional LP registers that are no longer programmed by VBIOS */
2643         cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
2644         cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
2645         cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
2646         cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
2647         cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
2648         cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
2649         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
2650         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
2651         cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
2652         cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
2653         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
2654         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
2655         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
2656         cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
2657         cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
2658         cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
2659         cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
2660         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
2661         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
2662         cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
2663
2664         memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
2665
2666         result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
2667
2668         if (0 == result)
2669                 result = iceland_copy_vbios_smc_reg_table(table, ni_table);
2670
2671         if (0 == result) {
2672                 iceland_set_s0_mc_reg_index(ni_table);
2673                 result = iceland_set_mc_special_registers(hwmgr, ni_table);
2674         }
2675
2676         if (0 == result)
2677                 iceland_set_valid_flag(ni_table);
2678
2679         kfree(table);
2680
2681         return result;
2682 }
2683
2684 static bool iceland_is_dpm_running(struct pp_hwmgr *hwmgr)
2685 {
2686         return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
2687                         CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
2688                         ? true : false;
2689 }
2690
2691 const struct pp_smumgr_func iceland_smu_funcs = {
2692         .smu_init = &iceland_smu_init,
2693         .smu_fini = &smu7_smu_fini,
2694         .start_smu = &iceland_start_smu,
2695         .check_fw_load_finish = &smu7_check_fw_load_finish,
2696         .request_smu_load_fw = &smu7_reload_firmware,
2697         .request_smu_load_specific_fw = &iceland_request_smu_load_specific_fw,
2698         .send_msg_to_smc = &smu7_send_msg_to_smc,
2699         .send_msg_to_smc_with_parameter = &smu7_send_msg_to_smc_with_parameter,
2700         .download_pptable_settings = NULL,
2701         .upload_pptable_settings = NULL,
2702         .get_offsetof = iceland_get_offsetof,
2703         .process_firmware_header = iceland_process_firmware_header,
2704         .init_smc_table = iceland_init_smc_table,
2705         .update_sclk_threshold = iceland_update_sclk_threshold,
2706         .thermal_setup_fan_table = iceland_thermal_setup_fan_table,
2707         .populate_all_graphic_levels = iceland_populate_all_graphic_levels,
2708         .populate_all_memory_levels = iceland_populate_all_memory_levels,
2709         .get_mac_definition = iceland_get_mac_definition,
2710         .initialize_mc_reg_table = iceland_initialize_mc_reg_table,
2711         .is_dpm_running = iceland_is_dpm_running,
2712 };
2713