2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/firmware.h>
27 #include "amdgpu_smu.h"
28 #include "atomfirmware.h"
29 #include "amdgpu_atomfirmware.h"
30 #include "smu_v11_0.h"
31 #include "smu11_driver_if_navi10.h"
32 #include "soc15_common.h"
34 #include "navi10_ppt.h"
35 #include "smu_v11_0_pptable.h"
36 #include "smu_v11_0_ppsmc.h"
38 #include "asic_reg/mp/mp_11_0_sh_mask.h"
40 #define FEATURE_MASK(feature) (1ULL << feature)
41 #define SMC_DPM_FEATURE ( \
42 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
43 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
44 FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT) | \
45 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
46 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
47 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | \
48 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
49 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
51 #define MSG_MAP(msg, index) \
52 [SMU_MSG_##msg] = index
54 static int navi10_message_map[SMU_MSG_MAX_COUNT] = {
55 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage),
56 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion),
57 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion),
58 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow),
59 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh),
60 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures),
61 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures),
62 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow),
63 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh),
64 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow),
65 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh),
66 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow),
67 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh),
68 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask),
69 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit),
70 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh),
71 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow),
72 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh),
73 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow),
74 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram),
75 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu),
76 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable),
77 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable),
78 MSG_MAP(RunBtc, PPSMC_MSG_RunBtc),
79 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco),
80 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq),
81 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq),
82 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq),
83 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq),
84 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq),
85 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq),
86 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex),
87 MSG_MAP(SetMemoryChannelConfig, PPSMC_MSG_SetMemoryChannelConfig),
88 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode),
89 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh),
90 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow),
91 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters),
92 MSG_MAP(SetMinDeepSleepDcefclk, PPSMC_MSG_SetMinDeepSleepDcefclk),
93 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt),
94 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource),
95 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch),
96 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps),
97 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload),
98 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh),
99 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow),
100 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize),
101 MSG_MAP(ConfigureGfxDidt, PPSMC_MSG_ConfigureGfxDidt),
102 MSG_MAP(NumOfDisplays, PPSMC_MSG_NumOfDisplays),
103 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh),
104 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow),
105 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff),
106 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff),
107 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit),
108 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq),
109 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData),
110 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco),
111 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset),
112 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown),
113 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn),
114 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn),
115 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg),
116 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg),
117 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME),
118 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3),
121 static int navi10_clk_map[SMU_CLK_COUNT] = {
122 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
123 CLK_MAP(SCLK, PPCLK_GFXCLK),
124 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
125 CLK_MAP(FCLK, PPCLK_SOCCLK),
126 CLK_MAP(UCLK, PPCLK_UCLK),
127 CLK_MAP(MCLK, PPCLK_UCLK),
128 CLK_MAP(DCLK, PPCLK_DCLK),
129 CLK_MAP(VCLK, PPCLK_VCLK),
130 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
131 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
132 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
133 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
136 static int navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
137 FEA_MAP(DPM_PREFETCHER),
139 FEA_MAP(DPM_GFX_PACE),
144 FEA_MAP(DPM_DCEFCLK),
145 FEA_MAP(MEM_VDDCI_SCALING),
146 FEA_MAP(MEM_MVDD_SCALING),
159 FEA_MAP(RSMU_SMN_CG),
169 FEA_MAP(FAN_CONTROL),
173 FEA_MAP(LED_DISPLAY),
175 FEA_MAP(OUT_OF_BAND_MONITOR),
176 FEA_MAP(TEMP_DEPENDENT_VMIN),
181 static int navi10_table_map[SMU_TABLE_COUNT] = {
185 TAB_MAP(AVFS_PSM_DEBUG),
186 TAB_MAP(AVFS_FUSE_OVERRIDE),
187 TAB_MAP(PMSTATUSLOG),
188 TAB_MAP(SMU_METRICS),
189 TAB_MAP(DRIVER_SMU_CONFIG),
190 TAB_MAP(ACTIVITY_MONITOR_COEFF),
192 TAB_MAP(I2C_COMMANDS),
196 static int navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
201 static int navi10_workload_map[] = {
202 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
203 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
204 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
205 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
206 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
207 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT),
208 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
211 static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
214 if (index > SMU_MSG_MAX_COUNT)
217 val = navi10_message_map[index];
218 if (val > PPSMC_Message_Count)
224 static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index)
227 if (index >= SMU_CLK_COUNT)
230 val = navi10_clk_map[index];
231 if (val >= PPCLK_COUNT)
237 static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index)
240 if (index >= SMU_FEATURE_COUNT)
243 val = navi10_feature_mask_map[index];
250 static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index)
253 if (index >= SMU_TABLE_COUNT)
256 val = navi10_table_map[index];
257 if (val >= TABLE_COUNT)
263 static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)
266 if (index >= SMU_POWER_SOURCE_COUNT)
269 val = navi10_pwr_src_map[index];
270 if (val >= POWER_SOURCE_COUNT)
277 static int navi10_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
280 if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
283 val = navi10_workload_map[profile];
288 static bool is_asic_secure(struct smu_context *smu)
290 struct amdgpu_device *adev = smu->adev;
291 bool is_secure = true;
292 uint32_t mp0_fw_intf;
294 mp0_fw_intf = RREG32_PCIE(MP0_Public |
295 (smnMP0_FW_INTF & 0xffffffff));
297 if (!(mp0_fw_intf & (1 << 19)))
304 navi10_get_allowed_feature_mask(struct smu_context *smu,
305 uint32_t *feature_mask, uint32_t num)
307 struct amdgpu_device *adev = smu->adev;
312 memset(feature_mask, 0, sizeof(uint32_t) * num);
314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
315 | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)
316 | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
317 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
318 | FEATURE_MASK(FEATURE_DPM_LINK_BIT)
319 | FEATURE_MASK(FEATURE_GFX_ULV_BIT)
320 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
321 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
322 | FEATURE_MASK(FEATURE_PPT_BIT)
323 | FEATURE_MASK(FEATURE_TDC_BIT)
324 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
325 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
326 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
327 | FEATURE_MASK(FEATURE_THERMAL_BIT)
328 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
329 | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)
330 | FEATURE_MASK(FEATURE_DS_GFXCLK_BIT)
331 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
332 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
333 | FEATURE_MASK(FEATURE_BACO_BIT)
334 | FEATURE_MASK(FEATURE_ACDC_BIT)
335 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
336 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
337 | FEATURE_MASK(FEATURE_FW_CTF_BIT);
339 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
340 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
341 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
342 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
344 if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
345 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
346 /* TODO: remove it once fw fix the bug */
347 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
350 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
351 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
353 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
354 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
356 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
357 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
359 /* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
360 if (is_asic_secure(smu)) {
361 /* only for navi10 A0 */
362 if ((adev->asic_type == CHIP_NAVI10) &&
363 (adev->rev_id == 0)) {
364 *(uint64_t *)feature_mask &=
365 ~(FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
366 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
367 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT));
368 *(uint64_t *)feature_mask &=
369 ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
376 static int navi10_check_powerplay_table(struct smu_context *smu)
381 static int navi10_append_powerplay_table(struct smu_context *smu)
383 struct amdgpu_device *adev = smu->adev;
384 struct smu_table_context *table_context = &smu->smu_table;
385 PPTable_t *smc_pptable = table_context->driver_pptable;
386 struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
389 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
392 ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
393 (uint8_t **)&smc_dpm_table);
397 memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
398 sizeof(I2cControllerConfig_t) * NUM_I2C_CONTROLLERS);
400 /* SVI2 Board Parameters */
401 smc_pptable->MaxVoltageStepGfx = smc_dpm_table->MaxVoltageStepGfx;
402 smc_pptable->MaxVoltageStepSoc = smc_dpm_table->MaxVoltageStepSoc;
403 smc_pptable->VddGfxVrMapping = smc_dpm_table->VddGfxVrMapping;
404 smc_pptable->VddSocVrMapping = smc_dpm_table->VddSocVrMapping;
405 smc_pptable->VddMem0VrMapping = smc_dpm_table->VddMem0VrMapping;
406 smc_pptable->VddMem1VrMapping = smc_dpm_table->VddMem1VrMapping;
407 smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->GfxUlvPhaseSheddingMask;
408 smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->SocUlvPhaseSheddingMask;
409 smc_pptable->ExternalSensorPresent = smc_dpm_table->ExternalSensorPresent;
410 smc_pptable->Padding8_V = smc_dpm_table->Padding8_V;
412 /* Telemetry Settings */
413 smc_pptable->GfxMaxCurrent = smc_dpm_table->GfxMaxCurrent;
414 smc_pptable->GfxOffset = smc_dpm_table->GfxOffset;
415 smc_pptable->Padding_TelemetryGfx = smc_dpm_table->Padding_TelemetryGfx;
416 smc_pptable->SocMaxCurrent = smc_dpm_table->SocMaxCurrent;
417 smc_pptable->SocOffset = smc_dpm_table->SocOffset;
418 smc_pptable->Padding_TelemetrySoc = smc_dpm_table->Padding_TelemetrySoc;
419 smc_pptable->Mem0MaxCurrent = smc_dpm_table->Mem0MaxCurrent;
420 smc_pptable->Mem0Offset = smc_dpm_table->Mem0Offset;
421 smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->Padding_TelemetryMem0;
422 smc_pptable->Mem1MaxCurrent = smc_dpm_table->Mem1MaxCurrent;
423 smc_pptable->Mem1Offset = smc_dpm_table->Mem1Offset;
424 smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->Padding_TelemetryMem1;
427 smc_pptable->AcDcGpio = smc_dpm_table->AcDcGpio;
428 smc_pptable->AcDcPolarity = smc_dpm_table->AcDcPolarity;
429 smc_pptable->VR0HotGpio = smc_dpm_table->VR0HotGpio;
430 smc_pptable->VR0HotPolarity = smc_dpm_table->VR0HotPolarity;
431 smc_pptable->VR1HotGpio = smc_dpm_table->VR1HotGpio;
432 smc_pptable->VR1HotPolarity = smc_dpm_table->VR1HotPolarity;
433 smc_pptable->GthrGpio = smc_dpm_table->GthrGpio;
434 smc_pptable->GthrPolarity = smc_dpm_table->GthrPolarity;
436 /* LED Display Settings */
437 smc_pptable->LedPin0 = smc_dpm_table->LedPin0;
438 smc_pptable->LedPin1 = smc_dpm_table->LedPin1;
439 smc_pptable->LedPin2 = smc_dpm_table->LedPin2;
440 smc_pptable->padding8_4 = smc_dpm_table->padding8_4;
442 /* GFXCLK PLL Spread Spectrum */
443 smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->PllGfxclkSpreadEnabled;
444 smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->PllGfxclkSpreadPercent;
445 smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->PllGfxclkSpreadFreq;
447 /* GFXCLK DFLL Spread Spectrum */
448 smc_pptable->DfllGfxclkSpreadEnabled = smc_dpm_table->DfllGfxclkSpreadEnabled;
449 smc_pptable->DfllGfxclkSpreadPercent = smc_dpm_table->DfllGfxclkSpreadPercent;
450 smc_pptable->DfllGfxclkSpreadFreq = smc_dpm_table->DfllGfxclkSpreadFreq;
452 /* UCLK Spread Spectrum */
453 smc_pptable->UclkSpreadEnabled = smc_dpm_table->UclkSpreadEnabled;
454 smc_pptable->UclkSpreadPercent = smc_dpm_table->UclkSpreadPercent;
455 smc_pptable->UclkSpreadFreq = smc_dpm_table->UclkSpreadFreq;
457 /* SOCCLK Spread Spectrum */
458 smc_pptable->SoclkSpreadEnabled = smc_dpm_table->SoclkSpreadEnabled;
459 smc_pptable->SocclkSpreadPercent = smc_dpm_table->SocclkSpreadPercent;
460 smc_pptable->SocclkSpreadFreq = smc_dpm_table->SocclkSpreadFreq;
462 /* Total board power */
463 smc_pptable->TotalBoardPower = smc_dpm_table->TotalBoardPower;
464 smc_pptable->BoardPadding = smc_dpm_table->BoardPadding;
466 /* Mvdd Svi2 Div Ratio Setting */
467 smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
469 if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
470 /* TODO: remove it once SMU fw fix it */
471 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
477 static int navi10_store_powerplay_table(struct smu_context *smu)
479 struct smu_11_0_powerplay_table *powerplay_table = NULL;
480 struct smu_table_context *table_context = &smu->smu_table;
481 struct smu_baco_context *smu_baco = &smu->smu_baco;
483 if (!table_context->power_play_table)
486 powerplay_table = table_context->power_play_table;
488 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
491 table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
493 mutex_lock(&smu_baco->mutex);
494 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
495 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
496 smu_baco->platform_support = true;
497 mutex_unlock(&smu_baco->mutex);
502 static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
504 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
505 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
506 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
507 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
508 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
509 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
510 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
511 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
512 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
513 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
514 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
515 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
516 AMDGPU_GEM_DOMAIN_VRAM);
521 static int navi10_allocate_dpm_context(struct smu_context *smu)
523 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
525 if (smu_dpm->dpm_context)
528 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
530 if (!smu_dpm->dpm_context)
533 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
538 static int navi10_set_default_dpm_table(struct smu_context *smu)
540 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
541 struct smu_table_context *table_context = &smu->smu_table;
542 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
543 PPTable_t *driver_ppt = NULL;
545 driver_ppt = table_context->driver_pptable;
547 dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
548 dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
550 dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
551 dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
553 dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
554 dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
556 dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
557 dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
559 dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
560 dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
562 dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
563 dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
565 dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
566 dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
568 dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
569 dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
571 dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
572 dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
577 static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
580 struct smu_power_context *smu_power = &smu->smu_power;
581 struct smu_power_gate *power_gate = &smu_power->power_gate;
583 if (enable && power_gate->uvd_gated) {
584 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
585 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
589 power_gate->uvd_gated = false;
591 if (!enable && !power_gate->uvd_gated) {
592 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
593 ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
597 power_gate->uvd_gated = true;
604 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
605 enum smu_clk_type clk_type,
608 static SmuMetrics_t metrics;
609 int ret = 0, clk_id = 0;
614 memset(&metrics, 0, sizeof(metrics));
616 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false);
620 clk_id = smu_clk_get_index(smu, clk_type);
624 *value = metrics.CurrClock[clk_id];
629 static int navi10_print_clk_levels(struct smu_context *smu,
630 enum smu_clk_type clk_type, char *buf)
632 int i, size = 0, ret = 0;
633 uint32_t cur_value = 0, value = 0, count = 0;
643 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
647 cur_value = cur_value / 100;
649 size += sprintf(buf, "current clk: %uMhz\n", cur_value);
651 ret = smu_get_dpm_level_count(smu, clk_type, &count);
655 for (i = 0; i < count; i++) {
656 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
660 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
661 cur_value == value ? "*" : "");
671 static int navi10_force_clk_levels(struct smu_context *smu,
672 enum smu_clk_type clk_type, uint32_t mask)
675 int ret = 0, size = 0;
676 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
678 soft_min_level = mask ? (ffs(mask) - 1) : 0;
679 soft_max_level = mask ? (fls(mask) - 1) : 0;
689 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
693 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
697 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
708 static int navi10_populate_umd_state_clk(struct smu_context *smu)
711 uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
713 ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL);
717 smu->pstate_sclk = min_sclk_freq * 100;
719 ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL);
723 smu->pstate_mclk = min_mclk_freq * 100;
728 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
729 enum smu_clk_type clk_type,
730 struct pp_clock_levels_with_latency *clocks)
733 uint32_t level_count = 0, freq = 0;
739 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
743 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
744 clocks->num_levels = level_count;
746 for (i = 0; i < level_count; i++) {
747 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
751 clocks->data[i].clocks_in_khz = freq * 1000;
752 clocks->data[i].latency_in_us = 0;
762 static int navi10_pre_display_config_changed(struct smu_context *smu)
765 uint32_t max_freq = 0;
767 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
771 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
772 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq);
775 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
783 static int navi10_display_config_changed(struct smu_context *smu)
787 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
788 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
789 ret = smu_write_watermarks_table(smu);
793 smu->watermarks_bitmap |= WATERMARKS_LOADED;
796 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
797 smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
798 smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
799 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
800 smu->display_config->num_display);
808 static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
811 uint32_t min_freq, max_freq, force_freq;
812 enum smu_clk_type clk_type;
814 enum smu_clk_type clks[] = {
820 for (i = 0; i < ARRAY_SIZE(clks); i++) {
822 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
826 force_freq = highest ? max_freq : min_freq;
827 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq);
835 static int navi10_unforce_dpm_levels(struct smu_context *smu)
838 uint32_t min_freq, max_freq;
839 enum smu_clk_type clk_type;
841 enum smu_clk_type clks[] = {
847 for (i = 0; i < ARRAY_SIZE(clks); i++) {
849 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
853 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
861 static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
864 SmuMetrics_t metrics;
869 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics,
874 *value = metrics.AverageSocketPower << 8;
879 static int navi10_get_current_activity_percent(struct smu_context *smu,
880 enum amd_pp_sensors sensor,
884 SmuMetrics_t metrics;
891 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
892 (void *)&metrics, false);
897 case AMDGPU_PP_SENSOR_GPU_LOAD:
898 *value = metrics.AverageGfxActivity;
900 case AMDGPU_PP_SENSOR_MEM_LOAD:
901 *value = metrics.AverageUclkActivity;
904 pr_err("Invalid sensor for retrieving clock activity\n");
911 static bool navi10_is_dpm_running(struct smu_context *smu)
914 uint32_t feature_mask[2];
915 unsigned long feature_enabled;
916 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
917 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
918 ((uint64_t)feature_mask[1] << 32));
919 return !!(feature_enabled & SMC_DPM_FEATURE);
922 static int navi10_get_fan_speed(struct smu_context *smu, uint16_t *value)
924 SmuMetrics_t metrics;
930 memset(&metrics, 0, sizeof(metrics));
932 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
933 (void *)&metrics, false);
937 *value = metrics.CurrFanSpeed;
942 static int navi10_get_fan_speed_percent(struct smu_context *smu,
946 uint32_t percent = 0;
947 uint16_t current_rpm;
948 PPTable_t *pptable = smu->smu_table.driver_pptable;
950 ret = navi10_get_fan_speed(smu, ¤t_rpm);
954 percent = current_rpm * 100 / pptable->FanMaximumRpm;
955 *speed = percent > 100 ? 100 : percent;
960 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
962 DpmActivityMonitorCoeffInt_t activity_monitor;
963 uint32_t i, size = 0;
964 uint16_t workload_type = 0;
965 static const char *profile_name[] = {
973 static const char *title[] = {
974 "PROFILE_INDEX(NAME)",
983 "PD_Data_error_coeff",
984 "PD_Data_error_rate_coeff"};
990 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
991 title[0], title[1], title[2], title[3], title[4], title[5],
992 title[6], title[7], title[8], title[9], title[10]);
994 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
995 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
996 workload_type = smu_workload_get_type(smu, i);
997 result = smu_update_table(smu,
998 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
999 (void *)(&activity_monitor), false);
1001 pr_err("[%s] Failed to get activity monitor!", __func__);
1005 size += sprintf(buf + size, "%2d %14s%s:\n",
1006 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1008 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1012 activity_monitor.Gfx_FPS,
1013 activity_monitor.Gfx_MinFreqStep,
1014 activity_monitor.Gfx_MinActiveFreqType,
1015 activity_monitor.Gfx_MinActiveFreq,
1016 activity_monitor.Gfx_BoosterFreqType,
1017 activity_monitor.Gfx_BoosterFreq,
1018 activity_monitor.Gfx_PD_Data_limit_c,
1019 activity_monitor.Gfx_PD_Data_error_coeff,
1020 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1022 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1026 activity_monitor.Soc_FPS,
1027 activity_monitor.Soc_MinFreqStep,
1028 activity_monitor.Soc_MinActiveFreqType,
1029 activity_monitor.Soc_MinActiveFreq,
1030 activity_monitor.Soc_BoosterFreqType,
1031 activity_monitor.Soc_BoosterFreq,
1032 activity_monitor.Soc_PD_Data_limit_c,
1033 activity_monitor.Soc_PD_Data_error_coeff,
1034 activity_monitor.Soc_PD_Data_error_rate_coeff);
1036 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1040 activity_monitor.Mem_FPS,
1041 activity_monitor.Mem_MinFreqStep,
1042 activity_monitor.Mem_MinActiveFreqType,
1043 activity_monitor.Mem_MinActiveFreq,
1044 activity_monitor.Mem_BoosterFreqType,
1045 activity_monitor.Mem_BoosterFreq,
1046 activity_monitor.Mem_PD_Data_limit_c,
1047 activity_monitor.Mem_PD_Data_error_coeff,
1048 activity_monitor.Mem_PD_Data_error_rate_coeff);
1054 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1056 DpmActivityMonitorCoeffInt_t activity_monitor;
1057 int workload_type, ret = 0;
1059 smu->power_profile_mode = input[size];
1061 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1062 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1066 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1070 ret = smu_update_table(smu,
1071 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1072 (void *)(&activity_monitor), false);
1074 pr_err("[%s] Failed to get activity monitor!", __func__);
1079 case 0: /* Gfxclk */
1080 activity_monitor.Gfx_FPS = input[1];
1081 activity_monitor.Gfx_MinFreqStep = input[2];
1082 activity_monitor.Gfx_MinActiveFreqType = input[3];
1083 activity_monitor.Gfx_MinActiveFreq = input[4];
1084 activity_monitor.Gfx_BoosterFreqType = input[5];
1085 activity_monitor.Gfx_BoosterFreq = input[6];
1086 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1087 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1088 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1090 case 1: /* Socclk */
1091 activity_monitor.Soc_FPS = input[1];
1092 activity_monitor.Soc_MinFreqStep = input[2];
1093 activity_monitor.Soc_MinActiveFreqType = input[3];
1094 activity_monitor.Soc_MinActiveFreq = input[4];
1095 activity_monitor.Soc_BoosterFreqType = input[5];
1096 activity_monitor.Soc_BoosterFreq = input[6];
1097 activity_monitor.Soc_PD_Data_limit_c = input[7];
1098 activity_monitor.Soc_PD_Data_error_coeff = input[8];
1099 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1102 activity_monitor.Mem_FPS = input[1];
1103 activity_monitor.Mem_MinFreqStep = input[2];
1104 activity_monitor.Mem_MinActiveFreqType = input[3];
1105 activity_monitor.Mem_MinActiveFreq = input[4];
1106 activity_monitor.Mem_BoosterFreqType = input[5];
1107 activity_monitor.Mem_BoosterFreq = input[6];
1108 activity_monitor.Mem_PD_Data_limit_c = input[7];
1109 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1110 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1114 ret = smu_update_table(smu,
1115 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1116 (void *)(&activity_monitor), true);
1118 pr_err("[%s] Failed to set activity monitor!", __func__);
1123 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1124 workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1125 smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1126 1 << workload_type);
1131 static int navi10_get_profiling_clk_mask(struct smu_context *smu,
1132 enum amd_dpm_forced_level level,
1133 uint32_t *sclk_mask,
1134 uint32_t *mclk_mask,
1138 uint32_t level_count = 0;
1140 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1143 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1146 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1148 ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
1151 *sclk_mask = level_count - 1;
1155 ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
1158 *mclk_mask = level_count - 1;
1162 ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
1165 *soc_mask = level_count - 1;
1172 static int navi10_notify_smc_dispaly_config(struct smu_context *smu)
1174 struct smu_clocks min_clocks = {0};
1175 struct pp_display_clock_request clock_req;
1178 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1179 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1180 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1182 if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1183 clock_req.clock_type = amd_pp_dcef_clock;
1184 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1185 if (!smu_display_clock_voltage_request(smu, &clock_req)) {
1186 if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1187 ret = smu_send_smc_msg_with_param(smu,
1188 SMU_MSG_SetMinDeepSleepDcefclk,
1189 min_clocks.dcef_clock_in_sr/100);
1191 pr_err("Attempt to set divider for DCEFCLK Failed!");
1196 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1200 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1201 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1203 pr_err("[%s] Set hard min uclk failed!", __func__);
1211 static int navi10_set_watermarks_table(struct smu_context *smu,
1212 void *watermarks, struct
1213 dm_pp_wm_sets_with_clock_ranges_soc15
1217 Watermarks_t *table = watermarks;
1219 if (!table || !clock_ranges)
1222 if (clock_ranges->num_wm_dmif_sets > 4 ||
1223 clock_ranges->num_wm_mcif_sets > 4)
1226 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1227 table->WatermarkRow[1][i].MinClock =
1228 cpu_to_le16((uint16_t)
1229 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1231 table->WatermarkRow[1][i].MaxClock =
1232 cpu_to_le16((uint16_t)
1233 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1235 table->WatermarkRow[1][i].MinUclk =
1236 cpu_to_le16((uint16_t)
1237 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1239 table->WatermarkRow[1][i].MaxUclk =
1240 cpu_to_le16((uint16_t)
1241 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1243 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1244 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1247 for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1248 table->WatermarkRow[0][i].MinClock =
1249 cpu_to_le16((uint16_t)
1250 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1252 table->WatermarkRow[0][i].MaxClock =
1253 cpu_to_le16((uint16_t)
1254 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1256 table->WatermarkRow[0][i].MinUclk =
1257 cpu_to_le16((uint16_t)
1258 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1260 table->WatermarkRow[0][i].MaxUclk =
1261 cpu_to_le16((uint16_t)
1262 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1264 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1265 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1271 static int navi10_thermal_get_temperature(struct smu_context *smu,
1272 enum amd_pp_sensors sensor,
1275 SmuMetrics_t metrics;
1281 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false);
1286 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1287 *value = metrics.TemperatureHotspot *
1288 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1290 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1291 *value = metrics.TemperatureEdge *
1292 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1294 case AMDGPU_PP_SENSOR_MEM_TEMP:
1295 *value = metrics.TemperatureMem *
1296 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1299 pr_err("Invalid sensor for retrieving temp\n");
1306 static int navi10_read_sensor(struct smu_context *smu,
1307 enum amd_pp_sensors sensor,
1308 void *data, uint32_t *size)
1311 struct smu_table_context *table_context = &smu->smu_table;
1312 PPTable_t *pptable = table_context->driver_pptable;
1315 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1316 *(uint32_t *)data = pptable->FanMaximumRpm;
1319 case AMDGPU_PP_SENSOR_MEM_LOAD:
1320 case AMDGPU_PP_SENSOR_GPU_LOAD:
1321 ret = navi10_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1324 case AMDGPU_PP_SENSOR_GPU_POWER:
1325 ret = navi10_get_gpu_power(smu, (uint32_t *)data);
1328 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1329 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1330 case AMDGPU_PP_SENSOR_MEM_TEMP:
1331 ret = navi10_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1341 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1343 uint32_t num_discrete_levels = 0;
1344 uint16_t *dpm_levels = NULL;
1346 struct smu_table_context *table_context = &smu->smu_table;
1347 PPTable_t *driver_ppt = NULL;
1349 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1352 driver_ppt = table_context->driver_pptable;
1353 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1354 dpm_levels = driver_ppt->FreqTableUclk;
1356 if (num_discrete_levels == 0 || dpm_levels == NULL)
1359 *num_states = num_discrete_levels;
1360 for (i = 0; i < num_discrete_levels; i++) {
1361 /* convert to khz */
1362 *clocks_in_khz = (*dpm_levels) * 1000;
1370 static int navi10_get_ppfeature_status(struct smu_context *smu,
1373 static const char *ppfeature_name[] = {
1382 "MEM_VDDCI_SCALING",
1412 "OUT_OF_BAND_MONITOR",
1413 "TEMP_DEPENDENT_VMIN",
1416 static const char *output_title[] = {
1420 uint64_t features_enabled;
1421 uint32_t feature_mask[2];
1426 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1427 PP_ASSERT_WITH_CODE(!ret,
1428 "[GetPPfeatureStatus] Failed to get enabled smc features!",
1430 features_enabled = (uint64_t)feature_mask[0] |
1431 (uint64_t)feature_mask[1] << 32;
1433 size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
1434 size += sprintf(buf + size, "%-19s %-22s %s\n",
1438 for (i = 0; i < (sizeof(ppfeature_name) / sizeof(ppfeature_name[0])); i++) {
1439 size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
1442 (features_enabled & (1ULL << i)) ? "Y" : "N");
1448 static int navi10_enable_smc_features(struct smu_context *smu,
1450 uint64_t feature_masks)
1452 struct smu_feature *feature = &smu->smu_feature;
1453 uint32_t feature_low, feature_high;
1454 uint32_t feature_mask[2];
1457 feature_low = (uint32_t)(feature_masks & 0xFFFFFFFF);
1458 feature_high = (uint32_t)((feature_masks & 0xFFFFFFFF00000000ULL) >> 32);
1461 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
1465 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
1470 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
1474 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
1480 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1484 mutex_lock(&feature->mutex);
1485 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
1486 feature->feature_num);
1487 mutex_unlock(&feature->mutex);
1492 static int navi10_set_ppfeature_status(struct smu_context *smu,
1493 uint64_t new_ppfeature_masks)
1495 uint64_t features_enabled;
1496 uint32_t feature_mask[2];
1497 uint64_t features_to_enable;
1498 uint64_t features_to_disable;
1501 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1502 PP_ASSERT_WITH_CODE(!ret,
1503 "[SetPPfeatureStatus] Failed to get enabled smc features!",
1505 features_enabled = (uint64_t)feature_mask[0] |
1506 (uint64_t)feature_mask[1] << 32;
1508 features_to_disable =
1509 features_enabled & ~new_ppfeature_masks;
1510 features_to_enable =
1511 ~features_enabled & new_ppfeature_masks;
1513 pr_debug("features_to_disable 0x%llx\n", features_to_disable);
1514 pr_debug("features_to_enable 0x%llx\n", features_to_enable);
1516 if (features_to_disable) {
1517 ret = navi10_enable_smc_features(smu, false, features_to_disable);
1518 PP_ASSERT_WITH_CODE(!ret,
1519 "[SetPPfeatureStatus] Failed to disable smc features!",
1523 if (features_to_enable) {
1524 ret = navi10_enable_smc_features(smu, true, features_to_enable);
1525 PP_ASSERT_WITH_CODE(!ret,
1526 "[SetPPfeatureStatus] Failed to enable smc features!",
1533 static const struct pptable_funcs navi10_ppt_funcs = {
1534 .tables_init = navi10_tables_init,
1535 .alloc_dpm_context = navi10_allocate_dpm_context,
1536 .store_powerplay_table = navi10_store_powerplay_table,
1537 .check_powerplay_table = navi10_check_powerplay_table,
1538 .append_powerplay_table = navi10_append_powerplay_table,
1539 .get_smu_msg_index = navi10_get_smu_msg_index,
1540 .get_smu_clk_index = navi10_get_smu_clk_index,
1541 .get_smu_feature_index = navi10_get_smu_feature_index,
1542 .get_smu_table_index = navi10_get_smu_table_index,
1543 .get_smu_power_index = navi10_get_pwr_src_index,
1544 .get_workload_type = navi10_get_workload_type,
1545 .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
1546 .set_default_dpm_table = navi10_set_default_dpm_table,
1547 .dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
1548 .get_current_clk_freq_by_table = navi10_get_current_clk_freq_by_table,
1549 .print_clk_levels = navi10_print_clk_levels,
1550 .force_clk_levels = navi10_force_clk_levels,
1551 .populate_umd_state_clk = navi10_populate_umd_state_clk,
1552 .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
1553 .pre_display_config_changed = navi10_pre_display_config_changed,
1554 .display_config_changed = navi10_display_config_changed,
1555 .notify_smc_dispaly_config = navi10_notify_smc_dispaly_config,
1556 .force_dpm_limit_value = navi10_force_dpm_limit_value,
1557 .unforce_dpm_levels = navi10_unforce_dpm_levels,
1558 .is_dpm_running = navi10_is_dpm_running,
1559 .get_fan_speed_percent = navi10_get_fan_speed_percent,
1560 .get_power_profile_mode = navi10_get_power_profile_mode,
1561 .set_power_profile_mode = navi10_set_power_profile_mode,
1562 .get_profiling_clk_mask = navi10_get_profiling_clk_mask,
1563 .set_watermarks_table = navi10_set_watermarks_table,
1564 .read_sensor = navi10_read_sensor,
1565 .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
1566 .get_ppfeature_status = navi10_get_ppfeature_status,
1567 .set_ppfeature_status = navi10_set_ppfeature_status,
1570 void navi10_set_ppt_funcs(struct smu_context *smu)
1572 struct smu_table_context *smu_table = &smu->smu_table;
1574 smu->ppt_funcs = &navi10_ppt_funcs;
1575 smu->smc_if_version = SMU11_DRIVER_IF_VERSION;
1576 smu_table->table_count = TABLE_COUNT;