drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef _VEGA20_HWMGR_H_
  25 #define _VEGA20_HWMGR_H_
  26
  27 #include "hwmgr.h"
  28 #include "smu11_driver_if.h"
  29 #include "ppatomfwctrl.h"
  30
  31 #define VEGA20_MAX_HARDWARE_POWERLEVELS 2
  32
  33 #define WaterMarksExist  1
  34 #define WaterMarksLoaded 2
  35
  36 #define VG20_PSUEDO_NUM_GFXCLK_DPM_LEVELS   8
  37 #define VG20_PSUEDO_NUM_SOCCLK_DPM_LEVELS   8
  38 #define VG20_PSUEDO_NUM_DCEFCLK_DPM_LEVELS  8
  39 #define VG20_PSUEDO_NUM_UCLK_DPM_LEVELS     4
  40
  41 //OverDriver8 macro defs
  42 #define AVFS_CURVE 0
  43 #define OD8_HOTCURVE_TEMPERATURE 85
  44
  45 typedef uint32_t PP_Clock;
  46
  47 enum {
  48         GNLD_DPM_PREFETCHER = 0,
  49         GNLD_DPM_GFXCLK,
  50         GNLD_DPM_UCLK,
  51         GNLD_DPM_SOCCLK,
  52         GNLD_DPM_UVD,
  53         GNLD_DPM_VCE,
  54         GNLD_ULV,
  55         GNLD_DPM_MP0CLK,
  56         GNLD_DPM_LINK,
  57         GNLD_DPM_DCEFCLK,
  58         GNLD_DS_GFXCLK,
  59         GNLD_DS_SOCCLK,
  60         GNLD_DS_LCLK,
  61         GNLD_PPT,
  62         GNLD_TDC,
  63         GNLD_THERMAL,
  64         GNLD_GFX_PER_CU_CG,
  65         GNLD_RM,
  66         GNLD_DS_DCEFCLK,
  67         GNLD_ACDC,
  68         GNLD_VR0HOT,
  69         GNLD_VR1HOT,
  70         GNLD_FW_CTF,
  71         GNLD_LED_DISPLAY,
  72         GNLD_FAN_CONTROL,
  73         GNLD_DIDT,
  74         GNLD_GFXOFF,
  75         GNLD_CG,
  76         GNLD_DPM_FCLK,
  77         GNLD_DS_FCLK,
  78         GNLD_DS_MP1CLK,
  79         GNLD_DS_MP0CLK,
  80         GNLD_XGMI,
  81
  82         GNLD_FEATURES_MAX
  83 };
  84
  85
  86 #define GNLD_DPM_MAX    (GNLD_DPM_DCEFCLK + 1)
  87
  88 #define SMC_DPM_FEATURES    0x30F
  89
  90 struct smu_features {
  91         bool supported;
  92         bool enabled;
  93         bool allowed;
  94         uint32_t smu_feature_id;
  95         uint64_t smu_feature_bitmap;
  96 };
  97
  98 struct vega20_performance_level {
  99         uint32_t  soc_clock;
 100         uint32_t  gfx_clock;
 101         uint32_t  mem_clock;
 102 };
 103
 104 struct vega20_bacos {
 105         uint32_t                       baco_flags;
 106         /* struct vega20_performance_level  performance_level; */
 107 };
 108
 109 struct vega20_uvd_clocks {
 110         uint32_t  vclk;
 111         uint32_t  dclk;
 112 };
 113
 114 struct vega20_vce_clocks {
 115         uint32_t  evclk;
 116         uint32_t  ecclk;
 117 };
 118
 119 struct vega20_power_state {
 120         uint32_t                  magic;
 121         struct vega20_uvd_clocks    uvd_clks;
 122         struct vega20_vce_clocks    vce_clks;
 123         uint16_t                  performance_level_count;
 124         bool                      dc_compatible;
 125         uint32_t                  sclk_threshold;
 126         struct vega20_performance_level  performance_levels[VEGA20_MAX_HARDWARE_POWERLEVELS];
 127 };
 128
 129 struct vega20_dpm_level {
 130         bool            enabled;
 131         uint32_t        value;
 132         uint32_t        param1;
 133 };
 134
 135 #define VEGA20_MAX_DEEPSLEEP_DIVIDER_ID 5
 136 #define MAX_REGULAR_DPM_NUMBER 16
 137 #define MAX_PCIE_CONF 2
 138 #define VEGA20_MINIMUM_ENGINE_CLOCK 2500
 139
 140 struct vega20_max_sustainable_clocks {
 141         PP_Clock display_clock;
 142         PP_Clock phy_clock;
 143         PP_Clock pixel_clock;
 144         PP_Clock uclock;
 145         PP_Clock dcef_clock;
 146         PP_Clock soc_clock;
 147 };
 148
 149 struct vega20_dpm_state {
 150         uint32_t  soft_min_level;
 151         uint32_t  soft_max_level;
 152         uint32_t  hard_min_level;
 153         uint32_t  hard_max_level;
 154 };
 155
 156 struct vega20_single_dpm_table {
 157         uint32_t                count;
 158         struct vega20_dpm_state dpm_state;
 159         struct vega20_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
 160 };
 161
 162 struct vega20_odn_dpm_control {
 163         uint32_t        count;
 164         uint32_t        entries[MAX_REGULAR_DPM_NUMBER];
 165 };
 166
 167 struct vega20_pcie_table {
 168         uint16_t count;
 169         uint8_t  pcie_gen[MAX_PCIE_CONF];
 170         uint8_t  pcie_lane[MAX_PCIE_CONF];
 171         uint32_t lclk[MAX_PCIE_CONF];
 172 };
 173
 174 struct vega20_dpm_table {
 175         struct vega20_single_dpm_table  soc_table;
 176         struct vega20_single_dpm_table  gfx_table;
 177         struct vega20_single_dpm_table  mem_table;
 178         struct vega20_single_dpm_table  eclk_table;
 179         struct vega20_single_dpm_table  vclk_table;
 180         struct vega20_single_dpm_table  dclk_table;
 181         struct vega20_single_dpm_table  dcef_table;
 182         struct vega20_single_dpm_table  pixel_table;
 183         struct vega20_single_dpm_table  display_table;
 184         struct vega20_single_dpm_table  phy_table;
 185         struct vega20_single_dpm_table  fclk_table;
 186         struct vega20_pcie_table        pcie_table;
 187 };
 188
 189 #define VEGA20_MAX_LEAKAGE_COUNT  8
 190 struct vega20_leakage_voltage {
 191         uint16_t  count;
 192         uint16_t  leakage_id[VEGA20_MAX_LEAKAGE_COUNT];
 193         uint16_t  actual_voltage[VEGA20_MAX_LEAKAGE_COUNT];
 194 };
 195
 196 struct vega20_display_timing {
 197         uint32_t  min_clock_in_sr;
 198         uint32_t  num_existing_displays;
 199 };
 200
 201 struct vega20_dpmlevel_enable_mask {
 202         uint32_t  uvd_dpm_enable_mask;
 203         uint32_t  vce_dpm_enable_mask;
 204         uint32_t  samu_dpm_enable_mask;
 205         uint32_t  sclk_dpm_enable_mask;
 206         uint32_t  mclk_dpm_enable_mask;
 207 };
 208
 209 struct vega20_vbios_boot_state {
 210         uint8_t     uc_cooling_id;
 211         uint16_t    vddc;
 212         uint16_t    vddci;
 213         uint16_t    mvddc;
 214         uint16_t    vdd_gfx;
 215         uint32_t    gfx_clock;
 216         uint32_t    mem_clock;
 217         uint32_t    soc_clock;
 218         uint32_t    dcef_clock;
 219         uint32_t    eclock;
 220         uint32_t    dclock;
 221         uint32_t    vclock;
 222 };
 223
 224 #define DPMTABLE_OD_UPDATE_SCLK     0x00000001
 225 #define DPMTABLE_OD_UPDATE_MCLK     0x00000002
 226 #define DPMTABLE_UPDATE_SCLK        0x00000004
 227 #define DPMTABLE_UPDATE_MCLK        0x00000008
 228 #define DPMTABLE_OD_UPDATE_VDDC     0x00000010
 229 #define DPMTABLE_OD_UPDATE_SCLK_MASK     0x00000020
 230 #define DPMTABLE_OD_UPDATE_MCLK_MASK     0x00000040
 231
 232 // To determine if sclk and mclk are in overdrive state
 233 #define SCLK_MASK_OVERDRIVE_ENABLED      0x00000008
 234 #define MCLK_MASK_OVERDRIVE_ENABLED      0x00000010
 235 #define SOCCLK_OVERDRIVE_ENABLED         0x00000020
 236
 237 struct vega20_smc_state_table {
 238         uint32_t        soc_boot_level;
 239         uint32_t        gfx_boot_level;
 240         uint32_t        dcef_boot_level;
 241         uint32_t        mem_boot_level;
 242         uint32_t        uvd_boot_level;
 243         uint32_t        vce_boot_level;
 244         uint32_t        gfx_max_level;
 245         uint32_t        mem_max_level;
 246         uint8_t         vr_hot_gpio;
 247         uint8_t         ac_dc_gpio;
 248         uint8_t         therm_out_gpio;
 249         uint8_t         therm_out_polarity;
 250         uint8_t         therm_out_mode;
 251         PPTable_t       pp_table;
 252         Watermarks_t    water_marks_table;
 253         AvfsDebugTable_t avfs_debug_table;
 254         AvfsFuseOverride_t avfs_fuse_override_table;
 255         SmuMetrics_t    smu_metrics;
 256         DriverSmuConfig_t driver_smu_config;
 257         DpmActivityMonitorCoeffInt_t dpm_activity_monitor_coeffint;
 258         OverDriveTable_t overdrive_table;
 259 };
 260
 261 struct vega20_mclk_latency_entries {
 262         uint32_t  frequency;
 263         uint32_t  latency;
 264 };
 265
 266 struct vega20_mclk_latency_table {
 267         uint32_t  count;
 268         struct vega20_mclk_latency_entries  entries[MAX_REGULAR_DPM_NUMBER];
 269 };
 270
 271 struct vega20_registry_data {
 272         uint64_t  disallowed_features;
 273         uint8_t   ac_dc_switch_gpio_support;
 274         uint8_t   acg_loop_support;
 275         uint8_t   clock_stretcher_support;
 276         uint8_t   db_ramping_support;
 277         uint8_t   didt_mode;
 278         uint8_t   didt_support;
 279         uint8_t   edc_didt_support;
 280         uint8_t   force_dpm_high;
 281         uint8_t   fuzzy_fan_control_support;
 282         uint8_t   mclk_dpm_key_disabled;
 283         uint8_t   od_state_in_dc_support;
 284         uint8_t   pcie_lane_override;
 285         uint8_t   pcie_speed_override;
 286         uint32_t  pcie_clock_override;
 287         uint8_t   pcie_dpm_key_disabled;
 288         uint8_t   dcefclk_dpm_key_disabled;
 289         uint8_t   prefetcher_dpm_key_disabled;
 290         uint8_t   quick_transition_support;
 291         uint8_t   regulator_hot_gpio_support;
 292         uint8_t   master_deep_sleep_support;
 293         uint8_t   gfx_clk_deep_sleep_support;
 294         uint8_t   sclk_deep_sleep_support;
 295         uint8_t   lclk_deep_sleep_support;
 296         uint8_t   dce_fclk_deep_sleep_support;
 297         uint8_t   sclk_dpm_key_disabled;
 298         uint8_t   sclk_throttle_low_notification;
 299         uint8_t   skip_baco_hardware;
 300         uint8_t   socclk_dpm_key_disabled;
 301         uint8_t   sq_ramping_support;
 302         uint8_t   tcp_ramping_support;
 303         uint8_t   td_ramping_support;
 304         uint8_t   dbr_ramping_support;
 305         uint8_t   gc_didt_support;
 306         uint8_t   psm_didt_support;
 307         uint8_t   thermal_support;
 308         uint8_t   fw_ctf_enabled;
 309         uint8_t   led_dpm_enabled;
 310         uint8_t   fan_control_support;
 311         uint8_t   ulv_support;
 312         uint8_t   od8_feature_enable;
 313         uint8_t   disable_water_mark;
 314         uint8_t   disable_workload_policy;
 315         uint32_t  force_workload_policy_mask;
 316         uint8_t   disable_3d_fs_detection;
 317         uint8_t   disable_pp_tuning;
 318         uint8_t   disable_xlpp_tuning;
 319         uint32_t  perf_ui_tuning_profile_turbo;
 320         uint32_t  perf_ui_tuning_profile_powerSave;
 321         uint32_t  perf_ui_tuning_profile_xl;
 322         uint16_t  zrpm_stop_temp;
 323         uint16_t  zrpm_start_temp;
 324         uint32_t  stable_pstate_sclk_dpm_percentage;
 325         uint8_t   fps_support;
 326         uint8_t   vr0hot;
 327         uint8_t   vr1hot;
 328         uint8_t   disable_auto_wattman;
 329         uint32_t  auto_wattman_debug;
 330         uint32_t  auto_wattman_sample_period;
 331         uint32_t  fclk_gfxclk_ratio;
 332         uint8_t   auto_wattman_threshold;
 333         uint8_t   log_avfs_param;
 334         uint8_t   enable_enginess;
 335         uint8_t   custom_fan_support;
 336         uint8_t   disable_pcc_limit_control;
 337         uint8_t   gfxoff_controlled_by_driver;
 338 };
 339
 340 struct vega20_odn_clock_voltage_dependency_table {
 341         uint32_t count;
 342         struct phm_ppt_v1_clock_voltage_dependency_record
 343                 entries[MAX_REGULAR_DPM_NUMBER];
 344 };
 345
 346 struct vega20_odn_dpm_table {
 347         struct vega20_odn_dpm_control           control_gfxclk_state;
 348         struct vega20_odn_dpm_control           control_memclk_state;
 349         struct phm_odn_clock_levels             odn_core_clock_dpm_levels;
 350         struct phm_odn_clock_levels             odn_memory_clock_dpm_levels;
 351         struct vega20_odn_clock_voltage_dependency_table                vdd_dependency_on_sclk;
 352         struct vega20_odn_clock_voltage_dependency_table                vdd_dependency_on_mclk;
 353         struct vega20_odn_clock_voltage_dependency_table                vdd_dependency_on_socclk;
 354         uint32_t                                odn_mclk_min_limit;
 355 };
 356
 357 struct vega20_odn_fan_table {
 358         uint32_t        target_fan_speed;
 359         uint32_t        target_temperature;
 360         uint32_t        min_performance_clock;
 361         uint32_t        min_fan_limit;
 362         bool            force_fan_pwm;
 363 };
 364
 365 struct vega20_odn_temp_table {
 366         uint16_t        target_operating_temp;
 367         uint16_t        default_target_operating_temp;
 368         uint16_t        operating_temp_min_limit;
 369         uint16_t        operating_temp_max_limit;
 370         uint16_t        operating_temp_step;
 371 };
 372
 373 struct vega20_odn_data {
 374         uint32_t        apply_overdrive_next_settings_mask;
 375         uint32_t        overdrive_next_state;
 376         uint32_t        overdrive_next_capabilities;
 377         uint32_t        odn_sclk_dpm_enable_mask;
 378         uint32_t        odn_mclk_dpm_enable_mask;
 379         struct vega20_odn_dpm_table     odn_dpm_table;
 380         struct vega20_odn_fan_table     odn_fan_table;
 381         struct vega20_odn_temp_table    odn_temp_table;
 382 };
 383
 384 enum OD8_FEATURE_ID
 385 {
 386         OD8_GFXCLK_LIMITS               = 1 << 0,
 387         OD8_GFXCLK_CURVE                = 1 << 1,
 388         OD8_UCLK_MAX                    = 1 << 2,
 389         OD8_POWER_LIMIT                 = 1 << 3,
 390         OD8_ACOUSTIC_LIMIT_SCLK         = 1 << 4,   //FanMaximumRpm
 391         OD8_FAN_SPEED_MIN               = 1 << 5,   //FanMinimumPwm
 392         OD8_TEMPERATURE_FAN             = 1 << 6,   //FanTargetTemperature
 393         OD8_TEMPERATURE_SYSTEM          = 1 << 7,   //MaxOpTemp
 394         OD8_MEMORY_TIMING_TUNE          = 1 << 8,
 395         OD8_FAN_ZERO_RPM_CONTROL        = 1 << 9
 396 };
 397
 398 enum OD8_SETTING_ID
 399 {
 400         OD8_SETTING_GFXCLK_FMIN = 0,
 401         OD8_SETTING_GFXCLK_FMAX,
 402         OD8_SETTING_GFXCLK_FREQ1,
 403         OD8_SETTING_GFXCLK_VOLTAGE1,
 404         OD8_SETTING_GFXCLK_FREQ2,
 405         OD8_SETTING_GFXCLK_VOLTAGE2,
 406         OD8_SETTING_GFXCLK_FREQ3,
 407         OD8_SETTING_GFXCLK_VOLTAGE3,
 408         OD8_SETTING_UCLK_FMAX,
 409         OD8_SETTING_POWER_PERCENTAGE,
 410         OD8_SETTING_FAN_ACOUSTIC_LIMIT,
 411         OD8_SETTING_FAN_MIN_SPEED,
 412         OD8_SETTING_FAN_TARGET_TEMP,
 413         OD8_SETTING_OPERATING_TEMP_MAX,
 414         OD8_SETTING_AC_TIMING,
 415         OD8_SETTING_FAN_ZERO_RPM_CONTROL,
 416         OD8_SETTING_COUNT
 417 };
 418
 419 struct vega20_od8_single_setting {
 420         uint32_t        feature_id;
 421         int32_t         min_value;
 422         int32_t         max_value;
 423         int32_t         current_value;
 424         int32_t         default_value;
 425 };
 426
 427 struct vega20_od8_settings {
 428         uint32_t        overdrive8_capabilities;
 429         struct vega20_od8_single_setting        od8_settings_array[OD8_SETTING_COUNT];
 430 };
 431
 432 struct vega20_hwmgr {
 433         struct vega20_dpm_table          dpm_table;
 434         struct vega20_dpm_table          golden_dpm_table;
 435         struct vega20_registry_data      registry_data;
 436         struct vega20_vbios_boot_state   vbios_boot_state;
 437         struct vega20_mclk_latency_table mclk_latency_table;
 438
 439         struct vega20_max_sustainable_clocks max_sustainable_clocks;
 440
 441         struct vega20_leakage_voltage    vddc_leakage;
 442
 443         uint32_t                           vddc_control;
 444         struct pp_atomfwctrl_voltage_table vddc_voltage_table;
 445         uint32_t                           mvdd_control;
 446         struct pp_atomfwctrl_voltage_table mvdd_voltage_table;
 447         uint32_t                           vddci_control;
 448         struct pp_atomfwctrl_voltage_table vddci_voltage_table;
 449
 450         uint32_t                           active_auto_throttle_sources;
 451         struct vega20_bacos                bacos;
 452
 453         /* ---- General data ---- */
 454         uint8_t                           need_update_dpm_table;
 455
 456         bool                           cac_enabled;
 457         bool                           battery_state;
 458         bool                           is_tlu_enabled;
 459         bool                           avfs_exist;
 460
 461         uint32_t                       low_sclk_interrupt_threshold;
 462
 463         uint32_t                       total_active_cus;
 464
 465         uint32_t                       water_marks_bitmap;
 466
 467         struct vega20_display_timing display_timing;
 468
 469         /* ---- Vega20 Dyn Register Settings ---- */
 470
 471         uint32_t                       debug_settings;
 472         uint32_t                       lowest_uclk_reserved_for_ulv;
 473         uint32_t                       gfxclk_average_alpha;
 474         uint32_t                       socclk_average_alpha;
 475         uint32_t                       uclk_average_alpha;
 476         uint32_t                       gfx_activity_average_alpha;
 477         uint32_t                       display_voltage_mode;
 478         uint32_t                       dcef_clk_quad_eqn_a;
 479         uint32_t                       dcef_clk_quad_eqn_b;
 480         uint32_t                       dcef_clk_quad_eqn_c;
 481         uint32_t                       disp_clk_quad_eqn_a;
 482         uint32_t                       disp_clk_quad_eqn_b;
 483         uint32_t                       disp_clk_quad_eqn_c;
 484         uint32_t                       pixel_clk_quad_eqn_a;
 485         uint32_t                       pixel_clk_quad_eqn_b;
 486         uint32_t                       pixel_clk_quad_eqn_c;
 487         uint32_t                       phy_clk_quad_eqn_a;
 488         uint32_t                       phy_clk_quad_eqn_b;
 489         uint32_t                       phy_clk_quad_eqn_c;
 490
 491         /* ---- Thermal Temperature Setting ---- */
 492         struct vega20_dpmlevel_enable_mask     dpm_level_enable_mask;
 493
 494         /* ---- Power Gating States ---- */
 495         bool                           uvd_power_gated;
 496         bool                           vce_power_gated;
 497         bool                           samu_power_gated;
 498         bool                           need_long_memory_training;
 499
 500         /* Internal settings to apply the application power optimization parameters */
 501         bool                           apply_optimized_settings;
 502         uint32_t                       disable_dpm_mask;
 503
 504         /* ---- Overdrive next setting ---- */
 505         struct vega20_odn_data         odn_data;
 506         bool                           gfxclk_overdrive;
 507         bool                           memclk_overdrive;
 508
 509         /* ---- Overdrive8 Setting ---- */
 510         struct vega20_od8_settings     od8_settings;
 511
 512         /* ---- Workload Mask ---- */
 513         uint32_t                       workload_mask;
 514
 515         /* ---- SMU9 ---- */
 516         uint32_t                       smu_version;
 517         struct smu_features            smu_features[GNLD_FEATURES_MAX];
 518         struct vega20_smc_state_table  smc_state_table;
 519
 520         /* ---- Gfxoff ---- */
 521         bool                           gfxoff_allowed;
 522         uint32_t                       counter_gfxoff;
 523 };
 524
 525 #define VEGA20_DPM2_NEAR_TDP_DEC                      10
 526 #define VEGA20_DPM2_ABOVE_SAFE_INC                    5
 527 #define VEGA20_DPM2_BELOW_SAFE_INC                    20
 528
 529 #define VEGA20_DPM2_LTA_WINDOW_SIZE                   7
 530
 531 #define VEGA20_DPM2_LTS_TRUNCATE                      0
 532
 533 #define VEGA20_DPM2_TDP_SAFE_LIMIT_PERCENT            80
 534
 535 #define VEGA20_DPM2_MAXPS_PERCENT_M                   90
 536 #define VEGA20_DPM2_MAXPS_PERCENT_H                   90
 537
 538 #define VEGA20_DPM2_PWREFFICIENCYRATIO_MARGIN         50
 539
 540 #define VEGA20_DPM2_SQ_RAMP_MAX_POWER                 0x3FFF
 541 #define VEGA20_DPM2_SQ_RAMP_MIN_POWER                 0x12
 542 #define VEGA20_DPM2_SQ_RAMP_MAX_POWER_DELTA           0x15
 543 #define VEGA20_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE  0x1E
 544 #define VEGA20_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO  0xF
 545
 546 #define VEGA20_VOLTAGE_CONTROL_NONE                   0x0
 547 #define VEGA20_VOLTAGE_CONTROL_BY_GPIO                0x1
 548 #define VEGA20_VOLTAGE_CONTROL_BY_SVID2               0x2
 549 #define VEGA20_VOLTAGE_CONTROL_MERGED                 0x3
 550 /* To convert to Q8.8 format for firmware */
 551 #define VEGA20_Q88_FORMAT_CONVERSION_UNIT             256
 552
 553 #define VEGA20_UNUSED_GPIO_PIN       0x7F
 554
 555 #define VEGA20_THERM_OUT_MODE_DISABLE       0x0
 556 #define VEGA20_THERM_OUT_MODE_THERM_ONLY    0x1
 557 #define VEGA20_THERM_OUT_MODE_THERM_VRHOT   0x2
 558
 559 #define PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT   0xffffffff
 560 #define PPREGKEY_VEGA20QUADRATICEQUATION_DFLT    0xffffffff
 561
 562 #define PPVEGA20_VEGA20GFXCLKAVERAGEALPHA_DFLT       25 /* 10% * 255 = 25 */
 563 #define PPVEGA20_VEGA20SOCCLKAVERAGEALPHA_DFLT       25 /* 10% * 255 = 25 */
 564 #define PPVEGA20_VEGA20UCLKCLKAVERAGEALPHA_DFLT      25 /* 10% * 255 = 25 */
 565 #define PPVEGA20_VEGA20GFXACTIVITYAVERAGEALPHA_DFLT  25 /* 10% * 255 = 25 */
 566 #define PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT   0xffffffff
 567 #define PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT         0xffffffff
 568 #define PPREGKEY_VEGA20QUADRATICEQUATION_DFLT          0xffffffff
 569
 570 #define VEGA20_UMD_PSTATE_GFXCLK_LEVEL         0x3
 571 #define VEGA20_UMD_PSTATE_SOCCLK_LEVEL         0x3
 572 #define VEGA20_UMD_PSTATE_MCLK_LEVEL           0x2
 573 #define VEGA20_UMD_PSTATE_UVDCLK_LEVEL         0x3
 574 #define VEGA20_UMD_PSTATE_VCEMCLK_LEVEL        0x3
 575
 576 #endif /* _VEGA20_HWMGR_H_ */