2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
30 #include "amd_powerplay.h"
31 #include "vega20_smumgr.h"
32 #include "hardwaremanager.h"
33 #include "ppatomfwctrl.h"
34 #include "atomfirmware.h"
35 #include "cgs_common.h"
36 #include "vega20_powertune.h"
37 #include "vega20_inc.h"
38 #include "pppcielanes.h"
39 #include "vega20_hwmgr.h"
40 #include "vega20_processpptables.h"
41 #include "vega20_pptable.h"
42 #include "vega20_thermal.h"
43 #include "vega20_ppsmc.h"
45 #include "amd_pcie_helpers.h"
46 #include "ppinterrupt.h"
47 #include "pp_overdriver.h"
48 #include "pp_thermal.h"
49 #include "soc15_common.h"
50 #include "smuio/smuio_9_0_offset.h"
51 #include "smuio/smuio_9_0_sh_mask.h"
52 #include "nbio/nbio_7_4_sh_mask.h"
54 #define smnPCIE_LC_SPEED_CNTL 0x11140290
55 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
57 static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
59 struct vega20_hwmgr *data =
60 (struct vega20_hwmgr *)(hwmgr->backend);
62 data->gfxclk_average_alpha = PPVEGA20_VEGA20GFXCLKAVERAGEALPHA_DFLT;
63 data->socclk_average_alpha = PPVEGA20_VEGA20SOCCLKAVERAGEALPHA_DFLT;
64 data->uclk_average_alpha = PPVEGA20_VEGA20UCLKCLKAVERAGEALPHA_DFLT;
65 data->gfx_activity_average_alpha = PPVEGA20_VEGA20GFXACTIVITYAVERAGEALPHA_DFLT;
66 data->lowest_uclk_reserved_for_ulv = PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT;
68 data->display_voltage_mode = PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT;
69 data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
70 data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
71 data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
72 data->disp_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
73 data->disp_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
74 data->disp_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
75 data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
76 data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
77 data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
78 data->phy_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
79 data->phy_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
80 data->phy_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
83 * Disable the following features for now:
92 data->registry_data.disallowed_features = 0xE0041C00;
93 data->registry_data.od_state_in_dc_support = 0;
94 data->registry_data.thermal_support = 1;
95 data->registry_data.skip_baco_hardware = 0;
97 data->registry_data.log_avfs_param = 0;
98 data->registry_data.sclk_throttle_low_notification = 1;
99 data->registry_data.force_dpm_high = 0;
100 data->registry_data.stable_pstate_sclk_dpm_percentage = 75;
102 data->registry_data.didt_support = 0;
103 if (data->registry_data.didt_support) {
104 data->registry_data.didt_mode = 6;
105 data->registry_data.sq_ramping_support = 1;
106 data->registry_data.db_ramping_support = 0;
107 data->registry_data.td_ramping_support = 0;
108 data->registry_data.tcp_ramping_support = 0;
109 data->registry_data.dbr_ramping_support = 0;
110 data->registry_data.edc_didt_support = 1;
111 data->registry_data.gc_didt_support = 0;
112 data->registry_data.psm_didt_support = 0;
115 data->registry_data.pcie_lane_override = 0xff;
116 data->registry_data.pcie_speed_override = 0xff;
117 data->registry_data.pcie_clock_override = 0xffffffff;
118 data->registry_data.regulator_hot_gpio_support = 1;
119 data->registry_data.ac_dc_switch_gpio_support = 0;
120 data->registry_data.quick_transition_support = 0;
121 data->registry_data.zrpm_start_temp = 0xffff;
122 data->registry_data.zrpm_stop_temp = 0xffff;
123 data->registry_data.od8_feature_enable = 1;
124 data->registry_data.disable_water_mark = 0;
125 data->registry_data.disable_pp_tuning = 0;
126 data->registry_data.disable_xlpp_tuning = 0;
127 data->registry_data.disable_workload_policy = 0;
128 data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F;
129 data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919;
130 data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A;
131 data->registry_data.force_workload_policy_mask = 0;
132 data->registry_data.disable_3d_fs_detection = 0;
133 data->registry_data.fps_support = 1;
134 data->registry_data.disable_auto_wattman = 1;
135 data->registry_data.auto_wattman_debug = 0;
136 data->registry_data.auto_wattman_sample_period = 100;
137 data->registry_data.fclk_gfxclk_ratio = 0x3F6CCCCD;
138 data->registry_data.auto_wattman_threshold = 50;
139 data->registry_data.gfxoff_controlled_by_driver = 1;
140 data->gfxoff_allowed = false;
141 data->counter_gfxoff = 0;
144 static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr)
146 struct vega20_hwmgr *data =
147 (struct vega20_hwmgr *)(hwmgr->backend);
148 struct amdgpu_device *adev = hwmgr->adev;
150 if (data->vddci_control == VEGA20_VOLTAGE_CONTROL_NONE)
151 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
152 PHM_PlatformCaps_ControlVDDCI);
154 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
155 PHM_PlatformCaps_TablelessHardwareInterface);
157 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
158 PHM_PlatformCaps_EnableSMU7ThermalManagement);
160 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
161 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
162 PHM_PlatformCaps_UVDPowerGating);
164 if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
165 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
166 PHM_PlatformCaps_VCEPowerGating);
168 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
169 PHM_PlatformCaps_UnTabledHardwareInterface);
171 if (data->registry_data.od8_feature_enable)
172 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
173 PHM_PlatformCaps_OD8inACSupport);
175 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
176 PHM_PlatformCaps_ActivityReporting);
177 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
178 PHM_PlatformCaps_FanSpeedInTableIsRPM);
180 if (data->registry_data.od_state_in_dc_support) {
181 if (data->registry_data.od8_feature_enable)
182 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
183 PHM_PlatformCaps_OD8inDCSupport);
186 if (data->registry_data.thermal_support &&
187 data->registry_data.fuzzy_fan_control_support &&
188 hwmgr->thermal_controller.advanceFanControlParameters.usTMax)
189 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
190 PHM_PlatformCaps_ODFuzzyFanControlSupport);
192 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
193 PHM_PlatformCaps_DynamicPowerManagement);
194 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
195 PHM_PlatformCaps_SMC);
196 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
197 PHM_PlatformCaps_ThermalPolicyDelay);
199 if (data->registry_data.force_dpm_high)
200 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
201 PHM_PlatformCaps_ExclusiveModeAlwaysHigh);
203 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
204 PHM_PlatformCaps_DynamicUVDState);
206 if (data->registry_data.sclk_throttle_low_notification)
207 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
208 PHM_PlatformCaps_SclkThrottleLowNotification);
210 /* power tune caps */
211 /* assume disabled */
212 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
213 PHM_PlatformCaps_PowerContainment);
214 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
215 PHM_PlatformCaps_DiDtSupport);
216 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
217 PHM_PlatformCaps_SQRamping);
218 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
219 PHM_PlatformCaps_DBRamping);
220 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
221 PHM_PlatformCaps_TDRamping);
222 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
223 PHM_PlatformCaps_TCPRamping);
224 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
225 PHM_PlatformCaps_DBRRamping);
226 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
227 PHM_PlatformCaps_DiDtEDCEnable);
228 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
229 PHM_PlatformCaps_GCEDC);
230 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
231 PHM_PlatformCaps_PSM);
233 if (data->registry_data.didt_support) {
234 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
235 PHM_PlatformCaps_DiDtSupport);
236 if (data->registry_data.sq_ramping_support)
237 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
238 PHM_PlatformCaps_SQRamping);
239 if (data->registry_data.db_ramping_support)
240 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
241 PHM_PlatformCaps_DBRamping);
242 if (data->registry_data.td_ramping_support)
243 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
244 PHM_PlatformCaps_TDRamping);
245 if (data->registry_data.tcp_ramping_support)
246 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
247 PHM_PlatformCaps_TCPRamping);
248 if (data->registry_data.dbr_ramping_support)
249 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
250 PHM_PlatformCaps_DBRRamping);
251 if (data->registry_data.edc_didt_support)
252 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
253 PHM_PlatformCaps_DiDtEDCEnable);
254 if (data->registry_data.gc_didt_support)
255 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
256 PHM_PlatformCaps_GCEDC);
257 if (data->registry_data.psm_didt_support)
258 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
259 PHM_PlatformCaps_PSM);
262 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
263 PHM_PlatformCaps_RegulatorHot);
265 if (data->registry_data.ac_dc_switch_gpio_support) {
266 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
267 PHM_PlatformCaps_AutomaticDCTransition);
268 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
269 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
272 if (data->registry_data.quick_transition_support) {
273 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
274 PHM_PlatformCaps_AutomaticDCTransition);
275 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
276 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
277 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
278 PHM_PlatformCaps_Falcon_QuickTransition);
281 if (data->lowest_uclk_reserved_for_ulv != PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT) {
282 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
283 PHM_PlatformCaps_LowestUclkReservedForUlv);
284 if (data->lowest_uclk_reserved_for_ulv == 1)
285 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
286 PHM_PlatformCaps_LowestUclkReservedForUlv);
289 if (data->registry_data.custom_fan_support)
290 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
291 PHM_PlatformCaps_CustomFanControlSupport);
296 static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr)
298 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
301 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
302 FEATURE_DPM_PREFETCHER_BIT;
303 data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
304 FEATURE_DPM_GFXCLK_BIT;
305 data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
306 FEATURE_DPM_UCLK_BIT;
307 data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
308 FEATURE_DPM_SOCCLK_BIT;
309 data->smu_features[GNLD_DPM_UVD].smu_feature_id =
311 data->smu_features[GNLD_DPM_VCE].smu_feature_id =
313 data->smu_features[GNLD_ULV].smu_feature_id =
315 data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
316 FEATURE_DPM_MP0CLK_BIT;
317 data->smu_features[GNLD_DPM_LINK].smu_feature_id =
318 FEATURE_DPM_LINK_BIT;
319 data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
320 FEATURE_DPM_DCEFCLK_BIT;
321 data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
322 FEATURE_DS_GFXCLK_BIT;
323 data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
324 FEATURE_DS_SOCCLK_BIT;
325 data->smu_features[GNLD_DS_LCLK].smu_feature_id =
327 data->smu_features[GNLD_PPT].smu_feature_id =
329 data->smu_features[GNLD_TDC].smu_feature_id =
331 data->smu_features[GNLD_THERMAL].smu_feature_id =
333 data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
334 FEATURE_GFX_PER_CU_CG_BIT;
335 data->smu_features[GNLD_RM].smu_feature_id =
337 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
338 FEATURE_DS_DCEFCLK_BIT;
339 data->smu_features[GNLD_ACDC].smu_feature_id =
341 data->smu_features[GNLD_VR0HOT].smu_feature_id =
343 data->smu_features[GNLD_VR1HOT].smu_feature_id =
345 data->smu_features[GNLD_FW_CTF].smu_feature_id =
347 data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
348 FEATURE_LED_DISPLAY_BIT;
349 data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
350 FEATURE_FAN_CONTROL_BIT;
351 data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
352 data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT;
353 data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT;
354 data->smu_features[GNLD_DPM_FCLK].smu_feature_id = FEATURE_DPM_FCLK_BIT;
355 data->smu_features[GNLD_DS_FCLK].smu_feature_id = FEATURE_DS_FCLK_BIT;
356 data->smu_features[GNLD_DS_MP1CLK].smu_feature_id = FEATURE_DS_MP1CLK_BIT;
357 data->smu_features[GNLD_DS_MP0CLK].smu_feature_id = FEATURE_DS_MP0CLK_BIT;
358 data->smu_features[GNLD_XGMI].smu_feature_id = FEATURE_XGMI_BIT;
360 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
361 data->smu_features[i].smu_feature_bitmap =
362 (uint64_t)(1ULL << data->smu_features[i].smu_feature_id);
363 data->smu_features[i].allowed =
364 ((data->registry_data.disallowed_features >> i) & 1) ?
369 static int vega20_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
374 static int vega20_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
376 kfree(hwmgr->backend);
377 hwmgr->backend = NULL;
382 static int vega20_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
384 struct vega20_hwmgr *data;
385 struct amdgpu_device *adev = hwmgr->adev;
387 data = kzalloc(sizeof(struct vega20_hwmgr), GFP_KERNEL);
391 hwmgr->backend = data;
393 hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO];
394 hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
395 hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
397 vega20_set_default_registry_data(hwmgr);
399 data->disable_dpm_mask = 0xff;
401 /* need to set voltage control types before EVV patching */
402 data->vddc_control = VEGA20_VOLTAGE_CONTROL_NONE;
403 data->mvdd_control = VEGA20_VOLTAGE_CONTROL_NONE;
404 data->vddci_control = VEGA20_VOLTAGE_CONTROL_NONE;
406 data->water_marks_bitmap = 0;
407 data->avfs_exist = false;
409 vega20_set_features_platform_caps(hwmgr);
411 vega20_init_dpm_defaults(hwmgr);
413 /* Parse pptable data read from VBIOS */
414 vega20_set_private_data_based_on_pptable(hwmgr);
416 data->is_tlu_enabled = false;
418 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
419 VEGA20_MAX_HARDWARE_POWERLEVELS;
420 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
421 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
423 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
424 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
425 hwmgr->platform_descriptor.clockStep.engineClock = 500;
426 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
428 data->total_active_cus = adev->gfx.cu_info.number;
433 static int vega20_init_sclk_threshold(struct pp_hwmgr *hwmgr)
435 struct vega20_hwmgr *data =
436 (struct vega20_hwmgr *)(hwmgr->backend);
438 data->low_sclk_interrupt_threshold = 0;
443 static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr)
447 ret = vega20_init_sclk_threshold(hwmgr);
448 PP_ASSERT_WITH_CODE(!ret,
449 "Failed to init sclk threshold!",
456 * @fn vega20_init_dpm_state
457 * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
459 * @param dpm_state - the address of the DPM Table to initiailize.
462 static void vega20_init_dpm_state(struct vega20_dpm_state *dpm_state)
464 dpm_state->soft_min_level = 0x0;
465 dpm_state->soft_max_level = 0xffff;
466 dpm_state->hard_min_level = 0x0;
467 dpm_state->hard_max_level = 0xffff;
470 static int vega20_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
471 PPCLK_e clk_id, uint32_t *num_of_levels)
475 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
476 PPSMC_MSG_GetDpmFreqByIndex,
477 (clk_id << 16 | 0xFF));
478 PP_ASSERT_WITH_CODE(!ret,
479 "[GetNumOfDpmLevel] failed to get dpm levels!",
482 *num_of_levels = smum_get_argument(hwmgr);
483 PP_ASSERT_WITH_CODE(*num_of_levels > 0,
484 "[GetNumOfDpmLevel] number of clk levels is invalid!",
490 static int vega20_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
491 PPCLK_e clk_id, uint32_t index, uint32_t *clk)
495 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
496 PPSMC_MSG_GetDpmFreqByIndex,
497 (clk_id << 16 | index));
498 PP_ASSERT_WITH_CODE(!ret,
499 "[GetDpmFreqByIndex] failed to get dpm freq by index!",
502 *clk = smum_get_argument(hwmgr);
503 PP_ASSERT_WITH_CODE(*clk,
504 "[GetDpmFreqByIndex] clk value is invalid!",
510 static int vega20_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
511 struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id)
514 uint32_t i, num_of_levels, clk;
516 ret = vega20_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
517 PP_ASSERT_WITH_CODE(!ret,
518 "[SetupSingleDpmTable] failed to get clk levels!",
521 dpm_table->count = num_of_levels;
523 for (i = 0; i < num_of_levels; i++) {
524 ret = vega20_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);
525 PP_ASSERT_WITH_CODE(!ret,
526 "[SetupSingleDpmTable] failed to get clk of specific level!",
528 dpm_table->dpm_levels[i].value = clk;
529 dpm_table->dpm_levels[i].enabled = true;
535 static int vega20_setup_gfxclk_dpm_table(struct pp_hwmgr *hwmgr)
537 struct vega20_hwmgr *data =
538 (struct vega20_hwmgr *)(hwmgr->backend);
539 struct vega20_single_dpm_table *dpm_table;
542 dpm_table = &(data->dpm_table.gfx_table);
543 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
544 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
545 PP_ASSERT_WITH_CODE(!ret,
546 "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!",
549 dpm_table->count = 1;
550 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100;
556 static int vega20_setup_memclk_dpm_table(struct pp_hwmgr *hwmgr)
558 struct vega20_hwmgr *data =
559 (struct vega20_hwmgr *)(hwmgr->backend);
560 struct vega20_single_dpm_table *dpm_table;
563 dpm_table = &(data->dpm_table.mem_table);
564 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
565 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
566 PP_ASSERT_WITH_CODE(!ret,
567 "[SetupDefaultDpmTable] failed to get memclk dpm levels!",
570 dpm_table->count = 1;
571 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100;
578 * This function is to initialize all DPM state tables
579 * for SMU based on the dependency table.
580 * Dynamic state patching function will then trim these
581 * state tables to the allowed range based
582 * on the power policy or external client requests,
583 * such as UVD request, etc.
585 static int vega20_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
587 struct vega20_hwmgr *data =
588 (struct vega20_hwmgr *)(hwmgr->backend);
589 struct vega20_single_dpm_table *dpm_table;
592 memset(&data->dpm_table, 0, sizeof(data->dpm_table));
595 dpm_table = &(data->dpm_table.soc_table);
596 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
597 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK);
598 PP_ASSERT_WITH_CODE(!ret,
599 "[SetupDefaultDpmTable] failed to get socclk dpm levels!",
602 dpm_table->count = 1;
603 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100;
605 vega20_init_dpm_state(&(dpm_table->dpm_state));
608 dpm_table = &(data->dpm_table.gfx_table);
609 ret = vega20_setup_gfxclk_dpm_table(hwmgr);
612 vega20_init_dpm_state(&(dpm_table->dpm_state));
615 dpm_table = &(data->dpm_table.mem_table);
616 ret = vega20_setup_memclk_dpm_table(hwmgr);
619 vega20_init_dpm_state(&(dpm_table->dpm_state));
622 dpm_table = &(data->dpm_table.eclk_table);
623 if (data->smu_features[GNLD_DPM_VCE].enabled) {
624 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK);
625 PP_ASSERT_WITH_CODE(!ret,
626 "[SetupDefaultDpmTable] failed to get eclk dpm levels!",
629 dpm_table->count = 1;
630 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100;
632 vega20_init_dpm_state(&(dpm_table->dpm_state));
635 dpm_table = &(data->dpm_table.vclk_table);
636 if (data->smu_features[GNLD_DPM_UVD].enabled) {
637 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
638 PP_ASSERT_WITH_CODE(!ret,
639 "[SetupDefaultDpmTable] failed to get vclk dpm levels!",
642 dpm_table->count = 1;
643 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100;
645 vega20_init_dpm_state(&(dpm_table->dpm_state));
648 dpm_table = &(data->dpm_table.dclk_table);
649 if (data->smu_features[GNLD_DPM_UVD].enabled) {
650 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK);
651 PP_ASSERT_WITH_CODE(!ret,
652 "[SetupDefaultDpmTable] failed to get dclk dpm levels!",
655 dpm_table->count = 1;
656 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100;
658 vega20_init_dpm_state(&(dpm_table->dpm_state));
661 dpm_table = &(data->dpm_table.dcef_table);
662 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
663 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK);
664 PP_ASSERT_WITH_CODE(!ret,
665 "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!",
668 dpm_table->count = 1;
669 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100;
671 vega20_init_dpm_state(&(dpm_table->dpm_state));
674 dpm_table = &(data->dpm_table.pixel_table);
675 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
676 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK);
677 PP_ASSERT_WITH_CODE(!ret,
678 "[SetupDefaultDpmTable] failed to get pixclk dpm levels!",
681 dpm_table->count = 0;
682 vega20_init_dpm_state(&(dpm_table->dpm_state));
685 dpm_table = &(data->dpm_table.display_table);
686 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
687 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
688 PP_ASSERT_WITH_CODE(!ret,
689 "[SetupDefaultDpmTable] failed to get dispclk dpm levels!",
692 dpm_table->count = 0;
693 vega20_init_dpm_state(&(dpm_table->dpm_state));
696 dpm_table = &(data->dpm_table.phy_table);
697 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
698 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
699 PP_ASSERT_WITH_CODE(!ret,
700 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!",
703 dpm_table->count = 0;
704 vega20_init_dpm_state(&(dpm_table->dpm_state));
707 dpm_table = &(data->dpm_table.fclk_table);
708 if (data->smu_features[GNLD_DPM_FCLK].enabled) {
709 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_FCLK);
710 PP_ASSERT_WITH_CODE(!ret,
711 "[SetupDefaultDpmTable] failed to get fclk dpm levels!",
714 dpm_table->count = 0;
715 vega20_init_dpm_state(&(dpm_table->dpm_state));
717 /* save a copy of the default DPM table */
718 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
719 sizeof(struct vega20_dpm_table));
725 * Initializes the SMC table and uploads it
727 * @param hwmgr the address of the powerplay hardware manager.
728 * @param pInput the pointer to input data (PowerState)
731 static int vega20_init_smc_table(struct pp_hwmgr *hwmgr)
734 struct vega20_hwmgr *data =
735 (struct vega20_hwmgr *)(hwmgr->backend);
736 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
737 struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
738 struct phm_ppt_v3_information *pptable_information =
739 (struct phm_ppt_v3_information *)hwmgr->pptable;
741 result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
742 PP_ASSERT_WITH_CODE(!result,
743 "[InitSMCTable] Failed to get vbios bootup values!",
746 data->vbios_boot_state.vddc = boot_up_values.usVddc;
747 data->vbios_boot_state.vddci = boot_up_values.usVddci;
748 data->vbios_boot_state.mvddc = boot_up_values.usMvddc;
749 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
750 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
751 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
752 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
753 data->vbios_boot_state.eclock = boot_up_values.ulEClk;
754 data->vbios_boot_state.vclock = boot_up_values.ulVClk;
755 data->vbios_boot_state.dclock = boot_up_values.ulDClk;
756 data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID;
758 smum_send_msg_to_smc_with_parameter(hwmgr,
759 PPSMC_MSG_SetMinDeepSleepDcefclk,
760 (uint32_t)(data->vbios_boot_state.dcef_clock / 100));
762 memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
764 result = smum_smc_table_manager(hwmgr,
765 (uint8_t *)pp_table, TABLE_PPTABLE, false);
766 PP_ASSERT_WITH_CODE(!result,
767 "[InitSMCTable] Failed to upload PPtable!",
773 static int vega20_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
775 struct vega20_hwmgr *data =
776 (struct vega20_hwmgr *)(hwmgr->backend);
777 uint32_t allowed_features_low = 0, allowed_features_high = 0;
781 for (i = 0; i < GNLD_FEATURES_MAX; i++)
782 if (data->smu_features[i].allowed)
783 data->smu_features[i].smu_feature_id > 31 ?
784 (allowed_features_high |=
785 ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT)
787 (allowed_features_low |=
788 ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT)
791 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
792 PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high);
793 PP_ASSERT_WITH_CODE(!ret,
794 "[SetAllowedFeaturesMask] Attempt to set allowed features mask(high) failed!",
797 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
798 PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low);
799 PP_ASSERT_WITH_CODE(!ret,
800 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!",
806 static int vega20_run_btc_afll(struct pp_hwmgr *hwmgr)
808 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAfllBtc);
811 static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr)
813 struct vega20_hwmgr *data =
814 (struct vega20_hwmgr *)(hwmgr->backend);
815 uint64_t features_enabled;
820 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
821 PPSMC_MSG_EnableAllSmuFeatures)) == 0,
822 "[EnableAllSMUFeatures] Failed to enable all smu features!",
825 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
826 PP_ASSERT_WITH_CODE(!ret,
827 "[EnableAllSmuFeatures] Failed to get enabled smc features!",
830 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
831 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
833 data->smu_features[i].enabled = enabled;
834 data->smu_features[i].supported = enabled;
837 if (data->smu_features[i].allowed && !enabled)
838 pr_info("[EnableAllSMUFeatures] feature %d is expected enabled!", i);
839 else if (!data->smu_features[i].allowed && enabled)
840 pr_info("[EnableAllSMUFeatures] feature %d is expected disabled!", i);
847 static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr)
849 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
851 if (data->smu_features[GNLD_DPM_UCLK].enabled)
852 return smum_send_msg_to_smc_with_parameter(hwmgr,
853 PPSMC_MSG_SetUclkFastSwitch,
859 static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr)
861 struct vega20_hwmgr *data =
862 (struct vega20_hwmgr *)(hwmgr->backend);
864 return smum_send_msg_to_smc_with_parameter(hwmgr,
865 PPSMC_MSG_SetFclkGfxClkRatio,
866 data->registry_data.fclk_gfxclk_ratio);
869 static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr)
871 struct vega20_hwmgr *data =
872 (struct vega20_hwmgr *)(hwmgr->backend);
873 uint64_t features_enabled;
878 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
879 PPSMC_MSG_DisableAllSmuFeatures)) == 0,
880 "[DisableAllSMUFeatures] Failed to disable all smu features!",
883 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
884 PP_ASSERT_WITH_CODE(!ret,
885 "[DisableAllSMUFeatures] Failed to get enabled smc features!",
888 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
889 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
891 data->smu_features[i].enabled = enabled;
892 data->smu_features[i].supported = enabled;
898 static int vega20_od8_set_feature_capabilities(
899 struct pp_hwmgr *hwmgr)
901 struct phm_ppt_v3_information *pptable_information =
902 (struct phm_ppt_v3_information *)hwmgr->pptable;
903 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
904 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
905 struct vega20_od8_settings *od_settings = &(data->od8_settings);
907 od_settings->overdrive8_capabilities = 0;
909 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
910 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
911 pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
912 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
913 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
914 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN]))
915 od_settings->overdrive8_capabilities |= OD8_GFXCLK_LIMITS;
917 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
918 (pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
919 pp_table->MinVoltageGfx / VOLTAGE_SCALE) &&
920 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
921 pp_table->MaxVoltageGfx / VOLTAGE_SCALE) &&
922 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] >=
923 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1]))
924 od_settings->overdrive8_capabilities |= OD8_GFXCLK_CURVE;
927 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
928 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
929 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
930 pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
931 (pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
932 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX]))
933 od_settings->overdrive8_capabilities |= OD8_UCLK_MAX;
936 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
937 pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
938 pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
939 pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
940 pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100)
941 od_settings->overdrive8_capabilities |= OD8_POWER_LIMIT;
943 if (data->smu_features[GNLD_FAN_CONTROL].enabled) {
944 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
945 pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
946 pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
947 (pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
948 pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT]))
949 od_settings->overdrive8_capabilities |= OD8_ACOUSTIC_LIMIT_SCLK;
951 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
952 (pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] >=
953 (pp_table->FanPwmMin * pp_table->FanMaximumRpm / 100)) &&
954 pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
955 (pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
956 pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED]))
957 od_settings->overdrive8_capabilities |= OD8_FAN_SPEED_MIN;
960 if (data->smu_features[GNLD_THERMAL].enabled) {
961 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
962 pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
963 pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
964 (pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
965 pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP]))
966 od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_FAN;
968 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
969 pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
970 pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
971 (pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
972 pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX]))
973 od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_SYSTEM;
976 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_MEMORY_TIMING_TUNE])
977 od_settings->overdrive8_capabilities |= OD8_MEMORY_TIMING_TUNE;
979 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ZERO_RPM_CONTROL] &&
980 pp_table->FanZeroRpmEnable)
981 od_settings->overdrive8_capabilities |= OD8_FAN_ZERO_RPM_CONTROL;
986 static int vega20_od8_set_feature_id(
987 struct pp_hwmgr *hwmgr)
989 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
990 struct vega20_od8_settings *od_settings = &(data->od8_settings);
992 if (od_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
993 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
995 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
998 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1000 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1004 if (od_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1005 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1007 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1009 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1011 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1013 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1015 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1018 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1020 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1022 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1024 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1026 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1028 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1032 if (od_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1033 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = OD8_UCLK_MAX;
1035 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = 0;
1037 if (od_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1038 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = OD8_POWER_LIMIT;
1040 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = 0;
1042 if (od_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1043 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1044 OD8_ACOUSTIC_LIMIT_SCLK;
1046 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1049 if (od_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1050 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1053 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1056 if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1057 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1058 OD8_TEMPERATURE_FAN;
1060 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1063 if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1064 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1065 OD8_TEMPERATURE_SYSTEM;
1067 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1073 static int vega20_od8_get_gfx_clock_base_voltage(
1074 struct pp_hwmgr *hwmgr,
1080 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1081 PPSMC_MSG_GetAVFSVoltageByDpm,
1082 ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq));
1083 PP_ASSERT_WITH_CODE(!ret,
1084 "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!",
1087 *voltage = smum_get_argument(hwmgr);
1088 *voltage = *voltage / VOLTAGE_SCALE;
1093 static int vega20_od8_initialize_default_settings(
1094 struct pp_hwmgr *hwmgr)
1096 struct phm_ppt_v3_information *pptable_information =
1097 (struct phm_ppt_v3_information *)hwmgr->pptable;
1098 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1099 struct vega20_od8_settings *od8_settings = &(data->od8_settings);
1100 OverDriveTable_t *od_table = &(data->smc_state_table.overdrive_table);
1103 /* Set Feature Capabilities */
1104 vega20_od8_set_feature_capabilities(hwmgr);
1106 /* Map FeatureID to individual settings */
1107 vega20_od8_set_feature_id(hwmgr);
1109 /* Set default values */
1110 ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, true);
1111 PP_ASSERT_WITH_CODE(!ret,
1112 "Failed to export over drive table!",
1115 if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
1116 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1117 od_table->GfxclkFmin;
1118 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1119 od_table->GfxclkFmax;
1121 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1123 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1127 if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1128 od_table->GfxclkFreq1 = od_table->GfxclkFmin;
1129 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1130 od_table->GfxclkFreq1;
1132 od_table->GfxclkFreq3 = od_table->GfxclkFmax;
1133 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1134 od_table->GfxclkFreq3;
1136 od_table->GfxclkFreq2 = (od_table->GfxclkFreq1 + od_table->GfxclkFreq3) / 2;
1137 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1138 od_table->GfxclkFreq2;
1140 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1141 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value),
1142 od_table->GfxclkFreq1),
1143 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1144 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0);
1145 od_table->GfxclkVolt1 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
1148 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1149 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value),
1150 od_table->GfxclkFreq2),
1151 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1152 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0);
1153 od_table->GfxclkVolt2 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
1156 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1157 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value),
1158 od_table->GfxclkFreq3),
1159 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1160 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0);
1161 od_table->GfxclkVolt3 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
1164 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1166 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value =
1168 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1170 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value =
1172 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1174 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value =
1178 if (od8_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1179 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1182 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1185 if (od8_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1186 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1187 od_table->OverDrivePct;
1189 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1192 if (od8_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1193 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1194 od_table->FanMaximumRpm;
1196 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1199 if (od8_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1200 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1201 od_table->FanMinimumPwm * data->smc_state_table.pp_table.FanMaximumRpm / 100;
1203 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1206 if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1207 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1208 od_table->FanTargetTemperature;
1210 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1213 if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1214 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1215 od_table->MaxOpTemp;
1217 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1220 for (i = 0; i < OD8_SETTING_COUNT; i++) {
1221 if (od8_settings->od8_settings_array[i].feature_id) {
1222 od8_settings->od8_settings_array[i].min_value =
1223 pptable_information->od_settings_min[i];
1224 od8_settings->od8_settings_array[i].max_value =
1225 pptable_information->od_settings_max[i];
1226 od8_settings->od8_settings_array[i].current_value =
1227 od8_settings->od8_settings_array[i].default_value;
1229 od8_settings->od8_settings_array[i].min_value =
1231 od8_settings->od8_settings_array[i].max_value =
1233 od8_settings->od8_settings_array[i].current_value =
1238 ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, false);
1239 PP_ASSERT_WITH_CODE(!ret,
1240 "Failed to import over drive table!",
1246 static int vega20_od8_set_settings(
1247 struct pp_hwmgr *hwmgr,
1251 OverDriveTable_t od_table;
1253 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1254 struct vega20_od8_single_setting *od8_settings =
1255 data->od8_settings.od8_settings_array;
1257 ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, true);
1258 PP_ASSERT_WITH_CODE(!ret,
1259 "Failed to export over drive table!",
1263 case OD8_SETTING_GFXCLK_FMIN:
1264 od_table.GfxclkFmin = (uint16_t)value;
1266 case OD8_SETTING_GFXCLK_FMAX:
1267 if (value < od8_settings[OD8_SETTING_GFXCLK_FMAX].min_value ||
1268 value > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value)
1271 od_table.GfxclkFmax = (uint16_t)value;
1273 case OD8_SETTING_GFXCLK_FREQ1:
1274 od_table.GfxclkFreq1 = (uint16_t)value;
1276 case OD8_SETTING_GFXCLK_VOLTAGE1:
1277 od_table.GfxclkVolt1 = (uint16_t)value;
1279 case OD8_SETTING_GFXCLK_FREQ2:
1280 od_table.GfxclkFreq2 = (uint16_t)value;
1282 case OD8_SETTING_GFXCLK_VOLTAGE2:
1283 od_table.GfxclkVolt2 = (uint16_t)value;
1285 case OD8_SETTING_GFXCLK_FREQ3:
1286 od_table.GfxclkFreq3 = (uint16_t)value;
1288 case OD8_SETTING_GFXCLK_VOLTAGE3:
1289 od_table.GfxclkVolt3 = (uint16_t)value;
1291 case OD8_SETTING_UCLK_FMAX:
1292 if (value < od8_settings[OD8_SETTING_UCLK_FMAX].min_value ||
1293 value > od8_settings[OD8_SETTING_UCLK_FMAX].max_value)
1295 od_table.UclkFmax = (uint16_t)value;
1297 case OD8_SETTING_POWER_PERCENTAGE:
1298 od_table.OverDrivePct = (int16_t)value;
1300 case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
1301 od_table.FanMaximumRpm = (uint16_t)value;
1303 case OD8_SETTING_FAN_MIN_SPEED:
1304 od_table.FanMinimumPwm = (uint16_t)value;
1306 case OD8_SETTING_FAN_TARGET_TEMP:
1307 od_table.FanTargetTemperature = (uint16_t)value;
1309 case OD8_SETTING_OPERATING_TEMP_MAX:
1310 od_table.MaxOpTemp = (uint16_t)value;
1314 ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, false);
1315 PP_ASSERT_WITH_CODE(!ret,
1316 "Failed to import over drive table!",
1322 static int vega20_get_sclk_od(
1323 struct pp_hwmgr *hwmgr)
1325 struct vega20_hwmgr *data = hwmgr->backend;
1326 struct vega20_single_dpm_table *sclk_table =
1327 &(data->dpm_table.gfx_table);
1328 struct vega20_single_dpm_table *golden_sclk_table =
1329 &(data->golden_dpm_table.gfx_table);
1330 int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
1331 int golden_value = golden_sclk_table->dpm_levels
1332 [golden_sclk_table->count - 1].value;
1335 value -= golden_value;
1336 value = DIV_ROUND_UP(value * 100, golden_value);
1341 static int vega20_set_sclk_od(
1342 struct pp_hwmgr *hwmgr, uint32_t value)
1344 struct vega20_hwmgr *data = hwmgr->backend;
1345 struct vega20_single_dpm_table *golden_sclk_table =
1346 &(data->golden_dpm_table.gfx_table);
1350 od_sclk = golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * value;
1352 od_sclk += golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
1354 ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_GFXCLK_FMAX, od_sclk);
1355 PP_ASSERT_WITH_CODE(!ret,
1356 "[SetSclkOD] failed to set od gfxclk!",
1359 /* retrieve updated gfxclk table */
1360 ret = vega20_setup_gfxclk_dpm_table(hwmgr);
1361 PP_ASSERT_WITH_CODE(!ret,
1362 "[SetSclkOD] failed to refresh gfxclk table!",
1368 static int vega20_get_mclk_od(
1369 struct pp_hwmgr *hwmgr)
1371 struct vega20_hwmgr *data = hwmgr->backend;
1372 struct vega20_single_dpm_table *mclk_table =
1373 &(data->dpm_table.mem_table);
1374 struct vega20_single_dpm_table *golden_mclk_table =
1375 &(data->golden_dpm_table.mem_table);
1376 int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
1377 int golden_value = golden_mclk_table->dpm_levels
1378 [golden_mclk_table->count - 1].value;
1381 value -= golden_value;
1382 value = DIV_ROUND_UP(value * 100, golden_value);
1387 static int vega20_set_mclk_od(
1388 struct pp_hwmgr *hwmgr, uint32_t value)
1390 struct vega20_hwmgr *data = hwmgr->backend;
1391 struct vega20_single_dpm_table *golden_mclk_table =
1392 &(data->golden_dpm_table.mem_table);
1396 od_mclk = golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * value;
1398 od_mclk += golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
1400 ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_UCLK_FMAX, od_mclk);
1401 PP_ASSERT_WITH_CODE(!ret,
1402 "[SetMclkOD] failed to set od memclk!",
1405 /* retrieve updated memclk table */
1406 ret = vega20_setup_memclk_dpm_table(hwmgr);
1407 PP_ASSERT_WITH_CODE(!ret,
1408 "[SetMclkOD] failed to refresh memclk table!",
1414 static int vega20_populate_umdpstate_clocks(
1415 struct pp_hwmgr *hwmgr)
1417 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1418 struct vega20_single_dpm_table *gfx_table = &(data->dpm_table.gfx_table);
1419 struct vega20_single_dpm_table *mem_table = &(data->dpm_table.mem_table);
1421 hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value;
1422 hwmgr->pstate_mclk = mem_table->dpm_levels[0].value;
1424 if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
1425 mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
1426 hwmgr->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
1427 hwmgr->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
1430 hwmgr->pstate_sclk = hwmgr->pstate_sclk * 100;
1431 hwmgr->pstate_mclk = hwmgr->pstate_mclk * 100;
1436 static int vega20_get_max_sustainable_clock(struct pp_hwmgr *hwmgr,
1437 PP_Clock *clock, PPCLK_e clock_select)
1441 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1442 PPSMC_MSG_GetDcModeMaxDpmFreq,
1443 (clock_select << 16))) == 0,
1444 "[GetMaxSustainableClock] Failed to get max DC clock from SMC!",
1446 *clock = smum_get_argument(hwmgr);
1448 /* if DC limit is zero, return AC limit */
1450 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1451 PPSMC_MSG_GetMaxDpmFreq,
1452 (clock_select << 16))) == 0,
1453 "[GetMaxSustainableClock] failed to get max AC clock from SMC!",
1455 *clock = smum_get_argument(hwmgr);
1461 static int vega20_init_max_sustainable_clocks(struct pp_hwmgr *hwmgr)
1463 struct vega20_hwmgr *data =
1464 (struct vega20_hwmgr *)(hwmgr->backend);
1465 struct vega20_max_sustainable_clocks *max_sustainable_clocks =
1466 &(data->max_sustainable_clocks);
1469 max_sustainable_clocks->uclock = data->vbios_boot_state.mem_clock / 100;
1470 max_sustainable_clocks->soc_clock = data->vbios_boot_state.soc_clock / 100;
1471 max_sustainable_clocks->dcef_clock = data->vbios_boot_state.dcef_clock / 100;
1472 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
1473 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
1474 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
1476 if (data->smu_features[GNLD_DPM_UCLK].enabled)
1477 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1478 &(max_sustainable_clocks->uclock),
1480 "[InitMaxSustainableClocks] failed to get max UCLK from SMC!",
1483 if (data->smu_features[GNLD_DPM_SOCCLK].enabled)
1484 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1485 &(max_sustainable_clocks->soc_clock),
1486 PPCLK_SOCCLK)) == 0,
1487 "[InitMaxSustainableClocks] failed to get max SOCCLK from SMC!",
1490 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1491 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1492 &(max_sustainable_clocks->dcef_clock),
1493 PPCLK_DCEFCLK)) == 0,
1494 "[InitMaxSustainableClocks] failed to get max DCEFCLK from SMC!",
1496 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1497 &(max_sustainable_clocks->display_clock),
1498 PPCLK_DISPCLK)) == 0,
1499 "[InitMaxSustainableClocks] failed to get max DISPCLK from SMC!",
1501 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1502 &(max_sustainable_clocks->phy_clock),
1503 PPCLK_PHYCLK)) == 0,
1504 "[InitMaxSustainableClocks] failed to get max PHYCLK from SMC!",
1506 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1507 &(max_sustainable_clocks->pixel_clock),
1508 PPCLK_PIXCLK)) == 0,
1509 "[InitMaxSustainableClocks] failed to get max PIXCLK from SMC!",
1513 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1514 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1519 static int vega20_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
1523 result = smum_send_msg_to_smc(hwmgr,
1524 PPSMC_MSG_SetMGpuFanBoostLimitRpm);
1525 PP_ASSERT_WITH_CODE(!result,
1526 "[EnableMgpuFan] Failed to enable mgpu fan boost!",
1532 static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr)
1534 struct vega20_hwmgr *data =
1535 (struct vega20_hwmgr *)(hwmgr->backend);
1537 data->uvd_power_gated = true;
1538 data->vce_power_gated = true;
1540 if (data->smu_features[GNLD_DPM_UVD].enabled)
1541 data->uvd_power_gated = false;
1543 if (data->smu_features[GNLD_DPM_VCE].enabled)
1544 data->vce_power_gated = false;
1547 static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1551 smum_send_msg_to_smc_with_parameter(hwmgr,
1552 PPSMC_MSG_NumOfDisplays, 0);
1554 result = vega20_set_allowed_featuresmask(hwmgr);
1555 PP_ASSERT_WITH_CODE(!result,
1556 "[EnableDPMTasks] Failed to set allowed featuresmask!\n",
1559 result = vega20_init_smc_table(hwmgr);
1560 PP_ASSERT_WITH_CODE(!result,
1561 "[EnableDPMTasks] Failed to initialize SMC table!",
1564 result = vega20_run_btc_afll(hwmgr);
1565 PP_ASSERT_WITH_CODE(!result,
1566 "[EnableDPMTasks] Failed to run btc afll!",
1569 result = vega20_enable_all_smu_features(hwmgr);
1570 PP_ASSERT_WITH_CODE(!result,
1571 "[EnableDPMTasks] Failed to enable all smu features!",
1574 result = vega20_notify_smc_display_change(hwmgr);
1575 PP_ASSERT_WITH_CODE(!result,
1576 "[EnableDPMTasks] Failed to notify smc display change!",
1579 result = vega20_send_clock_ratio(hwmgr);
1580 PP_ASSERT_WITH_CODE(!result,
1581 "[EnableDPMTasks] Failed to send clock ratio!",
1584 /* Initialize UVD/VCE powergating state */
1585 vega20_init_powergate_state(hwmgr);
1587 result = vega20_setup_default_dpm_tables(hwmgr);
1588 PP_ASSERT_WITH_CODE(!result,
1589 "[EnableDPMTasks] Failed to setup default DPM tables!",
1592 result = vega20_init_max_sustainable_clocks(hwmgr);
1593 PP_ASSERT_WITH_CODE(!result,
1594 "[EnableDPMTasks] Failed to get maximum sustainable clocks!",
1597 result = vega20_power_control_set_level(hwmgr);
1598 PP_ASSERT_WITH_CODE(!result,
1599 "[EnableDPMTasks] Failed to power control set level!",
1602 result = vega20_od8_initialize_default_settings(hwmgr);
1603 PP_ASSERT_WITH_CODE(!result,
1604 "[EnableDPMTasks] Failed to initialize odn settings!",
1607 result = vega20_populate_umdpstate_clocks(hwmgr);
1608 PP_ASSERT_WITH_CODE(!result,
1609 "[EnableDPMTasks] Failed to populate umdpstate clocks!",
1612 result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetPptLimit,
1613 POWER_SOURCE_AC << 16);
1614 PP_ASSERT_WITH_CODE(!result,
1615 "[GetPptLimit] get default PPT limit failed!",
1617 hwmgr->power_limit =
1618 hwmgr->default_power_limit = smum_get_argument(hwmgr);
1623 static uint32_t vega20_find_lowest_dpm_level(
1624 struct vega20_single_dpm_table *table)
1628 for (i = 0; i < table->count; i++) {
1629 if (table->dpm_levels[i].enabled)
1632 if (i >= table->count) {
1634 table->dpm_levels[i].enabled = true;
1640 static uint32_t vega20_find_highest_dpm_level(
1641 struct vega20_single_dpm_table *table)
1645 PP_ASSERT_WITH_CODE(table != NULL,
1646 "[FindHighestDPMLevel] DPM Table does not exist!",
1648 PP_ASSERT_WITH_CODE(table->count > 0,
1649 "[FindHighestDPMLevel] DPM Table has no entry!",
1651 PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
1652 "[FindHighestDPMLevel] DPM Table has too many entries!",
1653 return MAX_REGULAR_DPM_NUMBER - 1);
1655 for (i = table->count - 1; i >= 0; i--) {
1656 if (table->dpm_levels[i].enabled)
1661 table->dpm_levels[i].enabled = true;
1667 static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
1669 struct vega20_hwmgr *data =
1670 (struct vega20_hwmgr *)(hwmgr->backend);
1674 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1675 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
1676 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1677 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1678 (PPCLK_GFXCLK << 16) | (min_freq & 0xffff))),
1679 "Failed to set soft min gfxclk !",
1683 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1684 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
1685 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1686 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1687 (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
1688 "Failed to set soft min memclk !",
1691 min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level;
1692 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1693 hwmgr, PPSMC_MSG_SetHardMinByFreq,
1694 (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
1695 "Failed to set hard min memclk !",
1699 if (data->smu_features[GNLD_DPM_UVD].enabled) {
1700 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
1702 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1703 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1704 (PPCLK_VCLK << 16) | (min_freq & 0xffff))),
1705 "Failed to set soft min vclk!",
1708 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level;
1710 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1711 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1712 (PPCLK_DCLK << 16) | (min_freq & 0xffff))),
1713 "Failed to set soft min dclk!",
1717 if (data->smu_features[GNLD_DPM_VCE].enabled) {
1718 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
1720 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1721 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1722 (PPCLK_ECLK << 16) | (min_freq & 0xffff))),
1723 "Failed to set soft min eclk!",
1727 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
1728 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
1730 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1731 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1732 (PPCLK_SOCCLK << 16) | (min_freq & 0xffff))),
1733 "Failed to set soft min socclk!",
1740 static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
1742 struct vega20_hwmgr *data =
1743 (struct vega20_hwmgr *)(hwmgr->backend);
1747 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1748 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
1750 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1751 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1752 (PPCLK_GFXCLK << 16) | (max_freq & 0xffff))),
1753 "Failed to set soft max gfxclk!",
1757 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1758 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
1760 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1761 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1762 (PPCLK_UCLK << 16) | (max_freq & 0xffff))),
1763 "Failed to set soft max memclk!",
1767 if (data->smu_features[GNLD_DPM_UVD].enabled) {
1768 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
1770 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1771 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1772 (PPCLK_VCLK << 16) | (max_freq & 0xffff))),
1773 "Failed to set soft max vclk!",
1776 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level;
1777 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1778 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1779 (PPCLK_DCLK << 16) | (max_freq & 0xffff))),
1780 "Failed to set soft max dclk!",
1784 if (data->smu_features[GNLD_DPM_VCE].enabled) {
1785 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
1787 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1788 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1789 (PPCLK_ECLK << 16) | (max_freq & 0xffff))),
1790 "Failed to set soft max eclk!",
1794 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
1795 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
1797 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1798 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1799 (PPCLK_SOCCLK << 16) | (max_freq & 0xffff))),
1800 "Failed to set soft max socclk!",
1807 int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
1809 struct vega20_hwmgr *data =
1810 (struct vega20_hwmgr *)(hwmgr->backend);
1813 if (data->smu_features[GNLD_DPM_VCE].supported) {
1814 if (data->smu_features[GNLD_DPM_VCE].enabled == enable) {
1816 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already enabled!\n");
1818 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already disabled!\n");
1821 ret = vega20_enable_smc_features(hwmgr,
1823 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap);
1824 PP_ASSERT_WITH_CODE(!ret,
1825 "Attempt to Enable/Disable DPM VCE Failed!",
1827 data->smu_features[GNLD_DPM_VCE].enabled = enable;
1833 static int vega20_get_clock_ranges(struct pp_hwmgr *hwmgr,
1835 PPCLK_e clock_select,
1842 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1843 PPSMC_MSG_GetMaxDpmFreq, (clock_select << 16))) == 0,
1844 "[GetClockRanges] Failed to get max clock from SMC!",
1846 *clock = smum_get_argument(hwmgr);
1848 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1849 PPSMC_MSG_GetMinDpmFreq,
1850 (clock_select << 16))) == 0,
1851 "[GetClockRanges] Failed to get min clock from SMC!",
1853 *clock = smum_get_argument(hwmgr);
1859 static uint32_t vega20_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1861 struct vega20_hwmgr *data =
1862 (struct vega20_hwmgr *)(hwmgr->backend);
1866 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,
1867 "[GetSclks]: gfxclk dpm not enabled!\n",
1871 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false);
1872 PP_ASSERT_WITH_CODE(!ret,
1873 "[GetSclks]: fail to get min PPCLK_GFXCLK\n",
1876 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true);
1877 PP_ASSERT_WITH_CODE(!ret,
1878 "[GetSclks]: fail to get max PPCLK_GFXCLK\n",
1882 return (gfx_clk * 100);
1885 static uint32_t vega20_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1887 struct vega20_hwmgr *data =
1888 (struct vega20_hwmgr *)(hwmgr->backend);
1892 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,
1893 "[MemMclks]: memclk dpm not enabled!\n",
1897 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false);
1898 PP_ASSERT_WITH_CODE(!ret,
1899 "[GetMclks]: fail to get min PPCLK_UCLK\n",
1902 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true);
1903 PP_ASSERT_WITH_CODE(!ret,
1904 "[GetMclks]: fail to get max PPCLK_UCLK\n",
1908 return (mem_clk * 100);
1911 static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr,
1915 SmuMetrics_t metrics_table;
1917 ret = smum_smc_table_manager(hwmgr, (uint8_t *)&metrics_table, TABLE_SMU_METRICS, true);
1918 PP_ASSERT_WITH_CODE(!ret,
1919 "Failed to export SMU METRICS table!",
1922 *query = metrics_table.CurrSocketPower << 8;
1927 static int vega20_get_current_clk_freq(struct pp_hwmgr *hwmgr,
1928 PPCLK_e clk_id, uint32_t *clk_freq)
1934 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1935 PPSMC_MSG_GetDpmClockFreq, (clk_id << 16))) == 0,
1936 "[GetCurrentClkFreq] Attempt to get Current Frequency Failed!",
1938 *clk_freq = smum_get_argument(hwmgr);
1940 *clk_freq = *clk_freq * 100;
1945 static int vega20_get_current_activity_percent(struct pp_hwmgr *hwmgr,
1946 uint32_t *activity_percent)
1949 SmuMetrics_t metrics_table;
1951 ret = smum_smc_table_manager(hwmgr, (uint8_t *)&metrics_table, TABLE_SMU_METRICS, true);
1952 PP_ASSERT_WITH_CODE(!ret,
1953 "Failed to export SMU METRICS table!",
1956 *activity_percent = metrics_table.AverageGfxActivity;
1961 static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1962 void *value, int *size)
1964 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1965 struct amdgpu_device *adev = hwmgr->adev;
1970 case AMDGPU_PP_SENSOR_GFX_SCLK:
1971 ret = vega20_get_current_clk_freq(hwmgr,
1977 case AMDGPU_PP_SENSOR_GFX_MCLK:
1978 ret = vega20_get_current_clk_freq(hwmgr,
1984 case AMDGPU_PP_SENSOR_GPU_LOAD:
1985 ret = vega20_get_current_activity_percent(hwmgr, (uint32_t *)value);
1989 case AMDGPU_PP_SENSOR_GPU_TEMP:
1990 *((uint32_t *)value) = vega20_thermal_get_temperature(hwmgr);
1993 case AMDGPU_PP_SENSOR_UVD_POWER:
1994 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
1997 case AMDGPU_PP_SENSOR_VCE_POWER:
1998 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
2001 case AMDGPU_PP_SENSOR_GPU_POWER:
2003 ret = vega20_get_gpu_power(hwmgr, (uint32_t *)value);
2005 case AMDGPU_PP_SENSOR_VDDGFX:
2006 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
2007 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
2008 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
2009 *((uint32_t *)value) =
2010 (uint32_t)convert_to_vddc((uint8_t)val_vid);
2012 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2013 ret = vega20_get_enabled_smc_features(hwmgr, (uint64_t *)value);
2024 int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
2025 struct pp_display_clock_request *clock_req)
2028 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2029 enum amd_pp_clock_type clk_type = clock_req->clock_type;
2030 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
2031 PPCLK_e clk_select = 0;
2032 uint32_t clk_request = 0;
2034 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
2036 case amd_pp_dcef_clock:
2037 clk_select = PPCLK_DCEFCLK;
2039 case amd_pp_disp_clock:
2040 clk_select = PPCLK_DISPCLK;
2042 case amd_pp_pixel_clock:
2043 clk_select = PPCLK_PIXCLK;
2045 case amd_pp_phy_clock:
2046 clk_select = PPCLK_PHYCLK;
2049 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
2055 clk_request = (clk_select << 16) | clk_freq;
2056 result = smum_send_msg_to_smc_with_parameter(hwmgr,
2057 PPSMC_MSG_SetHardMinByFreq,
2065 static int vega20_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
2066 PHM_PerformanceLevelDesignation designation, uint32_t index,
2067 PHM_PerformanceLevel *level)
2072 static int vega20_notify_smc_display_config_after_ps_adjustment(
2073 struct pp_hwmgr *hwmgr)
2075 struct vega20_hwmgr *data =
2076 (struct vega20_hwmgr *)(hwmgr->backend);
2077 struct vega20_single_dpm_table *dpm_table =
2078 &data->dpm_table.mem_table;
2079 struct PP_Clocks min_clocks = {0};
2080 struct pp_display_clock_request clock_req;
2083 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
2084 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
2085 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
2087 if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
2088 clock_req.clock_type = amd_pp_dcef_clock;
2089 clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10;
2090 if (!vega20_display_clock_voltage_request(hwmgr, &clock_req)) {
2091 if (data->smu_features[GNLD_DS_DCEFCLK].supported)
2092 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(
2093 hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
2094 min_clocks.dcefClockInSR / 100)) == 0,
2095 "Attempt to set divider for DCEFCLK Failed!",
2098 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
2102 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2103 dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100;
2104 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2105 PPSMC_MSG_SetHardMinByFreq,
2106 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
2107 "[SetHardMinFreq] Set hard min uclk failed!",
2114 static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr)
2116 struct vega20_hwmgr *data =
2117 (struct vega20_hwmgr *)(hwmgr->backend);
2118 uint32_t soft_level;
2121 soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table));
2123 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2124 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2125 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2127 soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.mem_table));
2129 data->dpm_table.mem_table.dpm_state.soft_min_level =
2130 data->dpm_table.mem_table.dpm_state.soft_max_level =
2131 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2133 ret = vega20_upload_dpm_min_level(hwmgr);
2134 PP_ASSERT_WITH_CODE(!ret,
2135 "Failed to upload boot level to highest!",
2138 ret = vega20_upload_dpm_max_level(hwmgr);
2139 PP_ASSERT_WITH_CODE(!ret,
2140 "Failed to upload dpm max level to highest!",
2146 static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2148 struct vega20_hwmgr *data =
2149 (struct vega20_hwmgr *)(hwmgr->backend);
2150 uint32_t soft_level;
2153 soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
2155 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2156 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2157 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2159 soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table));
2161 data->dpm_table.mem_table.dpm_state.soft_min_level =
2162 data->dpm_table.mem_table.dpm_state.soft_max_level =
2163 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2165 ret = vega20_upload_dpm_min_level(hwmgr);
2166 PP_ASSERT_WITH_CODE(!ret,
2167 "Failed to upload boot level to highest!",
2170 ret = vega20_upload_dpm_max_level(hwmgr);
2171 PP_ASSERT_WITH_CODE(!ret,
2172 "Failed to upload dpm max level to highest!",
2179 static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
2183 ret = vega20_upload_dpm_min_level(hwmgr);
2184 PP_ASSERT_WITH_CODE(!ret,
2185 "Failed to upload DPM Bootup Levels!",
2188 ret = vega20_upload_dpm_max_level(hwmgr);
2189 PP_ASSERT_WITH_CODE(!ret,
2190 "Failed to upload DPM Max Levels!",
2196 static int vega20_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
2197 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
2199 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2200 struct vega20_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table);
2201 struct vega20_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table);
2202 struct vega20_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table);
2208 if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
2209 mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
2210 soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
2211 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
2212 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
2213 *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
2216 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2218 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2220 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2221 *sclk_mask = gfx_dpm_table->count - 1;
2222 *mclk_mask = mem_dpm_table->count - 1;
2223 *soc_mask = soc_dpm_table->count - 1;
2229 static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
2230 enum pp_clock_type type, uint32_t mask)
2232 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2233 uint32_t soft_min_level, soft_max_level;
2238 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2239 soft_max_level = mask ? (fls(mask) - 1) : 0;
2241 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2242 data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
2243 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2244 data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
2246 ret = vega20_upload_dpm_min_level(hwmgr);
2247 PP_ASSERT_WITH_CODE(!ret,
2248 "Failed to upload boot level to lowest!",
2251 ret = vega20_upload_dpm_max_level(hwmgr);
2252 PP_ASSERT_WITH_CODE(!ret,
2253 "Failed to upload dpm max level to highest!",
2258 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2259 soft_max_level = mask ? (fls(mask) - 1) : 0;
2261 data->dpm_table.mem_table.dpm_state.soft_min_level =
2262 data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
2263 data->dpm_table.mem_table.dpm_state.soft_max_level =
2264 data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
2266 ret = vega20_upload_dpm_min_level(hwmgr);
2267 PP_ASSERT_WITH_CODE(!ret,
2268 "Failed to upload boot level to lowest!",
2271 ret = vega20_upload_dpm_max_level(hwmgr);
2272 PP_ASSERT_WITH_CODE(!ret,
2273 "Failed to upload dpm max level to highest!",
2279 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2280 soft_max_level = mask ? (fls(mask) - 1) : 0;
2281 if (soft_min_level >= NUM_LINK_LEVELS ||
2282 soft_max_level >= NUM_LINK_LEVELS)
2285 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2286 PPSMC_MSG_SetMinLinkDpmByIndex, soft_min_level);
2287 PP_ASSERT_WITH_CODE(!ret,
2288 "Failed to set min link dpm level!",
2300 static int vega20_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
2301 enum amd_dpm_forced_level level)
2304 uint32_t sclk_mask, mclk_mask, soc_mask;
2307 case AMD_DPM_FORCED_LEVEL_HIGH:
2308 ret = vega20_force_dpm_highest(hwmgr);
2311 case AMD_DPM_FORCED_LEVEL_LOW:
2312 ret = vega20_force_dpm_lowest(hwmgr);
2315 case AMD_DPM_FORCED_LEVEL_AUTO:
2316 ret = vega20_unforce_dpm_levels(hwmgr);
2319 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
2320 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
2321 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
2322 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
2323 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
2326 vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
2327 vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
2330 case AMD_DPM_FORCED_LEVEL_MANUAL:
2331 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
2339 static uint32_t vega20_get_fan_control_mode(struct pp_hwmgr *hwmgr)
2341 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2343 if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
2344 return AMD_FAN_CTRL_MANUAL;
2346 return AMD_FAN_CTRL_AUTO;
2349 static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
2352 case AMD_FAN_CTRL_NONE:
2353 vega20_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
2355 case AMD_FAN_CTRL_MANUAL:
2356 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2357 vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
2359 case AMD_FAN_CTRL_AUTO:
2360 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2361 vega20_fan_ctrl_start_smc_fan_control(hwmgr);
2368 static int vega20_get_dal_power_level(struct pp_hwmgr *hwmgr,
2369 struct amd_pp_simple_clock_info *info)
2372 struct phm_ppt_v2_information *table_info =
2373 (struct phm_ppt_v2_information *)hwmgr->pptable;
2374 struct phm_clock_and_voltage_limits *max_limits =
2375 &table_info->max_clock_voltage_on_ac;
2377 info->engine_max_clock = max_limits->sclk;
2378 info->memory_max_clock = max_limits->mclk;
2384 static int vega20_get_sclks(struct pp_hwmgr *hwmgr,
2385 struct pp_clock_levels_with_latency *clocks)
2387 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2388 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
2391 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,
2392 "[GetSclks]: gfxclk dpm not enabled!\n",
2395 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2396 clocks->num_levels = count;
2398 for (i = 0; i < count; i++) {
2399 clocks->data[i].clocks_in_khz =
2400 dpm_table->dpm_levels[i].value * 1000;
2401 clocks->data[i].latency_in_us = 0;
2407 static uint32_t vega20_get_mem_latency(struct pp_hwmgr *hwmgr,
2413 static int vega20_get_memclocks(struct pp_hwmgr *hwmgr,
2414 struct pp_clock_levels_with_latency *clocks)
2416 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2417 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.mem_table);
2420 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,
2421 "[GetMclks]: uclk dpm not enabled!\n",
2424 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2425 clocks->num_levels = data->mclk_latency_table.count = count;
2427 for (i = 0; i < count; i++) {
2428 clocks->data[i].clocks_in_khz =
2429 data->mclk_latency_table.entries[i].frequency =
2430 dpm_table->dpm_levels[i].value * 1000;
2431 clocks->data[i].latency_in_us =
2432 data->mclk_latency_table.entries[i].latency =
2433 vega20_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
2439 static int vega20_get_dcefclocks(struct pp_hwmgr *hwmgr,
2440 struct pp_clock_levels_with_latency *clocks)
2442 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2443 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.dcef_table);
2446 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_DCEFCLK].enabled,
2447 "[GetDcfclocks]: dcefclk dpm not enabled!\n",
2450 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2451 clocks->num_levels = count;
2453 for (i = 0; i < count; i++) {
2454 clocks->data[i].clocks_in_khz =
2455 dpm_table->dpm_levels[i].value * 1000;
2456 clocks->data[i].latency_in_us = 0;
2462 static int vega20_get_socclocks(struct pp_hwmgr *hwmgr,
2463 struct pp_clock_levels_with_latency *clocks)
2465 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2466 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.soc_table);
2469 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_SOCCLK].enabled,
2470 "[GetSocclks]: socclk dpm not enabled!\n",
2473 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2474 clocks->num_levels = count;
2476 for (i = 0; i < count; i++) {
2477 clocks->data[i].clocks_in_khz =
2478 dpm_table->dpm_levels[i].value * 1000;
2479 clocks->data[i].latency_in_us = 0;
2486 static int vega20_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
2487 enum amd_pp_clock_type type,
2488 struct pp_clock_levels_with_latency *clocks)
2493 case amd_pp_sys_clock:
2494 ret = vega20_get_sclks(hwmgr, clocks);
2496 case amd_pp_mem_clock:
2497 ret = vega20_get_memclocks(hwmgr, clocks);
2499 case amd_pp_dcef_clock:
2500 ret = vega20_get_dcefclocks(hwmgr, clocks);
2502 case amd_pp_soc_clock:
2503 ret = vega20_get_socclocks(hwmgr, clocks);
2512 static int vega20_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
2513 enum amd_pp_clock_type type,
2514 struct pp_clock_levels_with_voltage *clocks)
2516 clocks->num_levels = 0;
2521 static int vega20_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
2524 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2525 Watermarks_t *table = &(data->smc_state_table.water_marks_table);
2526 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
2528 if (!data->registry_data.disable_water_mark &&
2529 data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2530 data->smu_features[GNLD_DPM_SOCCLK].supported) {
2531 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
2532 data->water_marks_bitmap |= WaterMarksExist;
2533 data->water_marks_bitmap &= ~WaterMarksLoaded;
2539 static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
2540 enum PP_OD_DPM_TABLE_COMMAND type,
2541 long *input, uint32_t size)
2543 struct vega20_hwmgr *data =
2544 (struct vega20_hwmgr *)(hwmgr->backend);
2545 struct vega20_od8_single_setting *od8_settings =
2546 data->od8_settings.od8_settings_array;
2547 OverDriveTable_t *od_table =
2548 &(data->smc_state_table.overdrive_table);
2549 struct pp_clock_levels_with_latency clocks;
2550 int32_t input_index, input_clk, input_vol, i;
2554 PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
2558 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2559 if (!(od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2560 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
2561 pr_info("Sclk min/max frequency overdrive not supported\n");
2565 for (i = 0; i < size; i += 2) {
2567 pr_info("invalid number of input parameters %d\n",
2572 input_index = input[i];
2573 input_clk = input[i + 1];
2575 if (input_index != 0 && input_index != 1) {
2576 pr_info("Invalid index %d\n", input_index);
2577 pr_info("Support min/max sclk frequency setting only which index by 0/1\n");
2581 if (input_clk < od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value ||
2582 input_clk > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) {
2583 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2585 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
2586 od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
2590 if ((input_index == 0 && od_table->GfxclkFmin != input_clk) ||
2591 (input_index == 1 && od_table->GfxclkFmax != input_clk))
2592 data->gfxclk_overdrive = true;
2594 if (input_index == 0)
2595 od_table->GfxclkFmin = input_clk;
2597 od_table->GfxclkFmax = input_clk;
2602 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2603 if (!od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2604 pr_info("Mclk max frequency overdrive not supported\n");
2608 ret = vega20_get_memclocks(hwmgr, &clocks);
2609 PP_ASSERT_WITH_CODE(!ret,
2610 "Attempt to get memory clk levels failed!",
2613 for (i = 0; i < size; i += 2) {
2615 pr_info("invalid number of input parameters %d\n",
2620 input_index = input[i];
2621 input_clk = input[i + 1];
2623 if (input_index != 1) {
2624 pr_info("Invalid index %d\n", input_index);
2625 pr_info("Support max Mclk frequency setting only which index by 1\n");
2629 if (input_clk < clocks.data[0].clocks_in_khz / 1000 ||
2630 input_clk > od8_settings[OD8_SETTING_UCLK_FMAX].max_value) {
2631 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2633 clocks.data[0].clocks_in_khz / 1000,
2634 od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
2638 if (input_index == 1 && od_table->UclkFmax != input_clk)
2639 data->memclk_overdrive = true;
2641 od_table->UclkFmax = input_clk;
2646 case PP_OD_EDIT_VDDC_CURVE:
2647 if (!(od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2648 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2649 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2650 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2651 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2652 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
2653 pr_info("Voltage curve calibrate not supported\n");
2657 for (i = 0; i < size; i += 3) {
2659 pr_info("invalid number of input parameters %d\n",
2664 input_index = input[i];
2665 input_clk = input[i + 1];
2666 input_vol = input[i + 2];
2668 if (input_index > 2) {
2669 pr_info("Setting for point %d is not supported\n",
2671 pr_info("Three supported points index by 0, 1, 2\n");
2675 od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
2676 if (input_clk < od8_settings[od8_id].min_value ||
2677 input_clk > od8_settings[od8_id].max_value) {
2678 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2680 od8_settings[od8_id].min_value,
2681 od8_settings[od8_id].max_value);
2685 od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
2686 if (input_vol < od8_settings[od8_id].min_value ||
2687 input_vol > od8_settings[od8_id].max_value) {
2688 pr_info("clock voltage %d is not within allowed range [%d - %d]\n",
2690 od8_settings[od8_id].min_value,
2691 od8_settings[od8_id].max_value);
2695 switch (input_index) {
2697 od_table->GfxclkFreq1 = input_clk;
2698 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
2701 od_table->GfxclkFreq2 = input_clk;
2702 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
2705 od_table->GfxclkFreq3 = input_clk;
2706 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
2712 case PP_OD_RESTORE_DEFAULT_TABLE:
2713 data->gfxclk_overdrive = false;
2714 data->memclk_overdrive = false;
2716 ret = smum_smc_table_manager(hwmgr,
2717 (uint8_t *)od_table,
2718 TABLE_OVERDRIVE, true);
2719 PP_ASSERT_WITH_CODE(!ret,
2720 "Failed to export overdrive table!",
2724 case PP_OD_COMMIT_DPM_TABLE:
2725 ret = smum_smc_table_manager(hwmgr,
2726 (uint8_t *)od_table,
2727 TABLE_OVERDRIVE, false);
2728 PP_ASSERT_WITH_CODE(!ret,
2729 "Failed to import overdrive table!",
2732 /* retrieve updated gfxclk table */
2733 if (data->gfxclk_overdrive) {
2734 data->gfxclk_overdrive = false;
2736 ret = vega20_setup_gfxclk_dpm_table(hwmgr);
2741 /* retrieve updated memclk table */
2742 if (data->memclk_overdrive) {
2743 data->memclk_overdrive = false;
2745 ret = vega20_setup_memclk_dpm_table(hwmgr);
2758 static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
2759 enum pp_clock_type type, char *buf)
2761 struct vega20_hwmgr *data =
2762 (struct vega20_hwmgr *)(hwmgr->backend);
2763 struct vega20_od8_single_setting *od8_settings =
2764 data->od8_settings.od8_settings_array;
2765 OverDriveTable_t *od_table =
2766 &(data->smc_state_table.overdrive_table);
2767 struct phm_ppt_v3_information *pptable_information =
2768 (struct phm_ppt_v3_information *)hwmgr->pptable;
2769 PPTable_t *pptable = (PPTable_t *)pptable_information->smc_pptable;
2770 struct amdgpu_device *adev = hwmgr->adev;
2771 struct pp_clock_levels_with_latency clocks;
2772 int i, now, size = 0;
2774 uint32_t gen_speed, lane_width;
2778 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_GFXCLK, &now);
2779 PP_ASSERT_WITH_CODE(!ret,
2780 "Attempt to get current gfx clk Failed!",
2783 ret = vega20_get_sclks(hwmgr, &clocks);
2784 PP_ASSERT_WITH_CODE(!ret,
2785 "Attempt to get gfx clk levels Failed!",
2788 for (i = 0; i < clocks.num_levels; i++)
2789 size += sprintf(buf + size, "%d: %uMhz %s\n",
2790 i, clocks.data[i].clocks_in_khz / 1000,
2791 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
2795 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_UCLK, &now);
2796 PP_ASSERT_WITH_CODE(!ret,
2797 "Attempt to get current mclk freq Failed!",
2800 ret = vega20_get_memclocks(hwmgr, &clocks);
2801 PP_ASSERT_WITH_CODE(!ret,
2802 "Attempt to get memory clk levels Failed!",
2805 for (i = 0; i < clocks.num_levels; i++)
2806 size += sprintf(buf + size, "%d: %uMhz %s\n",
2807 i, clocks.data[i].clocks_in_khz / 1000,
2808 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
2812 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2813 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2814 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2815 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2816 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2817 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2818 for (i = 0; i < NUM_LINK_LEVELS; i++)
2819 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
2820 (pptable->PcieGenSpeed[i] == 0) ? "2.5GT/s," :
2821 (pptable->PcieGenSpeed[i] == 1) ? "5.0GT/s," :
2822 (pptable->PcieGenSpeed[i] == 2) ? "8.0GT/s," :
2823 (pptable->PcieGenSpeed[i] == 3) ? "16.0GT/s," : "",
2824 (pptable->PcieLaneCount[i] == 1) ? "x1" :
2825 (pptable->PcieLaneCount[i] == 2) ? "x2" :
2826 (pptable->PcieLaneCount[i] == 3) ? "x4" :
2827 (pptable->PcieLaneCount[i] == 4) ? "x8" :
2828 (pptable->PcieLaneCount[i] == 5) ? "x12" :
2829 (pptable->PcieLaneCount[i] == 6) ? "x16" : "",
2830 pptable->LclkFreq[i],
2831 (gen_speed == pptable->PcieGenSpeed[i]) &&
2832 (lane_width == pptable->PcieLaneCount[i]) ?
2837 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2838 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
2839 size = sprintf(buf, "%s:\n", "OD_SCLK");
2840 size += sprintf(buf + size, "0: %10uMhz\n",
2841 od_table->GfxclkFmin);
2842 size += sprintf(buf + size, "1: %10uMhz\n",
2843 od_table->GfxclkFmax);
2848 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2849 size = sprintf(buf, "%s:\n", "OD_MCLK");
2850 size += sprintf(buf + size, "1: %10uMhz\n",
2851 od_table->UclkFmax);
2857 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2858 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2859 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2860 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2861 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2862 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
2863 size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");
2864 size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
2865 od_table->GfxclkFreq1,
2866 od_table->GfxclkVolt1 / VOLTAGE_SCALE);
2867 size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
2868 od_table->GfxclkFreq2,
2869 od_table->GfxclkVolt2 / VOLTAGE_SCALE);
2870 size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
2871 od_table->GfxclkFreq3,
2872 od_table->GfxclkVolt3 / VOLTAGE_SCALE);
2878 size = sprintf(buf, "%s:\n", "OD_RANGE");
2880 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2881 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
2882 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
2883 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
2884 od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
2887 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2888 ret = vega20_get_memclocks(hwmgr, &clocks);
2889 PP_ASSERT_WITH_CODE(!ret,
2890 "Fail to get memory clk levels!",
2893 size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
2894 clocks.data[0].clocks_in_khz / 1000,
2895 od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
2898 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2899 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2900 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2901 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2902 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2903 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
2904 size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
2905 od8_settings[OD8_SETTING_GFXCLK_FREQ1].min_value,
2906 od8_settings[OD8_SETTING_GFXCLK_FREQ1].max_value);
2907 size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
2908 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
2909 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
2910 size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
2911 od8_settings[OD8_SETTING_GFXCLK_FREQ2].min_value,
2912 od8_settings[OD8_SETTING_GFXCLK_FREQ2].max_value);
2913 size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
2914 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
2915 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
2916 size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
2917 od8_settings[OD8_SETTING_GFXCLK_FREQ3].min_value,
2918 od8_settings[OD8_SETTING_GFXCLK_FREQ3].max_value);
2919 size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
2920 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
2921 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
2931 static int vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
2932 struct vega20_single_dpm_table *dpm_table)
2934 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2937 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2938 PP_ASSERT_WITH_CODE(dpm_table->count > 0,
2939 "[SetUclkToHightestDpmLevel] Dpm table has no entry!",
2941 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
2942 "[SetUclkToHightestDpmLevel] Dpm table has too many entries!",
2945 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2946 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2947 PPSMC_MSG_SetHardMinByFreq,
2948 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
2949 "[SetUclkToHightestDpmLevel] Set hard min uclk failed!",
2956 static int vega20_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2958 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2961 smum_send_msg_to_smc_with_parameter(hwmgr,
2962 PPSMC_MSG_NumOfDisplays, 0);
2964 ret = vega20_set_uclk_to_highest_dpm_level(hwmgr,
2965 &data->dpm_table.mem_table);
2970 static int vega20_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2972 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2974 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
2976 if ((data->water_marks_bitmap & WaterMarksExist) &&
2977 !(data->water_marks_bitmap & WaterMarksLoaded)) {
2978 result = smum_smc_table_manager(hwmgr,
2979 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
2980 PP_ASSERT_WITH_CODE(!result,
2981 "Failed to update WMTABLE!",
2983 data->water_marks_bitmap |= WaterMarksLoaded;
2986 if ((data->water_marks_bitmap & WaterMarksExist) &&
2987 data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2988 data->smu_features[GNLD_DPM_SOCCLK].supported) {
2989 result = smum_send_msg_to_smc_with_parameter(hwmgr,
2990 PPSMC_MSG_NumOfDisplays,
2991 hwmgr->display_config->num_display);
2997 int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
2999 struct vega20_hwmgr *data =
3000 (struct vega20_hwmgr *)(hwmgr->backend);
3003 if (data->smu_features[GNLD_DPM_UVD].supported) {
3004 if (data->smu_features[GNLD_DPM_UVD].enabled == enable) {
3006 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already enabled!\n");
3008 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already disabled!\n");
3011 ret = vega20_enable_smc_features(hwmgr,
3013 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap);
3014 PP_ASSERT_WITH_CODE(!ret,
3015 "[EnableDisableUVDDPM] Attempt to Enable/Disable DPM UVD Failed!",
3017 data->smu_features[GNLD_DPM_UVD].enabled = enable;
3023 static void vega20_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
3025 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3027 if (data->vce_power_gated == bgate)
3030 data->vce_power_gated = bgate;
3031 vega20_enable_disable_vce_dpm(hwmgr, !bgate);
3034 static void vega20_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
3036 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3038 if (data->uvd_power_gated == bgate)
3041 data->uvd_power_gated = bgate;
3042 vega20_enable_disable_uvd_dpm(hwmgr, !bgate);
3045 static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
3047 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3048 struct vega20_single_dpm_table *dpm_table;
3049 bool vblank_too_short = false;
3050 bool disable_mclk_switching;
3051 uint32_t i, latency;
3053 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
3054 !hwmgr->display_config->multi_monitor_in_sync) ||
3056 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3059 dpm_table = &(data->dpm_table.gfx_table);
3060 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3061 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3062 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3063 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3065 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3066 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
3067 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3068 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3071 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
3072 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3073 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3076 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3077 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3078 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3083 dpm_table = &(data->dpm_table.mem_table);
3084 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3085 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3086 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3087 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3089 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3090 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
3091 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3092 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3095 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
3096 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3097 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3100 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3101 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3102 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3106 /* honour DAL's UCLK Hardmin */
3107 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
3108 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
3110 /* Hardmin is dependent on displayconfig */
3111 if (disable_mclk_switching) {
3112 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3113 for (i = 0; i < data->mclk_latency_table.count - 1; i++) {
3114 if (data->mclk_latency_table.entries[i].latency <= latency) {
3115 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
3116 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
3123 if (hwmgr->display_config->nb_pstate_switch_disable)
3124 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3127 dpm_table = &(data->dpm_table.vclk_table);
3128 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3129 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3130 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3131 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3133 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3134 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3135 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3136 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3139 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3140 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3141 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3146 dpm_table = &(data->dpm_table.dclk_table);
3147 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3148 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3149 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3150 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3152 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3153 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3154 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3155 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3158 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3159 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3160 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3165 dpm_table = &(data->dpm_table.soc_table);
3166 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3167 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3168 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3169 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3171 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3172 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
3173 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3174 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3177 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3178 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3179 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3184 dpm_table = &(data->dpm_table.eclk_table);
3185 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3186 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3187 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3188 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3190 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3191 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
3192 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3193 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3196 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3197 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3198 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3206 vega20_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
3208 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3209 bool is_update_required = false;
3211 if (data->display_timing.num_existing_displays !=
3212 hwmgr->display_config->num_display)
3213 is_update_required = true;
3215 if (data->registry_data.gfx_clk_deep_sleep_support &&
3216 (data->display_timing.min_clock_in_sr !=
3217 hwmgr->display_config->min_core_set_clock_in_sr))
3218 is_update_required = true;
3220 return is_update_required;
3223 static int vega20_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
3227 ret = vega20_disable_all_smu_features(hwmgr);
3228 PP_ASSERT_WITH_CODE(!ret,
3229 "[DisableDpmTasks] Failed to disable all smu features!",
3235 static int vega20_power_off_asic(struct pp_hwmgr *hwmgr)
3237 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3240 result = vega20_disable_dpm_tasks(hwmgr);
3241 PP_ASSERT_WITH_CODE((0 == result),
3242 "[PowerOffAsic] Failed to disable DPM!",
3244 data->water_marks_bitmap &= ~(WaterMarksLoaded);
3249 static int conv_power_profile_to_pplib_workload(int power_profile)
3251 int pplib_workload = 0;
3253 switch (power_profile) {
3254 case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
3255 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
3257 case PP_SMC_POWER_PROFILE_POWERSAVING:
3258 pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
3260 case PP_SMC_POWER_PROFILE_VIDEO:
3261 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
3263 case PP_SMC_POWER_PROFILE_VR:
3264 pplib_workload = WORKLOAD_PPLIB_VR_BIT;
3266 case PP_SMC_POWER_PROFILE_COMPUTE:
3267 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
3269 case PP_SMC_POWER_PROFILE_CUSTOM:
3270 pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
3274 return pplib_workload;
3277 static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
3279 DpmActivityMonitorCoeffInt_t activity_monitor;
3280 uint32_t i, size = 0;
3281 uint16_t workload_type = 0;
3282 static const char *profile_name[] = {
3289 static const char *title[] = {
3290 "PROFILE_INDEX(NAME)",
3294 "MinActiveFreqType",
3299 "PD_Data_error_coeff",
3300 "PD_Data_error_rate_coeff"};
3306 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
3307 title[0], title[1], title[2], title[3], title[4], title[5],
3308 title[6], title[7], title[8], title[9], title[10]);
3310 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
3311 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
3312 workload_type = conv_power_profile_to_pplib_workload(i);
3313 result = vega20_get_activity_monitor_coeff(hwmgr,
3314 (uint8_t *)(&activity_monitor), workload_type);
3315 PP_ASSERT_WITH_CODE(!result,
3316 "[GetPowerProfile] Failed to get activity monitor!",
3319 size += sprintf(buf + size, "%2d %14s%s:\n",
3320 i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ");
3322 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3326 activity_monitor.Gfx_FPS,
3327 activity_monitor.Gfx_UseRlcBusy,
3328 activity_monitor.Gfx_MinActiveFreqType,
3329 activity_monitor.Gfx_MinActiveFreq,
3330 activity_monitor.Gfx_BoosterFreqType,
3331 activity_monitor.Gfx_BoosterFreq,
3332 activity_monitor.Gfx_PD_Data_limit_c,
3333 activity_monitor.Gfx_PD_Data_error_coeff,
3334 activity_monitor.Gfx_PD_Data_error_rate_coeff);
3336 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3340 activity_monitor.Soc_FPS,
3341 activity_monitor.Soc_UseRlcBusy,
3342 activity_monitor.Soc_MinActiveFreqType,
3343 activity_monitor.Soc_MinActiveFreq,
3344 activity_monitor.Soc_BoosterFreqType,
3345 activity_monitor.Soc_BoosterFreq,
3346 activity_monitor.Soc_PD_Data_limit_c,
3347 activity_monitor.Soc_PD_Data_error_coeff,
3348 activity_monitor.Soc_PD_Data_error_rate_coeff);
3350 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3354 activity_monitor.Mem_FPS,
3355 activity_monitor.Mem_UseRlcBusy,
3356 activity_monitor.Mem_MinActiveFreqType,
3357 activity_monitor.Mem_MinActiveFreq,
3358 activity_monitor.Mem_BoosterFreqType,
3359 activity_monitor.Mem_BoosterFreq,
3360 activity_monitor.Mem_PD_Data_limit_c,
3361 activity_monitor.Mem_PD_Data_error_coeff,
3362 activity_monitor.Mem_PD_Data_error_rate_coeff);
3364 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3368 activity_monitor.Fclk_FPS,
3369 activity_monitor.Fclk_UseRlcBusy,
3370 activity_monitor.Fclk_MinActiveFreqType,
3371 activity_monitor.Fclk_MinActiveFreq,
3372 activity_monitor.Fclk_BoosterFreqType,
3373 activity_monitor.Fclk_BoosterFreq,
3374 activity_monitor.Fclk_PD_Data_limit_c,
3375 activity_monitor.Fclk_PD_Data_error_coeff,
3376 activity_monitor.Fclk_PD_Data_error_rate_coeff);
3382 static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
3384 DpmActivityMonitorCoeffInt_t activity_monitor;
3385 int workload_type, result = 0;
3387 hwmgr->power_profile_mode = input[size];
3389 if (hwmgr->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
3390 pr_err("Invalid power profile mode %d\n", hwmgr->power_profile_mode);
3394 if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
3398 result = vega20_get_activity_monitor_coeff(hwmgr,
3399 (uint8_t *)(&activity_monitor),
3400 WORKLOAD_PPLIB_CUSTOM_BIT);
3401 PP_ASSERT_WITH_CODE(!result,
3402 "[SetPowerProfile] Failed to get activity monitor!",
3406 case 0: /* Gfxclk */
3407 activity_monitor.Gfx_FPS = input[1];
3408 activity_monitor.Gfx_UseRlcBusy = input[2];
3409 activity_monitor.Gfx_MinActiveFreqType = input[3];
3410 activity_monitor.Gfx_MinActiveFreq = input[4];
3411 activity_monitor.Gfx_BoosterFreqType = input[5];
3412 activity_monitor.Gfx_BoosterFreq = input[6];
3413 activity_monitor.Gfx_PD_Data_limit_c = input[7];
3414 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
3415 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
3417 case 1: /* Socclk */
3418 activity_monitor.Soc_FPS = input[1];
3419 activity_monitor.Soc_UseRlcBusy = input[2];
3420 activity_monitor.Soc_MinActiveFreqType = input[3];
3421 activity_monitor.Soc_MinActiveFreq = input[4];
3422 activity_monitor.Soc_BoosterFreqType = input[5];
3423 activity_monitor.Soc_BoosterFreq = input[6];
3424 activity_monitor.Soc_PD_Data_limit_c = input[7];
3425 activity_monitor.Soc_PD_Data_error_coeff = input[8];
3426 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
3429 activity_monitor.Mem_FPS = input[1];
3430 activity_monitor.Mem_UseRlcBusy = input[2];
3431 activity_monitor.Mem_MinActiveFreqType = input[3];
3432 activity_monitor.Mem_MinActiveFreq = input[4];
3433 activity_monitor.Mem_BoosterFreqType = input[5];
3434 activity_monitor.Mem_BoosterFreq = input[6];
3435 activity_monitor.Mem_PD_Data_limit_c = input[7];
3436 activity_monitor.Mem_PD_Data_error_coeff = input[8];
3437 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
3440 activity_monitor.Fclk_FPS = input[1];
3441 activity_monitor.Fclk_UseRlcBusy = input[2];
3442 activity_monitor.Fclk_MinActiveFreqType = input[3];
3443 activity_monitor.Fclk_MinActiveFreq = input[4];
3444 activity_monitor.Fclk_BoosterFreqType = input[5];
3445 activity_monitor.Fclk_BoosterFreq = input[6];
3446 activity_monitor.Fclk_PD_Data_limit_c = input[7];
3447 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
3448 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
3452 result = vega20_set_activity_monitor_coeff(hwmgr,
3453 (uint8_t *)(&activity_monitor),
3454 WORKLOAD_PPLIB_CUSTOM_BIT);
3455 PP_ASSERT_WITH_CODE(!result,
3456 "[SetPowerProfile] Failed to set activity monitor!",
3460 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
3462 conv_power_profile_to_pplib_workload(hwmgr->power_profile_mode);
3463 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
3464 1 << workload_type);
3469 static int vega20_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
3470 uint32_t virtual_addr_low,
3471 uint32_t virtual_addr_hi,
3472 uint32_t mc_addr_low,
3473 uint32_t mc_addr_hi,
3476 smum_send_msg_to_smc_with_parameter(hwmgr,
3477 PPSMC_MSG_SetSystemVirtualDramAddrHigh,
3479 smum_send_msg_to_smc_with_parameter(hwmgr,
3480 PPSMC_MSG_SetSystemVirtualDramAddrLow,
3482 smum_send_msg_to_smc_with_parameter(hwmgr,
3483 PPSMC_MSG_DramLogSetDramAddrHigh,
3486 smum_send_msg_to_smc_with_parameter(hwmgr,
3487 PPSMC_MSG_DramLogSetDramAddrLow,
3490 smum_send_msg_to_smc_with_parameter(hwmgr,
3491 PPSMC_MSG_DramLogSetDramSize,
3496 static int vega20_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
3497 struct PP_TemperatureRange *thermal_data)
3499 struct phm_ppt_v3_information *pptable_information =
3500 (struct phm_ppt_v3_information *)hwmgr->pptable;
3502 memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
3504 thermal_data->max = pptable_information->us_software_shutdown_temp *
3505 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
3510 static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
3511 /* init/fini related */
3512 .backend_init = vega20_hwmgr_backend_init,
3513 .backend_fini = vega20_hwmgr_backend_fini,
3514 .asic_setup = vega20_setup_asic_task,
3515 .power_off_asic = vega20_power_off_asic,
3516 .dynamic_state_management_enable = vega20_enable_dpm_tasks,
3517 .dynamic_state_management_disable = vega20_disable_dpm_tasks,
3518 /* power state related */
3519 .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules,
3520 .pre_display_config_changed = vega20_pre_display_configuration_changed_task,
3521 .display_config_changed = vega20_display_configuration_changed_task,
3522 .check_smc_update_required_for_display_configuration =
3523 vega20_check_smc_update_required_for_display_configuration,
3524 .notify_smc_display_config_after_ps_adjustment =
3525 vega20_notify_smc_display_config_after_ps_adjustment,
3527 .get_sclk = vega20_dpm_get_sclk,
3528 .get_mclk = vega20_dpm_get_mclk,
3529 .get_dal_power_level = vega20_get_dal_power_level,
3530 .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
3531 .get_clock_by_type_with_voltage = vega20_get_clock_by_type_with_voltage,
3532 .set_watermarks_for_clocks_ranges = vega20_set_watermarks_for_clocks_ranges,
3533 .display_clock_voltage_request = vega20_display_clock_voltage_request,
3534 .get_performance_level = vega20_get_performance_level,
3535 /* UMD pstate, profile related */
3536 .force_dpm_level = vega20_dpm_force_dpm_level,
3537 .get_power_profile_mode = vega20_get_power_profile_mode,
3538 .set_power_profile_mode = vega20_set_power_profile_mode,
3540 .set_power_limit = vega20_set_power_limit,
3541 .get_sclk_od = vega20_get_sclk_od,
3542 .set_sclk_od = vega20_set_sclk_od,
3543 .get_mclk_od = vega20_get_mclk_od,
3544 .set_mclk_od = vega20_set_mclk_od,
3545 .odn_edit_dpm_table = vega20_odn_edit_dpm_table,
3546 /* for sysfs to retrive/set gfxclk/memclk */
3547 .force_clock_level = vega20_force_clock_level,
3548 .print_clock_levels = vega20_print_clock_levels,
3549 .read_sensor = vega20_read_sensor,
3550 /* powergate related */
3551 .powergate_uvd = vega20_power_gate_uvd,
3552 .powergate_vce = vega20_power_gate_vce,
3553 /* thermal related */
3554 .start_thermal_controller = vega20_start_thermal_controller,
3555 .stop_thermal_controller = vega20_thermal_stop_thermal_controller,
3556 .get_thermal_temperature_range = vega20_get_thermal_temperature_range,
3557 .register_irq_handlers = smu9_register_irq_handlers,
3558 .disable_smc_firmware_ctf = vega20_thermal_disable_alert,
3559 /* fan control related */
3560 .get_fan_speed_percent = vega20_fan_ctrl_get_fan_speed_percent,
3561 .set_fan_speed_percent = vega20_fan_ctrl_set_fan_speed_percent,
3562 .get_fan_speed_info = vega20_fan_ctrl_get_fan_speed_info,
3563 .get_fan_speed_rpm = vega20_fan_ctrl_get_fan_speed_rpm,
3564 .set_fan_speed_rpm = vega20_fan_ctrl_set_fan_speed_rpm,
3565 .get_fan_control_mode = vega20_get_fan_control_mode,
3566 .set_fan_control_mode = vega20_set_fan_control_mode,
3567 /* smu memory related */
3568 .notify_cac_buffer_info = vega20_notify_cac_buffer_info,
3569 .enable_mgpu_fan_boost = vega20_enable_mgpu_fan_boost,
3572 int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
3574 hwmgr->hwmgr_func = &vega20_hwmgr_funcs;
3575 hwmgr->pptable_func = &vega20_pptable_funcs;