drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/fb.h>
  26 #include <linux/module.h>
  27 #include <linux/slab.h>
  28
  29 #include "hwmgr.h"
  30 #include "amd_powerplay.h"
  31 #include "vega20_smumgr.h"
  32 #include "hardwaremanager.h"
  33 #include "ppatomfwctrl.h"
  34 #include "atomfirmware.h"
  35 #include "cgs_common.h"
  36 #include "vega20_powertune.h"
  37 #include "vega20_inc.h"
  38 #include "pppcielanes.h"
  39 #include "vega20_hwmgr.h"
  40 #include "vega20_processpptables.h"
  41 #include "vega20_pptable.h"
  42 #include "vega20_thermal.h"
  43 #include "vega20_ppsmc.h"
  44 #include "pp_debug.h"
  45 #include "amd_pcie_helpers.h"
  46 #include "ppinterrupt.h"
  47 #include "pp_overdriver.h"
  48 #include "pp_thermal.h"
  49 #include "soc15_common.h"
  50 #include "smuio/smuio_9_0_offset.h"
  51 #include "smuio/smuio_9_0_sh_mask.h"
  52 #include "nbio/nbio_7_4_sh_mask.h"
  53
  54 #define smnPCIE_LC_SPEED_CNTL                   0x11140290
  55 #define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288
  56
  57 static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
  58 {
  59         struct vega20_hwmgr *data =
  60                         (struct vega20_hwmgr *)(hwmgr->backend);
  61
  62         data->gfxclk_average_alpha = PPVEGA20_VEGA20GFXCLKAVERAGEALPHA_DFLT;
  63         data->socclk_average_alpha = PPVEGA20_VEGA20SOCCLKAVERAGEALPHA_DFLT;
  64         data->uclk_average_alpha = PPVEGA20_VEGA20UCLKCLKAVERAGEALPHA_DFLT;
  65         data->gfx_activity_average_alpha = PPVEGA20_VEGA20GFXACTIVITYAVERAGEALPHA_DFLT;
  66         data->lowest_uclk_reserved_for_ulv = PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT;
  67
  68         data->display_voltage_mode = PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT;
  69         data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  70         data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  71         data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  72         data->disp_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  73         data->disp_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  74         data->disp_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  75         data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  76         data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  77         data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  78         data->phy_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  79         data->phy_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  80         data->phy_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  81
  82         /*
  83          * Disable the following features for now:
  84          *   GFXCLK DS
  85          *   SOCLK DS
  86          *   LCLK DS
  87          *   DCEFCLK DS
  88          *   FCLK DS
  89          *   MP1CLK DS
  90          *   MP0CLK DS
  91          */
  92         data->registry_data.disallowed_features = 0xE0041C00;
  93         data->registry_data.od_state_in_dc_support = 0;
  94         data->registry_data.thermal_support = 1;
  95         data->registry_data.skip_baco_hardware = 0;
  96
  97         data->registry_data.log_avfs_param = 0;
  98         data->registry_data.sclk_throttle_low_notification = 1;
  99         data->registry_data.force_dpm_high = 0;
 100         data->registry_data.stable_pstate_sclk_dpm_percentage = 75;
 101
 102         data->registry_data.didt_support = 0;
 103         if (data->registry_data.didt_support) {
 104                 data->registry_data.didt_mode = 6;
 105                 data->registry_data.sq_ramping_support = 1;
 106                 data->registry_data.db_ramping_support = 0;
 107                 data->registry_data.td_ramping_support = 0;
 108                 data->registry_data.tcp_ramping_support = 0;
 109                 data->registry_data.dbr_ramping_support = 0;
 110                 data->registry_data.edc_didt_support = 1;
 111                 data->registry_data.gc_didt_support = 0;
 112                 data->registry_data.psm_didt_support = 0;
 113         }
 114
 115         data->registry_data.pcie_lane_override = 0xff;
 116         data->registry_data.pcie_speed_override = 0xff;
 117         data->registry_data.pcie_clock_override = 0xffffffff;
 118         data->registry_data.regulator_hot_gpio_support = 1;
 119         data->registry_data.ac_dc_switch_gpio_support = 0;
 120         data->registry_data.quick_transition_support = 0;
 121         data->registry_data.zrpm_start_temp = 0xffff;
 122         data->registry_data.zrpm_stop_temp = 0xffff;
 123         data->registry_data.od8_feature_enable = 1;
 124         data->registry_data.disable_water_mark = 0;
 125         data->registry_data.disable_pp_tuning = 0;
 126         data->registry_data.disable_xlpp_tuning = 0;
 127         data->registry_data.disable_workload_policy = 0;
 128         data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F;
 129         data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919;
 130         data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A;
 131         data->registry_data.force_workload_policy_mask = 0;
 132         data->registry_data.disable_3d_fs_detection = 0;
 133         data->registry_data.fps_support = 1;
 134         data->registry_data.disable_auto_wattman = 1;
 135         data->registry_data.auto_wattman_debug = 0;
 136         data->registry_data.auto_wattman_sample_period = 100;
 137         data->registry_data.fclk_gfxclk_ratio = 0x3F6CCCCD;
 138         data->registry_data.auto_wattman_threshold = 50;
 139         data->registry_data.gfxoff_controlled_by_driver = 1;
 140         data->gfxoff_allowed = false;
 141         data->counter_gfxoff = 0;
 142 }
 143
 144 static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr)
 145 {
 146         struct vega20_hwmgr *data =
 147                         (struct vega20_hwmgr *)(hwmgr->backend);
 148         struct amdgpu_device *adev = hwmgr->adev;
 149
 150         if (data->vddci_control == VEGA20_VOLTAGE_CONTROL_NONE)
 151                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 152                                 PHM_PlatformCaps_ControlVDDCI);
 153
 154         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 155                         PHM_PlatformCaps_TablelessHardwareInterface);
 156
 157         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 158                         PHM_PlatformCaps_EnableSMU7ThermalManagement);
 159
 160         if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
 161                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 162                                 PHM_PlatformCaps_UVDPowerGating);
 163
 164         if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
 165                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 166                                 PHM_PlatformCaps_VCEPowerGating);
 167
 168         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 169                         PHM_PlatformCaps_UnTabledHardwareInterface);
 170
 171         if (data->registry_data.od8_feature_enable)
 172                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 173                                 PHM_PlatformCaps_OD8inACSupport);
 174
 175         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 176                         PHM_PlatformCaps_ActivityReporting);
 177         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 178                         PHM_PlatformCaps_FanSpeedInTableIsRPM);
 179
 180         if (data->registry_data.od_state_in_dc_support) {
 181                 if (data->registry_data.od8_feature_enable)
 182                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 183                                         PHM_PlatformCaps_OD8inDCSupport);
 184         }
 185
 186         if (data->registry_data.thermal_support &&
 187             data->registry_data.fuzzy_fan_control_support &&
 188             hwmgr->thermal_controller.advanceFanControlParameters.usTMax)
 189                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 190                                 PHM_PlatformCaps_ODFuzzyFanControlSupport);
 191
 192         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 193                         PHM_PlatformCaps_DynamicPowerManagement);
 194         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 195                         PHM_PlatformCaps_SMC);
 196         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 197                         PHM_PlatformCaps_ThermalPolicyDelay);
 198
 199         if (data->registry_data.force_dpm_high)
 200                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 201                                 PHM_PlatformCaps_ExclusiveModeAlwaysHigh);
 202
 203         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 204                         PHM_PlatformCaps_DynamicUVDState);
 205
 206         if (data->registry_data.sclk_throttle_low_notification)
 207                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 208                                 PHM_PlatformCaps_SclkThrottleLowNotification);
 209
 210         /* power tune caps */
 211         /* assume disabled */
 212         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 213                         PHM_PlatformCaps_PowerContainment);
 214         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 215                         PHM_PlatformCaps_DiDtSupport);
 216         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 217                         PHM_PlatformCaps_SQRamping);
 218         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 219                         PHM_PlatformCaps_DBRamping);
 220         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 221                         PHM_PlatformCaps_TDRamping);
 222         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 223                         PHM_PlatformCaps_TCPRamping);
 224         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 225                         PHM_PlatformCaps_DBRRamping);
 226         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 227                         PHM_PlatformCaps_DiDtEDCEnable);
 228         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 229                         PHM_PlatformCaps_GCEDC);
 230         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 231                         PHM_PlatformCaps_PSM);
 232
 233         if (data->registry_data.didt_support) {
 234                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 235                                 PHM_PlatformCaps_DiDtSupport);
 236                 if (data->registry_data.sq_ramping_support)
 237                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 238                                         PHM_PlatformCaps_SQRamping);
 239                 if (data->registry_data.db_ramping_support)
 240                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 241                                         PHM_PlatformCaps_DBRamping);
 242                 if (data->registry_data.td_ramping_support)
 243                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 244                                         PHM_PlatformCaps_TDRamping);
 245                 if (data->registry_data.tcp_ramping_support)
 246                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 247                                         PHM_PlatformCaps_TCPRamping);
 248                 if (data->registry_data.dbr_ramping_support)
 249                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 250                                         PHM_PlatformCaps_DBRRamping);
 251                 if (data->registry_data.edc_didt_support)
 252                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 253                                         PHM_PlatformCaps_DiDtEDCEnable);
 254                 if (data->registry_data.gc_didt_support)
 255                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 256                                         PHM_PlatformCaps_GCEDC);
 257                 if (data->registry_data.psm_didt_support)
 258                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 259                                         PHM_PlatformCaps_PSM);
 260         }
 261
 262         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 263                         PHM_PlatformCaps_RegulatorHot);
 264
 265         if (data->registry_data.ac_dc_switch_gpio_support) {
 266                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 267                                 PHM_PlatformCaps_AutomaticDCTransition);
 268                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 269                                 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
 270         }
 271
 272         if (data->registry_data.quick_transition_support) {
 273                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 274                                 PHM_PlatformCaps_AutomaticDCTransition);
 275                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 276                                 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
 277                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 278                                 PHM_PlatformCaps_Falcon_QuickTransition);
 279         }
 280
 281         if (data->lowest_uclk_reserved_for_ulv != PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT) {
 282                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 283                                 PHM_PlatformCaps_LowestUclkReservedForUlv);
 284                 if (data->lowest_uclk_reserved_for_ulv == 1)
 285                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 286                                         PHM_PlatformCaps_LowestUclkReservedForUlv);
 287         }
 288
 289         if (data->registry_data.custom_fan_support)
 290                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 291                                 PHM_PlatformCaps_CustomFanControlSupport);
 292
 293         return 0;
 294 }
 295
 296 static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 297 {
 298         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
 299         int i;
 300
 301         data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
 302                         FEATURE_DPM_PREFETCHER_BIT;
 303         data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
 304                         FEATURE_DPM_GFXCLK_BIT;
 305         data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
 306                         FEATURE_DPM_UCLK_BIT;
 307         data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
 308                         FEATURE_DPM_SOCCLK_BIT;
 309         data->smu_features[GNLD_DPM_UVD].smu_feature_id =
 310                         FEATURE_DPM_UVD_BIT;
 311         data->smu_features[GNLD_DPM_VCE].smu_feature_id =
 312                         FEATURE_DPM_VCE_BIT;
 313         data->smu_features[GNLD_ULV].smu_feature_id =
 314                         FEATURE_ULV_BIT;
 315         data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
 316                         FEATURE_DPM_MP0CLK_BIT;
 317         data->smu_features[GNLD_DPM_LINK].smu_feature_id =
 318                         FEATURE_DPM_LINK_BIT;
 319         data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
 320                         FEATURE_DPM_DCEFCLK_BIT;
 321         data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
 322                         FEATURE_DS_GFXCLK_BIT;
 323         data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
 324                         FEATURE_DS_SOCCLK_BIT;
 325         data->smu_features[GNLD_DS_LCLK].smu_feature_id =
 326                         FEATURE_DS_LCLK_BIT;
 327         data->smu_features[GNLD_PPT].smu_feature_id =
 328                         FEATURE_PPT_BIT;
 329         data->smu_features[GNLD_TDC].smu_feature_id =
 330                         FEATURE_TDC_BIT;
 331         data->smu_features[GNLD_THERMAL].smu_feature_id =
 332                         FEATURE_THERMAL_BIT;
 333         data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
 334                         FEATURE_GFX_PER_CU_CG_BIT;
 335         data->smu_features[GNLD_RM].smu_feature_id =
 336                         FEATURE_RM_BIT;
 337         data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
 338                         FEATURE_DS_DCEFCLK_BIT;
 339         data->smu_features[GNLD_ACDC].smu_feature_id =
 340                         FEATURE_ACDC_BIT;
 341         data->smu_features[GNLD_VR0HOT].smu_feature_id =
 342                         FEATURE_VR0HOT_BIT;
 343         data->smu_features[GNLD_VR1HOT].smu_feature_id =
 344                         FEATURE_VR1HOT_BIT;
 345         data->smu_features[GNLD_FW_CTF].smu_feature_id =
 346                         FEATURE_FW_CTF_BIT;
 347         data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
 348                         FEATURE_LED_DISPLAY_BIT;
 349         data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
 350                         FEATURE_FAN_CONTROL_BIT;
 351         data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
 352         data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT;
 353         data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT;
 354         data->smu_features[GNLD_DPM_FCLK].smu_feature_id = FEATURE_DPM_FCLK_BIT;
 355         data->smu_features[GNLD_DS_FCLK].smu_feature_id = FEATURE_DS_FCLK_BIT;
 356         data->smu_features[GNLD_DS_MP1CLK].smu_feature_id = FEATURE_DS_MP1CLK_BIT;
 357         data->smu_features[GNLD_DS_MP0CLK].smu_feature_id = FEATURE_DS_MP0CLK_BIT;
 358         data->smu_features[GNLD_XGMI].smu_feature_id = FEATURE_XGMI_BIT;
 359
 360         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 361                 data->smu_features[i].smu_feature_bitmap =
 362                         (uint64_t)(1ULL << data->smu_features[i].smu_feature_id);
 363                 data->smu_features[i].allowed =
 364                         ((data->registry_data.disallowed_features >> i) & 1) ?
 365                         false : true;
 366         }
 367 }
 368
 369 static int vega20_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
 370 {
 371         return 0;
 372 }
 373
 374 static int vega20_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 375 {
 376         kfree(hwmgr->backend);
 377         hwmgr->backend = NULL;
 378
 379         return 0;
 380 }
 381
 382 static int vega20_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 383 {
 384         struct vega20_hwmgr *data;
 385         struct amdgpu_device *adev = hwmgr->adev;
 386
 387         data = kzalloc(sizeof(struct vega20_hwmgr), GFP_KERNEL);
 388         if (data == NULL)
 389                 return -ENOMEM;
 390
 391         hwmgr->backend = data;
 392
 393         hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO];
 394         hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
 395         hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
 396
 397         vega20_set_default_registry_data(hwmgr);
 398
 399         data->disable_dpm_mask = 0xff;
 400
 401         /* need to set voltage control types before EVV patching */
 402         data->vddc_control = VEGA20_VOLTAGE_CONTROL_NONE;
 403         data->mvdd_control = VEGA20_VOLTAGE_CONTROL_NONE;
 404         data->vddci_control = VEGA20_VOLTAGE_CONTROL_NONE;
 405
 406         data->water_marks_bitmap = 0;
 407         data->avfs_exist = false;
 408
 409         vega20_set_features_platform_caps(hwmgr);
 410
 411         vega20_init_dpm_defaults(hwmgr);
 412
 413         /* Parse pptable data read from VBIOS */
 414         vega20_set_private_data_based_on_pptable(hwmgr);
 415
 416         data->is_tlu_enabled = false;
 417
 418         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
 419                         VEGA20_MAX_HARDWARE_POWERLEVELS;
 420         hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
 421         hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
 422
 423         hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
 424         /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
 425         hwmgr->platform_descriptor.clockStep.engineClock = 500;
 426         hwmgr->platform_descriptor.clockStep.memoryClock = 500;
 427
 428         data->total_active_cus = adev->gfx.cu_info.number;
 429
 430         return 0;
 431 }
 432
 433 static int vega20_init_sclk_threshold(struct pp_hwmgr *hwmgr)
 434 {
 435         struct vega20_hwmgr *data =
 436                         (struct vega20_hwmgr *)(hwmgr->backend);
 437
 438         data->low_sclk_interrupt_threshold = 0;
 439
 440         return 0;
 441 }
 442
 443 static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr)
 444 {
 445         int ret = 0;
 446
 447         ret = vega20_init_sclk_threshold(hwmgr);
 448         PP_ASSERT_WITH_CODE(!ret,
 449                         "Failed to init sclk threshold!",
 450                         return ret);
 451
 452         return 0;
 453 }
 454
 455 /*
 456  * @fn vega20_init_dpm_state
 457  * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
 458  *
 459  * @param    dpm_state - the address of the DPM Table to initiailize.
 460  * @return   None.
 461  */
 462 static void vega20_init_dpm_state(struct vega20_dpm_state *dpm_state)
 463 {
 464         dpm_state->soft_min_level = 0x0;
 465         dpm_state->soft_max_level = 0xffff;
 466         dpm_state->hard_min_level = 0x0;
 467         dpm_state->hard_max_level = 0xffff;
 468 }
 469
 470 static int vega20_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
 471                 PPCLK_e clk_id, uint32_t *num_of_levels)
 472 {
 473         int ret = 0;
 474
 475         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 476                         PPSMC_MSG_GetDpmFreqByIndex,
 477                         (clk_id << 16 | 0xFF));
 478         PP_ASSERT_WITH_CODE(!ret,
 479                         "[GetNumOfDpmLevel] failed to get dpm levels!",
 480                         return ret);
 481
 482         *num_of_levels = smum_get_argument(hwmgr);
 483         PP_ASSERT_WITH_CODE(*num_of_levels > 0,
 484                         "[GetNumOfDpmLevel] number of clk levels is invalid!",
 485                         return -EINVAL);
 486
 487         return ret;
 488 }
 489
 490 static int vega20_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
 491                 PPCLK_e clk_id, uint32_t index, uint32_t *clk)
 492 {
 493         int ret = 0;
 494
 495         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 496                         PPSMC_MSG_GetDpmFreqByIndex,
 497                         (clk_id << 16 | index));
 498         PP_ASSERT_WITH_CODE(!ret,
 499                         "[GetDpmFreqByIndex] failed to get dpm freq by index!",
 500                         return ret);
 501
 502         *clk = smum_get_argument(hwmgr);
 503         PP_ASSERT_WITH_CODE(*clk,
 504                         "[GetDpmFreqByIndex] clk value is invalid!",
 505                         return -EINVAL);
 506
 507         return ret;
 508 }
 509
 510 static int vega20_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
 511                 struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id)
 512 {
 513         int ret = 0;
 514         uint32_t i, num_of_levels, clk;
 515
 516         ret = vega20_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
 517         PP_ASSERT_WITH_CODE(!ret,
 518                         "[SetupSingleDpmTable] failed to get clk levels!",
 519                         return ret);
 520
 521         dpm_table->count = num_of_levels;
 522
 523         for (i = 0; i < num_of_levels; i++) {
 524                 ret = vega20_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);
 525                 PP_ASSERT_WITH_CODE(!ret,
 526                         "[SetupSingleDpmTable] failed to get clk of specific level!",
 527                         return ret);
 528                 dpm_table->dpm_levels[i].value = clk;
 529                 dpm_table->dpm_levels[i].enabled = true;
 530         }
 531
 532         return ret;
 533 }
 534
 535 static int vega20_setup_gfxclk_dpm_table(struct pp_hwmgr *hwmgr)
 536 {
 537         struct vega20_hwmgr *data =
 538                         (struct vega20_hwmgr *)(hwmgr->backend);
 539         struct vega20_single_dpm_table *dpm_table;
 540         int ret = 0;
 541
 542         dpm_table = &(data->dpm_table.gfx_table);
 543         if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
 544                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
 545                 PP_ASSERT_WITH_CODE(!ret,
 546                                 "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!",
 547                                 return ret);
 548         } else {
 549                 dpm_table->count = 1;
 550                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100;
 551         }
 552
 553         return ret;
 554 }
 555
 556 static int vega20_setup_memclk_dpm_table(struct pp_hwmgr *hwmgr)
 557 {
 558         struct vega20_hwmgr *data =
 559                         (struct vega20_hwmgr *)(hwmgr->backend);
 560         struct vega20_single_dpm_table *dpm_table;
 561         int ret = 0;
 562
 563         dpm_table = &(data->dpm_table.mem_table);
 564         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
 565                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
 566                 PP_ASSERT_WITH_CODE(!ret,
 567                                 "[SetupDefaultDpmTable] failed to get memclk dpm levels!",
 568                                 return ret);
 569         } else {
 570                 dpm_table->count = 1;
 571                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100;
 572         }
 573
 574         return ret;
 575 }
 576
 577 /*
 578  * This function is to initialize all DPM state tables
 579  * for SMU based on the dependency table.
 580  * Dynamic state patching function will then trim these
 581  * state tables to the allowed range based
 582  * on the power policy or external client requests,
 583  * such as UVD request, etc.
 584  */
 585 static int vega20_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 586 {
 587         struct vega20_hwmgr *data =
 588                         (struct vega20_hwmgr *)(hwmgr->backend);
 589         struct vega20_single_dpm_table *dpm_table;
 590         int ret = 0;
 591
 592         memset(&data->dpm_table, 0, sizeof(data->dpm_table));
 593
 594         /* socclk */
 595         dpm_table = &(data->dpm_table.soc_table);
 596         if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
 597                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK);
 598                 PP_ASSERT_WITH_CODE(!ret,
 599                                 "[SetupDefaultDpmTable] failed to get socclk dpm levels!",
 600                                 return ret);
 601         } else {
 602                 dpm_table->count = 1;
 603                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100;
 604         }
 605         vega20_init_dpm_state(&(dpm_table->dpm_state));
 606
 607         /* gfxclk */
 608         dpm_table = &(data->dpm_table.gfx_table);
 609         ret = vega20_setup_gfxclk_dpm_table(hwmgr);
 610         if (ret)
 611                 return ret;
 612         vega20_init_dpm_state(&(dpm_table->dpm_state));
 613
 614         /* memclk */
 615         dpm_table = &(data->dpm_table.mem_table);
 616         ret = vega20_setup_memclk_dpm_table(hwmgr);
 617         if (ret)
 618                 return ret;
 619         vega20_init_dpm_state(&(dpm_table->dpm_state));
 620
 621         /* eclk */
 622         dpm_table = &(data->dpm_table.eclk_table);
 623         if (data->smu_features[GNLD_DPM_VCE].enabled) {
 624                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK);
 625                 PP_ASSERT_WITH_CODE(!ret,
 626                                 "[SetupDefaultDpmTable] failed to get eclk dpm levels!",
 627                                 return ret);
 628         } else {
 629                 dpm_table->count = 1;
 630                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100;
 631         }
 632         vega20_init_dpm_state(&(dpm_table->dpm_state));
 633
 634         /* vclk */
 635         dpm_table = &(data->dpm_table.vclk_table);
 636         if (data->smu_features[GNLD_DPM_UVD].enabled) {
 637                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
 638                 PP_ASSERT_WITH_CODE(!ret,
 639                                 "[SetupDefaultDpmTable] failed to get vclk dpm levels!",
 640                                 return ret);
 641         } else {
 642                 dpm_table->count = 1;
 643                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100;
 644         }
 645         vega20_init_dpm_state(&(dpm_table->dpm_state));
 646
 647         /* dclk */
 648         dpm_table = &(data->dpm_table.dclk_table);
 649         if (data->smu_features[GNLD_DPM_UVD].enabled) {
 650                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK);
 651                 PP_ASSERT_WITH_CODE(!ret,
 652                                 "[SetupDefaultDpmTable] failed to get dclk dpm levels!",
 653                                 return ret);
 654         } else {
 655                 dpm_table->count = 1;
 656                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100;
 657         }
 658         vega20_init_dpm_state(&(dpm_table->dpm_state));
 659
 660         /* dcefclk */
 661         dpm_table = &(data->dpm_table.dcef_table);
 662         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 663                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK);
 664                 PP_ASSERT_WITH_CODE(!ret,
 665                                 "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!",
 666                                 return ret);
 667         } else {
 668                 dpm_table->count = 1;
 669                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100;
 670         }
 671         vega20_init_dpm_state(&(dpm_table->dpm_state));
 672
 673         /* pixclk */
 674         dpm_table = &(data->dpm_table.pixel_table);
 675         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 676                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK);
 677                 PP_ASSERT_WITH_CODE(!ret,
 678                                 "[SetupDefaultDpmTable] failed to get pixclk dpm levels!",
 679                                 return ret);
 680         } else
 681                 dpm_table->count = 0;
 682         vega20_init_dpm_state(&(dpm_table->dpm_state));
 683
 684         /* dispclk */
 685         dpm_table = &(data->dpm_table.display_table);
 686         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 687                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
 688                 PP_ASSERT_WITH_CODE(!ret,
 689                                 "[SetupDefaultDpmTable] failed to get dispclk dpm levels!",
 690                                 return ret);
 691         } else
 692                 dpm_table->count = 0;
 693         vega20_init_dpm_state(&(dpm_table->dpm_state));
 694
 695         /* phyclk */
 696         dpm_table = &(data->dpm_table.phy_table);
 697         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 698                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
 699                 PP_ASSERT_WITH_CODE(!ret,
 700                                 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!",
 701                                 return ret);
 702         } else
 703                 dpm_table->count = 0;
 704         vega20_init_dpm_state(&(dpm_table->dpm_state));
 705
 706         /* fclk */
 707         dpm_table = &(data->dpm_table.fclk_table);
 708         if (data->smu_features[GNLD_DPM_FCLK].enabled) {
 709                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_FCLK);
 710                 PP_ASSERT_WITH_CODE(!ret,
 711                                 "[SetupDefaultDpmTable] failed to get fclk dpm levels!",
 712                                 return ret);
 713         } else
 714                 dpm_table->count = 0;
 715         vega20_init_dpm_state(&(dpm_table->dpm_state));
 716
 717         /* save a copy of the default DPM table */
 718         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
 719                         sizeof(struct vega20_dpm_table));
 720
 721         return 0;
 722 }
 723
 724 /**
 725 * Initializes the SMC table and uploads it
 726 *
 727 * @param    hwmgr  the address of the powerplay hardware manager.
 728 * @param    pInput  the pointer to input data (PowerState)
 729 * @return   always 0
 730 */
 731 static int vega20_init_smc_table(struct pp_hwmgr *hwmgr)
 732 {
 733         int result;
 734         struct vega20_hwmgr *data =
 735                         (struct vega20_hwmgr *)(hwmgr->backend);
 736         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
 737         struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
 738         struct phm_ppt_v3_information *pptable_information =
 739                 (struct phm_ppt_v3_information *)hwmgr->pptable;
 740
 741         result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
 742         PP_ASSERT_WITH_CODE(!result,
 743                         "[InitSMCTable] Failed to get vbios bootup values!",
 744                         return result);
 745
 746         data->vbios_boot_state.vddc     = boot_up_values.usVddc;
 747         data->vbios_boot_state.vddci    = boot_up_values.usVddci;
 748         data->vbios_boot_state.mvddc    = boot_up_values.usMvddc;
 749         data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
 750         data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
 751         data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
 752         data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
 753         data->vbios_boot_state.eclock = boot_up_values.ulEClk;
 754         data->vbios_boot_state.vclock = boot_up_values.ulVClk;
 755         data->vbios_boot_state.dclock = boot_up_values.ulDClk;
 756         data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID;
 757
 758         smum_send_msg_to_smc_with_parameter(hwmgr,
 759                         PPSMC_MSG_SetMinDeepSleepDcefclk,
 760                 (uint32_t)(data->vbios_boot_state.dcef_clock / 100));
 761
 762         memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
 763
 764         result = smum_smc_table_manager(hwmgr,
 765                                         (uint8_t *)pp_table, TABLE_PPTABLE, false);
 766         PP_ASSERT_WITH_CODE(!result,
 767                         "[InitSMCTable] Failed to upload PPtable!",
 768                         return result);
 769
 770         return 0;
 771 }
 772
 773 static int vega20_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
 774 {
 775         struct vega20_hwmgr *data =
 776                         (struct vega20_hwmgr *)(hwmgr->backend);
 777         uint32_t allowed_features_low = 0, allowed_features_high = 0;
 778         int i;
 779         int ret = 0;
 780
 781         for (i = 0; i < GNLD_FEATURES_MAX; i++)
 782                 if (data->smu_features[i].allowed)
 783                         data->smu_features[i].smu_feature_id > 31 ?
 784                                 (allowed_features_high |=
 785                                  ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT)
 786                                   & 0xFFFFFFFF)) :
 787                                 (allowed_features_low |=
 788                                  ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT)
 789                                   & 0xFFFFFFFF));
 790
 791         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 792                 PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high);
 793         PP_ASSERT_WITH_CODE(!ret,
 794                 "[SetAllowedFeaturesMask] Attempt to set allowed features mask(high) failed!",
 795                 return ret);
 796
 797         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 798                 PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low);
 799         PP_ASSERT_WITH_CODE(!ret,
 800                 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!",
 801                 return ret);
 802
 803         return 0;
 804 }
 805
 806 static int vega20_run_btc_afll(struct pp_hwmgr *hwmgr)
 807 {
 808         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAfllBtc);
 809 }
 810
 811 static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr)
 812 {
 813         struct vega20_hwmgr *data =
 814                         (struct vega20_hwmgr *)(hwmgr->backend);
 815         uint64_t features_enabled;
 816         int i;
 817         bool enabled;
 818         int ret = 0;
 819
 820         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
 821                         PPSMC_MSG_EnableAllSmuFeatures)) == 0,
 822                         "[EnableAllSMUFeatures] Failed to enable all smu features!",
 823                         return ret);
 824
 825         ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
 826         PP_ASSERT_WITH_CODE(!ret,
 827                         "[EnableAllSmuFeatures] Failed to get enabled smc features!",
 828                         return ret);
 829
 830         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 831                 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
 832                         true : false;
 833                 data->smu_features[i].enabled = enabled;
 834                 data->smu_features[i].supported = enabled;
 835
 836 #if 0
 837                 if (data->smu_features[i].allowed && !enabled)
 838                         pr_info("[EnableAllSMUFeatures] feature %d is expected enabled!", i);
 839                 else if (!data->smu_features[i].allowed && enabled)
 840                         pr_info("[EnableAllSMUFeatures] feature %d is expected disabled!", i);
 841 #endif
 842         }
 843
 844         return 0;
 845 }
 846
 847 static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr)
 848 {
 849         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
 850
 851         if (data->smu_features[GNLD_DPM_UCLK].enabled)
 852                 return smum_send_msg_to_smc_with_parameter(hwmgr,
 853                         PPSMC_MSG_SetUclkFastSwitch,
 854                         1);
 855
 856         return 0;
 857 }
 858
 859 static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr)
 860 {
 861         struct vega20_hwmgr *data =
 862                         (struct vega20_hwmgr *)(hwmgr->backend);
 863
 864         return smum_send_msg_to_smc_with_parameter(hwmgr,
 865                         PPSMC_MSG_SetFclkGfxClkRatio,
 866                         data->registry_data.fclk_gfxclk_ratio);
 867 }
 868
 869 static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr)
 870 {
 871         struct vega20_hwmgr *data =
 872                         (struct vega20_hwmgr *)(hwmgr->backend);
 873         uint64_t features_enabled;
 874         int i;
 875         bool enabled;
 876         int ret = 0;
 877
 878         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
 879                         PPSMC_MSG_DisableAllSmuFeatures)) == 0,
 880                         "[DisableAllSMUFeatures] Failed to disable all smu features!",
 881                         return ret);
 882
 883         ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
 884         PP_ASSERT_WITH_CODE(!ret,
 885                         "[DisableAllSMUFeatures] Failed to get enabled smc features!",
 886                         return ret);
 887
 888         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 889                 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
 890                         true : false;
 891                 data->smu_features[i].enabled = enabled;
 892                 data->smu_features[i].supported = enabled;
 893         }
 894
 895         return 0;
 896 }
 897
 898 static int vega20_od8_set_feature_capabilities(
 899                 struct pp_hwmgr *hwmgr)
 900 {
 901         struct phm_ppt_v3_information *pptable_information =
 902                 (struct phm_ppt_v3_information *)hwmgr->pptable;
 903         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
 904         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
 905         struct vega20_od8_settings *od_settings = &(data->od8_settings);
 906
 907         od_settings->overdrive8_capabilities = 0;
 908
 909         if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
 910                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
 911                     pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
 912                     pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
 913                     (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
 914                     pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN]))
 915                         od_settings->overdrive8_capabilities |= OD8_GFXCLK_LIMITS;
 916
 917                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
 918                     (pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
 919                      pp_table->MinVoltageGfx / VOLTAGE_SCALE) &&
 920                     (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
 921                      pp_table->MaxVoltageGfx / VOLTAGE_SCALE) &&
 922                     (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] >=
 923                      pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1]))
 924                         od_settings->overdrive8_capabilities |= OD8_GFXCLK_CURVE;
 925         }
 926
 927         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
 928                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
 929                     pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
 930                     pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
 931                     (pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
 932                     pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX]))
 933                         od_settings->overdrive8_capabilities |= OD8_UCLK_MAX;
 934         }
 935
 936         if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
 937             pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
 938             pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
 939             pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
 940             pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100)
 941                 od_settings->overdrive8_capabilities |= OD8_POWER_LIMIT;
 942
 943         if (data->smu_features[GNLD_FAN_CONTROL].enabled) {
 944                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
 945                     pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
 946                     pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
 947                     (pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
 948                      pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT]))
 949                         od_settings->overdrive8_capabilities |= OD8_ACOUSTIC_LIMIT_SCLK;
 950
 951                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
 952                     (pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] >=
 953                     (pp_table->FanPwmMin * pp_table->FanMaximumRpm / 100)) &&
 954                     pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
 955                     (pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
 956                      pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED]))
 957                         od_settings->overdrive8_capabilities |= OD8_FAN_SPEED_MIN;
 958         }
 959
 960         if (data->smu_features[GNLD_THERMAL].enabled) {
 961                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
 962                     pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
 963                     pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
 964                     (pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
 965                      pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP]))
 966                         od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_FAN;
 967
 968                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
 969                     pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
 970                     pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
 971                     (pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
 972                      pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX]))
 973                         od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_SYSTEM;
 974         }
 975
 976         if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_MEMORY_TIMING_TUNE])
 977                 od_settings->overdrive8_capabilities |= OD8_MEMORY_TIMING_TUNE;
 978
 979         if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ZERO_RPM_CONTROL] &&
 980             pp_table->FanZeroRpmEnable)
 981                 od_settings->overdrive8_capabilities |= OD8_FAN_ZERO_RPM_CONTROL;
 982
 983         return 0;
 984 }
 985
 986 static int vega20_od8_set_feature_id(
 987                 struct pp_hwmgr *hwmgr)
 988 {
 989         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
 990         struct vega20_od8_settings *od_settings = &(data->od8_settings);
 991
 992         if (od_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
 993                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
 994                         OD8_GFXCLK_LIMITS;
 995                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
 996                         OD8_GFXCLK_LIMITS;
 997         } else {
 998                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
 999                         0;
1000                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1001                         0;
1002         }
1003
1004         if (od_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1005                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1006                         OD8_GFXCLK_CURVE;
1007                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1008                         OD8_GFXCLK_CURVE;
1009                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1010                         OD8_GFXCLK_CURVE;
1011                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1012                         OD8_GFXCLK_CURVE;
1013                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1014                         OD8_GFXCLK_CURVE;
1015                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1016                         OD8_GFXCLK_CURVE;
1017         } else {
1018                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1019                         0;
1020                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1021                         0;
1022                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1023                         0;
1024                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1025                         0;
1026                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1027                         0;
1028                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1029                         0;
1030         }
1031
1032         if (od_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1033                 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = OD8_UCLK_MAX;
1034         else
1035                 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = 0;
1036
1037         if (od_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1038                 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = OD8_POWER_LIMIT;
1039         else
1040                 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = 0;
1041
1042         if (od_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1043                 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1044                         OD8_ACOUSTIC_LIMIT_SCLK;
1045         else
1046                 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1047                         0;
1048
1049         if (od_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1050                 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1051                         OD8_FAN_SPEED_MIN;
1052         else
1053                 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1054                         0;
1055
1056         if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1057                 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1058                         OD8_TEMPERATURE_FAN;
1059         else
1060                 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1061                         0;
1062
1063         if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1064                 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1065                         OD8_TEMPERATURE_SYSTEM;
1066         else
1067                 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1068                         0;
1069
1070         return 0;
1071 }
1072
1073 static int vega20_od8_get_gfx_clock_base_voltage(
1074                 struct pp_hwmgr *hwmgr,
1075                 uint32_t *voltage,
1076                 uint32_t freq)
1077 {
1078         int ret = 0;
1079
1080         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1081                         PPSMC_MSG_GetAVFSVoltageByDpm,
1082                         ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq));
1083         PP_ASSERT_WITH_CODE(!ret,
1084                         "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!",
1085                         return ret);
1086
1087         *voltage = smum_get_argument(hwmgr);
1088         *voltage = *voltage / VOLTAGE_SCALE;
1089
1090         return 0;
1091 }
1092
1093 static int vega20_od8_initialize_default_settings(
1094                 struct pp_hwmgr *hwmgr)
1095 {
1096         struct phm_ppt_v3_information *pptable_information =
1097                 (struct phm_ppt_v3_information *)hwmgr->pptable;
1098         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1099         struct vega20_od8_settings *od8_settings = &(data->od8_settings);
1100         OverDriveTable_t *od_table = &(data->smc_state_table.overdrive_table);
1101         int i, ret = 0;
1102
1103         /* Set Feature Capabilities */
1104         vega20_od8_set_feature_capabilities(hwmgr);
1105
1106         /* Map FeatureID to individual settings */
1107         vega20_od8_set_feature_id(hwmgr);
1108
1109         /* Set default values */
1110         ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, true);
1111         PP_ASSERT_WITH_CODE(!ret,
1112                         "Failed to export over drive table!",
1113                         return ret);
1114
1115         if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
1116                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1117                         od_table->GfxclkFmin;
1118                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1119                         od_table->GfxclkFmax;
1120         } else {
1121                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1122                         0;
1123                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1124                         0;
1125         }
1126
1127         if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1128                 od_table->GfxclkFreq1 = od_table->GfxclkFmin;
1129                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1130                         od_table->GfxclkFreq1;
1131
1132                 od_table->GfxclkFreq3 = od_table->GfxclkFmax;
1133                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1134                         od_table->GfxclkFreq3;
1135
1136                 od_table->GfxclkFreq2 = (od_table->GfxclkFreq1 + od_table->GfxclkFreq3) / 2;
1137                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1138                         od_table->GfxclkFreq2;
1139
1140                 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1141                                    &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value),
1142                                      od_table->GfxclkFreq1),
1143                                 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1144                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0);
1145                 od_table->GfxclkVolt1 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
1146                         * VOLTAGE_SCALE;
1147
1148                 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1149                                    &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value),
1150                                      od_table->GfxclkFreq2),
1151                                 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1152                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0);
1153                 od_table->GfxclkVolt2 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
1154                         * VOLTAGE_SCALE;
1155
1156                 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1157                                    &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value),
1158                                      od_table->GfxclkFreq3),
1159                                 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1160                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0);
1161                 od_table->GfxclkVolt3 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
1162                         * VOLTAGE_SCALE;
1163         } else {
1164                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1165                         0;
1166                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value =
1167                         0;
1168                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1169                         0;
1170                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value =
1171                         0;
1172                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1173                         0;
1174                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value =
1175                         0;
1176         }
1177
1178         if (od8_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1179                 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1180                         od_table->UclkFmax;
1181         else
1182                 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1183                         0;
1184
1185         if (od8_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1186                 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1187                         od_table->OverDrivePct;
1188         else
1189                 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1190                         0;
1191
1192         if (od8_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1193                 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1194                         od_table->FanMaximumRpm;
1195         else
1196                 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1197                         0;
1198
1199         if (od8_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1200                 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1201                         od_table->FanMinimumPwm * data->smc_state_table.pp_table.FanMaximumRpm / 100;
1202         else
1203                 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1204                         0;
1205
1206         if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1207                 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1208                         od_table->FanTargetTemperature;
1209         else
1210                 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1211                         0;
1212
1213         if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1214                 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1215                         od_table->MaxOpTemp;
1216         else
1217                 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1218                         0;
1219
1220         for (i = 0; i < OD8_SETTING_COUNT; i++) {
1221                 if (od8_settings->od8_settings_array[i].feature_id) {
1222                         od8_settings->od8_settings_array[i].min_value =
1223                                 pptable_information->od_settings_min[i];
1224                         od8_settings->od8_settings_array[i].max_value =
1225                                 pptable_information->od_settings_max[i];
1226                         od8_settings->od8_settings_array[i].current_value =
1227                                 od8_settings->od8_settings_array[i].default_value;
1228                 } else {
1229                         od8_settings->od8_settings_array[i].min_value =
1230                                 0;
1231                         od8_settings->od8_settings_array[i].max_value =
1232                                 0;
1233                         od8_settings->od8_settings_array[i].current_value =
1234                                 0;
1235                 }
1236         }
1237
1238         ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, false);
1239         PP_ASSERT_WITH_CODE(!ret,
1240                         "Failed to import over drive table!",
1241                         return ret);
1242
1243         return 0;
1244 }
1245
1246 static int vega20_od8_set_settings(
1247                 struct pp_hwmgr *hwmgr,
1248                 uint32_t index,
1249                 uint32_t value)
1250 {
1251         OverDriveTable_t od_table;
1252         int ret = 0;
1253         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1254         struct vega20_od8_single_setting *od8_settings =
1255                         data->od8_settings.od8_settings_array;
1256
1257         ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, true);
1258         PP_ASSERT_WITH_CODE(!ret,
1259                         "Failed to export over drive table!",
1260                         return ret);
1261
1262         switch(index) {
1263         case OD8_SETTING_GFXCLK_FMIN:
1264                 od_table.GfxclkFmin = (uint16_t)value;
1265                 break;
1266         case OD8_SETTING_GFXCLK_FMAX:
1267                 if (value < od8_settings[OD8_SETTING_GFXCLK_FMAX].min_value ||
1268                     value > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value)
1269                         return -EINVAL;
1270
1271                 od_table.GfxclkFmax = (uint16_t)value;
1272                 break;
1273         case OD8_SETTING_GFXCLK_FREQ1:
1274                 od_table.GfxclkFreq1 = (uint16_t)value;
1275                 break;
1276         case OD8_SETTING_GFXCLK_VOLTAGE1:
1277                 od_table.GfxclkVolt1 = (uint16_t)value;
1278                 break;
1279         case OD8_SETTING_GFXCLK_FREQ2:
1280                 od_table.GfxclkFreq2 = (uint16_t)value;
1281                 break;
1282         case OD8_SETTING_GFXCLK_VOLTAGE2:
1283                 od_table.GfxclkVolt2 = (uint16_t)value;
1284                 break;
1285         case OD8_SETTING_GFXCLK_FREQ3:
1286                 od_table.GfxclkFreq3 = (uint16_t)value;
1287                 break;
1288         case OD8_SETTING_GFXCLK_VOLTAGE3:
1289                 od_table.GfxclkVolt3 = (uint16_t)value;
1290                 break;
1291         case OD8_SETTING_UCLK_FMAX:
1292                 if (value < od8_settings[OD8_SETTING_UCLK_FMAX].min_value ||
1293                     value > od8_settings[OD8_SETTING_UCLK_FMAX].max_value)
1294                         return -EINVAL;
1295                 od_table.UclkFmax = (uint16_t)value;
1296                 break;
1297         case OD8_SETTING_POWER_PERCENTAGE:
1298                 od_table.OverDrivePct = (int16_t)value;
1299                 break;
1300         case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
1301                 od_table.FanMaximumRpm = (uint16_t)value;
1302                 break;
1303         case OD8_SETTING_FAN_MIN_SPEED:
1304                 od_table.FanMinimumPwm = (uint16_t)value;
1305                 break;
1306         case OD8_SETTING_FAN_TARGET_TEMP:
1307                 od_table.FanTargetTemperature = (uint16_t)value;
1308                 break;
1309         case OD8_SETTING_OPERATING_TEMP_MAX:
1310                 od_table.MaxOpTemp = (uint16_t)value;
1311                 break;
1312         }
1313
1314         ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, false);
1315         PP_ASSERT_WITH_CODE(!ret,
1316                         "Failed to import over drive table!",
1317                         return ret);
1318
1319         return 0;
1320 }
1321
1322 static int vega20_get_sclk_od(
1323                 struct pp_hwmgr *hwmgr)
1324 {
1325         struct vega20_hwmgr *data = hwmgr->backend;
1326         struct vega20_single_dpm_table *sclk_table =
1327                         &(data->dpm_table.gfx_table);
1328         struct vega20_single_dpm_table *golden_sclk_table =
1329                         &(data->golden_dpm_table.gfx_table);
1330         int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
1331         int golden_value = golden_sclk_table->dpm_levels
1332                         [golden_sclk_table->count - 1].value;
1333
1334         /* od percentage */
1335         value -= golden_value;
1336         value = DIV_ROUND_UP(value * 100, golden_value);
1337
1338         return value;
1339 }
1340
1341 static int vega20_set_sclk_od(
1342                 struct pp_hwmgr *hwmgr, uint32_t value)
1343 {
1344         struct vega20_hwmgr *data = hwmgr->backend;
1345         struct vega20_single_dpm_table *golden_sclk_table =
1346                         &(data->golden_dpm_table.gfx_table);
1347         uint32_t od_sclk;
1348         int ret = 0;
1349
1350         od_sclk = golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * value;
1351         od_sclk /= 100;
1352         od_sclk += golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
1353
1354         ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_GFXCLK_FMAX, od_sclk);
1355         PP_ASSERT_WITH_CODE(!ret,
1356                         "[SetSclkOD] failed to set od gfxclk!",
1357                         return ret);
1358
1359         /* retrieve updated gfxclk table */
1360         ret = vega20_setup_gfxclk_dpm_table(hwmgr);
1361         PP_ASSERT_WITH_CODE(!ret,
1362                         "[SetSclkOD] failed to refresh gfxclk table!",
1363                         return ret);
1364
1365         return 0;
1366 }
1367
1368 static int vega20_get_mclk_od(
1369                 struct pp_hwmgr *hwmgr)
1370 {
1371         struct vega20_hwmgr *data = hwmgr->backend;
1372         struct vega20_single_dpm_table *mclk_table =
1373                         &(data->dpm_table.mem_table);
1374         struct vega20_single_dpm_table *golden_mclk_table =
1375                         &(data->golden_dpm_table.mem_table);
1376         int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
1377         int golden_value = golden_mclk_table->dpm_levels
1378                         [golden_mclk_table->count - 1].value;
1379
1380         /* od percentage */
1381         value -= golden_value;
1382         value = DIV_ROUND_UP(value * 100, golden_value);
1383
1384         return value;
1385 }
1386
1387 static int vega20_set_mclk_od(
1388                 struct pp_hwmgr *hwmgr, uint32_t value)
1389 {
1390         struct vega20_hwmgr *data = hwmgr->backend;
1391         struct vega20_single_dpm_table *golden_mclk_table =
1392                         &(data->golden_dpm_table.mem_table);
1393         uint32_t od_mclk;
1394         int ret = 0;
1395
1396         od_mclk = golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * value;
1397         od_mclk /= 100;
1398         od_mclk += golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
1399
1400         ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_UCLK_FMAX, od_mclk);
1401         PP_ASSERT_WITH_CODE(!ret,
1402                         "[SetMclkOD] failed to set od memclk!",
1403                         return ret);
1404
1405         /* retrieve updated memclk table */
1406         ret = vega20_setup_memclk_dpm_table(hwmgr);
1407         PP_ASSERT_WITH_CODE(!ret,
1408                         "[SetMclkOD] failed to refresh memclk table!",
1409                         return ret);
1410
1411         return 0;
1412 }
1413
1414 static int vega20_populate_umdpstate_clocks(
1415                 struct pp_hwmgr *hwmgr)
1416 {
1417         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1418         struct vega20_single_dpm_table *gfx_table = &(data->dpm_table.gfx_table);
1419         struct vega20_single_dpm_table *mem_table = &(data->dpm_table.mem_table);
1420
1421         hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value;
1422         hwmgr->pstate_mclk = mem_table->dpm_levels[0].value;
1423
1424         if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
1425             mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
1426                 hwmgr->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
1427                 hwmgr->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
1428         }
1429
1430         hwmgr->pstate_sclk = hwmgr->pstate_sclk * 100;
1431         hwmgr->pstate_mclk = hwmgr->pstate_mclk * 100;
1432
1433         return 0;
1434 }
1435
1436 static int vega20_get_max_sustainable_clock(struct pp_hwmgr *hwmgr,
1437                 PP_Clock *clock, PPCLK_e clock_select)
1438 {
1439         int ret = 0;
1440
1441         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1442                         PPSMC_MSG_GetDcModeMaxDpmFreq,
1443                         (clock_select << 16))) == 0,
1444                         "[GetMaxSustainableClock] Failed to get max DC clock from SMC!",
1445                         return ret);
1446         *clock = smum_get_argument(hwmgr);
1447
1448         /* if DC limit is zero, return AC limit */
1449         if (*clock == 0) {
1450                 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1451                         PPSMC_MSG_GetMaxDpmFreq,
1452                         (clock_select << 16))) == 0,
1453                         "[GetMaxSustainableClock] failed to get max AC clock from SMC!",
1454                         return ret);
1455                 *clock = smum_get_argument(hwmgr);
1456         }
1457
1458         return 0;
1459 }
1460
1461 static int vega20_init_max_sustainable_clocks(struct pp_hwmgr *hwmgr)
1462 {
1463         struct vega20_hwmgr *data =
1464                 (struct vega20_hwmgr *)(hwmgr->backend);
1465         struct vega20_max_sustainable_clocks *max_sustainable_clocks =
1466                 &(data->max_sustainable_clocks);
1467         int ret = 0;
1468
1469         max_sustainable_clocks->uclock = data->vbios_boot_state.mem_clock / 100;
1470         max_sustainable_clocks->soc_clock = data->vbios_boot_state.soc_clock / 100;
1471         max_sustainable_clocks->dcef_clock = data->vbios_boot_state.dcef_clock / 100;
1472         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
1473         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
1474         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
1475
1476         if (data->smu_features[GNLD_DPM_UCLK].enabled)
1477                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1478                                 &(max_sustainable_clocks->uclock),
1479                                 PPCLK_UCLK)) == 0,
1480                                 "[InitMaxSustainableClocks] failed to get max UCLK from SMC!",
1481                                 return ret);
1482
1483         if (data->smu_features[GNLD_DPM_SOCCLK].enabled)
1484                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1485                                 &(max_sustainable_clocks->soc_clock),
1486                                 PPCLK_SOCCLK)) == 0,
1487                                 "[InitMaxSustainableClocks] failed to get max SOCCLK from SMC!",
1488                                 return ret);
1489
1490         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1491                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1492                                 &(max_sustainable_clocks->dcef_clock),
1493                                 PPCLK_DCEFCLK)) == 0,
1494                                 "[InitMaxSustainableClocks] failed to get max DCEFCLK from SMC!",
1495                                 return ret);
1496                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1497                                 &(max_sustainable_clocks->display_clock),
1498                                 PPCLK_DISPCLK)) == 0,
1499                                 "[InitMaxSustainableClocks] failed to get max DISPCLK from SMC!",
1500                                 return ret);
1501                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1502                                 &(max_sustainable_clocks->phy_clock),
1503                                 PPCLK_PHYCLK)) == 0,
1504                                 "[InitMaxSustainableClocks] failed to get max PHYCLK from SMC!",
1505                                 return ret);
1506                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1507                                 &(max_sustainable_clocks->pixel_clock),
1508                                 PPCLK_PIXCLK)) == 0,
1509                                 "[InitMaxSustainableClocks] failed to get max PIXCLK from SMC!",
1510                                 return ret);
1511         }
1512
1513         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1514                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1515
1516         return 0;
1517 }
1518
1519 static int vega20_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
1520 {
1521         int result;
1522
1523         result = smum_send_msg_to_smc(hwmgr,
1524                 PPSMC_MSG_SetMGpuFanBoostLimitRpm);
1525         PP_ASSERT_WITH_CODE(!result,
1526                         "[EnableMgpuFan] Failed to enable mgpu fan boost!",
1527                         return result);
1528
1529         return 0;
1530 }
1531
1532 static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr)
1533 {
1534         struct vega20_hwmgr *data =
1535                 (struct vega20_hwmgr *)(hwmgr->backend);
1536
1537         data->uvd_power_gated = true;
1538         data->vce_power_gated = true;
1539
1540         if (data->smu_features[GNLD_DPM_UVD].enabled)
1541                 data->uvd_power_gated = false;
1542
1543         if (data->smu_features[GNLD_DPM_VCE].enabled)
1544                 data->vce_power_gated = false;
1545 }
1546
1547 static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1548 {
1549         int result = 0;
1550
1551         smum_send_msg_to_smc_with_parameter(hwmgr,
1552                         PPSMC_MSG_NumOfDisplays, 0);
1553
1554         result = vega20_set_allowed_featuresmask(hwmgr);
1555         PP_ASSERT_WITH_CODE(!result,
1556                         "[EnableDPMTasks] Failed to set allowed featuresmask!\n",
1557                         return result);
1558
1559         result = vega20_init_smc_table(hwmgr);
1560         PP_ASSERT_WITH_CODE(!result,
1561                         "[EnableDPMTasks] Failed to initialize SMC table!",
1562                         return result);
1563
1564         result = vega20_run_btc_afll(hwmgr);
1565         PP_ASSERT_WITH_CODE(!result,
1566                         "[EnableDPMTasks] Failed to run btc afll!",
1567                         return result);
1568
1569         result = vega20_enable_all_smu_features(hwmgr);
1570         PP_ASSERT_WITH_CODE(!result,
1571                         "[EnableDPMTasks] Failed to enable all smu features!",
1572                         return result);
1573
1574         result = vega20_notify_smc_display_change(hwmgr);
1575         PP_ASSERT_WITH_CODE(!result,
1576                         "[EnableDPMTasks] Failed to notify smc display change!",
1577                         return result);
1578
1579         result = vega20_send_clock_ratio(hwmgr);
1580         PP_ASSERT_WITH_CODE(!result,
1581                         "[EnableDPMTasks] Failed to send clock ratio!",
1582                         return result);
1583
1584         /* Initialize UVD/VCE powergating state */
1585         vega20_init_powergate_state(hwmgr);
1586
1587         result = vega20_setup_default_dpm_tables(hwmgr);
1588         PP_ASSERT_WITH_CODE(!result,
1589                         "[EnableDPMTasks] Failed to setup default DPM tables!",
1590                         return result);
1591
1592         result = vega20_init_max_sustainable_clocks(hwmgr);
1593         PP_ASSERT_WITH_CODE(!result,
1594                         "[EnableDPMTasks] Failed to get maximum sustainable clocks!",
1595                         return result);
1596
1597         result = vega20_power_control_set_level(hwmgr);
1598         PP_ASSERT_WITH_CODE(!result,
1599                         "[EnableDPMTasks] Failed to power control set level!",
1600                         return result);
1601
1602         result = vega20_od8_initialize_default_settings(hwmgr);
1603         PP_ASSERT_WITH_CODE(!result,
1604                         "[EnableDPMTasks] Failed to initialize odn settings!",
1605                         return result);
1606
1607         result = vega20_populate_umdpstate_clocks(hwmgr);
1608         PP_ASSERT_WITH_CODE(!result,
1609                         "[EnableDPMTasks] Failed to populate umdpstate clocks!",
1610                         return result);
1611
1612         result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetPptLimit,
1613                         POWER_SOURCE_AC << 16);
1614         PP_ASSERT_WITH_CODE(!result,
1615                         "[GetPptLimit] get default PPT limit failed!",
1616                         return result);
1617         hwmgr->power_limit =
1618                 hwmgr->default_power_limit = smum_get_argument(hwmgr);
1619
1620         return 0;
1621 }
1622
1623 static uint32_t vega20_find_lowest_dpm_level(
1624                 struct vega20_single_dpm_table *table)
1625 {
1626         uint32_t i;
1627
1628         for (i = 0; i < table->count; i++) {
1629                 if (table->dpm_levels[i].enabled)
1630                         break;
1631         }
1632         if (i >= table->count) {
1633                 i = 0;
1634                 table->dpm_levels[i].enabled = true;
1635         }
1636
1637         return i;
1638 }
1639
1640 static uint32_t vega20_find_highest_dpm_level(
1641                 struct vega20_single_dpm_table *table)
1642 {
1643         int i = 0;
1644
1645         PP_ASSERT_WITH_CODE(table != NULL,
1646                         "[FindHighestDPMLevel] DPM Table does not exist!",
1647                         return 0);
1648         PP_ASSERT_WITH_CODE(table->count > 0,
1649                         "[FindHighestDPMLevel] DPM Table has no entry!",
1650                         return 0);
1651         PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
1652                         "[FindHighestDPMLevel] DPM Table has too many entries!",
1653                         return MAX_REGULAR_DPM_NUMBER - 1);
1654
1655         for (i = table->count - 1; i >= 0; i--) {
1656                 if (table->dpm_levels[i].enabled)
1657                         break;
1658         }
1659         if (i < 0) {
1660                 i = 0;
1661                 table->dpm_levels[i].enabled = true;
1662         }
1663
1664         return i;
1665 }
1666
1667 static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
1668 {
1669         struct vega20_hwmgr *data =
1670                         (struct vega20_hwmgr *)(hwmgr->backend);
1671         uint32_t min_freq;
1672         int ret = 0;
1673
1674         if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1675                 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
1676                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1677                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1678                                         (PPCLK_GFXCLK << 16) | (min_freq & 0xffff))),
1679                                         "Failed to set soft min gfxclk !",
1680                                         return ret);
1681         }
1682
1683         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1684                 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
1685                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1686                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1687                                         (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
1688                                         "Failed to set soft min memclk !",
1689                                         return ret);
1690
1691                 min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level;
1692                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1693                                         hwmgr, PPSMC_MSG_SetHardMinByFreq,
1694                                         (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
1695                                         "Failed to set hard min memclk !",
1696                                         return ret);
1697         }
1698
1699         if (data->smu_features[GNLD_DPM_UVD].enabled) {
1700                 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
1701
1702                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1703                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1704                                         (PPCLK_VCLK << 16) | (min_freq & 0xffff))),
1705                                         "Failed to set soft min vclk!",
1706                                         return ret);
1707
1708                 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level;
1709
1710                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1711                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1712                                         (PPCLK_DCLK << 16) | (min_freq & 0xffff))),
1713                                         "Failed to set soft min dclk!",
1714                                         return ret);
1715         }
1716
1717         if (data->smu_features[GNLD_DPM_VCE].enabled) {
1718                 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
1719
1720                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1721                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1722                                         (PPCLK_ECLK << 16) | (min_freq & 0xffff))),
1723                                         "Failed to set soft min eclk!",
1724                                         return ret);
1725         }
1726
1727         if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
1728                 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
1729
1730                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1731                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1732                                         (PPCLK_SOCCLK << 16) | (min_freq & 0xffff))),
1733                                         "Failed to set soft min socclk!",
1734                                         return ret);
1735         }
1736
1737         return ret;
1738 }
1739
1740 static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
1741 {
1742         struct vega20_hwmgr *data =
1743                         (struct vega20_hwmgr *)(hwmgr->backend);
1744         uint32_t max_freq;
1745         int ret = 0;
1746
1747         if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1748                 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
1749
1750                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1751                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1752                                         (PPCLK_GFXCLK << 16) | (max_freq & 0xffff))),
1753                                         "Failed to set soft max gfxclk!",
1754                                         return ret);
1755         }
1756
1757         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1758                 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
1759
1760                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1761                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1762                                         (PPCLK_UCLK << 16) | (max_freq & 0xffff))),
1763                                         "Failed to set soft max memclk!",
1764                                         return ret);
1765         }
1766
1767         if (data->smu_features[GNLD_DPM_UVD].enabled) {
1768                 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
1769
1770                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1771                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1772                                         (PPCLK_VCLK << 16) | (max_freq & 0xffff))),
1773                                         "Failed to set soft max vclk!",
1774                                         return ret);
1775
1776                 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level;
1777                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1778                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1779                                         (PPCLK_DCLK << 16) | (max_freq & 0xffff))),
1780                                         "Failed to set soft max dclk!",
1781                                         return ret);
1782         }
1783
1784         if (data->smu_features[GNLD_DPM_VCE].enabled) {
1785                 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
1786
1787                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1788                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1789                                         (PPCLK_ECLK << 16) | (max_freq & 0xffff))),
1790                                         "Failed to set soft max eclk!",
1791                                         return ret);
1792         }
1793
1794         if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
1795                 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
1796
1797                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1798                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1799                                         (PPCLK_SOCCLK << 16) | (max_freq & 0xffff))),
1800                                         "Failed to set soft max socclk!",
1801                                         return ret);
1802         }
1803
1804         return ret;
1805 }
1806
1807 int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
1808 {
1809         struct vega20_hwmgr *data =
1810                         (struct vega20_hwmgr *)(hwmgr->backend);
1811         int ret = 0;
1812
1813         if (data->smu_features[GNLD_DPM_VCE].supported) {
1814                 if (data->smu_features[GNLD_DPM_VCE].enabled == enable) {
1815                         if (enable)
1816                                 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already enabled!\n");
1817                         else
1818                                 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already disabled!\n");
1819                 }
1820
1821                 ret = vega20_enable_smc_features(hwmgr,
1822                                 enable,
1823                                 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap);
1824                 PP_ASSERT_WITH_CODE(!ret,
1825                                 "Attempt to Enable/Disable DPM VCE Failed!",
1826                                 return ret);
1827                 data->smu_features[GNLD_DPM_VCE].enabled = enable;
1828         }
1829
1830         return 0;
1831 }
1832
1833 static int vega20_get_clock_ranges(struct pp_hwmgr *hwmgr,
1834                 uint32_t *clock,
1835                 PPCLK_e clock_select,
1836                 bool max)
1837 {
1838         int ret;
1839         *clock = 0;
1840
1841         if (max) {
1842                 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1843                                 PPSMC_MSG_GetMaxDpmFreq, (clock_select << 16))) == 0,
1844                                 "[GetClockRanges] Failed to get max clock from SMC!",
1845                                 return ret);
1846                 *clock = smum_get_argument(hwmgr);
1847         } else {
1848                 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1849                                 PPSMC_MSG_GetMinDpmFreq,
1850                                 (clock_select << 16))) == 0,
1851                                 "[GetClockRanges] Failed to get min clock from SMC!",
1852                                 return ret);
1853                 *clock = smum_get_argument(hwmgr);
1854         }
1855
1856         return 0;
1857 }
1858
1859 static uint32_t vega20_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1860 {
1861         struct vega20_hwmgr *data =
1862                         (struct vega20_hwmgr *)(hwmgr->backend);
1863         uint32_t gfx_clk;
1864         int ret = 0;
1865
1866         PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,
1867                         "[GetSclks]: gfxclk dpm not enabled!\n",
1868                         return -EPERM);
1869
1870         if (low) {
1871                 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false);
1872                 PP_ASSERT_WITH_CODE(!ret,
1873                         "[GetSclks]: fail to get min PPCLK_GFXCLK\n",
1874                         return ret);
1875         } else {
1876                 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true);
1877                 PP_ASSERT_WITH_CODE(!ret,
1878                         "[GetSclks]: fail to get max PPCLK_GFXCLK\n",
1879                         return ret);
1880         }
1881
1882         return (gfx_clk * 100);
1883 }
1884
1885 static uint32_t vega20_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1886 {
1887         struct vega20_hwmgr *data =
1888                         (struct vega20_hwmgr *)(hwmgr->backend);
1889         uint32_t mem_clk;
1890         int ret = 0;
1891
1892         PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,
1893                         "[MemMclks]: memclk dpm not enabled!\n",
1894                         return -EPERM);
1895
1896         if (low) {
1897                 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false);
1898                 PP_ASSERT_WITH_CODE(!ret,
1899                         "[GetMclks]: fail to get min PPCLK_UCLK\n",
1900                         return ret);
1901         } else {
1902                 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true);
1903                 PP_ASSERT_WITH_CODE(!ret,
1904                         "[GetMclks]: fail to get max PPCLK_UCLK\n",
1905                         return ret);
1906         }
1907
1908         return (mem_clk * 100);
1909 }
1910
1911 static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr,
1912                 uint32_t *query)
1913 {
1914         int ret = 0;
1915         SmuMetrics_t metrics_table;
1916
1917         ret = smum_smc_table_manager(hwmgr, (uint8_t *)&metrics_table, TABLE_SMU_METRICS, true);
1918         PP_ASSERT_WITH_CODE(!ret,
1919                         "Failed to export SMU METRICS table!",
1920                         return ret);
1921
1922         *query = metrics_table.CurrSocketPower << 8;
1923
1924         return ret;
1925 }
1926
1927 static int vega20_get_current_clk_freq(struct pp_hwmgr *hwmgr,
1928                 PPCLK_e clk_id, uint32_t *clk_freq)
1929 {
1930         int ret = 0;
1931
1932         *clk_freq = 0;
1933
1934         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1935                         PPSMC_MSG_GetDpmClockFreq, (clk_id << 16))) == 0,
1936                         "[GetCurrentClkFreq] Attempt to get Current Frequency Failed!",
1937                         return ret);
1938         *clk_freq = smum_get_argument(hwmgr);
1939
1940         *clk_freq = *clk_freq * 100;
1941
1942         return 0;
1943 }
1944
1945 static int vega20_get_current_activity_percent(struct pp_hwmgr *hwmgr,
1946                 uint32_t *activity_percent)
1947 {
1948         int ret = 0;
1949         SmuMetrics_t metrics_table;
1950
1951         ret = smum_smc_table_manager(hwmgr, (uint8_t *)&metrics_table, TABLE_SMU_METRICS, true);
1952         PP_ASSERT_WITH_CODE(!ret,
1953                         "Failed to export SMU METRICS table!",
1954                         return ret);
1955
1956         *activity_percent = metrics_table.AverageGfxActivity;
1957
1958         return ret;
1959 }
1960
1961 static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1962                               void *value, int *size)
1963 {
1964         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1965         struct amdgpu_device *adev = hwmgr->adev;
1966         uint32_t val_vid;
1967         int ret = 0;
1968
1969         switch (idx) {
1970         case AMDGPU_PP_SENSOR_GFX_SCLK:
1971                 ret = vega20_get_current_clk_freq(hwmgr,
1972                                 PPCLK_GFXCLK,
1973                                 (uint32_t *)value);
1974                 if (!ret)
1975                         *size = 4;
1976                 break;
1977         case AMDGPU_PP_SENSOR_GFX_MCLK:
1978                 ret = vega20_get_current_clk_freq(hwmgr,
1979                                 PPCLK_UCLK,
1980                                 (uint32_t *)value);
1981                 if (!ret)
1982                         *size = 4;
1983                 break;
1984         case AMDGPU_PP_SENSOR_GPU_LOAD:
1985                 ret = vega20_get_current_activity_percent(hwmgr, (uint32_t *)value);
1986                 if (!ret)
1987                         *size = 4;
1988                 break;
1989         case AMDGPU_PP_SENSOR_GPU_TEMP:
1990                 *((uint32_t *)value) = vega20_thermal_get_temperature(hwmgr);
1991                 *size = 4;
1992                 break;
1993         case AMDGPU_PP_SENSOR_UVD_POWER:
1994                 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
1995                 *size = 4;
1996                 break;
1997         case AMDGPU_PP_SENSOR_VCE_POWER:
1998                 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
1999                 *size = 4;
2000                 break;
2001         case AMDGPU_PP_SENSOR_GPU_POWER:
2002                 *size = 16;
2003                 ret = vega20_get_gpu_power(hwmgr, (uint32_t *)value);
2004                 break;
2005         case AMDGPU_PP_SENSOR_VDDGFX:
2006                 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
2007                         SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
2008                         SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
2009                 *((uint32_t *)value) =
2010                         (uint32_t)convert_to_vddc((uint8_t)val_vid);
2011                 break;
2012         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2013                 ret = vega20_get_enabled_smc_features(hwmgr, (uint64_t *)value);
2014                 if (!ret)
2015                         *size = 8;
2016                 break;
2017         default:
2018                 ret = -EINVAL;
2019                 break;
2020         }
2021         return ret;
2022 }
2023
2024 int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
2025                 struct pp_display_clock_request *clock_req)
2026 {
2027         int result = 0;
2028         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2029         enum amd_pp_clock_type clk_type = clock_req->clock_type;
2030         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
2031         PPCLK_e clk_select = 0;
2032         uint32_t clk_request = 0;
2033
2034         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
2035                 switch (clk_type) {
2036                 case amd_pp_dcef_clock:
2037                         clk_select = PPCLK_DCEFCLK;
2038                         break;
2039                 case amd_pp_disp_clock:
2040                         clk_select = PPCLK_DISPCLK;
2041                         break;
2042                 case amd_pp_pixel_clock:
2043                         clk_select = PPCLK_PIXCLK;
2044                         break;
2045                 case amd_pp_phy_clock:
2046                         clk_select = PPCLK_PHYCLK;
2047                         break;
2048                 default:
2049                         pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
2050                         result = -EINVAL;
2051                         break;
2052                 }
2053
2054                 if (!result) {
2055                         clk_request = (clk_select << 16) | clk_freq;
2056                         result = smum_send_msg_to_smc_with_parameter(hwmgr,
2057                                         PPSMC_MSG_SetHardMinByFreq,
2058                                         clk_request);
2059                 }
2060         }
2061
2062         return result;
2063 }
2064
2065 static int vega20_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
2066                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
2067                                 PHM_PerformanceLevel *level)
2068 {
2069         return 0;
2070 }
2071
2072 static int vega20_notify_smc_display_config_after_ps_adjustment(
2073                 struct pp_hwmgr *hwmgr)
2074 {
2075         struct vega20_hwmgr *data =
2076                         (struct vega20_hwmgr *)(hwmgr->backend);
2077         struct vega20_single_dpm_table *dpm_table =
2078                         &data->dpm_table.mem_table;
2079         struct PP_Clocks min_clocks = {0};
2080         struct pp_display_clock_request clock_req;
2081         int ret = 0;
2082
2083         min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
2084         min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
2085         min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
2086
2087         if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
2088                 clock_req.clock_type = amd_pp_dcef_clock;
2089                 clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10;
2090                 if (!vega20_display_clock_voltage_request(hwmgr, &clock_req)) {
2091                         if (data->smu_features[GNLD_DS_DCEFCLK].supported)
2092                                 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(
2093                                         hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
2094                                         min_clocks.dcefClockInSR / 100)) == 0,
2095                                         "Attempt to set divider for DCEFCLK Failed!",
2096                                         return ret);
2097                 } else {
2098                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
2099                 }
2100         }
2101
2102         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2103                 dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100;
2104                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2105                                 PPSMC_MSG_SetHardMinByFreq,
2106                                 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
2107                                 "[SetHardMinFreq] Set hard min uclk failed!",
2108                                 return ret);
2109         }
2110
2111         return 0;
2112 }
2113
2114 static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr)
2115 {
2116         struct vega20_hwmgr *data =
2117                         (struct vega20_hwmgr *)(hwmgr->backend);
2118         uint32_t soft_level;
2119         int ret = 0;
2120
2121         soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table));
2122
2123         data->dpm_table.gfx_table.dpm_state.soft_min_level =
2124                 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2125                 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2126
2127         soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.mem_table));
2128
2129         data->dpm_table.mem_table.dpm_state.soft_min_level =
2130                 data->dpm_table.mem_table.dpm_state.soft_max_level =
2131                 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2132
2133         ret = vega20_upload_dpm_min_level(hwmgr);
2134         PP_ASSERT_WITH_CODE(!ret,
2135                         "Failed to upload boot level to highest!",
2136                         return ret);
2137
2138         ret = vega20_upload_dpm_max_level(hwmgr);
2139         PP_ASSERT_WITH_CODE(!ret,
2140                         "Failed to upload dpm max level to highest!",
2141                         return ret);
2142
2143         return 0;
2144 }
2145
2146 static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2147 {
2148         struct vega20_hwmgr *data =
2149                         (struct vega20_hwmgr *)(hwmgr->backend);
2150         uint32_t soft_level;
2151         int ret = 0;
2152
2153         soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
2154
2155         data->dpm_table.gfx_table.dpm_state.soft_min_level =
2156                 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2157                 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2158
2159         soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table));
2160
2161         data->dpm_table.mem_table.dpm_state.soft_min_level =
2162                 data->dpm_table.mem_table.dpm_state.soft_max_level =
2163                 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2164
2165         ret = vega20_upload_dpm_min_level(hwmgr);
2166         PP_ASSERT_WITH_CODE(!ret,
2167                         "Failed to upload boot level to highest!",
2168                         return ret);
2169
2170         ret = vega20_upload_dpm_max_level(hwmgr);
2171         PP_ASSERT_WITH_CODE(!ret,
2172                         "Failed to upload dpm max level to highest!",
2173                         return ret);
2174
2175         return 0;
2176
2177 }
2178
2179 static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
2180 {
2181         int ret = 0;
2182
2183         ret = vega20_upload_dpm_min_level(hwmgr);
2184         PP_ASSERT_WITH_CODE(!ret,
2185                         "Failed to upload DPM Bootup Levels!",
2186                         return ret);
2187
2188         ret = vega20_upload_dpm_max_level(hwmgr);
2189         PP_ASSERT_WITH_CODE(!ret,
2190                         "Failed to upload DPM Max Levels!",
2191                         return ret);
2192
2193         return 0;
2194 }
2195
2196 static int vega20_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
2197                                 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
2198 {
2199         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2200         struct vega20_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table);
2201         struct vega20_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table);
2202         struct vega20_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table);
2203
2204         *sclk_mask = 0;
2205         *mclk_mask = 0;
2206         *soc_mask  = 0;
2207
2208         if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
2209             mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
2210             soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
2211                 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
2212                 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
2213                 *soc_mask  = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
2214         }
2215
2216         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2217                 *sclk_mask = 0;
2218         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2219                 *mclk_mask = 0;
2220         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2221                 *sclk_mask = gfx_dpm_table->count - 1;
2222                 *mclk_mask = mem_dpm_table->count - 1;
2223                 *soc_mask  = soc_dpm_table->count - 1;
2224         }
2225
2226         return 0;
2227 }
2228
2229 static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
2230                 enum pp_clock_type type, uint32_t mask)
2231 {
2232         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2233         uint32_t soft_min_level, soft_max_level;
2234         int ret = 0;
2235
2236         switch (type) {
2237         case PP_SCLK:
2238                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2239                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2240
2241                 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2242                         data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
2243                 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2244                         data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
2245
2246                 ret = vega20_upload_dpm_min_level(hwmgr);
2247                 PP_ASSERT_WITH_CODE(!ret,
2248                         "Failed to upload boot level to lowest!",
2249                         return ret);
2250
2251                 ret = vega20_upload_dpm_max_level(hwmgr);
2252                 PP_ASSERT_WITH_CODE(!ret,
2253                         "Failed to upload dpm max level to highest!",
2254                         return ret);
2255                 break;
2256
2257         case PP_MCLK:
2258                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2259                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2260
2261                 data->dpm_table.mem_table.dpm_state.soft_min_level =
2262                         data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
2263                 data->dpm_table.mem_table.dpm_state.soft_max_level =
2264                         data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
2265
2266                 ret = vega20_upload_dpm_min_level(hwmgr);
2267                 PP_ASSERT_WITH_CODE(!ret,
2268                         "Failed to upload boot level to lowest!",
2269                         return ret);
2270
2271                 ret = vega20_upload_dpm_max_level(hwmgr);
2272                 PP_ASSERT_WITH_CODE(!ret,
2273                         "Failed to upload dpm max level to highest!",
2274                         return ret);
2275
2276                 break;
2277
2278         case PP_PCIE:
2279                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2280                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2281                 if (soft_min_level >= NUM_LINK_LEVELS ||
2282                     soft_max_level >= NUM_LINK_LEVELS)
2283                         return -EINVAL;
2284
2285                 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2286                         PPSMC_MSG_SetMinLinkDpmByIndex, soft_min_level);
2287                 PP_ASSERT_WITH_CODE(!ret,
2288                         "Failed to set min link dpm level!",
2289                         return ret);
2290
2291                 break;
2292
2293         default:
2294                 break;
2295         }
2296
2297         return 0;
2298 }
2299
2300 static int vega20_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
2301                                 enum amd_dpm_forced_level level)
2302 {
2303         int ret = 0;
2304         uint32_t sclk_mask, mclk_mask, soc_mask;
2305
2306         switch (level) {
2307         case AMD_DPM_FORCED_LEVEL_HIGH:
2308                 ret = vega20_force_dpm_highest(hwmgr);
2309                 break;
2310
2311         case AMD_DPM_FORCED_LEVEL_LOW:
2312                 ret = vega20_force_dpm_lowest(hwmgr);
2313                 break;
2314
2315         case AMD_DPM_FORCED_LEVEL_AUTO:
2316                 ret = vega20_unforce_dpm_levels(hwmgr);
2317                 break;
2318
2319         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
2320         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
2321         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
2322         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
2323                 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
2324                 if (ret)
2325                         return ret;
2326                 vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
2327                 vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
2328                 break;
2329
2330         case AMD_DPM_FORCED_LEVEL_MANUAL:
2331         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
2332         default:
2333                 break;
2334         }
2335
2336         return ret;
2337 }
2338
2339 static uint32_t vega20_get_fan_control_mode(struct pp_hwmgr *hwmgr)
2340 {
2341         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2342
2343         if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
2344                 return AMD_FAN_CTRL_MANUAL;
2345         else
2346                 return AMD_FAN_CTRL_AUTO;
2347 }
2348
2349 static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
2350 {
2351         switch (mode) {
2352         case AMD_FAN_CTRL_NONE:
2353                 vega20_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
2354                 break;
2355         case AMD_FAN_CTRL_MANUAL:
2356                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2357                         vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
2358                 break;
2359         case AMD_FAN_CTRL_AUTO:
2360                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2361                         vega20_fan_ctrl_start_smc_fan_control(hwmgr);
2362                 break;
2363         default:
2364                 break;
2365         }
2366 }
2367
2368 static int vega20_get_dal_power_level(struct pp_hwmgr *hwmgr,
2369                 struct amd_pp_simple_clock_info *info)
2370 {
2371 #if 0
2372         struct phm_ppt_v2_information *table_info =
2373                         (struct phm_ppt_v2_information *)hwmgr->pptable;
2374         struct phm_clock_and_voltage_limits *max_limits =
2375                         &table_info->max_clock_voltage_on_ac;
2376
2377         info->engine_max_clock = max_limits->sclk;
2378         info->memory_max_clock = max_limits->mclk;
2379 #endif
2380         return 0;
2381 }
2382
2383
2384 static int vega20_get_sclks(struct pp_hwmgr *hwmgr,
2385                 struct pp_clock_levels_with_latency *clocks)
2386 {
2387         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2388         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
2389         int i, count;
2390
2391         PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,
2392                 "[GetSclks]: gfxclk dpm not enabled!\n",
2393                 return -EPERM);
2394
2395         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2396         clocks->num_levels = count;
2397
2398         for (i = 0; i < count; i++) {
2399                 clocks->data[i].clocks_in_khz =
2400                         dpm_table->dpm_levels[i].value * 1000;
2401                 clocks->data[i].latency_in_us = 0;
2402         }
2403
2404         return 0;
2405 }
2406
2407 static uint32_t vega20_get_mem_latency(struct pp_hwmgr *hwmgr,
2408                 uint32_t clock)
2409 {
2410         return 25;
2411 }
2412
2413 static int vega20_get_memclocks(struct pp_hwmgr *hwmgr,
2414                 struct pp_clock_levels_with_latency *clocks)
2415 {
2416         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2417         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.mem_table);
2418         int i, count;
2419
2420         PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,
2421                 "[GetMclks]: uclk dpm not enabled!\n",
2422                 return -EPERM);
2423
2424         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2425         clocks->num_levels = data->mclk_latency_table.count = count;
2426
2427         for (i = 0; i < count; i++) {
2428                 clocks->data[i].clocks_in_khz =
2429                         data->mclk_latency_table.entries[i].frequency =
2430                         dpm_table->dpm_levels[i].value * 1000;
2431                 clocks->data[i].latency_in_us =
2432                         data->mclk_latency_table.entries[i].latency =
2433                         vega20_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
2434         }
2435
2436         return 0;
2437 }
2438
2439 static int vega20_get_dcefclocks(struct pp_hwmgr *hwmgr,
2440                 struct pp_clock_levels_with_latency *clocks)
2441 {
2442         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2443         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.dcef_table);
2444         int i, count;
2445
2446         PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_DCEFCLK].enabled,
2447                 "[GetDcfclocks]: dcefclk dpm not enabled!\n",
2448                 return -EPERM);
2449
2450         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2451         clocks->num_levels = count;
2452
2453         for (i = 0; i < count; i++) {
2454                 clocks->data[i].clocks_in_khz =
2455                         dpm_table->dpm_levels[i].value * 1000;
2456                 clocks->data[i].latency_in_us = 0;
2457         }
2458
2459         return 0;
2460 }
2461
2462 static int vega20_get_socclocks(struct pp_hwmgr *hwmgr,
2463                 struct pp_clock_levels_with_latency *clocks)
2464 {
2465         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2466         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.soc_table);
2467         int i, count;
2468
2469         PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_SOCCLK].enabled,
2470                 "[GetSocclks]: socclk dpm not enabled!\n",
2471                 return -EPERM);
2472
2473         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2474         clocks->num_levels = count;
2475
2476         for (i = 0; i < count; i++) {
2477                 clocks->data[i].clocks_in_khz =
2478                         dpm_table->dpm_levels[i].value * 1000;
2479                 clocks->data[i].latency_in_us = 0;
2480         }
2481
2482         return 0;
2483
2484 }
2485
2486 static int vega20_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
2487                 enum amd_pp_clock_type type,
2488                 struct pp_clock_levels_with_latency *clocks)
2489 {
2490         int ret;
2491
2492         switch (type) {
2493         case amd_pp_sys_clock:
2494                 ret = vega20_get_sclks(hwmgr, clocks);
2495                 break;
2496         case amd_pp_mem_clock:
2497                 ret = vega20_get_memclocks(hwmgr, clocks);
2498                 break;
2499         case amd_pp_dcef_clock:
2500                 ret = vega20_get_dcefclocks(hwmgr, clocks);
2501                 break;
2502         case amd_pp_soc_clock:
2503                 ret = vega20_get_socclocks(hwmgr, clocks);
2504                 break;
2505         default:
2506                 return -EINVAL;
2507         }
2508
2509         return ret;
2510 }
2511
2512 static int vega20_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
2513                 enum amd_pp_clock_type type,
2514                 struct pp_clock_levels_with_voltage *clocks)
2515 {
2516         clocks->num_levels = 0;
2517
2518         return 0;
2519 }
2520
2521 static int vega20_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
2522                                                    void *clock_ranges)
2523 {
2524         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2525         Watermarks_t *table = &(data->smc_state_table.water_marks_table);
2526         struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
2527
2528         if (!data->registry_data.disable_water_mark &&
2529             data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2530             data->smu_features[GNLD_DPM_SOCCLK].supported) {
2531                 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
2532                 data->water_marks_bitmap |= WaterMarksExist;
2533                 data->water_marks_bitmap &= ~WaterMarksLoaded;
2534         }
2535
2536         return 0;
2537 }
2538
2539 static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
2540                                         enum PP_OD_DPM_TABLE_COMMAND type,
2541                                         long *input, uint32_t size)
2542 {
2543         struct vega20_hwmgr *data =
2544                         (struct vega20_hwmgr *)(hwmgr->backend);
2545         struct vega20_od8_single_setting *od8_settings =
2546                         data->od8_settings.od8_settings_array;
2547         OverDriveTable_t *od_table =
2548                         &(data->smc_state_table.overdrive_table);
2549         struct pp_clock_levels_with_latency clocks;
2550         int32_t input_index, input_clk, input_vol, i;
2551         int od8_id;
2552         int ret;
2553
2554         PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
2555                                 return -EINVAL);
2556
2557         switch (type) {
2558         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2559                 if (!(od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2560                       od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
2561                         pr_info("Sclk min/max frequency overdrive not supported\n");
2562                         return -EOPNOTSUPP;
2563                 }
2564
2565                 for (i = 0; i < size; i += 2) {
2566                         if (i + 2 > size) {
2567                                 pr_info("invalid number of input parameters %d\n",
2568                                         size);
2569                                 return -EINVAL;
2570                         }
2571
2572                         input_index = input[i];
2573                         input_clk = input[i + 1];
2574
2575                         if (input_index != 0 && input_index != 1) {
2576                                 pr_info("Invalid index %d\n", input_index);
2577                                 pr_info("Support min/max sclk frequency setting only which index by 0/1\n");
2578                                 return -EINVAL;
2579                         }
2580
2581                         if (input_clk < od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value ||
2582                             input_clk > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) {
2583                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2584                                         input_clk,
2585                                         od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
2586                                         od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
2587                                 return -EINVAL;
2588                         }
2589
2590                         if ((input_index == 0 && od_table->GfxclkFmin != input_clk) ||
2591                             (input_index == 1 && od_table->GfxclkFmax != input_clk))
2592                                 data->gfxclk_overdrive = true;
2593
2594                         if (input_index == 0)
2595                                 od_table->GfxclkFmin = input_clk;
2596                         else
2597                                 od_table->GfxclkFmax = input_clk;
2598                 }
2599
2600                 break;
2601
2602         case PP_OD_EDIT_MCLK_VDDC_TABLE:
2603                 if (!od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2604                         pr_info("Mclk max frequency overdrive not supported\n");
2605                         return -EOPNOTSUPP;
2606                 }
2607
2608                 ret = vega20_get_memclocks(hwmgr, &clocks);
2609                 PP_ASSERT_WITH_CODE(!ret,
2610                                 "Attempt to get memory clk levels failed!",
2611                                 return ret);
2612
2613                 for (i = 0; i < size; i += 2) {
2614                         if (i + 2 > size) {
2615                                 pr_info("invalid number of input parameters %d\n",
2616                                         size);
2617                                 return -EINVAL;
2618                         }
2619
2620                         input_index = input[i];
2621                         input_clk = input[i + 1];
2622
2623                         if (input_index != 1) {
2624                                 pr_info("Invalid index %d\n", input_index);
2625                                 pr_info("Support max Mclk frequency setting only which index by 1\n");
2626                                 return -EINVAL;
2627                         }
2628
2629                         if (input_clk < clocks.data[0].clocks_in_khz / 1000 ||
2630                             input_clk > od8_settings[OD8_SETTING_UCLK_FMAX].max_value) {
2631                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2632                                         input_clk,
2633                                         clocks.data[0].clocks_in_khz / 1000,
2634                                         od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
2635                                 return -EINVAL;
2636                         }
2637
2638                         if (input_index == 1 && od_table->UclkFmax != input_clk)
2639                                 data->memclk_overdrive = true;
2640
2641                         od_table->UclkFmax = input_clk;
2642                 }
2643
2644                 break;
2645
2646         case PP_OD_EDIT_VDDC_CURVE:
2647                 if (!(od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2648                     od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2649                     od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2650                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2651                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2652                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
2653                         pr_info("Voltage curve calibrate not supported\n");
2654                         return -EOPNOTSUPP;
2655                 }
2656
2657                 for (i = 0; i < size; i += 3) {
2658                         if (i + 3 > size) {
2659                                 pr_info("invalid number of input parameters %d\n",
2660                                         size);
2661                                 return -EINVAL;
2662                         }
2663
2664                         input_index = input[i];
2665                         input_clk = input[i + 1];
2666                         input_vol = input[i + 2];
2667
2668                         if (input_index > 2) {
2669                                 pr_info("Setting for point %d is not supported\n",
2670                                                 input_index + 1);
2671                                 pr_info("Three supported points index by 0, 1, 2\n");
2672                                 return -EINVAL;
2673                         }
2674
2675                         od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
2676                         if (input_clk < od8_settings[od8_id].min_value ||
2677                             input_clk > od8_settings[od8_id].max_value) {
2678                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2679                                         input_clk,
2680                                         od8_settings[od8_id].min_value,
2681                                         od8_settings[od8_id].max_value);
2682                                 return -EINVAL;
2683                         }
2684
2685                         od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
2686                         if (input_vol < od8_settings[od8_id].min_value ||
2687                             input_vol > od8_settings[od8_id].max_value) {
2688                                 pr_info("clock voltage %d is not within allowed range [%d - %d]\n",
2689                                         input_vol,
2690                                         od8_settings[od8_id].min_value,
2691                                         od8_settings[od8_id].max_value);
2692                                 return -EINVAL;
2693                         }
2694
2695                         switch (input_index) {
2696                         case 0:
2697                                 od_table->GfxclkFreq1 = input_clk;
2698                                 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
2699                                 break;
2700                         case 1:
2701                                 od_table->GfxclkFreq2 = input_clk;
2702                                 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
2703                                 break;
2704                         case 2:
2705                                 od_table->GfxclkFreq3 = input_clk;
2706                                 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
2707                                 break;
2708                         }
2709                 }
2710                 break;
2711
2712         case PP_OD_RESTORE_DEFAULT_TABLE:
2713                 data->gfxclk_overdrive = false;
2714                 data->memclk_overdrive = false;
2715
2716                 ret = smum_smc_table_manager(hwmgr,
2717                                              (uint8_t *)od_table,
2718                                              TABLE_OVERDRIVE, true);
2719                 PP_ASSERT_WITH_CODE(!ret,
2720                                 "Failed to export overdrive table!",
2721                                 return ret);
2722                 break;
2723
2724         case PP_OD_COMMIT_DPM_TABLE:
2725                 ret = smum_smc_table_manager(hwmgr,
2726                                              (uint8_t *)od_table,
2727                                              TABLE_OVERDRIVE, false);
2728                 PP_ASSERT_WITH_CODE(!ret,
2729                                 "Failed to import overdrive table!",
2730                                 return ret);
2731
2732                 /* retrieve updated gfxclk table */
2733                 if (data->gfxclk_overdrive) {
2734                         data->gfxclk_overdrive = false;
2735
2736                         ret = vega20_setup_gfxclk_dpm_table(hwmgr);
2737                         if (ret)
2738                                 return ret;
2739                 }
2740
2741                 /* retrieve updated memclk table */
2742                 if (data->memclk_overdrive) {
2743                         data->memclk_overdrive = false;
2744
2745                         ret = vega20_setup_memclk_dpm_table(hwmgr);
2746                         if (ret)
2747                                 return ret;
2748                 }
2749                 break;
2750
2751         default:
2752                 return -EINVAL;
2753         }
2754
2755         return 0;
2756 }
2757
2758 static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
2759                 enum pp_clock_type type, char *buf)
2760 {
2761         struct vega20_hwmgr *data =
2762                         (struct vega20_hwmgr *)(hwmgr->backend);
2763         struct vega20_od8_single_setting *od8_settings =
2764                         data->od8_settings.od8_settings_array;
2765         OverDriveTable_t *od_table =
2766                         &(data->smc_state_table.overdrive_table);
2767         struct phm_ppt_v3_information *pptable_information =
2768                 (struct phm_ppt_v3_information *)hwmgr->pptable;
2769         PPTable_t *pptable = (PPTable_t *)pptable_information->smc_pptable;
2770         struct amdgpu_device *adev = hwmgr->adev;
2771         struct pp_clock_levels_with_latency clocks;
2772         int i, now, size = 0;
2773         int ret = 0;
2774         uint32_t gen_speed, lane_width;
2775
2776         switch (type) {
2777         case PP_SCLK:
2778                 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_GFXCLK, &now);
2779                 PP_ASSERT_WITH_CODE(!ret,
2780                                 "Attempt to get current gfx clk Failed!",
2781                                 return ret);
2782
2783                 ret = vega20_get_sclks(hwmgr, &clocks);
2784                 PP_ASSERT_WITH_CODE(!ret,
2785                                 "Attempt to get gfx clk levels Failed!",
2786                                 return ret);
2787
2788                 for (i = 0; i < clocks.num_levels; i++)
2789                         size += sprintf(buf + size, "%d: %uMhz %s\n",
2790                                 i, clocks.data[i].clocks_in_khz / 1000,
2791                                 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
2792                 break;
2793
2794         case PP_MCLK:
2795                 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_UCLK, &now);
2796                 PP_ASSERT_WITH_CODE(!ret,
2797                                 "Attempt to get current mclk freq Failed!",
2798                                 return ret);
2799
2800                 ret = vega20_get_memclocks(hwmgr, &clocks);
2801                 PP_ASSERT_WITH_CODE(!ret,
2802                                 "Attempt to get memory clk levels Failed!",
2803                                 return ret);
2804
2805                 for (i = 0; i < clocks.num_levels; i++)
2806                         size += sprintf(buf + size, "%d: %uMhz %s\n",
2807                                 i, clocks.data[i].clocks_in_khz / 1000,
2808                                 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
2809                 break;
2810
2811         case PP_PCIE:
2812                 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2813                              PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2814                             >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2815                 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2816                               PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2817                             >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2818                 for (i = 0; i < NUM_LINK_LEVELS; i++)
2819                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
2820                                         (pptable->PcieGenSpeed[i] == 0) ? "2.5GT/s," :
2821                                         (pptable->PcieGenSpeed[i] == 1) ? "5.0GT/s," :
2822                                         (pptable->PcieGenSpeed[i] == 2) ? "8.0GT/s," :
2823                                         (pptable->PcieGenSpeed[i] == 3) ? "16.0GT/s," : "",
2824                                         (pptable->PcieLaneCount[i] == 1) ? "x1" :
2825                                         (pptable->PcieLaneCount[i] == 2) ? "x2" :
2826                                         (pptable->PcieLaneCount[i] == 3) ? "x4" :
2827                                         (pptable->PcieLaneCount[i] == 4) ? "x8" :
2828                                         (pptable->PcieLaneCount[i] == 5) ? "x12" :
2829                                         (pptable->PcieLaneCount[i] == 6) ? "x16" : "",
2830                                         pptable->LclkFreq[i],
2831                                         (gen_speed == pptable->PcieGenSpeed[i]) &&
2832                                         (lane_width == pptable->PcieLaneCount[i]) ?
2833                                         "*" : "");
2834                 break;
2835
2836         case OD_SCLK:
2837                 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2838                     od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
2839                         size = sprintf(buf, "%s:\n", "OD_SCLK");
2840                         size += sprintf(buf + size, "0: %10uMhz\n",
2841                                 od_table->GfxclkFmin);
2842                         size += sprintf(buf + size, "1: %10uMhz\n",
2843                                 od_table->GfxclkFmax);
2844                 }
2845                 break;
2846
2847         case OD_MCLK:
2848                 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2849                         size = sprintf(buf, "%s:\n", "OD_MCLK");
2850                         size += sprintf(buf + size, "1: %10uMhz\n",
2851                                 od_table->UclkFmax);
2852                 }
2853
2854                 break;
2855
2856         case OD_VDDC_CURVE:
2857                 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2858                     od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2859                     od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2860                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2861                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2862                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
2863                         size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");
2864                         size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
2865                                 od_table->GfxclkFreq1,
2866                                 od_table->GfxclkVolt1 / VOLTAGE_SCALE);
2867                         size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
2868                                 od_table->GfxclkFreq2,
2869                                 od_table->GfxclkVolt2 / VOLTAGE_SCALE);
2870                         size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
2871                                 od_table->GfxclkFreq3,
2872                                 od_table->GfxclkVolt3 / VOLTAGE_SCALE);
2873                 }
2874
2875                 break;
2876
2877         case OD_RANGE:
2878                 size = sprintf(buf, "%s:\n", "OD_RANGE");
2879
2880                 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2881                     od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
2882                         size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
2883                                 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
2884                                 od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
2885                 }
2886
2887                 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2888                         ret = vega20_get_memclocks(hwmgr, &clocks);
2889                         PP_ASSERT_WITH_CODE(!ret,
2890                                         "Fail to get memory clk levels!",
2891                                         return ret);
2892
2893                         size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
2894                                 clocks.data[0].clocks_in_khz / 1000,
2895                                 od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
2896                 }
2897
2898                 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2899                     od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2900                     od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2901                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2902                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2903                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
2904                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
2905                                 od8_settings[OD8_SETTING_GFXCLK_FREQ1].min_value,
2906                                 od8_settings[OD8_SETTING_GFXCLK_FREQ1].max_value);
2907                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
2908                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
2909                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
2910                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
2911                                 od8_settings[OD8_SETTING_GFXCLK_FREQ2].min_value,
2912                                 od8_settings[OD8_SETTING_GFXCLK_FREQ2].max_value);
2913                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
2914                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
2915                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
2916                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
2917                                 od8_settings[OD8_SETTING_GFXCLK_FREQ3].min_value,
2918                                 od8_settings[OD8_SETTING_GFXCLK_FREQ3].max_value);
2919                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
2920                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
2921                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
2922                 }
2923
2924                 break;
2925         default:
2926                 break;
2927         }
2928         return size;
2929 }
2930
2931 static int vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
2932                 struct vega20_single_dpm_table *dpm_table)
2933 {
2934         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2935         int ret = 0;
2936
2937         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2938                 PP_ASSERT_WITH_CODE(dpm_table->count > 0,
2939                                 "[SetUclkToHightestDpmLevel] Dpm table has no entry!",
2940                                 return -EINVAL);
2941                 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
2942                                 "[SetUclkToHightestDpmLevel] Dpm table has too many entries!",
2943                                 return -EINVAL);
2944
2945                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2946                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2947                                 PPSMC_MSG_SetHardMinByFreq,
2948                                 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
2949                                 "[SetUclkToHightestDpmLevel] Set hard min uclk failed!",
2950                                 return ret);
2951         }
2952
2953         return ret;
2954 }
2955
2956 static int vega20_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2957 {
2958         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2959         int ret = 0;
2960
2961         smum_send_msg_to_smc_with_parameter(hwmgr,
2962                         PPSMC_MSG_NumOfDisplays, 0);
2963
2964         ret = vega20_set_uclk_to_highest_dpm_level(hwmgr,
2965                         &data->dpm_table.mem_table);
2966
2967         return ret;
2968 }
2969
2970 static int vega20_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2971 {
2972         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2973         int result = 0;
2974         Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
2975
2976         if ((data->water_marks_bitmap & WaterMarksExist) &&
2977             !(data->water_marks_bitmap & WaterMarksLoaded)) {
2978                 result = smum_smc_table_manager(hwmgr,
2979                                                 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
2980                 PP_ASSERT_WITH_CODE(!result,
2981                                 "Failed to update WMTABLE!",
2982                                 return result);
2983                 data->water_marks_bitmap |= WaterMarksLoaded;
2984         }
2985
2986         if ((data->water_marks_bitmap & WaterMarksExist) &&
2987             data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2988             data->smu_features[GNLD_DPM_SOCCLK].supported) {
2989                 result = smum_send_msg_to_smc_with_parameter(hwmgr,
2990                         PPSMC_MSG_NumOfDisplays,
2991                         hwmgr->display_config->num_display);
2992         }
2993
2994         return result;
2995 }
2996
2997 int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
2998 {
2999         struct vega20_hwmgr *data =
3000                         (struct vega20_hwmgr *)(hwmgr->backend);
3001         int ret = 0;
3002
3003         if (data->smu_features[GNLD_DPM_UVD].supported) {
3004                 if (data->smu_features[GNLD_DPM_UVD].enabled == enable) {
3005                         if (enable)
3006                                 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already enabled!\n");
3007                         else
3008                                 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already disabled!\n");
3009                 }
3010
3011                 ret = vega20_enable_smc_features(hwmgr,
3012                                 enable,
3013                                 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap);
3014                 PP_ASSERT_WITH_CODE(!ret,
3015                                 "[EnableDisableUVDDPM] Attempt to Enable/Disable DPM UVD Failed!",
3016                                 return ret);
3017                 data->smu_features[GNLD_DPM_UVD].enabled = enable;
3018         }
3019
3020         return 0;
3021 }
3022
3023 static void vega20_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
3024 {
3025         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3026
3027         if (data->vce_power_gated == bgate)
3028                 return ;
3029
3030         data->vce_power_gated = bgate;
3031         vega20_enable_disable_vce_dpm(hwmgr, !bgate);
3032 }
3033
3034 static void vega20_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
3035 {
3036         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3037
3038         if (data->uvd_power_gated == bgate)
3039                 return ;
3040
3041         data->uvd_power_gated = bgate;
3042         vega20_enable_disable_uvd_dpm(hwmgr, !bgate);
3043 }
3044
3045 static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
3046 {
3047         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3048         struct vega20_single_dpm_table *dpm_table;
3049         bool vblank_too_short = false;
3050         bool disable_mclk_switching;
3051         uint32_t i, latency;
3052
3053         disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
3054                            !hwmgr->display_config->multi_monitor_in_sync) ||
3055                             vblank_too_short;
3056     latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3057
3058         /* gfxclk */
3059         dpm_table = &(data->dpm_table.gfx_table);
3060         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3061         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3062         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3063         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3064
3065         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3066                 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
3067                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3068                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3069                 }
3070
3071                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
3072                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3073                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3074                 }
3075
3076                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3077                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3078                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3079                 }
3080         }
3081
3082         /* memclk */
3083         dpm_table = &(data->dpm_table.mem_table);
3084         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3085         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3086         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3087         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3088
3089         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3090                 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
3091                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3092                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3093                 }
3094
3095                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
3096                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3097                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3098                 }
3099
3100                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3101                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3102                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3103                 }
3104         }
3105
3106         /* honour DAL's UCLK Hardmin */
3107         if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
3108                 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
3109
3110         /* Hardmin is dependent on displayconfig */
3111         if (disable_mclk_switching) {
3112                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3113                 for (i = 0; i < data->mclk_latency_table.count - 1; i++) {
3114                         if (data->mclk_latency_table.entries[i].latency <= latency) {
3115                                 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
3116                                         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
3117                                         break;
3118                                 }
3119                         }
3120                 }
3121         }
3122
3123         if (hwmgr->display_config->nb_pstate_switch_disable)
3124                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3125
3126         /* vclk */
3127         dpm_table = &(data->dpm_table.vclk_table);
3128         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3129         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3130         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3131         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3132
3133         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3134                 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3135                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3136                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3137                 }
3138
3139                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3140                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3141                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3142                 }
3143         }
3144
3145         /* dclk */
3146         dpm_table = &(data->dpm_table.dclk_table);
3147         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3148         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3149         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3150         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3151
3152         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3153                 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3154                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3155                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3156                 }
3157
3158                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3159                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3160                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3161                 }
3162         }
3163
3164         /* socclk */
3165         dpm_table = &(data->dpm_table.soc_table);
3166         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3167         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3168         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3169         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3170
3171         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3172                 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
3173                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3174                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3175                 }
3176
3177                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3178                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3179                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3180                 }
3181         }
3182
3183         /* eclk */
3184         dpm_table = &(data->dpm_table.eclk_table);
3185         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3186         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3187         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3188         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3189
3190         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3191                 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
3192                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3193                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3194                 }
3195
3196                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3197                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3198                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3199                 }
3200         }
3201
3202         return 0;
3203 }
3204
3205 static bool
3206 vega20_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
3207 {
3208         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3209         bool is_update_required = false;
3210
3211         if (data->display_timing.num_existing_displays !=
3212                         hwmgr->display_config->num_display)
3213                 is_update_required = true;
3214
3215         if (data->registry_data.gfx_clk_deep_sleep_support &&
3216            (data->display_timing.min_clock_in_sr !=
3217             hwmgr->display_config->min_core_set_clock_in_sr))
3218                 is_update_required = true;
3219
3220         return is_update_required;
3221 }
3222
3223 static int vega20_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
3224 {
3225         int ret = 0;
3226
3227         ret = vega20_disable_all_smu_features(hwmgr);
3228         PP_ASSERT_WITH_CODE(!ret,
3229                         "[DisableDpmTasks] Failed to disable all smu features!",
3230                         return ret);
3231
3232         return 0;
3233 }
3234
3235 static int vega20_power_off_asic(struct pp_hwmgr *hwmgr)
3236 {
3237         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3238         int result;
3239
3240         result = vega20_disable_dpm_tasks(hwmgr);
3241         PP_ASSERT_WITH_CODE((0 == result),
3242                         "[PowerOffAsic] Failed to disable DPM!",
3243                         );
3244         data->water_marks_bitmap &= ~(WaterMarksLoaded);
3245
3246         return result;
3247 }
3248
3249 static int conv_power_profile_to_pplib_workload(int power_profile)
3250 {
3251         int pplib_workload = 0;
3252
3253         switch (power_profile) {
3254         case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
3255                 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
3256                 break;
3257         case PP_SMC_POWER_PROFILE_POWERSAVING:
3258                 pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
3259                 break;
3260         case PP_SMC_POWER_PROFILE_VIDEO:
3261                 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
3262                 break;
3263         case PP_SMC_POWER_PROFILE_VR:
3264                 pplib_workload = WORKLOAD_PPLIB_VR_BIT;
3265                 break;
3266         case PP_SMC_POWER_PROFILE_COMPUTE:
3267                 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
3268                 break;
3269         case PP_SMC_POWER_PROFILE_CUSTOM:
3270                 pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
3271                 break;
3272         }
3273
3274         return pplib_workload;
3275 }
3276
3277 static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
3278 {
3279         DpmActivityMonitorCoeffInt_t activity_monitor;
3280         uint32_t i, size = 0;
3281         uint16_t workload_type = 0;
3282         static const char *profile_name[] = {
3283                                         "3D_FULL_SCREEN",
3284                                         "POWER_SAVING",
3285                                         "VIDEO",
3286                                         "VR",
3287                                         "COMPUTE",
3288                                         "CUSTOM"};
3289         static const char *title[] = {
3290                         "PROFILE_INDEX(NAME)",
3291                         "CLOCK_TYPE(NAME)",
3292                         "FPS",
3293                         "UseRlcBusy",
3294                         "MinActiveFreqType",
3295                         "MinActiveFreq",
3296                         "BoosterFreqType",
3297                         "BoosterFreq",
3298                         "PD_Data_limit_c",
3299                         "PD_Data_error_coeff",
3300                         "PD_Data_error_rate_coeff"};
3301         int result = 0;
3302
3303         if (!buf)
3304                 return -EINVAL;
3305
3306         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
3307                         title[0], title[1], title[2], title[3], title[4], title[5],
3308                         title[6], title[7], title[8], title[9], title[10]);
3309
3310         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
3311                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
3312                 workload_type = conv_power_profile_to_pplib_workload(i);
3313                 result = vega20_get_activity_monitor_coeff(hwmgr,
3314                                 (uint8_t *)(&activity_monitor), workload_type);
3315                 PP_ASSERT_WITH_CODE(!result,
3316                                 "[GetPowerProfile] Failed to get activity monitor!",
3317                                 return result);
3318
3319                 size += sprintf(buf + size, "%2d %14s%s:\n",
3320                         i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ");
3321
3322                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3323                         " ",
3324                         0,
3325                         "GFXCLK",
3326                         activity_monitor.Gfx_FPS,
3327                         activity_monitor.Gfx_UseRlcBusy,
3328                         activity_monitor.Gfx_MinActiveFreqType,
3329                         activity_monitor.Gfx_MinActiveFreq,
3330                         activity_monitor.Gfx_BoosterFreqType,
3331                         activity_monitor.Gfx_BoosterFreq,
3332                         activity_monitor.Gfx_PD_Data_limit_c,
3333                         activity_monitor.Gfx_PD_Data_error_coeff,
3334                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
3335
3336                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3337                         " ",
3338                         1,
3339                         "SOCCLK",
3340                         activity_monitor.Soc_FPS,
3341                         activity_monitor.Soc_UseRlcBusy,
3342                         activity_monitor.Soc_MinActiveFreqType,
3343                         activity_monitor.Soc_MinActiveFreq,
3344                         activity_monitor.Soc_BoosterFreqType,
3345                         activity_monitor.Soc_BoosterFreq,
3346                         activity_monitor.Soc_PD_Data_limit_c,
3347                         activity_monitor.Soc_PD_Data_error_coeff,
3348                         activity_monitor.Soc_PD_Data_error_rate_coeff);
3349
3350                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3351                         " ",
3352                         2,
3353                         "UCLK",
3354                         activity_monitor.Mem_FPS,
3355                         activity_monitor.Mem_UseRlcBusy,
3356                         activity_monitor.Mem_MinActiveFreqType,
3357                         activity_monitor.Mem_MinActiveFreq,
3358                         activity_monitor.Mem_BoosterFreqType,
3359                         activity_monitor.Mem_BoosterFreq,
3360                         activity_monitor.Mem_PD_Data_limit_c,
3361                         activity_monitor.Mem_PD_Data_error_coeff,
3362                         activity_monitor.Mem_PD_Data_error_rate_coeff);
3363
3364                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3365                         " ",
3366                         3,
3367                         "FCLK",
3368                         activity_monitor.Fclk_FPS,
3369                         activity_monitor.Fclk_UseRlcBusy,
3370                         activity_monitor.Fclk_MinActiveFreqType,
3371                         activity_monitor.Fclk_MinActiveFreq,
3372                         activity_monitor.Fclk_BoosterFreqType,
3373                         activity_monitor.Fclk_BoosterFreq,
3374                         activity_monitor.Fclk_PD_Data_limit_c,
3375                         activity_monitor.Fclk_PD_Data_error_coeff,
3376                         activity_monitor.Fclk_PD_Data_error_rate_coeff);
3377         }
3378
3379         return size;
3380 }
3381
3382 static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
3383 {
3384         DpmActivityMonitorCoeffInt_t activity_monitor;
3385         int workload_type, result = 0;
3386
3387         hwmgr->power_profile_mode = input[size];
3388
3389         if (hwmgr->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
3390                 pr_err("Invalid power profile mode %d\n", hwmgr->power_profile_mode);
3391                 return -EINVAL;
3392         }
3393
3394         if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
3395                 if (size < 10)
3396                         return -EINVAL;
3397
3398                 result = vega20_get_activity_monitor_coeff(hwmgr,
3399                                 (uint8_t *)(&activity_monitor),
3400                                 WORKLOAD_PPLIB_CUSTOM_BIT);
3401                 PP_ASSERT_WITH_CODE(!result,
3402                                 "[SetPowerProfile] Failed to get activity monitor!",
3403                                 return result);
3404
3405                 switch (input[0]) {
3406                 case 0: /* Gfxclk */
3407                         activity_monitor.Gfx_FPS = input[1];
3408                         activity_monitor.Gfx_UseRlcBusy = input[2];
3409                         activity_monitor.Gfx_MinActiveFreqType = input[3];
3410                         activity_monitor.Gfx_MinActiveFreq = input[4];
3411                         activity_monitor.Gfx_BoosterFreqType = input[5];
3412                         activity_monitor.Gfx_BoosterFreq = input[6];
3413                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
3414                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
3415                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
3416                         break;
3417                 case 1: /* Socclk */
3418                         activity_monitor.Soc_FPS = input[1];
3419                         activity_monitor.Soc_UseRlcBusy = input[2];
3420                         activity_monitor.Soc_MinActiveFreqType = input[3];
3421                         activity_monitor.Soc_MinActiveFreq = input[4];
3422                         activity_monitor.Soc_BoosterFreqType = input[5];
3423                         activity_monitor.Soc_BoosterFreq = input[6];
3424                         activity_monitor.Soc_PD_Data_limit_c = input[7];
3425                         activity_monitor.Soc_PD_Data_error_coeff = input[8];
3426                         activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
3427                         break;
3428                 case 2: /* Uclk */
3429                         activity_monitor.Mem_FPS = input[1];
3430                         activity_monitor.Mem_UseRlcBusy = input[2];
3431                         activity_monitor.Mem_MinActiveFreqType = input[3];
3432                         activity_monitor.Mem_MinActiveFreq = input[4];
3433                         activity_monitor.Mem_BoosterFreqType = input[5];
3434                         activity_monitor.Mem_BoosterFreq = input[6];
3435                         activity_monitor.Mem_PD_Data_limit_c = input[7];
3436                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
3437                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
3438                         break;
3439                 case 3: /* Fclk */
3440                         activity_monitor.Fclk_FPS = input[1];
3441                         activity_monitor.Fclk_UseRlcBusy = input[2];
3442                         activity_monitor.Fclk_MinActiveFreqType = input[3];
3443                         activity_monitor.Fclk_MinActiveFreq = input[4];
3444                         activity_monitor.Fclk_BoosterFreqType = input[5];
3445                         activity_monitor.Fclk_BoosterFreq = input[6];
3446                         activity_monitor.Fclk_PD_Data_limit_c = input[7];
3447                         activity_monitor.Fclk_PD_Data_error_coeff = input[8];
3448                         activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
3449                         break;
3450                 }
3451
3452                 result = vega20_set_activity_monitor_coeff(hwmgr,
3453                                 (uint8_t *)(&activity_monitor),
3454                                 WORKLOAD_PPLIB_CUSTOM_BIT);
3455                 PP_ASSERT_WITH_CODE(!result,
3456                                 "[SetPowerProfile] Failed to set activity monitor!",
3457                                 return result);
3458         }
3459
3460         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
3461         workload_type =
3462                 conv_power_profile_to_pplib_workload(hwmgr->power_profile_mode);
3463         smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
3464                                                 1 << workload_type);
3465
3466         return 0;
3467 }
3468
3469 static int vega20_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
3470                                         uint32_t virtual_addr_low,
3471                                         uint32_t virtual_addr_hi,
3472                                         uint32_t mc_addr_low,
3473                                         uint32_t mc_addr_hi,
3474                                         uint32_t size)
3475 {
3476         smum_send_msg_to_smc_with_parameter(hwmgr,
3477                                         PPSMC_MSG_SetSystemVirtualDramAddrHigh,
3478                                         virtual_addr_hi);
3479         smum_send_msg_to_smc_with_parameter(hwmgr,
3480                                         PPSMC_MSG_SetSystemVirtualDramAddrLow,
3481                                         virtual_addr_low);
3482         smum_send_msg_to_smc_with_parameter(hwmgr,
3483                                         PPSMC_MSG_DramLogSetDramAddrHigh,
3484                                         mc_addr_hi);
3485
3486         smum_send_msg_to_smc_with_parameter(hwmgr,
3487                                         PPSMC_MSG_DramLogSetDramAddrLow,
3488                                         mc_addr_low);
3489
3490         smum_send_msg_to_smc_with_parameter(hwmgr,
3491                                         PPSMC_MSG_DramLogSetDramSize,
3492                                         size);
3493         return 0;
3494 }
3495
3496 static int vega20_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
3497                 struct PP_TemperatureRange *thermal_data)
3498 {
3499         struct phm_ppt_v3_information *pptable_information =
3500                 (struct phm_ppt_v3_information *)hwmgr->pptable;
3501
3502         memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
3503
3504         thermal_data->max = pptable_information->us_software_shutdown_temp *
3505                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
3506
3507         return 0;
3508 }
3509
3510 static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
3511         /* init/fini related */
3512         .backend_init = vega20_hwmgr_backend_init,
3513         .backend_fini = vega20_hwmgr_backend_fini,
3514         .asic_setup = vega20_setup_asic_task,
3515         .power_off_asic = vega20_power_off_asic,
3516         .dynamic_state_management_enable = vega20_enable_dpm_tasks,
3517         .dynamic_state_management_disable = vega20_disable_dpm_tasks,
3518         /* power state related */
3519         .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules,
3520         .pre_display_config_changed = vega20_pre_display_configuration_changed_task,
3521         .display_config_changed = vega20_display_configuration_changed_task,
3522         .check_smc_update_required_for_display_configuration =
3523                 vega20_check_smc_update_required_for_display_configuration,
3524         .notify_smc_display_config_after_ps_adjustment =
3525                 vega20_notify_smc_display_config_after_ps_adjustment,
3526         /* export to DAL */
3527         .get_sclk = vega20_dpm_get_sclk,
3528         .get_mclk = vega20_dpm_get_mclk,
3529         .get_dal_power_level = vega20_get_dal_power_level,
3530         .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
3531         .get_clock_by_type_with_voltage = vega20_get_clock_by_type_with_voltage,
3532         .set_watermarks_for_clocks_ranges = vega20_set_watermarks_for_clocks_ranges,
3533         .display_clock_voltage_request = vega20_display_clock_voltage_request,
3534         .get_performance_level = vega20_get_performance_level,
3535         /* UMD pstate, profile related */
3536         .force_dpm_level = vega20_dpm_force_dpm_level,
3537         .get_power_profile_mode = vega20_get_power_profile_mode,
3538         .set_power_profile_mode = vega20_set_power_profile_mode,
3539         /* od related */
3540         .set_power_limit = vega20_set_power_limit,
3541         .get_sclk_od = vega20_get_sclk_od,
3542         .set_sclk_od = vega20_set_sclk_od,
3543         .get_mclk_od = vega20_get_mclk_od,
3544         .set_mclk_od = vega20_set_mclk_od,
3545         .odn_edit_dpm_table = vega20_odn_edit_dpm_table,
3546         /* for sysfs to retrive/set gfxclk/memclk */
3547         .force_clock_level = vega20_force_clock_level,
3548         .print_clock_levels = vega20_print_clock_levels,
3549         .read_sensor = vega20_read_sensor,
3550         /* powergate related */
3551         .powergate_uvd = vega20_power_gate_uvd,
3552         .powergate_vce = vega20_power_gate_vce,
3553         /* thermal related */
3554         .start_thermal_controller = vega20_start_thermal_controller,
3555         .stop_thermal_controller = vega20_thermal_stop_thermal_controller,
3556         .get_thermal_temperature_range = vega20_get_thermal_temperature_range,
3557         .register_irq_handlers = smu9_register_irq_handlers,
3558         .disable_smc_firmware_ctf = vega20_thermal_disable_alert,
3559         /* fan control related */
3560         .get_fan_speed_percent = vega20_fan_ctrl_get_fan_speed_percent,
3561         .set_fan_speed_percent = vega20_fan_ctrl_set_fan_speed_percent,
3562         .get_fan_speed_info = vega20_fan_ctrl_get_fan_speed_info,
3563         .get_fan_speed_rpm = vega20_fan_ctrl_get_fan_speed_rpm,
3564         .set_fan_speed_rpm = vega20_fan_ctrl_set_fan_speed_rpm,
3565         .get_fan_control_mode = vega20_get_fan_control_mode,
3566         .set_fan_control_mode = vega20_set_fan_control_mode,
3567         /* smu memory related */
3568         .notify_cac_buffer_info = vega20_notify_cac_buffer_info,
3569         .enable_mgpu_fan_boost = vega20_enable_mgpu_fan_boost,
3570 };
3571
3572 int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
3573 {
3574         hwmgr->hwmgr_func = &vega20_hwmgr_funcs;
3575         hwmgr->pptable_func = &vega20_pptable_funcs;
3576
3577         return 0;
3578 }