2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
30 #include "amd_powerplay.h"
31 #include "vega20_smumgr.h"
32 #include "hardwaremanager.h"
33 #include "ppatomfwctrl.h"
34 #include "atomfirmware.h"
35 #include "cgs_common.h"
36 #include "vega20_powertune.h"
37 #include "vega20_inc.h"
38 #include "pppcielanes.h"
39 #include "vega20_hwmgr.h"
40 #include "vega20_processpptables.h"
41 #include "vega20_pptable.h"
42 #include "vega20_thermal.h"
43 #include "vega20_ppsmc.h"
45 #include "amd_pcie_helpers.h"
46 #include "ppinterrupt.h"
47 #include "pp_overdriver.h"
48 #include "pp_thermal.h"
49 #include "soc15_common.h"
50 #include "smuio/smuio_9_0_offset.h"
51 #include "smuio/smuio_9_0_sh_mask.h"
53 static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
55 struct vega20_hwmgr *data =
56 (struct vega20_hwmgr *)(hwmgr->backend);
58 data->gfxclk_average_alpha = PPVEGA20_VEGA20GFXCLKAVERAGEALPHA_DFLT;
59 data->socclk_average_alpha = PPVEGA20_VEGA20SOCCLKAVERAGEALPHA_DFLT;
60 data->uclk_average_alpha = PPVEGA20_VEGA20UCLKCLKAVERAGEALPHA_DFLT;
61 data->gfx_activity_average_alpha = PPVEGA20_VEGA20GFXACTIVITYAVERAGEALPHA_DFLT;
62 data->lowest_uclk_reserved_for_ulv = PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT;
64 data->display_voltage_mode = PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT;
65 data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
66 data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
67 data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
68 data->disp_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
69 data->disp_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
70 data->disp_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
71 data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
72 data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
73 data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
74 data->phy_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
75 data->phy_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
76 data->phy_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
78 data->registry_data.disallowed_features = 0x0;
79 data->registry_data.od_state_in_dc_support = 0;
80 data->registry_data.thermal_support = 1;
81 data->registry_data.skip_baco_hardware = 0;
83 data->registry_data.log_avfs_param = 0;
84 data->registry_data.sclk_throttle_low_notification = 1;
85 data->registry_data.force_dpm_high = 0;
86 data->registry_data.stable_pstate_sclk_dpm_percentage = 75;
88 data->registry_data.didt_support = 0;
89 if (data->registry_data.didt_support) {
90 data->registry_data.didt_mode = 6;
91 data->registry_data.sq_ramping_support = 1;
92 data->registry_data.db_ramping_support = 0;
93 data->registry_data.td_ramping_support = 0;
94 data->registry_data.tcp_ramping_support = 0;
95 data->registry_data.dbr_ramping_support = 0;
96 data->registry_data.edc_didt_support = 1;
97 data->registry_data.gc_didt_support = 0;
98 data->registry_data.psm_didt_support = 0;
101 data->registry_data.pcie_lane_override = 0xff;
102 data->registry_data.pcie_speed_override = 0xff;
103 data->registry_data.pcie_clock_override = 0xffffffff;
104 data->registry_data.regulator_hot_gpio_support = 1;
105 data->registry_data.ac_dc_switch_gpio_support = 0;
106 data->registry_data.quick_transition_support = 0;
107 data->registry_data.zrpm_start_temp = 0xffff;
108 data->registry_data.zrpm_stop_temp = 0xffff;
109 data->registry_data.od8_feature_enable = 1;
110 data->registry_data.disable_water_mark = 0;
111 data->registry_data.disable_pp_tuning = 0;
112 data->registry_data.disable_xlpp_tuning = 0;
113 data->registry_data.disable_workload_policy = 0;
114 data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F;
115 data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919;
116 data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A;
117 data->registry_data.force_workload_policy_mask = 0;
118 data->registry_data.disable_3d_fs_detection = 0;
119 data->registry_data.fps_support = 1;
120 data->registry_data.disable_auto_wattman = 1;
121 data->registry_data.auto_wattman_debug = 0;
122 data->registry_data.auto_wattman_sample_period = 100;
123 data->registry_data.auto_wattman_threshold = 50;
124 data->registry_data.gfxoff_controlled_by_driver = 1;
125 data->gfxoff_allowed = false;
126 data->counter_gfxoff = 0;
129 static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr)
131 struct vega20_hwmgr *data =
132 (struct vega20_hwmgr *)(hwmgr->backend);
133 struct amdgpu_device *adev = hwmgr->adev;
135 if (data->vddci_control == VEGA20_VOLTAGE_CONTROL_NONE)
136 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
137 PHM_PlatformCaps_ControlVDDCI);
139 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
140 PHM_PlatformCaps_TablelessHardwareInterface);
142 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
143 PHM_PlatformCaps_EnableSMU7ThermalManagement);
145 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
146 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
147 PHM_PlatformCaps_UVDPowerGating);
149 if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
150 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
151 PHM_PlatformCaps_VCEPowerGating);
153 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
154 PHM_PlatformCaps_UnTabledHardwareInterface);
156 if (data->registry_data.od8_feature_enable)
157 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
158 PHM_PlatformCaps_OD8inACSupport);
160 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
161 PHM_PlatformCaps_ActivityReporting);
162 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
163 PHM_PlatformCaps_FanSpeedInTableIsRPM);
165 if (data->registry_data.od_state_in_dc_support) {
166 if (data->registry_data.od8_feature_enable)
167 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
168 PHM_PlatformCaps_OD8inDCSupport);
171 if (data->registry_data.thermal_support &&
172 data->registry_data.fuzzy_fan_control_support &&
173 hwmgr->thermal_controller.advanceFanControlParameters.usTMax)
174 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
175 PHM_PlatformCaps_ODFuzzyFanControlSupport);
177 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
178 PHM_PlatformCaps_DynamicPowerManagement);
179 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
180 PHM_PlatformCaps_SMC);
181 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
182 PHM_PlatformCaps_ThermalPolicyDelay);
184 if (data->registry_data.force_dpm_high)
185 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
186 PHM_PlatformCaps_ExclusiveModeAlwaysHigh);
188 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
189 PHM_PlatformCaps_DynamicUVDState);
191 if (data->registry_data.sclk_throttle_low_notification)
192 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
193 PHM_PlatformCaps_SclkThrottleLowNotification);
195 /* power tune caps */
196 /* assume disabled */
197 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
198 PHM_PlatformCaps_PowerContainment);
199 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
200 PHM_PlatformCaps_DiDtSupport);
201 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
202 PHM_PlatformCaps_SQRamping);
203 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
204 PHM_PlatformCaps_DBRamping);
205 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
206 PHM_PlatformCaps_TDRamping);
207 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
208 PHM_PlatformCaps_TCPRamping);
209 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
210 PHM_PlatformCaps_DBRRamping);
211 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
212 PHM_PlatformCaps_DiDtEDCEnable);
213 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
214 PHM_PlatformCaps_GCEDC);
215 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
216 PHM_PlatformCaps_PSM);
218 if (data->registry_data.didt_support) {
219 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
220 PHM_PlatformCaps_DiDtSupport);
221 if (data->registry_data.sq_ramping_support)
222 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
223 PHM_PlatformCaps_SQRamping);
224 if (data->registry_data.db_ramping_support)
225 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
226 PHM_PlatformCaps_DBRamping);
227 if (data->registry_data.td_ramping_support)
228 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
229 PHM_PlatformCaps_TDRamping);
230 if (data->registry_data.tcp_ramping_support)
231 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
232 PHM_PlatformCaps_TCPRamping);
233 if (data->registry_data.dbr_ramping_support)
234 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
235 PHM_PlatformCaps_DBRRamping);
236 if (data->registry_data.edc_didt_support)
237 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
238 PHM_PlatformCaps_DiDtEDCEnable);
239 if (data->registry_data.gc_didt_support)
240 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
241 PHM_PlatformCaps_GCEDC);
242 if (data->registry_data.psm_didt_support)
243 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
244 PHM_PlatformCaps_PSM);
247 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
248 PHM_PlatformCaps_RegulatorHot);
250 if (data->registry_data.ac_dc_switch_gpio_support) {
251 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
252 PHM_PlatformCaps_AutomaticDCTransition);
253 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
254 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
257 if (data->registry_data.quick_transition_support) {
258 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
259 PHM_PlatformCaps_AutomaticDCTransition);
260 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
261 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
262 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
263 PHM_PlatformCaps_Falcon_QuickTransition);
266 if (data->lowest_uclk_reserved_for_ulv != PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT) {
267 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
268 PHM_PlatformCaps_LowestUclkReservedForUlv);
269 if (data->lowest_uclk_reserved_for_ulv == 1)
270 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
271 PHM_PlatformCaps_LowestUclkReservedForUlv);
274 if (data->registry_data.custom_fan_support)
275 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
276 PHM_PlatformCaps_CustomFanControlSupport);
281 static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr)
283 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
286 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
287 FEATURE_DPM_PREFETCHER_BIT;
288 data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
289 FEATURE_DPM_GFXCLK_BIT;
290 data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
291 FEATURE_DPM_UCLK_BIT;
292 data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
293 FEATURE_DPM_SOCCLK_BIT;
294 data->smu_features[GNLD_DPM_UVD].smu_feature_id =
296 data->smu_features[GNLD_DPM_VCE].smu_feature_id =
298 data->smu_features[GNLD_ULV].smu_feature_id =
300 data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
301 FEATURE_DPM_MP0CLK_BIT;
302 data->smu_features[GNLD_DPM_LINK].smu_feature_id =
303 FEATURE_DPM_LINK_BIT;
304 data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
305 FEATURE_DPM_DCEFCLK_BIT;
306 data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
307 FEATURE_DS_GFXCLK_BIT;
308 data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
309 FEATURE_DS_SOCCLK_BIT;
310 data->smu_features[GNLD_DS_LCLK].smu_feature_id =
312 data->smu_features[GNLD_PPT].smu_feature_id =
314 data->smu_features[GNLD_TDC].smu_feature_id =
316 data->smu_features[GNLD_THERMAL].smu_feature_id =
318 data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
319 FEATURE_GFX_PER_CU_CG_BIT;
320 data->smu_features[GNLD_RM].smu_feature_id =
322 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
323 FEATURE_DS_DCEFCLK_BIT;
324 data->smu_features[GNLD_ACDC].smu_feature_id =
326 data->smu_features[GNLD_VR0HOT].smu_feature_id =
328 data->smu_features[GNLD_VR1HOT].smu_feature_id =
330 data->smu_features[GNLD_FW_CTF].smu_feature_id =
332 data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
333 FEATURE_LED_DISPLAY_BIT;
334 data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
335 FEATURE_FAN_CONTROL_BIT;
336 data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
337 data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT;
338 data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT;
339 data->smu_features[GNLD_DPM_FCLK].smu_feature_id = FEATURE_DPM_FCLK_BIT;
340 data->smu_features[GNLD_DS_FCLK].smu_feature_id = FEATURE_DS_FCLK_BIT;
341 data->smu_features[GNLD_DS_MP1CLK].smu_feature_id = FEATURE_DS_MP1CLK_BIT;
342 data->smu_features[GNLD_DS_MP0CLK].smu_feature_id = FEATURE_DS_MP0CLK_BIT;
343 data->smu_features[GNLD_XGMI].smu_feature_id = FEATURE_XGMI_BIT;
345 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
346 data->smu_features[i].smu_feature_bitmap =
347 (uint64_t)(1ULL << data->smu_features[i].smu_feature_id);
348 data->smu_features[i].allowed =
349 ((data->registry_data.disallowed_features >> i) & 1) ?
354 static int vega20_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
359 static int vega20_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
361 kfree(hwmgr->backend);
362 hwmgr->backend = NULL;
367 static int vega20_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
369 struct vega20_hwmgr *data;
370 struct amdgpu_device *adev = hwmgr->adev;
372 data = kzalloc(sizeof(struct vega20_hwmgr), GFP_KERNEL);
376 hwmgr->backend = data;
378 hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO];
379 hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
380 hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
382 vega20_set_default_registry_data(hwmgr);
384 data->disable_dpm_mask = 0xff;
386 /* need to set voltage control types before EVV patching */
387 data->vddc_control = VEGA20_VOLTAGE_CONTROL_NONE;
388 data->mvdd_control = VEGA20_VOLTAGE_CONTROL_NONE;
389 data->vddci_control = VEGA20_VOLTAGE_CONTROL_NONE;
391 data->water_marks_bitmap = 0;
392 data->avfs_exist = false;
394 vega20_set_features_platform_caps(hwmgr);
396 vega20_init_dpm_defaults(hwmgr);
398 /* Parse pptable data read from VBIOS */
399 vega20_set_private_data_based_on_pptable(hwmgr);
401 data->is_tlu_enabled = false;
403 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
404 VEGA20_MAX_HARDWARE_POWERLEVELS;
405 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
406 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
408 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
409 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
410 hwmgr->platform_descriptor.clockStep.engineClock = 500;
411 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
413 data->total_active_cus = adev->gfx.cu_info.number;
418 static int vega20_init_sclk_threshold(struct pp_hwmgr *hwmgr)
420 struct vega20_hwmgr *data =
421 (struct vega20_hwmgr *)(hwmgr->backend);
423 data->low_sclk_interrupt_threshold = 0;
428 static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr)
432 ret = vega20_init_sclk_threshold(hwmgr);
433 PP_ASSERT_WITH_CODE(!ret,
434 "Failed to init sclk threshold!",
441 * @fn vega20_init_dpm_state
442 * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
444 * @param dpm_state - the address of the DPM Table to initiailize.
447 static void vega20_init_dpm_state(struct vega20_dpm_state *dpm_state)
449 dpm_state->soft_min_level = 0x0;
450 dpm_state->soft_max_level = 0xffff;
451 dpm_state->hard_min_level = 0x0;
452 dpm_state->hard_max_level = 0xffff;
455 static int vega20_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
456 PPCLK_e clk_id, uint32_t *num_of_levels)
460 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
461 PPSMC_MSG_GetDpmFreqByIndex,
462 (clk_id << 16 | 0xFF));
463 PP_ASSERT_WITH_CODE(!ret,
464 "[GetNumOfDpmLevel] failed to get dpm levels!",
467 *num_of_levels = smum_get_argument(hwmgr);
468 PP_ASSERT_WITH_CODE(*num_of_levels > 0,
469 "[GetNumOfDpmLevel] number of clk levels is invalid!",
475 static int vega20_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
476 PPCLK_e clk_id, uint32_t index, uint32_t *clk)
480 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
481 PPSMC_MSG_GetDpmFreqByIndex,
482 (clk_id << 16 | index));
483 PP_ASSERT_WITH_CODE(!ret,
484 "[GetDpmFreqByIndex] failed to get dpm freq by index!",
487 *clk = smum_get_argument(hwmgr);
488 PP_ASSERT_WITH_CODE(*clk,
489 "[GetDpmFreqByIndex] clk value is invalid!",
495 static int vega20_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
496 struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id)
499 uint32_t i, num_of_levels, clk;
501 ret = vega20_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
502 PP_ASSERT_WITH_CODE(!ret,
503 "[SetupSingleDpmTable] failed to get clk levels!",
506 dpm_table->count = num_of_levels;
508 for (i = 0; i < num_of_levels; i++) {
509 ret = vega20_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);
510 PP_ASSERT_WITH_CODE(!ret,
511 "[SetupSingleDpmTable] failed to get clk of specific level!",
513 dpm_table->dpm_levels[i].value = clk;
514 dpm_table->dpm_levels[i].enabled = true;
520 static int vega20_setup_gfxclk_dpm_table(struct pp_hwmgr *hwmgr)
522 struct vega20_hwmgr *data =
523 (struct vega20_hwmgr *)(hwmgr->backend);
524 struct vega20_single_dpm_table *dpm_table;
527 dpm_table = &(data->dpm_table.gfx_table);
528 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
529 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
530 PP_ASSERT_WITH_CODE(!ret,
531 "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!",
534 dpm_table->count = 1;
535 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100;
541 static int vega20_setup_memclk_dpm_table(struct pp_hwmgr *hwmgr)
543 struct vega20_hwmgr *data =
544 (struct vega20_hwmgr *)(hwmgr->backend);
545 struct vega20_single_dpm_table *dpm_table;
548 dpm_table = &(data->dpm_table.mem_table);
549 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
550 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
551 PP_ASSERT_WITH_CODE(!ret,
552 "[SetupDefaultDpmTable] failed to get memclk dpm levels!",
555 dpm_table->count = 1;
556 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100;
563 * This function is to initialize all DPM state tables
564 * for SMU based on the dependency table.
565 * Dynamic state patching function will then trim these
566 * state tables to the allowed range based
567 * on the power policy or external client requests,
568 * such as UVD request, etc.
570 static int vega20_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
572 struct vega20_hwmgr *data =
573 (struct vega20_hwmgr *)(hwmgr->backend);
574 struct vega20_single_dpm_table *dpm_table;
577 memset(&data->dpm_table, 0, sizeof(data->dpm_table));
580 dpm_table = &(data->dpm_table.soc_table);
581 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
582 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK);
583 PP_ASSERT_WITH_CODE(!ret,
584 "[SetupDefaultDpmTable] failed to get socclk dpm levels!",
587 dpm_table->count = 1;
588 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100;
590 vega20_init_dpm_state(&(dpm_table->dpm_state));
593 dpm_table = &(data->dpm_table.gfx_table);
594 ret = vega20_setup_gfxclk_dpm_table(hwmgr);
597 vega20_init_dpm_state(&(dpm_table->dpm_state));
600 dpm_table = &(data->dpm_table.mem_table);
601 ret = vega20_setup_memclk_dpm_table(hwmgr);
604 vega20_init_dpm_state(&(dpm_table->dpm_state));
607 dpm_table = &(data->dpm_table.eclk_table);
608 if (data->smu_features[GNLD_DPM_VCE].enabled) {
609 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK);
610 PP_ASSERT_WITH_CODE(!ret,
611 "[SetupDefaultDpmTable] failed to get eclk dpm levels!",
614 dpm_table->count = 1;
615 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100;
617 vega20_init_dpm_state(&(dpm_table->dpm_state));
620 dpm_table = &(data->dpm_table.vclk_table);
621 if (data->smu_features[GNLD_DPM_UVD].enabled) {
622 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
623 PP_ASSERT_WITH_CODE(!ret,
624 "[SetupDefaultDpmTable] failed to get vclk dpm levels!",
627 dpm_table->count = 1;
628 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100;
630 vega20_init_dpm_state(&(dpm_table->dpm_state));
633 dpm_table = &(data->dpm_table.dclk_table);
634 if (data->smu_features[GNLD_DPM_UVD].enabled) {
635 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK);
636 PP_ASSERT_WITH_CODE(!ret,
637 "[SetupDefaultDpmTable] failed to get dclk dpm levels!",
640 dpm_table->count = 1;
641 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100;
643 vega20_init_dpm_state(&(dpm_table->dpm_state));
646 dpm_table = &(data->dpm_table.dcef_table);
647 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
648 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK);
649 PP_ASSERT_WITH_CODE(!ret,
650 "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!",
653 dpm_table->count = 1;
654 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100;
656 vega20_init_dpm_state(&(dpm_table->dpm_state));
659 dpm_table = &(data->dpm_table.pixel_table);
660 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
661 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK);
662 PP_ASSERT_WITH_CODE(!ret,
663 "[SetupDefaultDpmTable] failed to get pixclk dpm levels!",
666 dpm_table->count = 0;
667 vega20_init_dpm_state(&(dpm_table->dpm_state));
670 dpm_table = &(data->dpm_table.display_table);
671 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
672 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
673 PP_ASSERT_WITH_CODE(!ret,
674 "[SetupDefaultDpmTable] failed to get dispclk dpm levels!",
677 dpm_table->count = 0;
678 vega20_init_dpm_state(&(dpm_table->dpm_state));
681 dpm_table = &(data->dpm_table.phy_table);
682 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
683 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
684 PP_ASSERT_WITH_CODE(!ret,
685 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!",
688 dpm_table->count = 0;
689 vega20_init_dpm_state(&(dpm_table->dpm_state));
692 dpm_table = &(data->dpm_table.fclk_table);
693 if (data->smu_features[GNLD_DPM_FCLK].enabled) {
694 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_FCLK);
695 PP_ASSERT_WITH_CODE(!ret,
696 "[SetupDefaultDpmTable] failed to get fclk dpm levels!",
699 dpm_table->count = 0;
700 vega20_init_dpm_state(&(dpm_table->dpm_state));
702 /* save a copy of the default DPM table */
703 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
704 sizeof(struct vega20_dpm_table));
710 * Initializes the SMC table and uploads it
712 * @param hwmgr the address of the powerplay hardware manager.
713 * @param pInput the pointer to input data (PowerState)
716 static int vega20_init_smc_table(struct pp_hwmgr *hwmgr)
719 struct vega20_hwmgr *data =
720 (struct vega20_hwmgr *)(hwmgr->backend);
721 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
722 struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
723 struct phm_ppt_v3_information *pptable_information =
724 (struct phm_ppt_v3_information *)hwmgr->pptable;
726 result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
727 PP_ASSERT_WITH_CODE(!result,
728 "[InitSMCTable] Failed to get vbios bootup values!",
731 data->vbios_boot_state.vddc = boot_up_values.usVddc;
732 data->vbios_boot_state.vddci = boot_up_values.usVddci;
733 data->vbios_boot_state.mvddc = boot_up_values.usMvddc;
734 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
735 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
736 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
737 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
738 data->vbios_boot_state.eclock = boot_up_values.ulEClk;
739 data->vbios_boot_state.vclock = boot_up_values.ulVClk;
740 data->vbios_boot_state.dclock = boot_up_values.ulDClk;
741 data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID;
743 smum_send_msg_to_smc_with_parameter(hwmgr,
744 PPSMC_MSG_SetMinDeepSleepDcefclk,
745 (uint32_t)(data->vbios_boot_state.dcef_clock / 100));
747 memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
749 result = smum_smc_table_manager(hwmgr,
750 (uint8_t *)pp_table, TABLE_PPTABLE, false);
751 PP_ASSERT_WITH_CODE(!result,
752 "[InitSMCTable] Failed to upload PPtable!",
758 static int vega20_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
760 struct vega20_hwmgr *data =
761 (struct vega20_hwmgr *)(hwmgr->backend);
762 uint32_t allowed_features_low = 0, allowed_features_high = 0;
766 for (i = 0; i < GNLD_FEATURES_MAX; i++)
767 if (data->smu_features[i].allowed)
768 data->smu_features[i].smu_feature_id > 31 ?
769 (allowed_features_high |=
770 ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT)
772 (allowed_features_low |=
773 ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT)
776 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
777 PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high);
778 PP_ASSERT_WITH_CODE(!ret,
779 "[SetAllowedFeaturesMask] Attempt to set allowed features mask(high) failed!",
782 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
783 PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low);
784 PP_ASSERT_WITH_CODE(!ret,
785 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!",
791 static int vega20_run_btc_afll(struct pp_hwmgr *hwmgr)
793 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAfllBtc);
796 static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr)
798 struct vega20_hwmgr *data =
799 (struct vega20_hwmgr *)(hwmgr->backend);
800 uint64_t features_enabled;
805 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
806 PPSMC_MSG_EnableAllSmuFeatures)) == 0,
807 "[EnableAllSMUFeatures] Failed to enable all smu features!",
810 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
811 PP_ASSERT_WITH_CODE(!ret,
812 "[EnableAllSmuFeatures] Failed to get enabled smc features!",
815 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
816 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
818 data->smu_features[i].enabled = enabled;
819 data->smu_features[i].supported = enabled;
822 if (data->smu_features[i].allowed && !enabled)
823 pr_info("[EnableAllSMUFeatures] feature %d is expected enabled!", i);
824 else if (!data->smu_features[i].allowed && enabled)
825 pr_info("[EnableAllSMUFeatures] feature %d is expected disabled!", i);
832 static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr)
834 struct vega20_hwmgr *data =
835 (struct vega20_hwmgr *)(hwmgr->backend);
836 uint64_t features_enabled;
841 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
842 PPSMC_MSG_DisableAllSmuFeatures)) == 0,
843 "[DisableAllSMUFeatures] Failed to disable all smu features!",
846 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
847 PP_ASSERT_WITH_CODE(!ret,
848 "[DisableAllSMUFeatures] Failed to get enabled smc features!",
851 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
852 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
854 data->smu_features[i].enabled = enabled;
855 data->smu_features[i].supported = enabled;
861 static int vega20_od8_set_feature_capabilities(
862 struct pp_hwmgr *hwmgr)
864 struct phm_ppt_v3_information *pptable_information =
865 (struct phm_ppt_v3_information *)hwmgr->pptable;
866 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
867 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
868 struct vega20_od8_settings *od_settings = &(data->od8_settings);
870 od_settings->overdrive8_capabilities = 0;
872 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
873 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
874 pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
875 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
876 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
877 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN]))
878 od_settings->overdrive8_capabilities |= OD8_GFXCLK_LIMITS;
880 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
881 (pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
882 pp_table->MinVoltageGfx / VOLTAGE_SCALE) &&
883 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
884 pp_table->MaxVoltageGfx / VOLTAGE_SCALE) &&
885 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] >=
886 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1]))
887 od_settings->overdrive8_capabilities |= OD8_GFXCLK_CURVE;
890 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
891 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
892 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
893 pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
894 (pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
895 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX]))
896 od_settings->overdrive8_capabilities |= OD8_UCLK_MAX;
899 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
900 pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
901 pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
902 pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
903 pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100)
904 od_settings->overdrive8_capabilities |= OD8_POWER_LIMIT;
906 if (data->smu_features[GNLD_FAN_CONTROL].enabled) {
907 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
908 pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
909 pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
910 (pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
911 pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT]))
912 od_settings->overdrive8_capabilities |= OD8_ACOUSTIC_LIMIT_SCLK;
914 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
915 (pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] >=
916 (pp_table->FanPwmMin * pp_table->FanMaximumRpm / 100)) &&
917 pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
918 (pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
919 pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED]))
920 od_settings->overdrive8_capabilities |= OD8_FAN_SPEED_MIN;
923 if (data->smu_features[GNLD_THERMAL].enabled) {
924 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
925 pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
926 pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
927 (pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
928 pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP]))
929 od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_FAN;
931 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
932 pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
933 pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
934 (pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
935 pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX]))
936 od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_SYSTEM;
939 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_MEMORY_TIMING_TUNE])
940 od_settings->overdrive8_capabilities |= OD8_MEMORY_TIMING_TUNE;
942 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ZERO_RPM_CONTROL] &&
943 pp_table->FanZeroRpmEnable)
944 od_settings->overdrive8_capabilities |= OD8_FAN_ZERO_RPM_CONTROL;
949 static int vega20_od8_set_feature_id(
950 struct pp_hwmgr *hwmgr)
952 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
953 struct vega20_od8_settings *od_settings = &(data->od8_settings);
955 if (od_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
956 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
958 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
961 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
963 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
967 if (od_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
968 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
970 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
972 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
974 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
976 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
978 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
981 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
983 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
985 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
987 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
989 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
991 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
995 if (od_settings->overdrive8_capabilities & OD8_UCLK_MAX)
996 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = OD8_UCLK_MAX;
998 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = 0;
1000 if (od_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1001 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = OD8_POWER_LIMIT;
1003 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = 0;
1005 if (od_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1006 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1007 OD8_ACOUSTIC_LIMIT_SCLK;
1009 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1012 if (od_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1013 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1016 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1019 if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1020 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1021 OD8_TEMPERATURE_FAN;
1023 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1026 if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1027 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1028 OD8_TEMPERATURE_SYSTEM;
1030 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1036 static int vega20_od8_get_gfx_clock_base_voltage(
1037 struct pp_hwmgr *hwmgr,
1043 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1044 PPSMC_MSG_GetAVFSVoltageByDpm,
1045 ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq));
1046 PP_ASSERT_WITH_CODE(!ret,
1047 "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!",
1050 *voltage = smum_get_argument(hwmgr);
1051 *voltage = *voltage / VOLTAGE_SCALE;
1056 static int vega20_od8_initialize_default_settings(
1057 struct pp_hwmgr *hwmgr)
1059 struct phm_ppt_v3_information *pptable_information =
1060 (struct phm_ppt_v3_information *)hwmgr->pptable;
1061 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1062 struct vega20_od8_settings *od8_settings = &(data->od8_settings);
1063 OverDriveTable_t *od_table = &(data->smc_state_table.overdrive_table);
1066 /* Set Feature Capabilities */
1067 vega20_od8_set_feature_capabilities(hwmgr);
1069 /* Map FeatureID to individual settings */
1070 vega20_od8_set_feature_id(hwmgr);
1072 /* Set default values */
1073 ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, true);
1074 PP_ASSERT_WITH_CODE(!ret,
1075 "Failed to export over drive table!",
1078 if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
1079 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1080 od_table->GfxclkFmin;
1081 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1082 od_table->GfxclkFmax;
1084 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1086 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1090 if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1091 od_table->GfxclkFreq1 = od_table->GfxclkFmin;
1092 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1093 od_table->GfxclkFreq1;
1095 od_table->GfxclkFreq3 = od_table->GfxclkFmax;
1096 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1097 od_table->GfxclkFreq3;
1099 od_table->GfxclkFreq2 = (od_table->GfxclkFreq1 + od_table->GfxclkFreq3) / 2;
1100 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1101 od_table->GfxclkFreq2;
1103 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1104 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value),
1105 od_table->GfxclkFreq1),
1106 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1107 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0);
1108 od_table->GfxclkVolt1 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
1111 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1112 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value),
1113 od_table->GfxclkFreq2),
1114 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1115 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0);
1116 od_table->GfxclkVolt2 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
1119 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1120 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value),
1121 od_table->GfxclkFreq3),
1122 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1123 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0);
1124 od_table->GfxclkVolt3 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
1127 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1129 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value =
1131 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1133 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value =
1135 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1137 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value =
1141 if (od8_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1142 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1145 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1148 if (od8_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1149 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1150 od_table->OverDrivePct;
1152 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1155 if (od8_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1156 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1157 od_table->FanMaximumRpm;
1159 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1162 if (od8_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1163 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1164 od_table->FanMinimumPwm * data->smc_state_table.pp_table.FanMaximumRpm / 100;
1166 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1169 if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1170 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1171 od_table->FanTargetTemperature;
1173 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1176 if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1177 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1178 od_table->MaxOpTemp;
1180 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1183 for (i = 0; i < OD8_SETTING_COUNT; i++) {
1184 if (od8_settings->od8_settings_array[i].feature_id) {
1185 od8_settings->od8_settings_array[i].min_value =
1186 pptable_information->od_settings_min[i];
1187 od8_settings->od8_settings_array[i].max_value =
1188 pptable_information->od_settings_max[i];
1189 od8_settings->od8_settings_array[i].current_value =
1190 od8_settings->od8_settings_array[i].default_value;
1192 od8_settings->od8_settings_array[i].min_value =
1194 od8_settings->od8_settings_array[i].max_value =
1196 od8_settings->od8_settings_array[i].current_value =
1201 ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, false);
1202 PP_ASSERT_WITH_CODE(!ret,
1203 "Failed to import over drive table!",
1209 static int vega20_od8_set_settings(
1210 struct pp_hwmgr *hwmgr,
1214 OverDriveTable_t od_table;
1216 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1217 struct vega20_od8_single_setting *od8_settings =
1218 data->od8_settings.od8_settings_array;
1220 ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, true);
1221 PP_ASSERT_WITH_CODE(!ret,
1222 "Failed to export over drive table!",
1226 case OD8_SETTING_GFXCLK_FMIN:
1227 od_table.GfxclkFmin = (uint16_t)value;
1229 case OD8_SETTING_GFXCLK_FMAX:
1230 if (value < od8_settings[OD8_SETTING_GFXCLK_FMAX].min_value ||
1231 value > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value)
1234 od_table.GfxclkFmax = (uint16_t)value;
1236 case OD8_SETTING_GFXCLK_FREQ1:
1237 od_table.GfxclkFreq1 = (uint16_t)value;
1239 case OD8_SETTING_GFXCLK_VOLTAGE1:
1240 od_table.GfxclkVolt1 = (uint16_t)value;
1242 case OD8_SETTING_GFXCLK_FREQ2:
1243 od_table.GfxclkFreq2 = (uint16_t)value;
1245 case OD8_SETTING_GFXCLK_VOLTAGE2:
1246 od_table.GfxclkVolt2 = (uint16_t)value;
1248 case OD8_SETTING_GFXCLK_FREQ3:
1249 od_table.GfxclkFreq3 = (uint16_t)value;
1251 case OD8_SETTING_GFXCLK_VOLTAGE3:
1252 od_table.GfxclkVolt3 = (uint16_t)value;
1254 case OD8_SETTING_UCLK_FMAX:
1255 if (value < od8_settings[OD8_SETTING_UCLK_FMAX].min_value ||
1256 value > od8_settings[OD8_SETTING_UCLK_FMAX].max_value)
1258 od_table.UclkFmax = (uint16_t)value;
1260 case OD8_SETTING_POWER_PERCENTAGE:
1261 od_table.OverDrivePct = (int16_t)value;
1263 case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
1264 od_table.FanMaximumRpm = (uint16_t)value;
1266 case OD8_SETTING_FAN_MIN_SPEED:
1267 od_table.FanMinimumPwm = (uint16_t)value;
1269 case OD8_SETTING_FAN_TARGET_TEMP:
1270 od_table.FanTargetTemperature = (uint16_t)value;
1272 case OD8_SETTING_OPERATING_TEMP_MAX:
1273 od_table.MaxOpTemp = (uint16_t)value;
1277 ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, false);
1278 PP_ASSERT_WITH_CODE(!ret,
1279 "Failed to import over drive table!",
1285 static int vega20_get_sclk_od(
1286 struct pp_hwmgr *hwmgr)
1288 struct vega20_hwmgr *data = hwmgr->backend;
1289 struct vega20_single_dpm_table *sclk_table =
1290 &(data->dpm_table.gfx_table);
1291 struct vega20_single_dpm_table *golden_sclk_table =
1292 &(data->golden_dpm_table.gfx_table);
1296 value = DIV_ROUND_UP((sclk_table->dpm_levels[sclk_table->count - 1].value -
1297 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) * 100,
1298 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value);
1303 static int vega20_set_sclk_od(
1304 struct pp_hwmgr *hwmgr, uint32_t value)
1306 struct vega20_hwmgr *data = hwmgr->backend;
1307 struct vega20_single_dpm_table *golden_sclk_table =
1308 &(data->golden_dpm_table.gfx_table);
1312 od_sclk = golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * value;
1314 od_sclk += golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
1316 ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_GFXCLK_FMAX, od_sclk);
1317 PP_ASSERT_WITH_CODE(!ret,
1318 "[SetSclkOD] failed to set od gfxclk!",
1321 /* retrieve updated gfxclk table */
1322 ret = vega20_setup_gfxclk_dpm_table(hwmgr);
1323 PP_ASSERT_WITH_CODE(!ret,
1324 "[SetSclkOD] failed to refresh gfxclk table!",
1330 static int vega20_get_mclk_od(
1331 struct pp_hwmgr *hwmgr)
1333 struct vega20_hwmgr *data = hwmgr->backend;
1334 struct vega20_single_dpm_table *mclk_table =
1335 &(data->dpm_table.mem_table);
1336 struct vega20_single_dpm_table *golden_mclk_table =
1337 &(data->golden_dpm_table.mem_table);
1341 value = DIV_ROUND_UP((mclk_table->dpm_levels[mclk_table->count - 1].value -
1342 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) * 100,
1343 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value);
1348 static int vega20_set_mclk_od(
1349 struct pp_hwmgr *hwmgr, uint32_t value)
1351 struct vega20_hwmgr *data = hwmgr->backend;
1352 struct vega20_single_dpm_table *golden_mclk_table =
1353 &(data->golden_dpm_table.mem_table);
1357 od_mclk = golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * value;
1359 od_mclk += golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
1361 ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_UCLK_FMAX, od_mclk);
1362 PP_ASSERT_WITH_CODE(!ret,
1363 "[SetMclkOD] failed to set od memclk!",
1366 /* retrieve updated memclk table */
1367 ret = vega20_setup_memclk_dpm_table(hwmgr);
1368 PP_ASSERT_WITH_CODE(!ret,
1369 "[SetMclkOD] failed to refresh memclk table!",
1375 static int vega20_populate_umdpstate_clocks(
1376 struct pp_hwmgr *hwmgr)
1378 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1379 struct vega20_single_dpm_table *gfx_table = &(data->dpm_table.gfx_table);
1380 struct vega20_single_dpm_table *mem_table = &(data->dpm_table.mem_table);
1382 hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value;
1383 hwmgr->pstate_mclk = mem_table->dpm_levels[0].value;
1385 if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
1386 mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
1387 hwmgr->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
1388 hwmgr->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
1391 hwmgr->pstate_sclk = hwmgr->pstate_sclk * 100;
1392 hwmgr->pstate_mclk = hwmgr->pstate_mclk * 100;
1397 static int vega20_get_max_sustainable_clock(struct pp_hwmgr *hwmgr,
1398 PP_Clock *clock, PPCLK_e clock_select)
1402 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1403 PPSMC_MSG_GetDcModeMaxDpmFreq,
1404 (clock_select << 16))) == 0,
1405 "[GetMaxSustainableClock] Failed to get max DC clock from SMC!",
1407 *clock = smum_get_argument(hwmgr);
1409 /* if DC limit is zero, return AC limit */
1411 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1412 PPSMC_MSG_GetMaxDpmFreq,
1413 (clock_select << 16))) == 0,
1414 "[GetMaxSustainableClock] failed to get max AC clock from SMC!",
1416 *clock = smum_get_argument(hwmgr);
1422 static int vega20_init_max_sustainable_clocks(struct pp_hwmgr *hwmgr)
1424 struct vega20_hwmgr *data =
1425 (struct vega20_hwmgr *)(hwmgr->backend);
1426 struct vega20_max_sustainable_clocks *max_sustainable_clocks =
1427 &(data->max_sustainable_clocks);
1430 max_sustainable_clocks->uclock = data->vbios_boot_state.mem_clock / 100;
1431 max_sustainable_clocks->soc_clock = data->vbios_boot_state.soc_clock / 100;
1432 max_sustainable_clocks->dcef_clock = data->vbios_boot_state.dcef_clock / 100;
1433 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
1434 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
1435 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
1437 if (data->smu_features[GNLD_DPM_UCLK].enabled)
1438 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1439 &(max_sustainable_clocks->uclock),
1441 "[InitMaxSustainableClocks] failed to get max UCLK from SMC!",
1444 if (data->smu_features[GNLD_DPM_SOCCLK].enabled)
1445 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1446 &(max_sustainable_clocks->soc_clock),
1447 PPCLK_SOCCLK)) == 0,
1448 "[InitMaxSustainableClocks] failed to get max SOCCLK from SMC!",
1451 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1452 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1453 &(max_sustainable_clocks->dcef_clock),
1454 PPCLK_DCEFCLK)) == 0,
1455 "[InitMaxSustainableClocks] failed to get max DCEFCLK from SMC!",
1457 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1458 &(max_sustainable_clocks->display_clock),
1459 PPCLK_DISPCLK)) == 0,
1460 "[InitMaxSustainableClocks] failed to get max DISPCLK from SMC!",
1462 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1463 &(max_sustainable_clocks->phy_clock),
1464 PPCLK_PHYCLK)) == 0,
1465 "[InitMaxSustainableClocks] failed to get max PHYCLK from SMC!",
1467 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1468 &(max_sustainable_clocks->pixel_clock),
1469 PPCLK_PIXCLK)) == 0,
1470 "[InitMaxSustainableClocks] failed to get max PIXCLK from SMC!",
1474 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1475 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1480 static int vega20_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
1484 result = smum_send_msg_to_smc(hwmgr,
1485 PPSMC_MSG_SetMGpuFanBoostLimitRpm);
1486 PP_ASSERT_WITH_CODE(!result,
1487 "[EnableMgpuFan] Failed to enable mgpu fan boost!",
1493 static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr)
1495 struct vega20_hwmgr *data =
1496 (struct vega20_hwmgr *)(hwmgr->backend);
1498 data->uvd_power_gated = true;
1499 data->vce_power_gated = true;
1501 if (data->smu_features[GNLD_DPM_UVD].enabled)
1502 data->uvd_power_gated = false;
1504 if (data->smu_features[GNLD_DPM_VCE].enabled)
1505 data->vce_power_gated = false;
1508 static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1512 smum_send_msg_to_smc_with_parameter(hwmgr,
1513 PPSMC_MSG_NumOfDisplays, 0);
1515 result = vega20_set_allowed_featuresmask(hwmgr);
1516 PP_ASSERT_WITH_CODE(!result,
1517 "[EnableDPMTasks] Failed to set allowed featuresmask!\n",
1520 result = vega20_init_smc_table(hwmgr);
1521 PP_ASSERT_WITH_CODE(!result,
1522 "[EnableDPMTasks] Failed to initialize SMC table!",
1525 result = vega20_run_btc_afll(hwmgr);
1526 PP_ASSERT_WITH_CODE(!result,
1527 "[EnableDPMTasks] Failed to run btc afll!",
1530 result = vega20_enable_all_smu_features(hwmgr);
1531 PP_ASSERT_WITH_CODE(!result,
1532 "[EnableDPMTasks] Failed to enable all smu features!",
1535 /* Initialize UVD/VCE powergating state */
1536 vega20_init_powergate_state(hwmgr);
1538 result = vega20_setup_default_dpm_tables(hwmgr);
1539 PP_ASSERT_WITH_CODE(!result,
1540 "[EnableDPMTasks] Failed to setup default DPM tables!",
1543 result = vega20_init_max_sustainable_clocks(hwmgr);
1544 PP_ASSERT_WITH_CODE(!result,
1545 "[EnableDPMTasks] Failed to get maximum sustainable clocks!",
1548 result = vega20_power_control_set_level(hwmgr);
1549 PP_ASSERT_WITH_CODE(!result,
1550 "[EnableDPMTasks] Failed to power control set level!",
1553 result = vega20_od8_initialize_default_settings(hwmgr);
1554 PP_ASSERT_WITH_CODE(!result,
1555 "[EnableDPMTasks] Failed to initialize odn settings!",
1558 result = vega20_populate_umdpstate_clocks(hwmgr);
1559 PP_ASSERT_WITH_CODE(!result,
1560 "[EnableDPMTasks] Failed to populate umdpstate clocks!",
1563 result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetPptLimit,
1564 POWER_SOURCE_AC << 16);
1565 PP_ASSERT_WITH_CODE(!result,
1566 "[GetPptLimit] get default PPT limit failed!",
1568 hwmgr->power_limit =
1569 hwmgr->default_power_limit = smum_get_argument(hwmgr);
1574 static uint32_t vega20_find_lowest_dpm_level(
1575 struct vega20_single_dpm_table *table)
1579 for (i = 0; i < table->count; i++) {
1580 if (table->dpm_levels[i].enabled)
1583 if (i >= table->count) {
1585 table->dpm_levels[i].enabled = true;
1591 static uint32_t vega20_find_highest_dpm_level(
1592 struct vega20_single_dpm_table *table)
1596 PP_ASSERT_WITH_CODE(table != NULL,
1597 "[FindHighestDPMLevel] DPM Table does not exist!",
1599 PP_ASSERT_WITH_CODE(table->count > 0,
1600 "[FindHighestDPMLevel] DPM Table has no entry!",
1602 PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
1603 "[FindHighestDPMLevel] DPM Table has too many entries!",
1604 return MAX_REGULAR_DPM_NUMBER - 1);
1606 for (i = table->count - 1; i >= 0; i--) {
1607 if (table->dpm_levels[i].enabled)
1612 table->dpm_levels[i].enabled = true;
1618 static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
1620 struct vega20_hwmgr *data =
1621 (struct vega20_hwmgr *)(hwmgr->backend);
1625 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1626 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
1627 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1628 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1629 (PPCLK_GFXCLK << 16) | (min_freq & 0xffff))),
1630 "Failed to set soft min gfxclk !",
1634 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1635 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
1636 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1637 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1638 (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
1639 "Failed to set soft min memclk !",
1642 min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level;
1643 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1644 hwmgr, PPSMC_MSG_SetHardMinByFreq,
1645 (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
1646 "Failed to set hard min memclk !",
1650 if (data->smu_features[GNLD_DPM_UVD].enabled) {
1651 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
1653 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1654 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1655 (PPCLK_VCLK << 16) | (min_freq & 0xffff))),
1656 "Failed to set soft min vclk!",
1659 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level;
1661 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1662 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1663 (PPCLK_DCLK << 16) | (min_freq & 0xffff))),
1664 "Failed to set soft min dclk!",
1668 if (data->smu_features[GNLD_DPM_VCE].enabled) {
1669 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
1671 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1672 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1673 (PPCLK_ECLK << 16) | (min_freq & 0xffff))),
1674 "Failed to set soft min eclk!",
1678 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
1679 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
1681 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1682 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1683 (PPCLK_SOCCLK << 16) | (min_freq & 0xffff))),
1684 "Failed to set soft min socclk!",
1691 static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
1693 struct vega20_hwmgr *data =
1694 (struct vega20_hwmgr *)(hwmgr->backend);
1698 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1699 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
1701 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1702 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1703 (PPCLK_GFXCLK << 16) | (max_freq & 0xffff))),
1704 "Failed to set soft max gfxclk!",
1708 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1709 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
1711 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1712 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1713 (PPCLK_UCLK << 16) | (max_freq & 0xffff))),
1714 "Failed to set soft max memclk!",
1718 if (data->smu_features[GNLD_DPM_UVD].enabled) {
1719 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
1721 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1722 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1723 (PPCLK_VCLK << 16) | (max_freq & 0xffff))),
1724 "Failed to set soft max vclk!",
1727 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level;
1728 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1729 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1730 (PPCLK_DCLK << 16) | (max_freq & 0xffff))),
1731 "Failed to set soft max dclk!",
1735 if (data->smu_features[GNLD_DPM_VCE].enabled) {
1736 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
1738 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1739 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1740 (PPCLK_ECLK << 16) | (max_freq & 0xffff))),
1741 "Failed to set soft max eclk!",
1745 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
1746 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
1748 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1749 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1750 (PPCLK_SOCCLK << 16) | (max_freq & 0xffff))),
1751 "Failed to set soft max socclk!",
1758 int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
1760 struct vega20_hwmgr *data =
1761 (struct vega20_hwmgr *)(hwmgr->backend);
1764 if (data->smu_features[GNLD_DPM_VCE].supported) {
1765 if (data->smu_features[GNLD_DPM_VCE].enabled == enable) {
1767 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already enabled!\n");
1769 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already disabled!\n");
1772 ret = vega20_enable_smc_features(hwmgr,
1774 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap);
1775 PP_ASSERT_WITH_CODE(!ret,
1776 "Attempt to Enable/Disable DPM VCE Failed!",
1778 data->smu_features[GNLD_DPM_VCE].enabled = enable;
1784 static int vega20_get_clock_ranges(struct pp_hwmgr *hwmgr,
1786 PPCLK_e clock_select,
1793 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1794 PPSMC_MSG_GetMaxDpmFreq, (clock_select << 16))) == 0,
1795 "[GetClockRanges] Failed to get max clock from SMC!",
1797 *clock = smum_get_argument(hwmgr);
1799 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1800 PPSMC_MSG_GetMinDpmFreq,
1801 (clock_select << 16))) == 0,
1802 "[GetClockRanges] Failed to get min clock from SMC!",
1804 *clock = smum_get_argument(hwmgr);
1810 static uint32_t vega20_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1812 struct vega20_hwmgr *data =
1813 (struct vega20_hwmgr *)(hwmgr->backend);
1817 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,
1818 "[GetSclks]: gfxclk dpm not enabled!\n",
1822 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false);
1823 PP_ASSERT_WITH_CODE(!ret,
1824 "[GetSclks]: fail to get min PPCLK_GFXCLK\n",
1827 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true);
1828 PP_ASSERT_WITH_CODE(!ret,
1829 "[GetSclks]: fail to get max PPCLK_GFXCLK\n",
1833 return (gfx_clk * 100);
1836 static uint32_t vega20_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1838 struct vega20_hwmgr *data =
1839 (struct vega20_hwmgr *)(hwmgr->backend);
1843 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,
1844 "[MemMclks]: memclk dpm not enabled!\n",
1848 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false);
1849 PP_ASSERT_WITH_CODE(!ret,
1850 "[GetMclks]: fail to get min PPCLK_UCLK\n",
1853 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true);
1854 PP_ASSERT_WITH_CODE(!ret,
1855 "[GetMclks]: fail to get max PPCLK_UCLK\n",
1859 return (mem_clk * 100);
1862 static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr,
1866 SmuMetrics_t metrics_table;
1868 ret = smum_smc_table_manager(hwmgr, (uint8_t *)&metrics_table, TABLE_SMU_METRICS, true);
1869 PP_ASSERT_WITH_CODE(!ret,
1870 "Failed to export SMU METRICS table!",
1873 *query = metrics_table.CurrSocketPower << 8;
1878 static int vega20_get_current_clk_freq(struct pp_hwmgr *hwmgr,
1879 PPCLK_e clk_id, uint32_t *clk_freq)
1885 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1886 PPSMC_MSG_GetDpmClockFreq, (clk_id << 16))) == 0,
1887 "[GetCurrentClkFreq] Attempt to get Current Frequency Failed!",
1889 *clk_freq = smum_get_argument(hwmgr);
1891 *clk_freq = *clk_freq * 100;
1896 static int vega20_get_current_activity_percent(struct pp_hwmgr *hwmgr,
1897 uint32_t *activity_percent)
1900 SmuMetrics_t metrics_table;
1902 ret = smum_smc_table_manager(hwmgr, (uint8_t *)&metrics_table, TABLE_SMU_METRICS, true);
1903 PP_ASSERT_WITH_CODE(!ret,
1904 "Failed to export SMU METRICS table!",
1907 *activity_percent = metrics_table.AverageGfxActivity;
1912 static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1913 void *value, int *size)
1915 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1916 struct amdgpu_device *adev = hwmgr->adev;
1921 case AMDGPU_PP_SENSOR_GFX_SCLK:
1922 ret = vega20_get_current_clk_freq(hwmgr,
1928 case AMDGPU_PP_SENSOR_GFX_MCLK:
1929 ret = vega20_get_current_clk_freq(hwmgr,
1935 case AMDGPU_PP_SENSOR_GPU_LOAD:
1936 ret = vega20_get_current_activity_percent(hwmgr, (uint32_t *)value);
1940 case AMDGPU_PP_SENSOR_GPU_TEMP:
1941 *((uint32_t *)value) = vega20_thermal_get_temperature(hwmgr);
1944 case AMDGPU_PP_SENSOR_UVD_POWER:
1945 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
1948 case AMDGPU_PP_SENSOR_VCE_POWER:
1949 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
1952 case AMDGPU_PP_SENSOR_GPU_POWER:
1954 ret = vega20_get_gpu_power(hwmgr, (uint32_t *)value);
1956 case AMDGPU_PP_SENSOR_VDDGFX:
1957 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1958 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1959 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1960 *((uint32_t *)value) =
1961 (uint32_t)convert_to_vddc((uint8_t)val_vid);
1963 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
1964 ret = vega20_get_enabled_smc_features(hwmgr, (uint64_t *)value);
1975 static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr,
1978 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1980 if (data->smu_features[GNLD_DPM_UCLK].enabled)
1981 return smum_send_msg_to_smc_with_parameter(hwmgr,
1982 PPSMC_MSG_SetUclkFastSwitch,
1988 int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
1989 struct pp_display_clock_request *clock_req)
1992 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1993 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1994 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1995 PPCLK_e clk_select = 0;
1996 uint32_t clk_request = 0;
1998 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
2000 case amd_pp_dcef_clock:
2001 clk_select = PPCLK_DCEFCLK;
2003 case amd_pp_disp_clock:
2004 clk_select = PPCLK_DISPCLK;
2006 case amd_pp_pixel_clock:
2007 clk_select = PPCLK_PIXCLK;
2009 case amd_pp_phy_clock:
2010 clk_select = PPCLK_PHYCLK;
2013 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
2019 clk_request = (clk_select << 16) | clk_freq;
2020 result = smum_send_msg_to_smc_with_parameter(hwmgr,
2021 PPSMC_MSG_SetHardMinByFreq,
2029 static int vega20_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
2030 PHM_PerformanceLevelDesignation designation, uint32_t index,
2031 PHM_PerformanceLevel *level)
2036 static int vega20_notify_smc_display_config_after_ps_adjustment(
2037 struct pp_hwmgr *hwmgr)
2039 struct vega20_hwmgr *data =
2040 (struct vega20_hwmgr *)(hwmgr->backend);
2041 struct vega20_single_dpm_table *dpm_table =
2042 &data->dpm_table.mem_table;
2043 struct PP_Clocks min_clocks = {0};
2044 struct pp_display_clock_request clock_req;
2047 if ((hwmgr->display_config->num_display > 1) &&
2048 !hwmgr->display_config->multi_monitor_in_sync &&
2049 !hwmgr->display_config->nb_pstate_switch_disable)
2050 vega20_notify_smc_display_change(hwmgr, false);
2052 vega20_notify_smc_display_change(hwmgr, true);
2054 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
2055 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
2056 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
2058 if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
2059 clock_req.clock_type = amd_pp_dcef_clock;
2060 clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10;
2061 if (!vega20_display_clock_voltage_request(hwmgr, &clock_req)) {
2062 if (data->smu_features[GNLD_DS_DCEFCLK].supported)
2063 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(
2064 hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
2065 min_clocks.dcefClockInSR / 100)) == 0,
2066 "Attempt to set divider for DCEFCLK Failed!",
2069 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
2073 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2074 dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100;
2075 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2076 PPSMC_MSG_SetHardMinByFreq,
2077 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
2078 "[SetHardMinFreq] Set hard min uclk failed!",
2085 static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr)
2087 struct vega20_hwmgr *data =
2088 (struct vega20_hwmgr *)(hwmgr->backend);
2089 uint32_t soft_level;
2092 soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table));
2094 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2095 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2096 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2098 soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.mem_table));
2100 data->dpm_table.mem_table.dpm_state.soft_min_level =
2101 data->dpm_table.mem_table.dpm_state.soft_max_level =
2102 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2104 ret = vega20_upload_dpm_min_level(hwmgr);
2105 PP_ASSERT_WITH_CODE(!ret,
2106 "Failed to upload boot level to highest!",
2109 ret = vega20_upload_dpm_max_level(hwmgr);
2110 PP_ASSERT_WITH_CODE(!ret,
2111 "Failed to upload dpm max level to highest!",
2117 static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2119 struct vega20_hwmgr *data =
2120 (struct vega20_hwmgr *)(hwmgr->backend);
2121 uint32_t soft_level;
2124 soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
2126 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2127 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2128 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2130 soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table));
2132 data->dpm_table.mem_table.dpm_state.soft_min_level =
2133 data->dpm_table.mem_table.dpm_state.soft_max_level =
2134 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2136 ret = vega20_upload_dpm_min_level(hwmgr);
2137 PP_ASSERT_WITH_CODE(!ret,
2138 "Failed to upload boot level to highest!",
2141 ret = vega20_upload_dpm_max_level(hwmgr);
2142 PP_ASSERT_WITH_CODE(!ret,
2143 "Failed to upload dpm max level to highest!",
2150 static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
2154 ret = vega20_upload_dpm_min_level(hwmgr);
2155 PP_ASSERT_WITH_CODE(!ret,
2156 "Failed to upload DPM Bootup Levels!",
2159 ret = vega20_upload_dpm_max_level(hwmgr);
2160 PP_ASSERT_WITH_CODE(!ret,
2161 "Failed to upload DPM Max Levels!",
2167 static int vega20_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
2168 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
2170 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2171 struct vega20_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table);
2172 struct vega20_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table);
2173 struct vega20_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table);
2179 if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
2180 mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
2181 soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
2182 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
2183 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
2184 *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
2187 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2189 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2191 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2192 *sclk_mask = gfx_dpm_table->count - 1;
2193 *mclk_mask = mem_dpm_table->count - 1;
2194 *soc_mask = soc_dpm_table->count - 1;
2200 static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
2201 enum pp_clock_type type, uint32_t mask)
2203 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2204 uint32_t soft_min_level, soft_max_level;
2209 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2210 soft_max_level = mask ? (fls(mask) - 1) : 0;
2212 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2213 data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
2214 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2215 data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
2217 ret = vega20_upload_dpm_min_level(hwmgr);
2218 PP_ASSERT_WITH_CODE(!ret,
2219 "Failed to upload boot level to lowest!",
2222 ret = vega20_upload_dpm_max_level(hwmgr);
2223 PP_ASSERT_WITH_CODE(!ret,
2224 "Failed to upload dpm max level to highest!",
2229 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2230 soft_max_level = mask ? (fls(mask) - 1) : 0;
2232 data->dpm_table.mem_table.dpm_state.soft_min_level =
2233 data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
2234 data->dpm_table.mem_table.dpm_state.soft_max_level =
2235 data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
2237 ret = vega20_upload_dpm_min_level(hwmgr);
2238 PP_ASSERT_WITH_CODE(!ret,
2239 "Failed to upload boot level to lowest!",
2242 ret = vega20_upload_dpm_max_level(hwmgr);
2243 PP_ASSERT_WITH_CODE(!ret,
2244 "Failed to upload dpm max level to highest!",
2259 static int vega20_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
2260 enum amd_dpm_forced_level level)
2263 uint32_t sclk_mask, mclk_mask, soc_mask;
2266 case AMD_DPM_FORCED_LEVEL_HIGH:
2267 ret = vega20_force_dpm_highest(hwmgr);
2270 case AMD_DPM_FORCED_LEVEL_LOW:
2271 ret = vega20_force_dpm_lowest(hwmgr);
2274 case AMD_DPM_FORCED_LEVEL_AUTO:
2275 ret = vega20_unforce_dpm_levels(hwmgr);
2278 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
2279 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
2280 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
2281 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
2282 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
2285 vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
2286 vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
2289 case AMD_DPM_FORCED_LEVEL_MANUAL:
2290 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
2298 static uint32_t vega20_get_fan_control_mode(struct pp_hwmgr *hwmgr)
2300 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2302 if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
2303 return AMD_FAN_CTRL_MANUAL;
2305 return AMD_FAN_CTRL_AUTO;
2308 static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
2311 case AMD_FAN_CTRL_NONE:
2312 vega20_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
2314 case AMD_FAN_CTRL_MANUAL:
2315 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2316 vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
2318 case AMD_FAN_CTRL_AUTO:
2319 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2320 vega20_fan_ctrl_start_smc_fan_control(hwmgr);
2327 static int vega20_get_dal_power_level(struct pp_hwmgr *hwmgr,
2328 struct amd_pp_simple_clock_info *info)
2331 struct phm_ppt_v2_information *table_info =
2332 (struct phm_ppt_v2_information *)hwmgr->pptable;
2333 struct phm_clock_and_voltage_limits *max_limits =
2334 &table_info->max_clock_voltage_on_ac;
2336 info->engine_max_clock = max_limits->sclk;
2337 info->memory_max_clock = max_limits->mclk;
2343 static int vega20_get_sclks(struct pp_hwmgr *hwmgr,
2344 struct pp_clock_levels_with_latency *clocks)
2346 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2347 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
2350 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,
2351 "[GetSclks]: gfxclk dpm not enabled!\n",
2354 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2355 clocks->num_levels = count;
2357 for (i = 0; i < count; i++) {
2358 clocks->data[i].clocks_in_khz =
2359 dpm_table->dpm_levels[i].value * 1000;
2360 clocks->data[i].latency_in_us = 0;
2366 static uint32_t vega20_get_mem_latency(struct pp_hwmgr *hwmgr,
2372 static int vega20_get_memclocks(struct pp_hwmgr *hwmgr,
2373 struct pp_clock_levels_with_latency *clocks)
2375 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2376 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.mem_table);
2379 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,
2380 "[GetMclks]: uclk dpm not enabled!\n",
2383 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2384 clocks->num_levels = data->mclk_latency_table.count = count;
2386 for (i = 0; i < count; i++) {
2387 clocks->data[i].clocks_in_khz =
2388 data->mclk_latency_table.entries[i].frequency =
2389 dpm_table->dpm_levels[i].value * 1000;
2390 clocks->data[i].latency_in_us =
2391 data->mclk_latency_table.entries[i].latency =
2392 vega20_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
2398 static int vega20_get_dcefclocks(struct pp_hwmgr *hwmgr,
2399 struct pp_clock_levels_with_latency *clocks)
2401 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2402 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.dcef_table);
2405 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_DCEFCLK].enabled,
2406 "[GetDcfclocks]: dcefclk dpm not enabled!\n",
2409 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2410 clocks->num_levels = count;
2412 for (i = 0; i < count; i++) {
2413 clocks->data[i].clocks_in_khz =
2414 dpm_table->dpm_levels[i].value * 1000;
2415 clocks->data[i].latency_in_us = 0;
2421 static int vega20_get_socclocks(struct pp_hwmgr *hwmgr,
2422 struct pp_clock_levels_with_latency *clocks)
2424 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2425 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.soc_table);
2428 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_SOCCLK].enabled,
2429 "[GetSocclks]: socclk dpm not enabled!\n",
2432 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2433 clocks->num_levels = count;
2435 for (i = 0; i < count; i++) {
2436 clocks->data[i].clocks_in_khz =
2437 dpm_table->dpm_levels[i].value * 1000;
2438 clocks->data[i].latency_in_us = 0;
2445 static int vega20_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
2446 enum amd_pp_clock_type type,
2447 struct pp_clock_levels_with_latency *clocks)
2452 case amd_pp_sys_clock:
2453 ret = vega20_get_sclks(hwmgr, clocks);
2455 case amd_pp_mem_clock:
2456 ret = vega20_get_memclocks(hwmgr, clocks);
2458 case amd_pp_dcef_clock:
2459 ret = vega20_get_dcefclocks(hwmgr, clocks);
2461 case amd_pp_soc_clock:
2462 ret = vega20_get_socclocks(hwmgr, clocks);
2471 static int vega20_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
2472 enum amd_pp_clock_type type,
2473 struct pp_clock_levels_with_voltage *clocks)
2475 clocks->num_levels = 0;
2480 static int vega20_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
2483 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2484 Watermarks_t *table = &(data->smc_state_table.water_marks_table);
2485 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
2487 if (!data->registry_data.disable_water_mark &&
2488 data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2489 data->smu_features[GNLD_DPM_SOCCLK].supported) {
2490 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
2491 data->water_marks_bitmap |= WaterMarksExist;
2492 data->water_marks_bitmap &= ~WaterMarksLoaded;
2498 static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
2499 enum PP_OD_DPM_TABLE_COMMAND type,
2500 long *input, uint32_t size)
2502 struct vega20_hwmgr *data =
2503 (struct vega20_hwmgr *)(hwmgr->backend);
2504 struct vega20_od8_single_setting *od8_settings =
2505 data->od8_settings.od8_settings_array;
2506 OverDriveTable_t *od_table =
2507 &(data->smc_state_table.overdrive_table);
2508 struct pp_clock_levels_with_latency clocks;
2509 int32_t input_index, input_clk, input_vol, i;
2513 PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
2517 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2518 if (!(od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2519 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
2520 pr_info("Sclk min/max frequency overdrive not supported\n");
2524 for (i = 0; i < size; i += 2) {
2526 pr_info("invalid number of input parameters %d\n",
2531 input_index = input[i];
2532 input_clk = input[i + 1];
2534 if (input_index != 0 && input_index != 1) {
2535 pr_info("Invalid index %d\n", input_index);
2536 pr_info("Support min/max sclk frequency setting only which index by 0/1\n");
2540 if (input_clk < od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value ||
2541 input_clk > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) {
2542 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2544 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
2545 od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
2549 if ((input_index == 0 && od_table->GfxclkFmin != input_clk) ||
2550 (input_index == 1 && od_table->GfxclkFmax != input_clk))
2551 data->gfxclk_overdrive = true;
2553 if (input_index == 0)
2554 od_table->GfxclkFmin = input_clk;
2556 od_table->GfxclkFmax = input_clk;
2561 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2562 if (!od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2563 pr_info("Mclk max frequency overdrive not supported\n");
2567 ret = vega20_get_memclocks(hwmgr, &clocks);
2568 PP_ASSERT_WITH_CODE(!ret,
2569 "Attempt to get memory clk levels failed!",
2572 for (i = 0; i < size; i += 2) {
2574 pr_info("invalid number of input parameters %d\n",
2579 input_index = input[i];
2580 input_clk = input[i + 1];
2582 if (input_index != 1) {
2583 pr_info("Invalid index %d\n", input_index);
2584 pr_info("Support max Mclk frequency setting only which index by 1\n");
2588 if (input_clk < clocks.data[0].clocks_in_khz / 1000 ||
2589 input_clk > od8_settings[OD8_SETTING_UCLK_FMAX].max_value) {
2590 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2592 clocks.data[0].clocks_in_khz / 1000,
2593 od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
2597 if (input_index == 1 && od_table->UclkFmax != input_clk)
2598 data->memclk_overdrive = true;
2600 od_table->UclkFmax = input_clk;
2605 case PP_OD_EDIT_VDDC_CURVE:
2606 if (!(od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2607 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2608 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2609 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2610 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2611 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
2612 pr_info("Voltage curve calibrate not supported\n");
2616 for (i = 0; i < size; i += 3) {
2618 pr_info("invalid number of input parameters %d\n",
2623 input_index = input[i];
2624 input_clk = input[i + 1];
2625 input_vol = input[i + 2];
2627 if (input_index > 2) {
2628 pr_info("Setting for point %d is not supported\n",
2630 pr_info("Three supported points index by 0, 1, 2\n");
2634 od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
2635 if (input_clk < od8_settings[od8_id].min_value ||
2636 input_clk > od8_settings[od8_id].max_value) {
2637 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2639 od8_settings[od8_id].min_value,
2640 od8_settings[od8_id].max_value);
2644 od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
2645 if (input_vol < od8_settings[od8_id].min_value ||
2646 input_vol > od8_settings[od8_id].max_value) {
2647 pr_info("clock voltage %d is not within allowed range [%d - %d]\n",
2649 od8_settings[od8_id].min_value,
2650 od8_settings[od8_id].max_value);
2654 switch (input_index) {
2656 od_table->GfxclkFreq1 = input_clk;
2657 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
2660 od_table->GfxclkFreq2 = input_clk;
2661 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
2664 od_table->GfxclkFreq3 = input_clk;
2665 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
2671 case PP_OD_RESTORE_DEFAULT_TABLE:
2672 data->gfxclk_overdrive = false;
2673 data->memclk_overdrive = false;
2675 ret = smum_smc_table_manager(hwmgr,
2676 (uint8_t *)od_table,
2677 TABLE_OVERDRIVE, true);
2678 PP_ASSERT_WITH_CODE(!ret,
2679 "Failed to export overdrive table!",
2683 case PP_OD_COMMIT_DPM_TABLE:
2684 ret = smum_smc_table_manager(hwmgr,
2685 (uint8_t *)od_table,
2686 TABLE_OVERDRIVE, false);
2687 PP_ASSERT_WITH_CODE(!ret,
2688 "Failed to import overdrive table!",
2691 /* retrieve updated gfxclk table */
2692 if (data->gfxclk_overdrive) {
2693 data->gfxclk_overdrive = false;
2695 ret = vega20_setup_gfxclk_dpm_table(hwmgr);
2700 /* retrieve updated memclk table */
2701 if (data->memclk_overdrive) {
2702 data->memclk_overdrive = false;
2704 ret = vega20_setup_memclk_dpm_table(hwmgr);
2717 static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
2718 enum pp_clock_type type, char *buf)
2720 struct vega20_hwmgr *data =
2721 (struct vega20_hwmgr *)(hwmgr->backend);
2722 struct vega20_od8_single_setting *od8_settings =
2723 data->od8_settings.od8_settings_array;
2724 OverDriveTable_t *od_table =
2725 &(data->smc_state_table.overdrive_table);
2726 struct pp_clock_levels_with_latency clocks;
2727 int i, now, size = 0;
2732 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_GFXCLK, &now);
2733 PP_ASSERT_WITH_CODE(!ret,
2734 "Attempt to get current gfx clk Failed!",
2737 ret = vega20_get_sclks(hwmgr, &clocks);
2738 PP_ASSERT_WITH_CODE(!ret,
2739 "Attempt to get gfx clk levels Failed!",
2742 for (i = 0; i < clocks.num_levels; i++)
2743 size += sprintf(buf + size, "%d: %uMhz %s\n",
2744 i, clocks.data[i].clocks_in_khz / 1000,
2745 (clocks.data[i].clocks_in_khz == now) ? "*" : "");
2749 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_UCLK, &now);
2750 PP_ASSERT_WITH_CODE(!ret,
2751 "Attempt to get current mclk freq Failed!",
2754 ret = vega20_get_memclocks(hwmgr, &clocks);
2755 PP_ASSERT_WITH_CODE(!ret,
2756 "Attempt to get memory clk levels Failed!",
2759 for (i = 0; i < clocks.num_levels; i++)
2760 size += sprintf(buf + size, "%d: %uMhz %s\n",
2761 i, clocks.data[i].clocks_in_khz / 1000,
2762 (clocks.data[i].clocks_in_khz == now) ? "*" : "");
2769 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2770 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
2771 size = sprintf(buf, "%s:\n", "OD_SCLK");
2772 size += sprintf(buf + size, "0: %10uMhz\n",
2773 od_table->GfxclkFmin);
2774 size += sprintf(buf + size, "1: %10uMhz\n",
2775 od_table->GfxclkFmax);
2780 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2781 size = sprintf(buf, "%s:\n", "OD_MCLK");
2782 size += sprintf(buf + size, "1: %10uMhz\n",
2783 od_table->UclkFmax);
2789 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2790 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2791 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2792 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2793 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2794 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
2795 size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");
2796 size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
2797 od_table->GfxclkFreq1,
2798 od_table->GfxclkVolt1 / VOLTAGE_SCALE);
2799 size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
2800 od_table->GfxclkFreq2,
2801 od_table->GfxclkVolt2 / VOLTAGE_SCALE);
2802 size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
2803 od_table->GfxclkFreq3,
2804 od_table->GfxclkVolt3 / VOLTAGE_SCALE);
2810 size = sprintf(buf, "%s:\n", "OD_RANGE");
2812 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2813 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
2814 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
2815 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
2816 od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
2819 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2820 ret = vega20_get_memclocks(hwmgr, &clocks);
2821 PP_ASSERT_WITH_CODE(!ret,
2822 "Fail to get memory clk levels!",
2825 size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
2826 clocks.data[0].clocks_in_khz / 1000,
2827 od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
2830 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2831 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2832 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2833 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2834 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2835 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
2836 size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
2837 od8_settings[OD8_SETTING_GFXCLK_FREQ1].min_value,
2838 od8_settings[OD8_SETTING_GFXCLK_FREQ1].max_value);
2839 size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
2840 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
2841 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
2842 size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
2843 od8_settings[OD8_SETTING_GFXCLK_FREQ2].min_value,
2844 od8_settings[OD8_SETTING_GFXCLK_FREQ2].max_value);
2845 size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
2846 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
2847 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
2848 size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
2849 od8_settings[OD8_SETTING_GFXCLK_FREQ3].min_value,
2850 od8_settings[OD8_SETTING_GFXCLK_FREQ3].max_value);
2851 size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
2852 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
2853 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
2863 static int vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
2864 struct vega20_single_dpm_table *dpm_table)
2866 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2869 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2870 PP_ASSERT_WITH_CODE(dpm_table->count > 0,
2871 "[SetUclkToHightestDpmLevel] Dpm table has no entry!",
2873 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
2874 "[SetUclkToHightestDpmLevel] Dpm table has too many entries!",
2877 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2878 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2879 PPSMC_MSG_SetHardMinByFreq,
2880 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
2881 "[SetUclkToHightestDpmLevel] Set hard min uclk failed!",
2888 static int vega20_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2890 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2893 smum_send_msg_to_smc_with_parameter(hwmgr,
2894 PPSMC_MSG_NumOfDisplays, 0);
2896 ret = vega20_set_uclk_to_highest_dpm_level(hwmgr,
2897 &data->dpm_table.mem_table);
2902 static int vega20_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2904 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2906 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
2908 if ((data->water_marks_bitmap & WaterMarksExist) &&
2909 !(data->water_marks_bitmap & WaterMarksLoaded)) {
2910 result = smum_smc_table_manager(hwmgr,
2911 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
2912 PP_ASSERT_WITH_CODE(!result,
2913 "Failed to update WMTABLE!",
2915 data->water_marks_bitmap |= WaterMarksLoaded;
2918 if ((data->water_marks_bitmap & WaterMarksExist) &&
2919 data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2920 data->smu_features[GNLD_DPM_SOCCLK].supported) {
2921 result = smum_send_msg_to_smc_with_parameter(hwmgr,
2922 PPSMC_MSG_NumOfDisplays,
2923 hwmgr->display_config->num_display);
2929 int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
2931 struct vega20_hwmgr *data =
2932 (struct vega20_hwmgr *)(hwmgr->backend);
2935 if (data->smu_features[GNLD_DPM_UVD].supported) {
2936 if (data->smu_features[GNLD_DPM_UVD].enabled == enable) {
2938 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already enabled!\n");
2940 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already disabled!\n");
2943 ret = vega20_enable_smc_features(hwmgr,
2945 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap);
2946 PP_ASSERT_WITH_CODE(!ret,
2947 "[EnableDisableUVDDPM] Attempt to Enable/Disable DPM UVD Failed!",
2949 data->smu_features[GNLD_DPM_UVD].enabled = enable;
2955 static void vega20_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
2957 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2959 if (data->vce_power_gated == bgate)
2962 data->vce_power_gated = bgate;
2963 vega20_enable_disable_vce_dpm(hwmgr, !bgate);
2966 static void vega20_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
2968 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2970 if (data->uvd_power_gated == bgate)
2973 data->uvd_power_gated = bgate;
2974 vega20_enable_disable_uvd_dpm(hwmgr, !bgate);
2977 static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
2979 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2980 struct vega20_single_dpm_table *dpm_table;
2981 bool vblank_too_short = false;
2982 bool disable_mclk_switching;
2983 uint32_t i, latency;
2985 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
2986 !hwmgr->display_config->multi_monitor_in_sync) ||
2988 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
2991 dpm_table = &(data->dpm_table.gfx_table);
2992 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2993 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2994 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2995 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2997 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2998 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
2999 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3000 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3003 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
3004 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3005 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3008 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3009 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3010 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3015 dpm_table = &(data->dpm_table.mem_table);
3016 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3017 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3018 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3019 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3021 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3022 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
3023 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3024 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3027 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
3028 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3029 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3032 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3033 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3034 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3038 /* honour DAL's UCLK Hardmin */
3039 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
3040 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
3042 /* Hardmin is dependent on displayconfig */
3043 if (disable_mclk_switching) {
3044 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3045 for (i = 0; i < data->mclk_latency_table.count - 1; i++) {
3046 if (data->mclk_latency_table.entries[i].latency <= latency) {
3047 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
3048 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
3055 if (hwmgr->display_config->nb_pstate_switch_disable)
3056 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3059 dpm_table = &(data->dpm_table.vclk_table);
3060 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3061 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3062 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3063 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3065 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3066 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3067 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3068 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3071 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3072 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3073 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3078 dpm_table = &(data->dpm_table.dclk_table);
3079 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3080 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3081 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3082 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3084 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3085 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3086 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3087 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3090 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3091 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3092 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3097 dpm_table = &(data->dpm_table.soc_table);
3098 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3099 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3100 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3101 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3103 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3104 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
3105 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3106 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3109 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3110 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3111 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3116 dpm_table = &(data->dpm_table.eclk_table);
3117 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3118 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3119 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3120 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3122 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3123 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
3124 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3125 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3128 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3129 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3130 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3138 vega20_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
3140 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3141 bool is_update_required = false;
3143 if (data->display_timing.num_existing_displays !=
3144 hwmgr->display_config->num_display)
3145 is_update_required = true;
3147 if (data->registry_data.gfx_clk_deep_sleep_support &&
3148 (data->display_timing.min_clock_in_sr !=
3149 hwmgr->display_config->min_core_set_clock_in_sr))
3150 is_update_required = true;
3152 return is_update_required;
3155 static int vega20_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
3159 ret = vega20_disable_all_smu_features(hwmgr);
3160 PP_ASSERT_WITH_CODE(!ret,
3161 "[DisableDpmTasks] Failed to disable all smu features!",
3167 static int vega20_power_off_asic(struct pp_hwmgr *hwmgr)
3169 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3172 result = vega20_disable_dpm_tasks(hwmgr);
3173 PP_ASSERT_WITH_CODE((0 == result),
3174 "[PowerOffAsic] Failed to disable DPM!",
3176 data->water_marks_bitmap &= ~(WaterMarksLoaded);
3181 static int conv_power_profile_to_pplib_workload(int power_profile)
3183 int pplib_workload = 0;
3185 switch (power_profile) {
3186 case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
3187 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
3189 case PP_SMC_POWER_PROFILE_POWERSAVING:
3190 pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
3192 case PP_SMC_POWER_PROFILE_VIDEO:
3193 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
3195 case PP_SMC_POWER_PROFILE_VR:
3196 pplib_workload = WORKLOAD_PPLIB_VR_BIT;
3198 case PP_SMC_POWER_PROFILE_COMPUTE:
3199 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
3201 case PP_SMC_POWER_PROFILE_CUSTOM:
3202 pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
3206 return pplib_workload;
3209 static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
3211 DpmActivityMonitorCoeffInt_t activity_monitor;
3212 uint32_t i, size = 0;
3213 uint16_t workload_type = 0;
3214 static const char *profile_name[] = {
3221 static const char *title[] = {
3222 "PROFILE_INDEX(NAME)",
3226 "MinActiveFreqType",
3231 "PD_Data_error_coeff",
3232 "PD_Data_error_rate_coeff"};
3238 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
3239 title[0], title[1], title[2], title[3], title[4], title[5],
3240 title[6], title[7], title[8], title[9], title[10]);
3242 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
3243 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
3244 workload_type = conv_power_profile_to_pplib_workload(i);
3245 result = vega20_get_activity_monitor_coeff(hwmgr,
3246 (uint8_t *)(&activity_monitor), workload_type);
3247 PP_ASSERT_WITH_CODE(!result,
3248 "[GetPowerProfile] Failed to get activity monitor!",
3251 size += sprintf(buf + size, "%2d %14s%s:\n",
3252 i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ");
3254 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3258 activity_monitor.Gfx_FPS,
3259 activity_monitor.Gfx_UseRlcBusy,
3260 activity_monitor.Gfx_MinActiveFreqType,
3261 activity_monitor.Gfx_MinActiveFreq,
3262 activity_monitor.Gfx_BoosterFreqType,
3263 activity_monitor.Gfx_BoosterFreq,
3264 activity_monitor.Gfx_PD_Data_limit_c,
3265 activity_monitor.Gfx_PD_Data_error_coeff,
3266 activity_monitor.Gfx_PD_Data_error_rate_coeff);
3268 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3272 activity_monitor.Soc_FPS,
3273 activity_monitor.Soc_UseRlcBusy,
3274 activity_monitor.Soc_MinActiveFreqType,
3275 activity_monitor.Soc_MinActiveFreq,
3276 activity_monitor.Soc_BoosterFreqType,
3277 activity_monitor.Soc_BoosterFreq,
3278 activity_monitor.Soc_PD_Data_limit_c,
3279 activity_monitor.Soc_PD_Data_error_coeff,
3280 activity_monitor.Soc_PD_Data_error_rate_coeff);
3282 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3286 activity_monitor.Mem_FPS,
3287 activity_monitor.Mem_UseRlcBusy,
3288 activity_monitor.Mem_MinActiveFreqType,
3289 activity_monitor.Mem_MinActiveFreq,
3290 activity_monitor.Mem_BoosterFreqType,
3291 activity_monitor.Mem_BoosterFreq,
3292 activity_monitor.Mem_PD_Data_limit_c,
3293 activity_monitor.Mem_PD_Data_error_coeff,
3294 activity_monitor.Mem_PD_Data_error_rate_coeff);
3296 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3300 activity_monitor.Fclk_FPS,
3301 activity_monitor.Fclk_UseRlcBusy,
3302 activity_monitor.Fclk_MinActiveFreqType,
3303 activity_monitor.Fclk_MinActiveFreq,
3304 activity_monitor.Fclk_BoosterFreqType,
3305 activity_monitor.Fclk_BoosterFreq,
3306 activity_monitor.Fclk_PD_Data_limit_c,
3307 activity_monitor.Fclk_PD_Data_error_coeff,
3308 activity_monitor.Fclk_PD_Data_error_rate_coeff);
3314 static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
3316 DpmActivityMonitorCoeffInt_t activity_monitor;
3317 int workload_type, result = 0;
3319 hwmgr->power_profile_mode = input[size];
3321 if (hwmgr->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
3322 pr_err("Invalid power profile mode %d\n", hwmgr->power_profile_mode);
3326 if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
3330 result = vega20_get_activity_monitor_coeff(hwmgr,
3331 (uint8_t *)(&activity_monitor),
3332 WORKLOAD_PPLIB_CUSTOM_BIT);
3333 PP_ASSERT_WITH_CODE(!result,
3334 "[SetPowerProfile] Failed to get activity monitor!",
3338 case 0: /* Gfxclk */
3339 activity_monitor.Gfx_FPS = input[1];
3340 activity_monitor.Gfx_UseRlcBusy = input[2];
3341 activity_monitor.Gfx_MinActiveFreqType = input[3];
3342 activity_monitor.Gfx_MinActiveFreq = input[4];
3343 activity_monitor.Gfx_BoosterFreqType = input[5];
3344 activity_monitor.Gfx_BoosterFreq = input[6];
3345 activity_monitor.Gfx_PD_Data_limit_c = input[7];
3346 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
3347 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
3349 case 1: /* Socclk */
3350 activity_monitor.Soc_FPS = input[1];
3351 activity_monitor.Soc_UseRlcBusy = input[2];
3352 activity_monitor.Soc_MinActiveFreqType = input[3];
3353 activity_monitor.Soc_MinActiveFreq = input[4];
3354 activity_monitor.Soc_BoosterFreqType = input[5];
3355 activity_monitor.Soc_BoosterFreq = input[6];
3356 activity_monitor.Soc_PD_Data_limit_c = input[7];
3357 activity_monitor.Soc_PD_Data_error_coeff = input[8];
3358 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
3361 activity_monitor.Mem_FPS = input[1];
3362 activity_monitor.Mem_UseRlcBusy = input[2];
3363 activity_monitor.Mem_MinActiveFreqType = input[3];
3364 activity_monitor.Mem_MinActiveFreq = input[4];
3365 activity_monitor.Mem_BoosterFreqType = input[5];
3366 activity_monitor.Mem_BoosterFreq = input[6];
3367 activity_monitor.Mem_PD_Data_limit_c = input[7];
3368 activity_monitor.Mem_PD_Data_error_coeff = input[8];
3369 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
3372 activity_monitor.Fclk_FPS = input[1];
3373 activity_monitor.Fclk_UseRlcBusy = input[2];
3374 activity_monitor.Fclk_MinActiveFreqType = input[3];
3375 activity_monitor.Fclk_MinActiveFreq = input[4];
3376 activity_monitor.Fclk_BoosterFreqType = input[5];
3377 activity_monitor.Fclk_BoosterFreq = input[6];
3378 activity_monitor.Fclk_PD_Data_limit_c = input[7];
3379 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
3380 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
3384 result = vega20_set_activity_monitor_coeff(hwmgr,
3385 (uint8_t *)(&activity_monitor),
3386 WORKLOAD_PPLIB_CUSTOM_BIT);
3387 PP_ASSERT_WITH_CODE(!result,
3388 "[SetPowerProfile] Failed to set activity monitor!",
3392 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
3394 conv_power_profile_to_pplib_workload(hwmgr->power_profile_mode);
3395 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
3396 1 << workload_type);
3401 static int vega20_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
3402 uint32_t virtual_addr_low,
3403 uint32_t virtual_addr_hi,
3404 uint32_t mc_addr_low,
3405 uint32_t mc_addr_hi,
3408 smum_send_msg_to_smc_with_parameter(hwmgr,
3409 PPSMC_MSG_SetSystemVirtualDramAddrHigh,
3411 smum_send_msg_to_smc_with_parameter(hwmgr,
3412 PPSMC_MSG_SetSystemVirtualDramAddrLow,
3414 smum_send_msg_to_smc_with_parameter(hwmgr,
3415 PPSMC_MSG_DramLogSetDramAddrHigh,
3418 smum_send_msg_to_smc_with_parameter(hwmgr,
3419 PPSMC_MSG_DramLogSetDramAddrLow,
3422 smum_send_msg_to_smc_with_parameter(hwmgr,
3423 PPSMC_MSG_DramLogSetDramSize,
3428 static int vega20_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
3429 struct PP_TemperatureRange *thermal_data)
3431 struct phm_ppt_v3_information *pptable_information =
3432 (struct phm_ppt_v3_information *)hwmgr->pptable;
3434 memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
3436 thermal_data->max = pptable_information->us_software_shutdown_temp *
3437 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
3442 static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
3443 /* init/fini related */
3445 vega20_hwmgr_backend_init,
3447 vega20_hwmgr_backend_fini,
3449 vega20_setup_asic_task,
3451 vega20_power_off_asic,
3452 .dynamic_state_management_enable =
3453 vega20_enable_dpm_tasks,
3454 .dynamic_state_management_disable =
3455 vega20_disable_dpm_tasks,
3456 /* power state related */
3457 .apply_clocks_adjust_rules =
3458 vega20_apply_clocks_adjust_rules,
3459 .pre_display_config_changed =
3460 vega20_pre_display_configuration_changed_task,
3461 .display_config_changed =
3462 vega20_display_configuration_changed_task,
3463 .check_smc_update_required_for_display_configuration =
3464 vega20_check_smc_update_required_for_display_configuration,
3465 .notify_smc_display_config_after_ps_adjustment =
3466 vega20_notify_smc_display_config_after_ps_adjustment,
3469 vega20_dpm_get_sclk,
3471 vega20_dpm_get_mclk,
3472 .get_dal_power_level =
3473 vega20_get_dal_power_level,
3474 .get_clock_by_type_with_latency =
3475 vega20_get_clock_by_type_with_latency,
3476 .get_clock_by_type_with_voltage =
3477 vega20_get_clock_by_type_with_voltage,
3478 .set_watermarks_for_clocks_ranges =
3479 vega20_set_watermarks_for_clocks_ranges,
3480 .display_clock_voltage_request =
3481 vega20_display_clock_voltage_request,
3482 .get_performance_level =
3483 vega20_get_performance_level,
3484 /* UMD pstate, profile related */
3486 vega20_dpm_force_dpm_level,
3487 .get_power_profile_mode =
3488 vega20_get_power_profile_mode,
3489 .set_power_profile_mode =
3490 vega20_set_power_profile_mode,
3493 vega20_set_power_limit,
3502 .odn_edit_dpm_table =
3503 vega20_odn_edit_dpm_table,
3504 /* for sysfs to retrive/set gfxclk/memclk */
3505 .force_clock_level =
3506 vega20_force_clock_level,
3507 .print_clock_levels =
3508 vega20_print_clock_levels,
3511 /* powergate related */
3513 vega20_power_gate_uvd,
3515 vega20_power_gate_vce,
3516 /* thermal related */
3517 .start_thermal_controller =
3518 vega20_start_thermal_controller,
3519 .stop_thermal_controller =
3520 vega20_thermal_stop_thermal_controller,
3521 .get_thermal_temperature_range =
3522 vega20_get_thermal_temperature_range,
3523 .register_irq_handlers =
3524 smu9_register_irq_handlers,
3525 .disable_smc_firmware_ctf =
3526 vega20_thermal_disable_alert,
3527 /* fan control related */
3528 .get_fan_speed_percent =
3529 vega20_fan_ctrl_get_fan_speed_percent,
3530 .set_fan_speed_percent =
3531 vega20_fan_ctrl_set_fan_speed_percent,
3532 .get_fan_speed_info =
3533 vega20_fan_ctrl_get_fan_speed_info,
3534 .get_fan_speed_rpm =
3535 vega20_fan_ctrl_get_fan_speed_rpm,
3536 .set_fan_speed_rpm =
3537 vega20_fan_ctrl_set_fan_speed_rpm,
3538 .get_fan_control_mode =
3539 vega20_get_fan_control_mode,
3540 .set_fan_control_mode =
3541 vega20_set_fan_control_mode,
3542 /* smu memory related */
3543 .notify_cac_buffer_info =
3544 vega20_notify_cac_buffer_info,
3545 .enable_mgpu_fan_boost =
3546 vega20_enable_mgpu_fan_boost,
3549 int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
3551 hwmgr->hwmgr_func = &vega20_hwmgr_funcs;
3552 hwmgr->pptable_func = &vega20_pptable_funcs;