drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/fb.h>
  26 #include <linux/module.h>
  27 #include <linux/slab.h>
  28
  29 #include "hwmgr.h"
  30 #include "amd_powerplay.h"
  31 #include "vega12_smumgr.h"
  32 #include "hardwaremanager.h"
  33 #include "ppatomfwctrl.h"
  34 #include "atomfirmware.h"
  35 #include "cgs_common.h"
  36 #include "vega12_inc.h"
  37 #include "pppcielanes.h"
  38 #include "vega12_hwmgr.h"
  39 #include "vega12_processpptables.h"
  40 #include "vega12_pptable.h"
  41 #include "vega12_thermal.h"
  42 #include "vega12_ppsmc.h"
  43 #include "pp_debug.h"
  44 #include "amd_pcie_helpers.h"
  45 #include "ppinterrupt.h"
  46 #include "pp_overdriver.h"
  47 #include "pp_thermal.h"
  48
  49
  50 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
  51                 enum pp_clock_type type, uint32_t mask);
  52 static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr,
  53                 uint32_t *clock,
  54                 PPCLK_e clock_select,
  55                 bool max);
  56
  57 static void vega12_set_default_registry_data(struct pp_hwmgr *hwmgr)
  58 {
  59         struct vega12_hwmgr *data =
  60                         (struct vega12_hwmgr *)(hwmgr->backend);
  61
  62         data->gfxclk_average_alpha = PPVEGA12_VEGA12GFXCLKAVERAGEALPHA_DFLT;
  63         data->socclk_average_alpha = PPVEGA12_VEGA12SOCCLKAVERAGEALPHA_DFLT;
  64         data->uclk_average_alpha = PPVEGA12_VEGA12UCLKCLKAVERAGEALPHA_DFLT;
  65         data->gfx_activity_average_alpha = PPVEGA12_VEGA12GFXACTIVITYAVERAGEALPHA_DFLT;
  66         data->lowest_uclk_reserved_for_ulv = PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT;
  67
  68         data->display_voltage_mode = PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT;
  69         data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
  70         data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
  71         data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
  72         data->disp_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
  73         data->disp_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
  74         data->disp_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
  75         data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
  76         data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
  77         data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
  78         data->phy_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
  79         data->phy_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
  80         data->phy_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
  81
  82         data->registry_data.disallowed_features = 0x0;
  83         data->registry_data.od_state_in_dc_support = 0;
  84         data->registry_data.thermal_support = 1;
  85         data->registry_data.skip_baco_hardware = 0;
  86
  87         data->registry_data.log_avfs_param = 0;
  88         data->registry_data.sclk_throttle_low_notification = 1;
  89         data->registry_data.force_dpm_high = 0;
  90         data->registry_data.stable_pstate_sclk_dpm_percentage = 75;
  91
  92         data->registry_data.didt_support = 0;
  93         if (data->registry_data.didt_support) {
  94                 data->registry_data.didt_mode = 6;
  95                 data->registry_data.sq_ramping_support = 1;
  96                 data->registry_data.db_ramping_support = 0;
  97                 data->registry_data.td_ramping_support = 0;
  98                 data->registry_data.tcp_ramping_support = 0;
  99                 data->registry_data.dbr_ramping_support = 0;
 100                 data->registry_data.edc_didt_support = 1;
 101                 data->registry_data.gc_didt_support = 0;
 102                 data->registry_data.psm_didt_support = 0;
 103         }
 104
 105         data->registry_data.pcie_lane_override = 0xff;
 106         data->registry_data.pcie_speed_override = 0xff;
 107         data->registry_data.pcie_clock_override = 0xffffffff;
 108         data->registry_data.regulator_hot_gpio_support = 1;
 109         data->registry_data.ac_dc_switch_gpio_support = 0;
 110         data->registry_data.quick_transition_support = 0;
 111         data->registry_data.zrpm_start_temp = 0xffff;
 112         data->registry_data.zrpm_stop_temp = 0xffff;
 113         data->registry_data.odn_feature_enable = 1;
 114         data->registry_data.disable_water_mark = 0;
 115         data->registry_data.disable_pp_tuning = 0;
 116         data->registry_data.disable_xlpp_tuning = 0;
 117         data->registry_data.disable_workload_policy = 0;
 118         data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F;
 119         data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919;
 120         data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A;
 121         data->registry_data.force_workload_policy_mask = 0;
 122         data->registry_data.disable_3d_fs_detection = 0;
 123         data->registry_data.fps_support = 1;
 124         data->registry_data.disable_auto_wattman = 1;
 125         data->registry_data.auto_wattman_debug = 0;
 126         data->registry_data.auto_wattman_sample_period = 100;
 127         data->registry_data.auto_wattman_threshold = 50;
 128 }
 129
 130 static int vega12_set_features_platform_caps(struct pp_hwmgr *hwmgr)
 131 {
 132         struct vega12_hwmgr *data =
 133                         (struct vega12_hwmgr *)(hwmgr->backend);
 134         struct amdgpu_device *adev = hwmgr->adev;
 135
 136         if (data->vddci_control == VEGA12_VOLTAGE_CONTROL_NONE)
 137                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 138                                 PHM_PlatformCaps_ControlVDDCI);
 139
 140         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 141                         PHM_PlatformCaps_TablelessHardwareInterface);
 142
 143         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 144                         PHM_PlatformCaps_EnableSMU7ThermalManagement);
 145
 146         if (adev->pg_flags & AMD_PG_SUPPORT_UVD) {
 147                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 148                                 PHM_PlatformCaps_UVDPowerGating);
 149                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 150                                 PHM_PlatformCaps_UVDDynamicPowerGating);
 151         }
 152
 153         if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
 154                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 155                                 PHM_PlatformCaps_VCEPowerGating);
 156
 157         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 158                         PHM_PlatformCaps_UnTabledHardwareInterface);
 159
 160         if (data->registry_data.odn_feature_enable)
 161                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 162                                 PHM_PlatformCaps_ODNinACSupport);
 163         else {
 164                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 165                                 PHM_PlatformCaps_OD6inACSupport);
 166                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 167                                 PHM_PlatformCaps_OD6PlusinACSupport);
 168         }
 169
 170         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 171                         PHM_PlatformCaps_ActivityReporting);
 172         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 173                         PHM_PlatformCaps_FanSpeedInTableIsRPM);
 174
 175         if (data->registry_data.od_state_in_dc_support) {
 176                 if (data->registry_data.odn_feature_enable)
 177                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 178                                         PHM_PlatformCaps_ODNinDCSupport);
 179                 else {
 180                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 181                                         PHM_PlatformCaps_OD6inDCSupport);
 182                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 183                                         PHM_PlatformCaps_OD6PlusinDCSupport);
 184                 }
 185         }
 186
 187         if (data->registry_data.thermal_support
 188                         && data->registry_data.fuzzy_fan_control_support
 189                         && hwmgr->thermal_controller.advanceFanControlParameters.usTMax)
 190                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 191                                 PHM_PlatformCaps_ODFuzzyFanControlSupport);
 192
 193         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 194                                 PHM_PlatformCaps_DynamicPowerManagement);
 195         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 196                         PHM_PlatformCaps_SMC);
 197         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 198                         PHM_PlatformCaps_ThermalPolicyDelay);
 199
 200         if (data->registry_data.force_dpm_high)
 201                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 202                                 PHM_PlatformCaps_ExclusiveModeAlwaysHigh);
 203
 204         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 205                         PHM_PlatformCaps_DynamicUVDState);
 206
 207         if (data->registry_data.sclk_throttle_low_notification)
 208                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 209                                 PHM_PlatformCaps_SclkThrottleLowNotification);
 210
 211         /* power tune caps */
 212         /* assume disabled */
 213         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 214                         PHM_PlatformCaps_PowerContainment);
 215         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 216                         PHM_PlatformCaps_DiDtSupport);
 217         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 218                         PHM_PlatformCaps_SQRamping);
 219         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 220                         PHM_PlatformCaps_DBRamping);
 221         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 222                         PHM_PlatformCaps_TDRamping);
 223         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 224                         PHM_PlatformCaps_TCPRamping);
 225         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 226                         PHM_PlatformCaps_DBRRamping);
 227         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 228                         PHM_PlatformCaps_DiDtEDCEnable);
 229         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 230                         PHM_PlatformCaps_GCEDC);
 231         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 232                         PHM_PlatformCaps_PSM);
 233
 234         if (data->registry_data.didt_support) {
 235                 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport);
 236                 if (data->registry_data.sq_ramping_support)
 237                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping);
 238                 if (data->registry_data.db_ramping_support)
 239                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping);
 240                 if (data->registry_data.td_ramping_support)
 241                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping);
 242                 if (data->registry_data.tcp_ramping_support)
 243                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping);
 244                 if (data->registry_data.dbr_ramping_support)
 245                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping);
 246                 if (data->registry_data.edc_didt_support)
 247                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable);
 248                 if (data->registry_data.gc_didt_support)
 249                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC);
 250                 if (data->registry_data.psm_didt_support)
 251                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM);
 252         }
 253
 254         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 255                         PHM_PlatformCaps_RegulatorHot);
 256
 257         if (data->registry_data.ac_dc_switch_gpio_support) {
 258                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 259                                 PHM_PlatformCaps_AutomaticDCTransition);
 260                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 261                                 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
 262         }
 263
 264         if (data->registry_data.quick_transition_support) {
 265                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 266                                 PHM_PlatformCaps_AutomaticDCTransition);
 267                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 268                                 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
 269                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 270                                 PHM_PlatformCaps_Falcon_QuickTransition);
 271         }
 272
 273         if (data->lowest_uclk_reserved_for_ulv != PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT) {
 274                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 275                                 PHM_PlatformCaps_LowestUclkReservedForUlv);
 276                 if (data->lowest_uclk_reserved_for_ulv == 1)
 277                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 278                                         PHM_PlatformCaps_LowestUclkReservedForUlv);
 279         }
 280
 281         if (data->registry_data.custom_fan_support)
 282                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 283                                 PHM_PlatformCaps_CustomFanControlSupport);
 284
 285         return 0;
 286 }
 287
 288 static void vega12_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 289 {
 290         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
 291         int i;
 292
 293         data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
 294                         FEATURE_DPM_PREFETCHER_BIT;
 295         data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
 296                         FEATURE_DPM_GFXCLK_BIT;
 297         data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
 298                         FEATURE_DPM_UCLK_BIT;
 299         data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
 300                         FEATURE_DPM_SOCCLK_BIT;
 301         data->smu_features[GNLD_DPM_UVD].smu_feature_id =
 302                         FEATURE_DPM_UVD_BIT;
 303         data->smu_features[GNLD_DPM_VCE].smu_feature_id =
 304                         FEATURE_DPM_VCE_BIT;
 305         data->smu_features[GNLD_ULV].smu_feature_id =
 306                         FEATURE_ULV_BIT;
 307         data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
 308                         FEATURE_DPM_MP0CLK_BIT;
 309         data->smu_features[GNLD_DPM_LINK].smu_feature_id =
 310                         FEATURE_DPM_LINK_BIT;
 311         data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
 312                         FEATURE_DPM_DCEFCLK_BIT;
 313         data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
 314                         FEATURE_DS_GFXCLK_BIT;
 315         data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
 316                         FEATURE_DS_SOCCLK_BIT;
 317         data->smu_features[GNLD_DS_LCLK].smu_feature_id =
 318                         FEATURE_DS_LCLK_BIT;
 319         data->smu_features[GNLD_PPT].smu_feature_id =
 320                         FEATURE_PPT_BIT;
 321         data->smu_features[GNLD_TDC].smu_feature_id =
 322                         FEATURE_TDC_BIT;
 323         data->smu_features[GNLD_THERMAL].smu_feature_id =
 324                         FEATURE_THERMAL_BIT;
 325         data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
 326                         FEATURE_GFX_PER_CU_CG_BIT;
 327         data->smu_features[GNLD_RM].smu_feature_id =
 328                         FEATURE_RM_BIT;
 329         data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
 330                         FEATURE_DS_DCEFCLK_BIT;
 331         data->smu_features[GNLD_ACDC].smu_feature_id =
 332                         FEATURE_ACDC_BIT;
 333         data->smu_features[GNLD_VR0HOT].smu_feature_id =
 334                         FEATURE_VR0HOT_BIT;
 335         data->smu_features[GNLD_VR1HOT].smu_feature_id =
 336                         FEATURE_VR1HOT_BIT;
 337         data->smu_features[GNLD_FW_CTF].smu_feature_id =
 338                         FEATURE_FW_CTF_BIT;
 339         data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
 340                         FEATURE_LED_DISPLAY_BIT;
 341         data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
 342                         FEATURE_FAN_CONTROL_BIT;
 343         data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
 344         data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT;
 345         data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT;
 346         data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT;
 347
 348         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 349                 data->smu_features[i].smu_feature_bitmap =
 350                         (uint64_t)(1ULL << data->smu_features[i].smu_feature_id);
 351                 data->smu_features[i].allowed =
 352                         ((data->registry_data.disallowed_features >> i) & 1) ?
 353                         false : true;
 354         }
 355 }
 356
 357 static int vega12_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
 358 {
 359         return 0;
 360 }
 361
 362 static int vega12_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 363 {
 364         kfree(hwmgr->backend);
 365         hwmgr->backend = NULL;
 366
 367         return 0;
 368 }
 369
 370 static int vega12_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 371 {
 372         int result = 0;
 373         struct vega12_hwmgr *data;
 374         struct amdgpu_device *adev = hwmgr->adev;
 375
 376         data = kzalloc(sizeof(struct vega12_hwmgr), GFP_KERNEL);
 377         if (data == NULL)
 378                 return -ENOMEM;
 379
 380         hwmgr->backend = data;
 381
 382         vega12_set_default_registry_data(hwmgr);
 383
 384         data->disable_dpm_mask = 0xff;
 385         data->workload_mask = 0xff;
 386
 387         /* need to set voltage control types before EVV patching */
 388         data->vddc_control = VEGA12_VOLTAGE_CONTROL_NONE;
 389         data->mvdd_control = VEGA12_VOLTAGE_CONTROL_NONE;
 390         data->vddci_control = VEGA12_VOLTAGE_CONTROL_NONE;
 391
 392         data->water_marks_bitmap = 0;
 393         data->avfs_exist = false;
 394
 395         vega12_set_features_platform_caps(hwmgr);
 396
 397         vega12_init_dpm_defaults(hwmgr);
 398
 399         /* Parse pptable data read from VBIOS */
 400         vega12_set_private_data_based_on_pptable(hwmgr);
 401
 402         data->is_tlu_enabled = false;
 403
 404         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
 405                         VEGA12_MAX_HARDWARE_POWERLEVELS;
 406         hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
 407         hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
 408
 409         hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
 410         /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
 411         hwmgr->platform_descriptor.clockStep.engineClock = 500;
 412         hwmgr->platform_descriptor.clockStep.memoryClock = 500;
 413
 414         data->total_active_cus = adev->gfx.cu_info.number;
 415         /* Setup default Overdrive Fan control settings */
 416         data->odn_fan_table.target_fan_speed =
 417                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;
 418         data->odn_fan_table.target_temperature =
 419                         hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature;
 420         data->odn_fan_table.min_performance_clock =
 421                         hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit;
 422         data->odn_fan_table.min_fan_limit =
 423                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit *
 424                         hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
 425
 426         if (hwmgr->feature_mask & PP_GFXOFF_MASK)
 427                 data->gfxoff_controlled_by_driver = true;
 428         else
 429                 data->gfxoff_controlled_by_driver = false;
 430
 431         return result;
 432 }
 433
 434 static int vega12_init_sclk_threshold(struct pp_hwmgr *hwmgr)
 435 {
 436         struct vega12_hwmgr *data =
 437                         (struct vega12_hwmgr *)(hwmgr->backend);
 438
 439         data->low_sclk_interrupt_threshold = 0;
 440
 441         return 0;
 442 }
 443
 444 static int vega12_setup_asic_task(struct pp_hwmgr *hwmgr)
 445 {
 446         PP_ASSERT_WITH_CODE(!vega12_init_sclk_threshold(hwmgr),
 447                         "Failed to init sclk threshold!",
 448                         return -EINVAL);
 449
 450         return 0;
 451 }
 452
 453 /*
 454  * @fn vega12_init_dpm_state
 455  * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
 456  *
 457  * @param    dpm_state - the address of the DPM Table to initiailize.
 458  * @return   None.
 459  */
 460 static void vega12_init_dpm_state(struct vega12_dpm_state *dpm_state)
 461 {
 462         dpm_state->soft_min_level = 0x0;
 463         dpm_state->soft_max_level = 0xffff;
 464         dpm_state->hard_min_level = 0x0;
 465         dpm_state->hard_max_level = 0xffff;
 466 }
 467
 468 static int vega12_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
 469                 PPCLK_e clk_id, uint32_t *num_of_levels)
 470 {
 471         int ret = 0;
 472
 473         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 474                         PPSMC_MSG_GetDpmFreqByIndex,
 475                         (clk_id << 16 | 0xFF));
 476         PP_ASSERT_WITH_CODE(!ret,
 477                         "[GetNumOfDpmLevel] failed to get dpm levels!",
 478                         return ret);
 479
 480         *num_of_levels = smum_get_argument(hwmgr);
 481         PP_ASSERT_WITH_CODE(*num_of_levels > 0,
 482                         "[GetNumOfDpmLevel] number of clk levels is invalid!",
 483                         return -EINVAL);
 484
 485         return ret;
 486 }
 487
 488 static int vega12_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
 489                 PPCLK_e clkID, uint32_t index, uint32_t *clock)
 490 {
 491         int result = 0;
 492
 493         /*
 494          *SMU expects the Clock ID to be in the top 16 bits.
 495          *Lower 16 bits specify the level
 496          */
 497         PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
 498                 PPSMC_MSG_GetDpmFreqByIndex, (clkID << 16 | index)) == 0,
 499                 "[GetDpmFrequencyByIndex] Failed to get dpm frequency from SMU!",
 500                 return -EINVAL);
 501
 502         *clock = smum_get_argument(hwmgr);
 503
 504         return result;
 505 }
 506
 507 static int vega12_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
 508                 struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id)
 509 {
 510         int ret = 0;
 511         uint32_t i, num_of_levels, clk;
 512
 513         ret = vega12_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
 514         PP_ASSERT_WITH_CODE(!ret,
 515                         "[SetupSingleDpmTable] failed to get clk levels!",
 516                         return ret);
 517
 518         dpm_table->count = num_of_levels;
 519
 520         for (i = 0; i < num_of_levels; i++) {
 521                 ret = vega12_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);
 522                 PP_ASSERT_WITH_CODE(!ret,
 523                         "[SetupSingleDpmTable] failed to get clk of specific level!",
 524                         return ret);
 525                 dpm_table->dpm_levels[i].value = clk;
 526                 dpm_table->dpm_levels[i].enabled = true;
 527         }
 528
 529         return ret;
 530 }
 531
 532 /*
 533  * This function is to initialize all DPM state tables
 534  * for SMU based on the dependency table.
 535  * Dynamic state patching function will then trim these
 536  * state tables to the allowed range based
 537  * on the power policy or external client requests,
 538  * such as UVD request, etc.
 539  */
 540 static int vega12_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 541 {
 542
 543         struct vega12_hwmgr *data =
 544                         (struct vega12_hwmgr *)(hwmgr->backend);
 545         struct vega12_single_dpm_table *dpm_table;
 546         int ret = 0;
 547
 548         memset(&data->dpm_table, 0, sizeof(data->dpm_table));
 549
 550         /* socclk */
 551         dpm_table = &(data->dpm_table.soc_table);
 552         if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
 553                 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK);
 554                 PP_ASSERT_WITH_CODE(!ret,
 555                                 "[SetupDefaultDpmTable] failed to get socclk dpm levels!",
 556                                 return ret);
 557         } else {
 558                 dpm_table->count = 1;
 559                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100;
 560         }
 561         vega12_init_dpm_state(&(dpm_table->dpm_state));
 562
 563         /* gfxclk */
 564         dpm_table = &(data->dpm_table.gfx_table);
 565         if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
 566                 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
 567                 PP_ASSERT_WITH_CODE(!ret,
 568                                 "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!",
 569                                 return ret);
 570         } else {
 571                 dpm_table->count = 1;
 572                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100;
 573         }
 574         vega12_init_dpm_state(&(dpm_table->dpm_state));
 575
 576         /* memclk */
 577         dpm_table = &(data->dpm_table.mem_table);
 578         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
 579                 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
 580                 PP_ASSERT_WITH_CODE(!ret,
 581                                 "[SetupDefaultDpmTable] failed to get memclk dpm levels!",
 582                                 return ret);
 583         } else {
 584                 dpm_table->count = 1;
 585                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100;
 586         }
 587         vega12_init_dpm_state(&(dpm_table->dpm_state));
 588
 589         /* eclk */
 590         dpm_table = &(data->dpm_table.eclk_table);
 591         if (data->smu_features[GNLD_DPM_VCE].enabled) {
 592                 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK);
 593                 PP_ASSERT_WITH_CODE(!ret,
 594                                 "[SetupDefaultDpmTable] failed to get eclk dpm levels!",
 595                                 return ret);
 596         } else {
 597                 dpm_table->count = 1;
 598                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100;
 599         }
 600         vega12_init_dpm_state(&(dpm_table->dpm_state));
 601
 602         /* vclk */
 603         dpm_table = &(data->dpm_table.vclk_table);
 604         if (data->smu_features[GNLD_DPM_UVD].enabled) {
 605                 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
 606                 PP_ASSERT_WITH_CODE(!ret,
 607                                 "[SetupDefaultDpmTable] failed to get vclk dpm levels!",
 608                                 return ret);
 609         } else {
 610                 dpm_table->count = 1;
 611                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100;
 612         }
 613         vega12_init_dpm_state(&(dpm_table->dpm_state));
 614
 615         /* dclk */
 616         dpm_table = &(data->dpm_table.dclk_table);
 617         if (data->smu_features[GNLD_DPM_UVD].enabled) {
 618                 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK);
 619                 PP_ASSERT_WITH_CODE(!ret,
 620                                 "[SetupDefaultDpmTable] failed to get dclk dpm levels!",
 621                                 return ret);
 622         } else {
 623                 dpm_table->count = 1;
 624                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100;
 625         }
 626         vega12_init_dpm_state(&(dpm_table->dpm_state));
 627
 628         /* dcefclk */
 629         dpm_table = &(data->dpm_table.dcef_table);
 630         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 631                 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK);
 632                 PP_ASSERT_WITH_CODE(!ret,
 633                                 "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!",
 634                                 return ret);
 635         } else {
 636                 dpm_table->count = 1;
 637                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100;
 638         }
 639         vega12_init_dpm_state(&(dpm_table->dpm_state));
 640
 641         /* pixclk */
 642         dpm_table = &(data->dpm_table.pixel_table);
 643         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 644                 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK);
 645                 PP_ASSERT_WITH_CODE(!ret,
 646                                 "[SetupDefaultDpmTable] failed to get pixclk dpm levels!",
 647                                 return ret);
 648         } else
 649                 dpm_table->count = 0;
 650         vega12_init_dpm_state(&(dpm_table->dpm_state));
 651
 652         /* dispclk */
 653         dpm_table = &(data->dpm_table.display_table);
 654         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 655                 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
 656                 PP_ASSERT_WITH_CODE(!ret,
 657                                 "[SetupDefaultDpmTable] failed to get dispclk dpm levels!",
 658                                 return ret);
 659         } else
 660                 dpm_table->count = 0;
 661         vega12_init_dpm_state(&(dpm_table->dpm_state));
 662
 663         /* phyclk */
 664         dpm_table = &(data->dpm_table.phy_table);
 665         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 666                 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
 667                 PP_ASSERT_WITH_CODE(!ret,
 668                                 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!",
 669                                 return ret);
 670         } else
 671                 dpm_table->count = 0;
 672         vega12_init_dpm_state(&(dpm_table->dpm_state));
 673
 674         /* save a copy of the default DPM table */
 675         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
 676                         sizeof(struct vega12_dpm_table));
 677
 678         return 0;
 679 }
 680
 681 #if 0
 682 static int vega12_save_default_power_profile(struct pp_hwmgr *hwmgr)
 683 {
 684         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
 685         struct vega12_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
 686         uint32_t min_level;
 687
 688         hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
 689         hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
 690
 691         /* Optimize compute power profile: Use only highest
 692          * 2 power levels (if more than 2 are available)
 693          */
 694         if (dpm_table->count > 2)
 695                 min_level = dpm_table->count - 2;
 696         else if (dpm_table->count == 2)
 697                 min_level = 1;
 698         else
 699                 min_level = 0;
 700
 701         hwmgr->default_compute_power_profile.min_sclk =
 702                         dpm_table->dpm_levels[min_level].value;
 703
 704         hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
 705         hwmgr->compute_power_profile = hwmgr->default_compute_power_profile;
 706
 707         return 0;
 708 }
 709 #endif
 710
 711 /**
 712 * Initializes the SMC table and uploads it
 713 *
 714 * @param    hwmgr  the address of the powerplay hardware manager.
 715 * @param    pInput  the pointer to input data (PowerState)
 716 * @return   always 0
 717 */
 718 static int vega12_init_smc_table(struct pp_hwmgr *hwmgr)
 719 {
 720         int result;
 721         struct vega12_hwmgr *data =
 722                         (struct vega12_hwmgr *)(hwmgr->backend);
 723         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
 724         struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
 725         struct phm_ppt_v3_information *pptable_information =
 726                 (struct phm_ppt_v3_information *)hwmgr->pptable;
 727
 728         result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
 729         if (!result) {
 730                 data->vbios_boot_state.vddc     = boot_up_values.usVddc;
 731                 data->vbios_boot_state.vddci    = boot_up_values.usVddci;
 732                 data->vbios_boot_state.mvddc    = boot_up_values.usMvddc;
 733                 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
 734                 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
 735                 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
 736                 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
 737                 data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID;
 738                 data->vbios_boot_state.eclock = boot_up_values.ulEClk;
 739                 data->vbios_boot_state.dclock = boot_up_values.ulDClk;
 740                 data->vbios_boot_state.vclock = boot_up_values.ulVClk;
 741                 smum_send_msg_to_smc_with_parameter(hwmgr,
 742                                 PPSMC_MSG_SetMinDeepSleepDcefclk,
 743                         (uint32_t)(data->vbios_boot_state.dcef_clock / 100));
 744         }
 745
 746         memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
 747
 748         result = smum_smc_table_manager(hwmgr,
 749                                         (uint8_t *)pp_table, TABLE_PPTABLE, false);
 750         PP_ASSERT_WITH_CODE(!result,
 751                         "Failed to upload PPtable!", return result);
 752
 753         return 0;
 754 }
 755
 756 static int vega12_run_acg_btc(struct pp_hwmgr *hwmgr)
 757 {
 758         uint32_t result;
 759
 760         PP_ASSERT_WITH_CODE(
 761                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc) == 0,
 762                 "[Run_ACG_BTC] Attempt to run ACG BTC failed!",
 763                 return -EINVAL);
 764
 765         result = smum_get_argument(hwmgr);
 766         PP_ASSERT_WITH_CODE(result == 1,
 767                         "Failed to run ACG BTC!", return -EINVAL);
 768
 769         return 0;
 770 }
 771
 772 static int vega12_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
 773 {
 774         struct vega12_hwmgr *data =
 775                         (struct vega12_hwmgr *)(hwmgr->backend);
 776         int i;
 777         uint32_t allowed_features_low = 0, allowed_features_high = 0;
 778
 779         for (i = 0; i < GNLD_FEATURES_MAX; i++)
 780                 if (data->smu_features[i].allowed)
 781                         data->smu_features[i].smu_feature_id > 31 ?
 782                                 (allowed_features_high |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT) & 0xFFFFFFFF)) :
 783                                 (allowed_features_low |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT) & 0xFFFFFFFF));
 784
 785         PP_ASSERT_WITH_CODE(
 786                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high) == 0,
 787                 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (high) failed!",
 788                 return -1);
 789
 790         PP_ASSERT_WITH_CODE(
 791                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low) == 0,
 792                 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!",
 793                 return -1);
 794
 795         return 0;
 796 }
 797
 798 static void vega12_init_powergate_state(struct pp_hwmgr *hwmgr)
 799 {
 800         struct vega12_hwmgr *data =
 801                         (struct vega12_hwmgr *)(hwmgr->backend);
 802
 803         data->uvd_power_gated = true;
 804         data->vce_power_gated = true;
 805
 806         if (data->smu_features[GNLD_DPM_UVD].enabled)
 807                 data->uvd_power_gated = false;
 808
 809         if (data->smu_features[GNLD_DPM_VCE].enabled)
 810                 data->vce_power_gated = false;
 811 }
 812
 813 static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr)
 814 {
 815         struct vega12_hwmgr *data =
 816                         (struct vega12_hwmgr *)(hwmgr->backend);
 817         uint64_t features_enabled;
 818         int i;
 819         bool enabled;
 820
 821         PP_ASSERT_WITH_CODE(
 822                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAllSmuFeatures) == 0,
 823                 "[EnableAllSMUFeatures] Failed to enable all smu features!",
 824                 return -1);
 825
 826         if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) {
 827                 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 828                         enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false;
 829                         data->smu_features[i].enabled = enabled;
 830                         data->smu_features[i].supported = enabled;
 831                 }
 832         }
 833
 834         vega12_init_powergate_state(hwmgr);
 835
 836         return 0;
 837 }
 838
 839 static int vega12_disable_all_smu_features(struct pp_hwmgr *hwmgr)
 840 {
 841         struct vega12_hwmgr *data =
 842                         (struct vega12_hwmgr *)(hwmgr->backend);
 843         uint64_t features_enabled;
 844         int i;
 845         bool enabled;
 846
 847         PP_ASSERT_WITH_CODE(
 848                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableAllSmuFeatures) == 0,
 849                 "[DisableAllSMUFeatures] Failed to disable all smu features!",
 850                 return -1);
 851
 852         if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) {
 853                 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 854                         enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false;
 855                         data->smu_features[i].enabled = enabled;
 856                         data->smu_features[i].supported = enabled;
 857                 }
 858         }
 859
 860         return 0;
 861 }
 862
 863 static int vega12_odn_initialize_default_settings(
 864                 struct pp_hwmgr *hwmgr)
 865 {
 866         return 0;
 867 }
 868
 869 static int vega12_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
 870                 uint32_t adjust_percent)
 871 {
 872         return smum_send_msg_to_smc_with_parameter(hwmgr,
 873                         PPSMC_MSG_OverDriveSetPercentage, adjust_percent);
 874 }
 875
 876 static int vega12_power_control_set_level(struct pp_hwmgr *hwmgr)
 877 {
 878         int adjust_percent, result = 0;
 879
 880         if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
 881                 adjust_percent =
 882                                 hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
 883                                 hwmgr->platform_descriptor.TDPAdjustment :
 884                                 (-1 * hwmgr->platform_descriptor.TDPAdjustment);
 885                 result = vega12_set_overdrive_target_percentage(hwmgr,
 886                                 (uint32_t)adjust_percent);
 887         }
 888         return result;
 889 }
 890
 891 static int vega12_get_all_clock_ranges_helper(struct pp_hwmgr *hwmgr,
 892                 PPCLK_e clkid, struct vega12_clock_range *clock)
 893 {
 894         /* AC Max */
 895         PP_ASSERT_WITH_CODE(
 896                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMaxDpmFreq, (clkid << 16)) == 0,
 897                 "[GetClockRanges] Failed to get max ac clock from SMC!",
 898                 return -EINVAL);
 899         clock->ACMax = smum_get_argument(hwmgr);
 900
 901         /* AC Min */
 902         PP_ASSERT_WITH_CODE(
 903                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMinDpmFreq, (clkid << 16)) == 0,
 904                 "[GetClockRanges] Failed to get min ac clock from SMC!",
 905                 return -EINVAL);
 906         clock->ACMin = smum_get_argument(hwmgr);
 907
 908         /* DC Max */
 909         PP_ASSERT_WITH_CODE(
 910                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDcModeMaxDpmFreq, (clkid << 16)) == 0,
 911                 "[GetClockRanges] Failed to get max dc clock from SMC!",
 912                 return -EINVAL);
 913         clock->DCMax = smum_get_argument(hwmgr);
 914
 915         return 0;
 916 }
 917
 918 static int vega12_get_all_clock_ranges(struct pp_hwmgr *hwmgr)
 919 {
 920         struct vega12_hwmgr *data =
 921                         (struct vega12_hwmgr *)(hwmgr->backend);
 922         uint32_t i;
 923
 924         for (i = 0; i < PPCLK_COUNT; i++)
 925                 PP_ASSERT_WITH_CODE(!vega12_get_all_clock_ranges_helper(hwmgr,
 926                                         i, &(data->clk_range[i])),
 927                                 "Failed to get clk range from SMC!",
 928                                 return -EINVAL);
 929
 930         return 0;
 931 }
 932
 933 static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
 934 {
 935         int tmp_result, result = 0;
 936
 937         smum_send_msg_to_smc_with_parameter(hwmgr,
 938                         PPSMC_MSG_NumOfDisplays, 0);
 939
 940         result = vega12_set_allowed_featuresmask(hwmgr);
 941         PP_ASSERT_WITH_CODE(result == 0,
 942                         "[EnableDPMTasks] Failed to set allowed featuresmask!\n",
 943                         return result);
 944
 945         tmp_result = vega12_init_smc_table(hwmgr);
 946         PP_ASSERT_WITH_CODE(!tmp_result,
 947                         "Failed to initialize SMC table!",
 948                         result = tmp_result);
 949
 950         tmp_result = vega12_run_acg_btc(hwmgr);
 951         PP_ASSERT_WITH_CODE(!tmp_result,
 952                         "Failed to run ACG BTC!",
 953                         result = tmp_result);
 954
 955         result = vega12_enable_all_smu_features(hwmgr);
 956         PP_ASSERT_WITH_CODE(!result,
 957                         "Failed to enable all smu features!",
 958                         return result);
 959
 960         tmp_result = vega12_power_control_set_level(hwmgr);
 961         PP_ASSERT_WITH_CODE(!tmp_result,
 962                         "Failed to power control set level!",
 963                         result = tmp_result);
 964
 965         result = vega12_get_all_clock_ranges(hwmgr);
 966         PP_ASSERT_WITH_CODE(!result,
 967                         "Failed to get all clock ranges!",
 968                         return result);
 969
 970         result = vega12_odn_initialize_default_settings(hwmgr);
 971         PP_ASSERT_WITH_CODE(!result,
 972                         "Failed to power control set level!",
 973                         return result);
 974
 975         result = vega12_setup_default_dpm_tables(hwmgr);
 976         PP_ASSERT_WITH_CODE(!result,
 977                         "Failed to setup default DPM tables!",
 978                         return result);
 979         return result;
 980 }
 981
 982 static int vega12_patch_boot_state(struct pp_hwmgr *hwmgr,
 983              struct pp_hw_power_state *hw_ps)
 984 {
 985         return 0;
 986 }
 987
 988 static uint32_t vega12_find_lowest_dpm_level(
 989                 struct vega12_single_dpm_table *table)
 990 {
 991         uint32_t i;
 992
 993         for (i = 0; i < table->count; i++) {
 994                 if (table->dpm_levels[i].enabled)
 995                         break;
 996         }
 997
 998         if (i >= table->count) {
 999                 i = 0;
1000                 table->dpm_levels[i].enabled = true;
1001         }
1002
1003         return i;
1004 }
1005
1006 static uint32_t vega12_find_highest_dpm_level(
1007                 struct vega12_single_dpm_table *table)
1008 {
1009         int32_t i = 0;
1010         PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
1011                         "[FindHighestDPMLevel] DPM Table has too many entries!",
1012                         return MAX_REGULAR_DPM_NUMBER - 1);
1013
1014         for (i = table->count - 1; i >= 0; i--) {
1015                 if (table->dpm_levels[i].enabled)
1016                         break;
1017         }
1018
1019         if (i < 0) {
1020                 i = 0;
1021                 table->dpm_levels[i].enabled = true;
1022         }
1023
1024         return (uint32_t)i;
1025 }
1026
1027 static int vega12_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
1028 {
1029         struct vega12_hwmgr *data = hwmgr->backend;
1030         uint32_t min_freq;
1031         int ret = 0;
1032
1033         if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1034                 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
1035                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1036                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1037                                         (PPCLK_GFXCLK << 16) | (min_freq & 0xffff))),
1038                                         "Failed to set soft min gfxclk !",
1039                                         return ret);
1040         }
1041
1042         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1043                 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
1044                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1045                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1046                                         (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
1047                                         "Failed to set soft min memclk !",
1048                                         return ret);
1049
1050                 min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level;
1051                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1052                                         hwmgr, PPSMC_MSG_SetHardMinByFreq,
1053                                         (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
1054                                         "Failed to set hard min memclk !",
1055                                         return ret);
1056         }
1057
1058         if (data->smu_features[GNLD_DPM_UVD].enabled) {
1059                 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
1060
1061                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1062                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1063                                         (PPCLK_VCLK << 16) | (min_freq & 0xffff))),
1064                                         "Failed to set soft min vclk!",
1065                                         return ret);
1066
1067                 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level;
1068
1069                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1070                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1071                                         (PPCLK_DCLK << 16) | (min_freq & 0xffff))),
1072                                         "Failed to set soft min dclk!",
1073                                         return ret);
1074         }
1075
1076         if (data->smu_features[GNLD_DPM_VCE].enabled) {
1077                 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
1078
1079                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1080                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1081                                         (PPCLK_ECLK << 16) | (min_freq & 0xffff))),
1082                                         "Failed to set soft min eclk!",
1083                                         return ret);
1084         }
1085
1086         if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
1087                 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
1088
1089                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1090                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1091                                         (PPCLK_SOCCLK << 16) | (min_freq & 0xffff))),
1092                                         "Failed to set soft min socclk!",
1093                                         return ret);
1094         }
1095
1096         return ret;
1097
1098 }
1099
1100 static int vega12_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
1101 {
1102         struct vega12_hwmgr *data = hwmgr->backend;
1103         uint32_t max_freq;
1104         int ret = 0;
1105
1106         if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1107                 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
1108
1109                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1110                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1111                                         (PPCLK_GFXCLK << 16) | (max_freq & 0xffff))),
1112                                         "Failed to set soft max gfxclk!",
1113                                         return ret);
1114         }
1115
1116         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1117                 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
1118
1119                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1120                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1121                                         (PPCLK_UCLK << 16) | (max_freq & 0xffff))),
1122                                         "Failed to set soft max memclk!",
1123                                         return ret);
1124         }
1125
1126         if (data->smu_features[GNLD_DPM_UVD].enabled) {
1127                 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
1128
1129                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1130                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1131                                         (PPCLK_VCLK << 16) | (max_freq & 0xffff))),
1132                                         "Failed to set soft max vclk!",
1133                                         return ret);
1134
1135                 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level;
1136                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1137                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1138                                         (PPCLK_DCLK << 16) | (max_freq & 0xffff))),
1139                                         "Failed to set soft max dclk!",
1140                                         return ret);
1141         }
1142
1143         if (data->smu_features[GNLD_DPM_VCE].enabled) {
1144                 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
1145
1146                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1147                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1148                                         (PPCLK_ECLK << 16) | (max_freq & 0xffff))),
1149                                         "Failed to set soft max eclk!",
1150                                         return ret);
1151         }
1152
1153         if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
1154                 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
1155
1156                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1157                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1158                                         (PPCLK_SOCCLK << 16) | (max_freq & 0xffff))),
1159                                         "Failed to set soft max socclk!",
1160                                         return ret);
1161         }
1162
1163         return ret;
1164 }
1165
1166 int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
1167 {
1168         struct vega12_hwmgr *data =
1169                         (struct vega12_hwmgr *)(hwmgr->backend);
1170
1171         if (data->smu_features[GNLD_DPM_VCE].supported) {
1172                 PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,
1173                                 enable,
1174                                 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap),
1175                                 "Attempt to Enable/Disable DPM VCE Failed!",
1176                                 return -1);
1177                 data->smu_features[GNLD_DPM_VCE].enabled = enable;
1178         }
1179
1180         return 0;
1181 }
1182
1183 static uint32_t vega12_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1184 {
1185         struct vega12_hwmgr *data =
1186                         (struct vega12_hwmgr *)(hwmgr->backend);
1187         uint32_t gfx_clk;
1188
1189         if (!data->smu_features[GNLD_DPM_GFXCLK].enabled)
1190                 return -1;
1191
1192         if (low)
1193                 PP_ASSERT_WITH_CODE(
1194                         vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false) == 0,
1195                         "[GetSclks]: fail to get min PPCLK_GFXCLK\n",
1196                         return -1);
1197         else
1198                 PP_ASSERT_WITH_CODE(
1199                         vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true) == 0,
1200                         "[GetSclks]: fail to get max PPCLK_GFXCLK\n",
1201                         return -1);
1202
1203         return (gfx_clk * 100);
1204 }
1205
1206 static uint32_t vega12_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1207 {
1208         struct vega12_hwmgr *data =
1209                         (struct vega12_hwmgr *)(hwmgr->backend);
1210         uint32_t mem_clk;
1211
1212         if (!data->smu_features[GNLD_DPM_UCLK].enabled)
1213                 return -1;
1214
1215         if (low)
1216                 PP_ASSERT_WITH_CODE(
1217                         vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false) == 0,
1218                         "[GetMclks]: fail to get min PPCLK_UCLK\n",
1219                         return -1);
1220         else
1221                 PP_ASSERT_WITH_CODE(
1222                         vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true) == 0,
1223                         "[GetMclks]: fail to get max PPCLK_UCLK\n",
1224                         return -1);
1225
1226         return (mem_clk * 100);
1227 }
1228
1229 static int vega12_get_gpu_power(struct pp_hwmgr *hwmgr, uint32_t *query)
1230 {
1231 #if 0
1232         uint32_t value;
1233
1234         PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
1235                         PPSMC_MSG_GetCurrPkgPwr),
1236                         "Failed to get current package power!",
1237                         return -EINVAL);
1238
1239         value = smum_get_argument(hwmgr);
1240         /* power value is an integer */
1241         *query = value << 8;
1242 #endif
1243         return 0;
1244 }
1245
1246 static int vega12_get_current_gfx_clk_freq(struct pp_hwmgr *hwmgr, uint32_t *gfx_freq)
1247 {
1248         uint32_t gfx_clk = 0;
1249
1250         *gfx_freq = 0;
1251
1252         PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
1253                         PPSMC_MSG_GetDpmClockFreq, (PPCLK_GFXCLK << 16)) == 0,
1254                         "[GetCurrentGfxClkFreq] Attempt to get Current GFXCLK Frequency Failed!",
1255                         return -EINVAL);
1256         gfx_clk = smum_get_argument(hwmgr);
1257
1258         *gfx_freq = gfx_clk * 100;
1259
1260         return 0;
1261 }
1262
1263 static int vega12_get_current_mclk_freq(struct pp_hwmgr *hwmgr, uint32_t *mclk_freq)
1264 {
1265         uint32_t mem_clk = 0;
1266
1267         *mclk_freq = 0;
1268
1269         PP_ASSERT_WITH_CODE(
1270                         smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDpmClockFreq, (PPCLK_UCLK << 16)) == 0,
1271                         "[GetCurrentMClkFreq] Attempt to get Current MCLK Frequency Failed!",
1272                         return -EINVAL);
1273         mem_clk = smum_get_argument(hwmgr);
1274
1275         *mclk_freq = mem_clk * 100;
1276
1277         return 0;
1278 }
1279
1280 static int vega12_get_current_activity_percent(
1281                 struct pp_hwmgr *hwmgr,
1282                 uint32_t *activity_percent)
1283 {
1284         int ret = 0;
1285         uint32_t current_activity = 50;
1286
1287 #if 0
1288         ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0);
1289         if (!ret) {
1290                 current_activity = smum_get_argument(hwmgr);
1291                 if (current_activity > 100) {
1292                         PP_ASSERT(false,
1293                                   "[GetCurrentActivityPercent] Activity Percentage Exceeds 100!");
1294                         current_activity = 100;
1295                 }
1296         } else
1297                 PP_ASSERT(false,
1298                         "[GetCurrentActivityPercent] Attempt To Send Get Average Graphics Activity to SMU Failed!");
1299 #endif
1300         *activity_percent = current_activity;
1301
1302         return ret;
1303 }
1304
1305 static int vega12_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1306                               void *value, int *size)
1307 {
1308         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1309         int ret = 0;
1310
1311         switch (idx) {
1312         case AMDGPU_PP_SENSOR_GFX_SCLK:
1313                 ret = vega12_get_current_gfx_clk_freq(hwmgr, (uint32_t *)value);
1314                 if (!ret)
1315                         *size = 4;
1316                 break;
1317         case AMDGPU_PP_SENSOR_GFX_MCLK:
1318                 ret = vega12_get_current_mclk_freq(hwmgr, (uint32_t *)value);
1319                 if (!ret)
1320                         *size = 4;
1321                 break;
1322         case AMDGPU_PP_SENSOR_GPU_LOAD:
1323                 ret = vega12_get_current_activity_percent(hwmgr, (uint32_t *)value);
1324                 if (!ret)
1325                         *size = 4;
1326                 break;
1327         case AMDGPU_PP_SENSOR_GPU_TEMP:
1328                 *((uint32_t *)value) = vega12_thermal_get_temperature(hwmgr);
1329                 *size = 4;
1330                 break;
1331         case AMDGPU_PP_SENSOR_UVD_POWER:
1332                 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
1333                 *size = 4;
1334                 break;
1335         case AMDGPU_PP_SENSOR_VCE_POWER:
1336                 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
1337                 *size = 4;
1338                 break;
1339         case AMDGPU_PP_SENSOR_GPU_POWER:
1340                 ret = vega12_get_gpu_power(hwmgr, (uint32_t *)value);
1341                 break;
1342         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
1343                 ret = vega12_get_enabled_smc_features(hwmgr, (uint64_t *)value);
1344                 if (!ret)
1345                         *size = 8;
1346                 break;
1347         default:
1348                 ret = -EINVAL;
1349                 break;
1350         }
1351         return ret;
1352 }
1353
1354 static int vega12_notify_smc_display_change(struct pp_hwmgr *hwmgr,
1355                 bool has_disp)
1356 {
1357         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1358
1359         if (data->smu_features[GNLD_DPM_UCLK].enabled)
1360                 return smum_send_msg_to_smc_with_parameter(hwmgr,
1361                         PPSMC_MSG_SetUclkFastSwitch,
1362                         has_disp ? 1 : 0);
1363
1364         return 0;
1365 }
1366
1367 int vega12_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
1368                 struct pp_display_clock_request *clock_req)
1369 {
1370         int result = 0;
1371         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1372         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1373         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1374         PPCLK_e clk_select = 0;
1375         uint32_t clk_request = 0;
1376
1377         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1378                 switch (clk_type) {
1379                 case amd_pp_dcef_clock:
1380                         clk_select = PPCLK_DCEFCLK;
1381                         break;
1382                 case amd_pp_disp_clock:
1383                         clk_select = PPCLK_DISPCLK;
1384                         break;
1385                 case amd_pp_pixel_clock:
1386                         clk_select = PPCLK_PIXCLK;
1387                         break;
1388                 case amd_pp_phy_clock:
1389                         clk_select = PPCLK_PHYCLK;
1390                         break;
1391                 default:
1392                         pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
1393                         result = -1;
1394                         break;
1395                 }
1396
1397                 if (!result) {
1398                         clk_request = (clk_select << 16) | clk_freq;
1399                         result = smum_send_msg_to_smc_with_parameter(hwmgr,
1400                                         PPSMC_MSG_SetHardMinByFreq,
1401                                         clk_request);
1402                 }
1403         }
1404
1405         return result;
1406 }
1407
1408 static int vega12_notify_smc_display_config_after_ps_adjustment(
1409                 struct pp_hwmgr *hwmgr)
1410 {
1411         struct vega12_hwmgr *data =
1412                         (struct vega12_hwmgr *)(hwmgr->backend);
1413         struct PP_Clocks min_clocks = {0};
1414         struct pp_display_clock_request clock_req;
1415
1416         if ((hwmgr->display_config->num_display > 1) &&
1417              !hwmgr->display_config->multi_monitor_in_sync &&
1418              !hwmgr->display_config->nb_pstate_switch_disable)
1419                 vega12_notify_smc_display_change(hwmgr, false);
1420         else
1421                 vega12_notify_smc_display_change(hwmgr, true);
1422
1423         min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
1424         min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
1425         min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
1426
1427         if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
1428                 clock_req.clock_type = amd_pp_dcef_clock;
1429                 clock_req.clock_freq_in_khz = min_clocks.dcefClock/10;
1430                 if (!vega12_display_clock_voltage_request(hwmgr, &clock_req)) {
1431                         if (data->smu_features[GNLD_DS_DCEFCLK].supported)
1432                                 PP_ASSERT_WITH_CODE(
1433                                         !smum_send_msg_to_smc_with_parameter(
1434                                         hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
1435                                         min_clocks.dcefClockInSR /100),
1436                                         "Attempt to set divider for DCEFCLK Failed!",
1437                                         return -1);
1438                 } else {
1439                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1440                 }
1441         }
1442
1443         return 0;
1444 }
1445
1446 static int vega12_force_dpm_highest(struct pp_hwmgr *hwmgr)
1447 {
1448         struct vega12_hwmgr *data =
1449                         (struct vega12_hwmgr *)(hwmgr->backend);
1450
1451         uint32_t soft_level;
1452
1453         soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.gfx_table));
1454
1455         data->dpm_table.gfx_table.dpm_state.soft_min_level =
1456                 data->dpm_table.gfx_table.dpm_state.soft_max_level =
1457                 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
1458
1459         soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.mem_table));
1460
1461         data->dpm_table.mem_table.dpm_state.soft_min_level =
1462                 data->dpm_table.mem_table.dpm_state.soft_max_level =
1463                 data->dpm_table.mem_table.dpm_levels[soft_level].value;
1464
1465         PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
1466                         "Failed to upload boot level to highest!",
1467                         return -1);
1468
1469         PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
1470                         "Failed to upload dpm max level to highest!",
1471                         return -1);
1472
1473         return 0;
1474 }
1475
1476 static int vega12_force_dpm_lowest(struct pp_hwmgr *hwmgr)
1477 {
1478         struct vega12_hwmgr *data =
1479                         (struct vega12_hwmgr *)(hwmgr->backend);
1480         uint32_t soft_level;
1481
1482         soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
1483
1484         data->dpm_table.gfx_table.dpm_state.soft_min_level =
1485                 data->dpm_table.gfx_table.dpm_state.soft_max_level =
1486                 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
1487
1488         soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.mem_table));
1489
1490         data->dpm_table.mem_table.dpm_state.soft_min_level =
1491                 data->dpm_table.mem_table.dpm_state.soft_max_level =
1492                 data->dpm_table.mem_table.dpm_levels[soft_level].value;
1493
1494         PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
1495                         "Failed to upload boot level to highest!",
1496                         return -1);
1497
1498         PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
1499                         "Failed to upload dpm max level to highest!",
1500                         return -1);
1501
1502         return 0;
1503
1504 }
1505
1506 static int vega12_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
1507 {
1508         PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
1509                         "Failed to upload DPM Bootup Levels!",
1510                         return -1);
1511
1512         PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
1513                         "Failed to upload DPM Max Levels!",
1514                         return -1);
1515
1516         return 0;
1517 }
1518
1519 static int vega12_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
1520                                 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
1521 {
1522         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1523         struct vega12_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table);
1524         struct vega12_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table);
1525         struct vega12_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table);
1526
1527         *sclk_mask = 0;
1528         *mclk_mask = 0;
1529         *soc_mask  = 0;
1530
1531         if (gfx_dpm_table->count > VEGA12_UMD_PSTATE_GFXCLK_LEVEL &&
1532             mem_dpm_table->count > VEGA12_UMD_PSTATE_MCLK_LEVEL &&
1533             soc_dpm_table->count > VEGA12_UMD_PSTATE_SOCCLK_LEVEL) {
1534                 *sclk_mask = VEGA12_UMD_PSTATE_GFXCLK_LEVEL;
1535                 *mclk_mask = VEGA12_UMD_PSTATE_MCLK_LEVEL;
1536                 *soc_mask  = VEGA12_UMD_PSTATE_SOCCLK_LEVEL;
1537         }
1538
1539         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1540                 *sclk_mask = 0;
1541         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1542                 *mclk_mask = 0;
1543         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1544                 *sclk_mask = gfx_dpm_table->count - 1;
1545                 *mclk_mask = mem_dpm_table->count - 1;
1546                 *soc_mask  = soc_dpm_table->count - 1;
1547         }
1548
1549         return 0;
1550 }
1551
1552 static void vega12_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
1553 {
1554         switch (mode) {
1555         case AMD_FAN_CTRL_NONE:
1556                 break;
1557         case AMD_FAN_CTRL_MANUAL:
1558                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
1559                         vega12_fan_ctrl_stop_smc_fan_control(hwmgr);
1560                 break;
1561         case AMD_FAN_CTRL_AUTO:
1562                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
1563                         vega12_fan_ctrl_start_smc_fan_control(hwmgr);
1564                 break;
1565         default:
1566                 break;
1567         }
1568 }
1569
1570 static int vega12_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
1571                                 enum amd_dpm_forced_level level)
1572 {
1573         int ret = 0;
1574         uint32_t sclk_mask = 0;
1575         uint32_t mclk_mask = 0;
1576         uint32_t soc_mask = 0;
1577
1578         switch (level) {
1579         case AMD_DPM_FORCED_LEVEL_HIGH:
1580                 ret = vega12_force_dpm_highest(hwmgr);
1581                 break;
1582         case AMD_DPM_FORCED_LEVEL_LOW:
1583                 ret = vega12_force_dpm_lowest(hwmgr);
1584                 break;
1585         case AMD_DPM_FORCED_LEVEL_AUTO:
1586                 ret = vega12_unforce_dpm_levels(hwmgr);
1587                 break;
1588         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1589         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1590         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1591         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1592                 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
1593                 if (ret)
1594                         return ret;
1595                 vega12_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
1596                 vega12_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
1597                 break;
1598         case AMD_DPM_FORCED_LEVEL_MANUAL:
1599         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1600         default:
1601                 break;
1602         }
1603
1604         return ret;
1605 }
1606
1607 static uint32_t vega12_get_fan_control_mode(struct pp_hwmgr *hwmgr)
1608 {
1609         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1610
1611         if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
1612                 return AMD_FAN_CTRL_MANUAL;
1613         else
1614                 return AMD_FAN_CTRL_AUTO;
1615 }
1616
1617 static int vega12_get_dal_power_level(struct pp_hwmgr *hwmgr,
1618                 struct amd_pp_simple_clock_info *info)
1619 {
1620 #if 0
1621         struct phm_ppt_v2_information *table_info =
1622                         (struct phm_ppt_v2_information *)hwmgr->pptable;
1623         struct phm_clock_and_voltage_limits *max_limits =
1624                         &table_info->max_clock_voltage_on_ac;
1625
1626         info->engine_max_clock = max_limits->sclk;
1627         info->memory_max_clock = max_limits->mclk;
1628 #endif
1629         return 0;
1630 }
1631
1632 static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr,
1633                 uint32_t *clock,
1634                 PPCLK_e clock_select,
1635                 bool max)
1636 {
1637         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1638
1639         if (max)
1640                 *clock = data->clk_range[clock_select].ACMax;
1641         else
1642                 *clock = data->clk_range[clock_select].ACMin;
1643
1644         return 0;
1645 }
1646
1647 static int vega12_get_sclks(struct pp_hwmgr *hwmgr,
1648                 struct pp_clock_levels_with_latency *clocks)
1649 {
1650         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1651         uint32_t ucount;
1652         int i;
1653         struct vega12_single_dpm_table *dpm_table;
1654
1655         if (!data->smu_features[GNLD_DPM_GFXCLK].enabled)
1656                 return -1;
1657
1658         dpm_table = &(data->dpm_table.gfx_table);
1659         ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1660                 MAX_NUM_CLOCKS : dpm_table->count;
1661
1662         for (i = 0; i < ucount; i++) {
1663                 clocks->data[i].clocks_in_khz =
1664                         dpm_table->dpm_levels[i].value * 1000;
1665
1666                 clocks->data[i].latency_in_us = 0;
1667         }
1668
1669         clocks->num_levels = ucount;
1670
1671         return 0;
1672 }
1673
1674 static uint32_t vega12_get_mem_latency(struct pp_hwmgr *hwmgr,
1675                 uint32_t clock)
1676 {
1677         return 25;
1678 }
1679
1680 static int vega12_get_memclocks(struct pp_hwmgr *hwmgr,
1681                 struct pp_clock_levels_with_latency *clocks)
1682 {
1683         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1684         uint32_t ucount;
1685         int i;
1686         struct vega12_single_dpm_table *dpm_table;
1687         if (!data->smu_features[GNLD_DPM_UCLK].enabled)
1688                 return -1;
1689
1690         dpm_table = &(data->dpm_table.mem_table);
1691         ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1692                 MAX_NUM_CLOCKS : dpm_table->count;
1693
1694         for (i = 0; i < ucount; i++) {
1695                 clocks->data[i].clocks_in_khz = dpm_table->dpm_levels[i].value * 1000;
1696                 data->mclk_latency_table.entries[i].frequency = dpm_table->dpm_levels[i].value * 100;
1697                 clocks->data[i].latency_in_us =
1698                         data->mclk_latency_table.entries[i].latency =
1699                         vega12_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
1700         }
1701
1702         clocks->num_levels = data->mclk_latency_table.count = ucount;
1703
1704         return 0;
1705 }
1706
1707 static int vega12_get_dcefclocks(struct pp_hwmgr *hwmgr,
1708                 struct pp_clock_levels_with_latency *clocks)
1709 {
1710         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1711         uint32_t ucount;
1712         int i;
1713         struct vega12_single_dpm_table *dpm_table;
1714
1715         if (!data->smu_features[GNLD_DPM_DCEFCLK].enabled)
1716                 return -1;
1717
1718
1719         dpm_table = &(data->dpm_table.dcef_table);
1720         ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1721                 MAX_NUM_CLOCKS : dpm_table->count;
1722
1723         for (i = 0; i < ucount; i++) {
1724                 clocks->data[i].clocks_in_khz =
1725                         dpm_table->dpm_levels[i].value * 1000;
1726
1727                 clocks->data[i].latency_in_us = 0;
1728         }
1729
1730         clocks->num_levels = ucount;
1731
1732         return 0;
1733 }
1734
1735 static int vega12_get_socclocks(struct pp_hwmgr *hwmgr,
1736                 struct pp_clock_levels_with_latency *clocks)
1737 {
1738         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1739         uint32_t ucount;
1740         int i;
1741         struct vega12_single_dpm_table *dpm_table;
1742
1743         if (!data->smu_features[GNLD_DPM_SOCCLK].enabled)
1744                 return -1;
1745
1746
1747         dpm_table = &(data->dpm_table.soc_table);
1748         ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1749                 MAX_NUM_CLOCKS : dpm_table->count;
1750
1751         for (i = 0; i < ucount; i++) {
1752                 clocks->data[i].clocks_in_khz =
1753                         dpm_table->dpm_levels[i].value * 1000;
1754
1755                 clocks->data[i].latency_in_us = 0;
1756         }
1757
1758         clocks->num_levels = ucount;
1759
1760         return 0;
1761
1762 }
1763
1764 static int vega12_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
1765                 enum amd_pp_clock_type type,
1766                 struct pp_clock_levels_with_latency *clocks)
1767 {
1768         int ret;
1769
1770         switch (type) {
1771         case amd_pp_sys_clock:
1772                 ret = vega12_get_sclks(hwmgr, clocks);
1773                 break;
1774         case amd_pp_mem_clock:
1775                 ret = vega12_get_memclocks(hwmgr, clocks);
1776                 break;
1777         case amd_pp_dcef_clock:
1778                 ret = vega12_get_dcefclocks(hwmgr, clocks);
1779                 break;
1780         case amd_pp_soc_clock:
1781                 ret = vega12_get_socclocks(hwmgr, clocks);
1782                 break;
1783         default:
1784                 return -EINVAL;
1785         }
1786
1787         return ret;
1788 }
1789
1790 static int vega12_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
1791                 enum amd_pp_clock_type type,
1792                 struct pp_clock_levels_with_voltage *clocks)
1793 {
1794         clocks->num_levels = 0;
1795
1796         return 0;
1797 }
1798
1799 static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
1800                                                         void *clock_ranges)
1801 {
1802         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1803         Watermarks_t *table = &(data->smc_state_table.water_marks_table);
1804         struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
1805
1806         if (!data->registry_data.disable_water_mark &&
1807                         data->smu_features[GNLD_DPM_DCEFCLK].supported &&
1808                         data->smu_features[GNLD_DPM_SOCCLK].supported) {
1809                 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
1810                 data->water_marks_bitmap |= WaterMarksExist;
1811                 data->water_marks_bitmap &= ~WaterMarksLoaded;
1812         }
1813
1814         return 0;
1815 }
1816
1817 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
1818                 enum pp_clock_type type, uint32_t mask)
1819 {
1820         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1821         uint32_t soft_min_level, soft_max_level;
1822         int ret = 0;
1823
1824         switch (type) {
1825         case PP_SCLK:
1826                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1827                 soft_max_level = mask ? (fls(mask) - 1) : 0;
1828
1829                 data->dpm_table.gfx_table.dpm_state.soft_min_level =
1830                         data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
1831                 data->dpm_table.gfx_table.dpm_state.soft_max_level =
1832                         data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
1833
1834                 ret = vega12_upload_dpm_min_level(hwmgr);
1835                 PP_ASSERT_WITH_CODE(!ret,
1836                         "Failed to upload boot level to lowest!",
1837                         return ret);
1838
1839                 ret = vega12_upload_dpm_max_level(hwmgr);
1840                 PP_ASSERT_WITH_CODE(!ret,
1841                         "Failed to upload dpm max level to highest!",
1842                         return ret);
1843                 break;
1844
1845         case PP_MCLK:
1846                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1847                 soft_max_level = mask ? (fls(mask) - 1) : 0;
1848
1849                 data->dpm_table.mem_table.dpm_state.soft_min_level =
1850                         data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
1851                 data->dpm_table.mem_table.dpm_state.soft_max_level =
1852                         data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
1853
1854                 ret = vega12_upload_dpm_min_level(hwmgr);
1855                 PP_ASSERT_WITH_CODE(!ret,
1856                         "Failed to upload boot level to lowest!",
1857                         return ret);
1858
1859                 ret = vega12_upload_dpm_max_level(hwmgr);
1860                 PP_ASSERT_WITH_CODE(!ret,
1861                         "Failed to upload dpm max level to highest!",
1862                         return ret);
1863
1864                 break;
1865
1866         case PP_PCIE:
1867                 break;
1868
1869         default:
1870                 break;
1871         }
1872
1873         return 0;
1874 }
1875
1876 static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
1877                 enum pp_clock_type type, char *buf)
1878 {
1879         int i, now, size = 0;
1880         struct pp_clock_levels_with_latency clocks;
1881
1882         switch (type) {
1883         case PP_SCLK:
1884                 PP_ASSERT_WITH_CODE(
1885                                 vega12_get_current_gfx_clk_freq(hwmgr, &now) == 0,
1886                                 "Attempt to get current gfx clk Failed!",
1887                                 return -1);
1888
1889                 PP_ASSERT_WITH_CODE(
1890                                 vega12_get_sclks(hwmgr, &clocks) == 0,
1891                                 "Attempt to get gfx clk levels Failed!",
1892                                 return -1);
1893                 for (i = 0; i < clocks.num_levels; i++)
1894                         size += sprintf(buf + size, "%d: %uMhz %s\n",
1895                                 i, clocks.data[i].clocks_in_khz / 1000,
1896                                 (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");
1897                 break;
1898
1899         case PP_MCLK:
1900                 PP_ASSERT_WITH_CODE(
1901                                 vega12_get_current_mclk_freq(hwmgr, &now) == 0,
1902                                 "Attempt to get current mclk freq Failed!",
1903                                 return -1);
1904
1905                 PP_ASSERT_WITH_CODE(
1906                                 vega12_get_memclocks(hwmgr, &clocks) == 0,
1907                                 "Attempt to get memory clk levels Failed!",
1908                                 return -1);
1909                 for (i = 0; i < clocks.num_levels; i++)
1910                         size += sprintf(buf + size, "%d: %uMhz %s\n",
1911                                 i, clocks.data[i].clocks_in_khz / 1000,
1912                                 (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");
1913                 break;
1914
1915         case PP_PCIE:
1916                 break;
1917
1918         default:
1919                 break;
1920         }
1921         return size;
1922 }
1923
1924 static int vega12_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
1925 {
1926         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1927         struct vega12_single_dpm_table *dpm_table;
1928         bool vblank_too_short = false;
1929         bool disable_mclk_switching;
1930         uint32_t i, latency;
1931
1932         disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
1933                                   !hwmgr->display_config->multi_monitor_in_sync) ||
1934                                   vblank_too_short;
1935         latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
1936
1937         /* gfxclk */
1938         dpm_table = &(data->dpm_table.gfx_table);
1939         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
1940         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1941         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
1942         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1943
1944         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
1945                 if (VEGA12_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
1946                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
1947                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
1948                 }
1949
1950                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1951                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
1952                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
1953                 }
1954
1955                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1956                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1957                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1958                 }
1959         }
1960
1961         /* memclk */
1962         dpm_table = &(data->dpm_table.mem_table);
1963         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
1964         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1965         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
1966         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1967
1968         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
1969                 if (VEGA12_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
1970                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
1971                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
1972                 }
1973
1974                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1975                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
1976                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
1977                 }
1978
1979                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1980                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1981                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1982                 }
1983         }
1984
1985         /* honour DAL's UCLK Hardmin */
1986         if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
1987                 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
1988
1989         /* Hardmin is dependent on displayconfig */
1990         if (disable_mclk_switching) {
1991                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1992                 for (i = 0; i < data->mclk_latency_table.count - 1; i++) {
1993                         if (data->mclk_latency_table.entries[i].latency <= latency) {
1994                                 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
1995                                         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
1996                                         break;
1997                                 }
1998                         }
1999                 }
2000         }
2001
2002         if (hwmgr->display_config->nb_pstate_switch_disable)
2003                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2004
2005         /* vclk */
2006         dpm_table = &(data->dpm_table.vclk_table);
2007         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2008         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2009         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2010         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2011
2012         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2013                 if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2014                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2015                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2016                 }
2017
2018                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2019                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2020                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2021                 }
2022         }
2023
2024         /* dclk */
2025         dpm_table = &(data->dpm_table.dclk_table);
2026         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2027         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2028         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2029         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2030
2031         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2032                 if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2033                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2034                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2035                 }
2036
2037                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2038                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2039                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2040                 }
2041         }
2042
2043         /* socclk */
2044         dpm_table = &(data->dpm_table.soc_table);
2045         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2046         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2047         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2048         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2049
2050         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2051                 if (VEGA12_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
2052                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value;
2053                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value;
2054                 }
2055
2056                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2057                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2058                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2059                 }
2060         }
2061
2062         /* eclk */
2063         dpm_table = &(data->dpm_table.eclk_table);
2064         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2065         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2066         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2067         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2068
2069         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2070                 if (VEGA12_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
2071                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value;
2072                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value;
2073                 }
2074
2075                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2076                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2077                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2078                 }
2079         }
2080
2081         return 0;
2082 }
2083
2084 static int vega12_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
2085                 struct vega12_single_dpm_table *dpm_table)
2086 {
2087         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2088         int ret = 0;
2089
2090         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2091                 PP_ASSERT_WITH_CODE(dpm_table->count > 0,
2092                                 "[SetUclkToHightestDpmLevel] Dpm table has no entry!",
2093                                 return -EINVAL);
2094                 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
2095                                 "[SetUclkToHightestDpmLevel] Dpm table has too many entries!",
2096                                 return -EINVAL);
2097
2098                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2099                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2100                                 PPSMC_MSG_SetHardMinByFreq,
2101                                 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
2102                                 "[SetUclkToHightestDpmLevel] Set hard min uclk failed!",
2103                                 return ret);
2104         }
2105
2106         return ret;
2107 }
2108
2109 static int vega12_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2110 {
2111         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2112         int ret = 0;
2113
2114         smum_send_msg_to_smc_with_parameter(hwmgr,
2115                         PPSMC_MSG_NumOfDisplays, 0);
2116
2117         ret = vega12_set_uclk_to_highest_dpm_level(hwmgr,
2118                         &data->dpm_table.mem_table);
2119
2120         return ret;
2121 }
2122
2123 static int vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2124 {
2125         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2126         int result = 0;
2127         Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
2128
2129         if ((data->water_marks_bitmap & WaterMarksExist) &&
2130                         !(data->water_marks_bitmap & WaterMarksLoaded)) {
2131                 result = smum_smc_table_manager(hwmgr,
2132                                                 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
2133                 PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return EINVAL);
2134                 data->water_marks_bitmap |= WaterMarksLoaded;
2135         }
2136
2137         if ((data->water_marks_bitmap & WaterMarksExist) &&
2138                 data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2139                 data->smu_features[GNLD_DPM_SOCCLK].supported)
2140                 smum_send_msg_to_smc_with_parameter(hwmgr,
2141                         PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display);
2142
2143         return result;
2144 }
2145
2146 int vega12_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
2147 {
2148         struct vega12_hwmgr *data =
2149                         (struct vega12_hwmgr *)(hwmgr->backend);
2150
2151         if (data->smu_features[GNLD_DPM_UVD].supported) {
2152                 PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,
2153                                 enable,
2154                                 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap),
2155                                 "Attempt to Enable/Disable DPM UVD Failed!",
2156                                 return -1);
2157                 data->smu_features[GNLD_DPM_UVD].enabled = enable;
2158         }
2159
2160         return 0;
2161 }
2162
2163 static void vega12_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
2164 {
2165         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2166
2167         if (data->vce_power_gated == bgate)
2168                 return;
2169
2170         data->vce_power_gated = bgate;
2171         vega12_enable_disable_vce_dpm(hwmgr, !bgate);
2172 }
2173
2174 static void vega12_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
2175 {
2176         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2177
2178         if (data->uvd_power_gated == bgate)
2179                 return;
2180
2181         data->uvd_power_gated = bgate;
2182         vega12_enable_disable_uvd_dpm(hwmgr, !bgate);
2183 }
2184
2185 static bool
2186 vega12_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
2187 {
2188         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2189         bool is_update_required = false;
2190
2191         if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
2192                 is_update_required = true;
2193
2194         if (data->registry_data.gfx_clk_deep_sleep_support) {
2195                 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
2196                         is_update_required = true;
2197         }
2198
2199         return is_update_required;
2200 }
2201
2202 static int vega12_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
2203 {
2204         int tmp_result, result = 0;
2205
2206         tmp_result = vega12_disable_all_smu_features(hwmgr);
2207         PP_ASSERT_WITH_CODE((tmp_result == 0),
2208                         "Failed to disable all smu features!", result = tmp_result);
2209
2210         return result;
2211 }
2212
2213 static int vega12_power_off_asic(struct pp_hwmgr *hwmgr)
2214 {
2215         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2216         int result;
2217
2218         result = vega12_disable_dpm_tasks(hwmgr);
2219         PP_ASSERT_WITH_CODE((0 == result),
2220                         "[disable_dpm_tasks] Failed to disable DPM!",
2221                         );
2222         data->water_marks_bitmap &= ~(WaterMarksLoaded);
2223
2224         return result;
2225 }
2226
2227 #if 0
2228 static void vega12_find_min_clock_index(struct pp_hwmgr *hwmgr,
2229                 uint32_t *sclk_idx, uint32_t *mclk_idx,
2230                 uint32_t min_sclk, uint32_t min_mclk)
2231 {
2232         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2233         struct vega12_dpm_table *dpm_table = &(data->dpm_table);
2234         uint32_t i;
2235
2236         for (i = 0; i < dpm_table->gfx_table.count; i++) {
2237                 if (dpm_table->gfx_table.dpm_levels[i].enabled &&
2238                         dpm_table->gfx_table.dpm_levels[i].value >= min_sclk) {
2239                         *sclk_idx = i;
2240                         break;
2241                 }
2242         }
2243
2244         for (i = 0; i < dpm_table->mem_table.count; i++) {
2245                 if (dpm_table->mem_table.dpm_levels[i].enabled &&
2246                         dpm_table->mem_table.dpm_levels[i].value >= min_mclk) {
2247                         *mclk_idx = i;
2248                         break;
2249                 }
2250         }
2251 }
2252 #endif
2253
2254 #if 0
2255 static int vega12_set_power_profile_state(struct pp_hwmgr *hwmgr,
2256                 struct amd_pp_profile *request)
2257 {
2258         return 0;
2259 }
2260
2261 static int vega12_get_sclk_od(struct pp_hwmgr *hwmgr)
2262 {
2263         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2264         struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
2265         struct vega12_single_dpm_table *golden_sclk_table =
2266                         &(data->golden_dpm_table.gfx_table);
2267         int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
2268         int golden_value = golden_sclk_table->dpm_levels
2269                         [golden_sclk_table->count - 1].value;
2270
2271         value -= golden_value;
2272         value = DIV_ROUND_UP(value * 100, golden_value);
2273
2274         return value;
2275 }
2276
2277 static int vega12_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
2278 {
2279         return 0;
2280 }
2281
2282 static int vega12_get_mclk_od(struct pp_hwmgr *hwmgr)
2283 {
2284         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2285         struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
2286         struct vega12_single_dpm_table *golden_mclk_table =
2287                         &(data->golden_dpm_table.mem_table);
2288         int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
2289         int golden_value = golden_mclk_table->dpm_levels
2290                         [golden_mclk_table->count - 1].value;
2291
2292         value -= golden_value;
2293         value = DIV_ROUND_UP(value * 100, golden_value);
2294
2295         return value;
2296 }
2297
2298 static int vega12_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
2299 {
2300         return 0;
2301 }
2302 #endif
2303
2304 static int vega12_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
2305                                         uint32_t virtual_addr_low,
2306                                         uint32_t virtual_addr_hi,
2307                                         uint32_t mc_addr_low,
2308                                         uint32_t mc_addr_hi,
2309                                         uint32_t size)
2310 {
2311         smum_send_msg_to_smc_with_parameter(hwmgr,
2312                                         PPSMC_MSG_SetSystemVirtualDramAddrHigh,
2313                                         virtual_addr_hi);
2314         smum_send_msg_to_smc_with_parameter(hwmgr,
2315                                         PPSMC_MSG_SetSystemVirtualDramAddrLow,
2316                                         virtual_addr_low);
2317         smum_send_msg_to_smc_with_parameter(hwmgr,
2318                                         PPSMC_MSG_DramLogSetDramAddrHigh,
2319                                         mc_addr_hi);
2320
2321         smum_send_msg_to_smc_with_parameter(hwmgr,
2322                                         PPSMC_MSG_DramLogSetDramAddrLow,
2323                                         mc_addr_low);
2324
2325         smum_send_msg_to_smc_with_parameter(hwmgr,
2326                                         PPSMC_MSG_DramLogSetDramSize,
2327                                         size);
2328         return 0;
2329 }
2330
2331 static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
2332                 struct PP_TemperatureRange *thermal_data)
2333 {
2334         struct phm_ppt_v3_information *pptable_information =
2335                 (struct phm_ppt_v3_information *)hwmgr->pptable;
2336
2337         memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
2338
2339         thermal_data->max = pptable_information->us_software_shutdown_temp *
2340                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2341
2342         return 0;
2343 }
2344
2345 static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr)
2346 {
2347         struct vega12_hwmgr *data =
2348                         (struct vega12_hwmgr *)(hwmgr->backend);
2349         int ret = 0;
2350
2351         if (data->gfxoff_controlled_by_driver)
2352                 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_AllowGfxOff);
2353
2354         return ret;
2355 }
2356
2357 static int vega12_disable_gfx_off(struct pp_hwmgr *hwmgr)
2358 {
2359         struct vega12_hwmgr *data =
2360                         (struct vega12_hwmgr *)(hwmgr->backend);
2361         int ret = 0;
2362
2363         if (data->gfxoff_controlled_by_driver)
2364                 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisallowGfxOff);
2365
2366         return ret;
2367 }
2368
2369 static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
2370 {
2371         if (enable)
2372                 return vega12_enable_gfx_off(hwmgr);
2373         else
2374                 return vega12_disable_gfx_off(hwmgr);
2375 }
2376
2377 static int vega12_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
2378                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
2379                                 PHM_PerformanceLevel *level)
2380 {
2381         return 0;
2382 }
2383
2384 static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
2385         .backend_init = vega12_hwmgr_backend_init,
2386         .backend_fini = vega12_hwmgr_backend_fini,
2387         .asic_setup = vega12_setup_asic_task,
2388         .dynamic_state_management_enable = vega12_enable_dpm_tasks,
2389         .dynamic_state_management_disable = vega12_disable_dpm_tasks,
2390         .patch_boot_state = vega12_patch_boot_state,
2391         .get_sclk = vega12_dpm_get_sclk,
2392         .get_mclk = vega12_dpm_get_mclk,
2393         .notify_smc_display_config_after_ps_adjustment =
2394                         vega12_notify_smc_display_config_after_ps_adjustment,
2395         .force_dpm_level = vega12_dpm_force_dpm_level,
2396         .stop_thermal_controller = vega12_thermal_stop_thermal_controller,
2397         .get_fan_speed_info = vega12_fan_ctrl_get_fan_speed_info,
2398         .reset_fan_speed_to_default =
2399                         vega12_fan_ctrl_reset_fan_speed_to_default,
2400         .get_fan_speed_rpm = vega12_fan_ctrl_get_fan_speed_rpm,
2401         .set_fan_control_mode = vega12_set_fan_control_mode,
2402         .get_fan_control_mode = vega12_get_fan_control_mode,
2403         .read_sensor = vega12_read_sensor,
2404         .get_dal_power_level = vega12_get_dal_power_level,
2405         .get_clock_by_type_with_latency = vega12_get_clock_by_type_with_latency,
2406         .get_clock_by_type_with_voltage = vega12_get_clock_by_type_with_voltage,
2407         .set_watermarks_for_clocks_ranges = vega12_set_watermarks_for_clocks_ranges,
2408         .display_clock_voltage_request = vega12_display_clock_voltage_request,
2409         .force_clock_level = vega12_force_clock_level,
2410         .print_clock_levels = vega12_print_clock_levels,
2411         .apply_clocks_adjust_rules =
2412                 vega12_apply_clocks_adjust_rules,
2413         .pre_display_config_changed =
2414                 vega12_pre_display_configuration_changed_task,
2415         .display_config_changed = vega12_display_configuration_changed_task,
2416         .powergate_uvd = vega12_power_gate_uvd,
2417         .powergate_vce = vega12_power_gate_vce,
2418         .check_smc_update_required_for_display_configuration =
2419                         vega12_check_smc_update_required_for_display_configuration,
2420         .power_off_asic = vega12_power_off_asic,
2421         .disable_smc_firmware_ctf = vega12_thermal_disable_alert,
2422 #if 0
2423         .set_power_profile_state = vega12_set_power_profile_state,
2424         .get_sclk_od = vega12_get_sclk_od,
2425         .set_sclk_od = vega12_set_sclk_od,
2426         .get_mclk_od = vega12_get_mclk_od,
2427         .set_mclk_od = vega12_set_mclk_od,
2428 #endif
2429         .notify_cac_buffer_info = vega12_notify_cac_buffer_info,
2430         .get_thermal_temperature_range = vega12_get_thermal_temperature_range,
2431         .register_irq_handlers = smu9_register_irq_handlers,
2432         .start_thermal_controller = vega12_start_thermal_controller,
2433         .powergate_gfx = vega12_gfx_off_control,
2434         .get_performance_level = vega12_get_performance_level,
2435 };
2436
2437 int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
2438 {
2439         hwmgr->hwmgr_func = &vega12_hwmgr_funcs;
2440         hwmgr->pptable_func = &vega12_pptable_funcs;
2441
2442         return 0;
2443 }