Merge tag 'drm-misc-fixes-2019-01-10' of git://anongit.freedesktop.org/drm/drm-misc...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / powerplay / hwmgr / smu7_hwmgr.c
1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #include "pp_debug.h"
24 #include <linux/delay.h>
25 #include <linux/fb.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
28 #include <asm/div64.h>
29 #include <drm/amdgpu_drm.h>
30 #include "ppatomctrl.h"
31 #include "atombios.h"
32 #include "pptable_v1_0.h"
33 #include "pppcielanes.h"
34 #include "amd_pcie_helpers.h"
35 #include "hardwaremanager.h"
36 #include "process_pptables_v1_0.h"
37 #include "cgs_common.h"
38
39 #include "smu7_common.h"
40
41 #include "hwmgr.h"
42 #include "smu7_hwmgr.h"
43 #include "smu_ucode_xfer_vi.h"
44 #include "smu7_powertune.h"
45 #include "smu7_dyn_defaults.h"
46 #include "smu7_thermal.h"
47 #include "smu7_clockpowergating.h"
48 #include "processpptables.h"
49 #include "pp_thermal.h"
50
51 #include "ivsrcid/ivsrcid_vislands30.h"
52
53 #define MC_CG_ARB_FREQ_F0           0x0a
54 #define MC_CG_ARB_FREQ_F1           0x0b
55 #define MC_CG_ARB_FREQ_F2           0x0c
56 #define MC_CG_ARB_FREQ_F3           0x0d
57
58 #define MC_CG_SEQ_DRAMCONF_S0       0x05
59 #define MC_CG_SEQ_DRAMCONF_S1       0x06
60 #define MC_CG_SEQ_YCLK_SUSPEND      0x04
61 #define MC_CG_SEQ_YCLK_RESUME       0x0a
62
63 #define SMC_CG_IND_START            0xc0030000
64 #define SMC_CG_IND_END              0xc0040000
65
66 #define MEM_FREQ_LOW_LATENCY        25000
67 #define MEM_FREQ_HIGH_LATENCY       80000
68
69 #define MEM_LATENCY_HIGH            45
70 #define MEM_LATENCY_LOW             35
71 #define MEM_LATENCY_ERR             0xFFFF
72
73 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
74 #define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
75 #define MC_SEQ_MISC0_GDDR5_VALUE 5
76
77 #define PCIE_BUS_CLK                10000
78 #define TCLK                        (PCIE_BUS_CLK / 10)
79
80 static const struct profile_mode_setting smu7_profiling[6] =
81                                         {{1, 0, 100, 30, 1, 0, 100, 10},
82                                          {1, 10, 0, 30, 0, 0, 0, 0},
83                                          {0, 0, 0, 0, 1, 10, 16, 31},
84                                          {1, 0, 11, 50, 1, 0, 100, 10},
85                                          {1, 0, 5, 30, 0, 0, 0, 0},
86                                          {0, 0, 0, 0, 0, 0, 0, 0},
87                                         };
88
89 #define PPSMC_MSG_SetVBITimeout_VEGAM    ((uint16_t) 0x310)
90
91 #define ixPWR_SVI2_PLANE1_LOAD                     0xC0200280
92 #define PWR_SVI2_PLANE1_LOAD__PSI1_MASK                    0x00000020L
93 #define PWR_SVI2_PLANE1_LOAD__PSI0_EN_MASK                 0x00000040L
94 #define PWR_SVI2_PLANE1_LOAD__PSI1__SHIFT                  0x00000005
95 #define PWR_SVI2_PLANE1_LOAD__PSI0_EN__SHIFT               0x00000006
96
97 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
98 enum DPM_EVENT_SRC {
99         DPM_EVENT_SRC_ANALOG = 0,
100         DPM_EVENT_SRC_EXTERNAL = 1,
101         DPM_EVENT_SRC_DIGITAL = 2,
102         DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
103         DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
104 };
105
106 static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic);
107 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
108                 enum pp_clock_type type, uint32_t mask);
109
110 static struct smu7_power_state *cast_phw_smu7_power_state(
111                                   struct pp_hw_power_state *hw_ps)
112 {
113         PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
114                                 "Invalid Powerstate Type!",
115                                  return NULL);
116
117         return (struct smu7_power_state *)hw_ps;
118 }
119
120 static const struct smu7_power_state *cast_const_phw_smu7_power_state(
121                                  const struct pp_hw_power_state *hw_ps)
122 {
123         PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
124                                 "Invalid Powerstate Type!",
125                                  return NULL);
126
127         return (const struct smu7_power_state *)hw_ps;
128 }
129
130 /**
131  * Find the MC microcode version and store it in the HwMgr struct
132  *
133  * @param    hwmgr  the address of the powerplay hardware manager.
134  * @return   always 0
135  */
136 static int smu7_get_mc_microcode_version(struct pp_hwmgr *hwmgr)
137 {
138         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
139
140         hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
141
142         return 0;
143 }
144
145 static uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
146 {
147         uint32_t speedCntl = 0;
148
149         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
150         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
151                         ixPCIE_LC_SPEED_CNTL);
152         return((uint16_t)PHM_GET_FIELD(speedCntl,
153                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
154 }
155
156 static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
157 {
158         uint32_t link_width;
159
160         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
161         link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
162                         PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
163
164         PP_ASSERT_WITH_CODE((7 >= link_width),
165                         "Invalid PCIe lane width!", return 0);
166
167         return decode_pcie_lane_width(link_width);
168 }
169
170 /**
171 * Enable voltage control
172 *
173 * @param    pHwMgr  the address of the powerplay hardware manager.
174 * @return   always PP_Result_OK
175 */
176 static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
177 {
178         if (hwmgr->chip_id == CHIP_VEGAM) {
179                 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
180                                 CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI1, 0);
181                 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
182                                 CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI0_EN, 0);
183         }
184
185         if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK)
186                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Enable);
187
188         return 0;
189 }
190
191 /**
192 * Checks if we want to support voltage control
193 *
194 * @param    hwmgr  the address of the powerplay hardware manager.
195 */
196 static bool smu7_voltage_control(const struct pp_hwmgr *hwmgr)
197 {
198         const struct smu7_hwmgr *data =
199                         (const struct smu7_hwmgr *)(hwmgr->backend);
200
201         return (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control);
202 }
203
204 /**
205 * Enable voltage control
206 *
207 * @param    hwmgr  the address of the powerplay hardware manager.
208 * @return   always 0
209 */
210 static int smu7_enable_voltage_control(struct pp_hwmgr *hwmgr)
211 {
212         /* enable voltage control */
213         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
214                         GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
215
216         return 0;
217 }
218
219 static int phm_get_svi2_voltage_table_v0(pp_atomctrl_voltage_table *voltage_table,
220                 struct phm_clock_voltage_dependency_table *voltage_dependency_table
221                 )
222 {
223         uint32_t i;
224
225         PP_ASSERT_WITH_CODE((NULL != voltage_table),
226                         "Voltage Dependency Table empty.", return -EINVAL;);
227
228         voltage_table->mask_low = 0;
229         voltage_table->phase_delay = 0;
230         voltage_table->count = voltage_dependency_table->count;
231
232         for (i = 0; i < voltage_dependency_table->count; i++) {
233                 voltage_table->entries[i].value =
234                         voltage_dependency_table->entries[i].v;
235                 voltage_table->entries[i].smio_low = 0;
236         }
237
238         return 0;
239 }
240
241
242 /**
243 * Create Voltage Tables.
244 *
245 * @param    hwmgr  the address of the powerplay hardware manager.
246 * @return   always 0
247 */
248 static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr)
249 {
250         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
251         struct phm_ppt_v1_information *table_info =
252                         (struct phm_ppt_v1_information *)hwmgr->pptable;
253         int result = 0;
254         uint32_t tmp;
255
256         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
257                 result = atomctrl_get_voltage_table_v3(hwmgr,
258                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
259                                 &(data->mvdd_voltage_table));
260                 PP_ASSERT_WITH_CODE((0 == result),
261                                 "Failed to retrieve MVDD table.",
262                                 return result);
263         } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
264                 if (hwmgr->pp_table_version == PP_TABLE_V1)
265                         result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
266                                         table_info->vdd_dep_on_mclk);
267                 else if (hwmgr->pp_table_version == PP_TABLE_V0)
268                         result = phm_get_svi2_voltage_table_v0(&(data->mvdd_voltage_table),
269                                         hwmgr->dyn_state.mvdd_dependency_on_mclk);
270
271                 PP_ASSERT_WITH_CODE((0 == result),
272                                 "Failed to retrieve SVI2 MVDD table from dependency table.",
273                                 return result;);
274         }
275
276         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
277                 result = atomctrl_get_voltage_table_v3(hwmgr,
278                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
279                                 &(data->vddci_voltage_table));
280                 PP_ASSERT_WITH_CODE((0 == result),
281                                 "Failed to retrieve VDDCI table.",
282                                 return result);
283         } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
284                 if (hwmgr->pp_table_version == PP_TABLE_V1)
285                         result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
286                                         table_info->vdd_dep_on_mclk);
287                 else if (hwmgr->pp_table_version == PP_TABLE_V0)
288                         result = phm_get_svi2_voltage_table_v0(&(data->vddci_voltage_table),
289                                         hwmgr->dyn_state.vddci_dependency_on_mclk);
290                 PP_ASSERT_WITH_CODE((0 == result),
291                                 "Failed to retrieve SVI2 VDDCI table from dependency table.",
292                                 return result);
293         }
294
295         if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
296                 /* VDDGFX has only SVI2 voltage control */
297                 result = phm_get_svi2_vdd_voltage_table(&(data->vddgfx_voltage_table),
298                                         table_info->vddgfx_lookup_table);
299                 PP_ASSERT_WITH_CODE((0 == result),
300                         "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;);
301         }
302
303
304         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
305                 result = atomctrl_get_voltage_table_v3(hwmgr,
306                                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT,
307                                         &data->vddc_voltage_table);
308                 PP_ASSERT_WITH_CODE((0 == result),
309                         "Failed to retrieve VDDC table.", return result;);
310         } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
311
312                 if (hwmgr->pp_table_version == PP_TABLE_V0)
313                         result = phm_get_svi2_voltage_table_v0(&data->vddc_voltage_table,
314                                         hwmgr->dyn_state.vddc_dependency_on_mclk);
315                 else if (hwmgr->pp_table_version == PP_TABLE_V1)
316                         result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
317                                 table_info->vddc_lookup_table);
318
319                 PP_ASSERT_WITH_CODE((0 == result),
320                         "Failed to retrieve SVI2 VDDC table from dependency table.", return result;);
321         }
322
323         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDC);
324         PP_ASSERT_WITH_CODE(
325                         (data->vddc_voltage_table.count <= tmp),
326                 "Too many voltage values for VDDC. Trimming to fit state table.",
327                         phm_trim_voltage_table_to_fit_state_table(tmp,
328                                                 &(data->vddc_voltage_table)));
329
330         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
331         PP_ASSERT_WITH_CODE(
332                         (data->vddgfx_voltage_table.count <= tmp),
333                 "Too many voltage values for VDDC. Trimming to fit state table.",
334                         phm_trim_voltage_table_to_fit_state_table(tmp,
335                                                 &(data->vddgfx_voltage_table)));
336
337         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDCI);
338         PP_ASSERT_WITH_CODE(
339                         (data->vddci_voltage_table.count <= tmp),
340                 "Too many voltage values for VDDCI. Trimming to fit state table.",
341                         phm_trim_voltage_table_to_fit_state_table(tmp,
342                                         &(data->vddci_voltage_table)));
343
344         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_MVDD);
345         PP_ASSERT_WITH_CODE(
346                         (data->mvdd_voltage_table.count <= tmp),
347                 "Too many voltage values for MVDD. Trimming to fit state table.",
348                         phm_trim_voltage_table_to_fit_state_table(tmp,
349                                                 &(data->mvdd_voltage_table)));
350
351         return 0;
352 }
353
354 /**
355 * Programs static screed detection parameters
356 *
357 * @param    hwmgr  the address of the powerplay hardware manager.
358 * @return   always 0
359 */
360 static int smu7_program_static_screen_threshold_parameters(
361                                                         struct pp_hwmgr *hwmgr)
362 {
363         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
364
365         /* Set static screen threshold unit */
366         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
367                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
368                         data->static_screen_threshold_unit);
369         /* Set static screen threshold */
370         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
371                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
372                         data->static_screen_threshold);
373
374         return 0;
375 }
376
377 /**
378 * Setup display gap for glitch free memory clock switching.
379 *
380 * @param    hwmgr  the address of the powerplay hardware manager.
381 * @return   always  0
382 */
383 static int smu7_enable_display_gap(struct pp_hwmgr *hwmgr)
384 {
385         uint32_t display_gap =
386                         cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
387                                         ixCG_DISPLAY_GAP_CNTL);
388
389         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
390                         DISP_GAP, DISPLAY_GAP_IGNORE);
391
392         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
393                         DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
394
395         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
396                         ixCG_DISPLAY_GAP_CNTL, display_gap);
397
398         return 0;
399 }
400
401 /**
402 * Programs activity state transition voting clients
403 *
404 * @param    hwmgr  the address of the powerplay hardware manager.
405 * @return   always  0
406 */
407 static int smu7_program_voting_clients(struct pp_hwmgr *hwmgr)
408 {
409         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
410         int i;
411
412         /* Clear reset for voting clients before enabling DPM */
413         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
414                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
415         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
416                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
417
418         for (i = 0; i < 8; i++)
419                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
420                                         ixCG_FREQ_TRAN_VOTING_0 + i * 4,
421                                         data->voting_rights_clients[i]);
422         return 0;
423 }
424
425 static int smu7_clear_voting_clients(struct pp_hwmgr *hwmgr)
426 {
427         int i;
428
429         /* Reset voting clients before disabling DPM */
430         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
431                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1);
432         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
433                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1);
434
435         for (i = 0; i < 8; i++)
436                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
437                                 ixCG_FREQ_TRAN_VOTING_0 + i * 4, 0);
438
439         return 0;
440 }
441
442 /* Copy one arb setting to another and then switch the active set.
443  * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
444  */
445 static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
446                 uint32_t arb_src, uint32_t arb_dest)
447 {
448         uint32_t mc_arb_dram_timing;
449         uint32_t mc_arb_dram_timing2;
450         uint32_t burst_time;
451         uint32_t mc_cg_config;
452
453         switch (arb_src) {
454         case MC_CG_ARB_FREQ_F0:
455                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
456                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
457                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
458                 break;
459         case MC_CG_ARB_FREQ_F1:
460                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
461                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
462                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
463                 break;
464         default:
465                 return -EINVAL;
466         }
467
468         switch (arb_dest) {
469         case MC_CG_ARB_FREQ_F0:
470                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
471                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
472                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
473                 break;
474         case MC_CG_ARB_FREQ_F1:
475                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
476                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
477                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
478                 break;
479         default:
480                 return -EINVAL;
481         }
482
483         mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
484         mc_cg_config |= 0x0000000F;
485         cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
486         PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
487
488         return 0;
489 }
490
491 static int smu7_reset_to_default(struct pp_hwmgr *hwmgr)
492 {
493         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ResetToDefaults);
494 }
495
496 /**
497 * Initial switch from ARB F0->F1
498 *
499 * @param    hwmgr  the address of the powerplay hardware manager.
500 * @return   always 0
501 * This function is to be called from the SetPowerState table.
502 */
503 static int smu7_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
504 {
505         return smu7_copy_and_switch_arb_sets(hwmgr,
506                         MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
507 }
508
509 static int smu7_force_switch_to_arbf0(struct pp_hwmgr *hwmgr)
510 {
511         uint32_t tmp;
512
513         tmp = (cgs_read_ind_register(hwmgr->device,
514                         CGS_IND_REG__SMC, ixSMC_SCRATCH9) &
515                         0x0000ff00) >> 8;
516
517         if (tmp == MC_CG_ARB_FREQ_F0)
518                 return 0;
519
520         return smu7_copy_and_switch_arb_sets(hwmgr,
521                         tmp, MC_CG_ARB_FREQ_F0);
522 }
523
524 static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
525 {
526         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
527
528         struct phm_ppt_v1_information *table_info =
529                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
530         struct phm_ppt_v1_pcie_table *pcie_table = NULL;
531
532         uint32_t i, max_entry;
533         uint32_t tmp;
534
535         PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
536                         data->use_pcie_power_saving_levels), "No pcie performance levels!",
537                         return -EINVAL);
538
539         if (table_info != NULL)
540                 pcie_table = table_info->pcie_table;
541
542         if (data->use_pcie_performance_levels &&
543                         !data->use_pcie_power_saving_levels) {
544                 data->pcie_gen_power_saving = data->pcie_gen_performance;
545                 data->pcie_lane_power_saving = data->pcie_lane_performance;
546         } else if (!data->use_pcie_performance_levels &&
547                         data->use_pcie_power_saving_levels) {
548                 data->pcie_gen_performance = data->pcie_gen_power_saving;
549                 data->pcie_lane_performance = data->pcie_lane_power_saving;
550         }
551         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_LINK);
552         phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
553                                         tmp,
554                                         MAX_REGULAR_DPM_NUMBER);
555
556         if (pcie_table != NULL) {
557                 /* max_entry is used to make sure we reserve one PCIE level
558                  * for boot level (fix for A+A PSPP issue).
559                  * If PCIE table from PPTable have ULV entry + 8 entries,
560                  * then ignore the last entry.*/
561                 max_entry = (tmp < pcie_table->count) ? tmp : pcie_table->count;
562                 for (i = 1; i < max_entry; i++) {
563                         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
564                                         get_pcie_gen_support(data->pcie_gen_cap,
565                                                         pcie_table->entries[i].gen_speed),
566                                         get_pcie_lane_support(data->pcie_lane_cap,
567                                                         pcie_table->entries[i].lane_width));
568                 }
569                 data->dpm_table.pcie_speed_table.count = max_entry - 1;
570                 smum_update_smc_table(hwmgr, SMU_BIF_TABLE);
571         } else {
572                 /* Hardcode Pcie Table */
573                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
574                                 get_pcie_gen_support(data->pcie_gen_cap,
575                                                 PP_Min_PCIEGen),
576                                 get_pcie_lane_support(data->pcie_lane_cap,
577                                                 PP_Max_PCIELane));
578                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
579                                 get_pcie_gen_support(data->pcie_gen_cap,
580                                                 PP_Min_PCIEGen),
581                                 get_pcie_lane_support(data->pcie_lane_cap,
582                                                 PP_Max_PCIELane));
583                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
584                                 get_pcie_gen_support(data->pcie_gen_cap,
585                                                 PP_Max_PCIEGen),
586                                 get_pcie_lane_support(data->pcie_lane_cap,
587                                                 PP_Max_PCIELane));
588                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
589                                 get_pcie_gen_support(data->pcie_gen_cap,
590                                                 PP_Max_PCIEGen),
591                                 get_pcie_lane_support(data->pcie_lane_cap,
592                                                 PP_Max_PCIELane));
593                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
594                                 get_pcie_gen_support(data->pcie_gen_cap,
595                                                 PP_Max_PCIEGen),
596                                 get_pcie_lane_support(data->pcie_lane_cap,
597                                                 PP_Max_PCIELane));
598                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
599                                 get_pcie_gen_support(data->pcie_gen_cap,
600                                                 PP_Max_PCIEGen),
601                                 get_pcie_lane_support(data->pcie_lane_cap,
602                                                 PP_Max_PCIELane));
603
604                 data->dpm_table.pcie_speed_table.count = 6;
605         }
606         /* Populate last level for boot PCIE level, but do not increment count. */
607         if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
608                 for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++)
609                         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i,
610                                 get_pcie_gen_support(data->pcie_gen_cap,
611                                                 PP_Max_PCIEGen),
612                                 data->vbios_boot_state.pcie_lane_bootup_value);
613         } else {
614                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
615                         data->dpm_table.pcie_speed_table.count,
616                         get_pcie_gen_support(data->pcie_gen_cap,
617                                         PP_Min_PCIEGen),
618                         get_pcie_lane_support(data->pcie_lane_cap,
619                                         PP_Max_PCIELane));
620         }
621         return 0;
622 }
623
624 static int smu7_reset_dpm_tables(struct pp_hwmgr *hwmgr)
625 {
626         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
627
628         memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table));
629
630         phm_reset_single_dpm_table(
631                         &data->dpm_table.sclk_table,
632                                 smum_get_mac_definition(hwmgr,
633                                         SMU_MAX_LEVELS_GRAPHICS),
634                                         MAX_REGULAR_DPM_NUMBER);
635         phm_reset_single_dpm_table(
636                         &data->dpm_table.mclk_table,
637                         smum_get_mac_definition(hwmgr,
638                                 SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER);
639
640         phm_reset_single_dpm_table(
641                         &data->dpm_table.vddc_table,
642                                 smum_get_mac_definition(hwmgr,
643                                         SMU_MAX_LEVELS_VDDC),
644                                         MAX_REGULAR_DPM_NUMBER);
645         phm_reset_single_dpm_table(
646                         &data->dpm_table.vddci_table,
647                         smum_get_mac_definition(hwmgr,
648                                 SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER);
649
650         phm_reset_single_dpm_table(
651                         &data->dpm_table.mvdd_table,
652                                 smum_get_mac_definition(hwmgr,
653                                         SMU_MAX_LEVELS_MVDD),
654                                         MAX_REGULAR_DPM_NUMBER);
655         return 0;
656 }
657 /*
658  * This function is to initialize all DPM state tables
659  * for SMU7 based on the dependency table.
660  * Dynamic state patching function will then trim these
661  * state tables to the allowed range based
662  * on the power policy or external client requests,
663  * such as UVD request, etc.
664  */
665
666 static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr)
667 {
668         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
669         struct phm_clock_voltage_dependency_table *allowed_vdd_sclk_table =
670                 hwmgr->dyn_state.vddc_dependency_on_sclk;
671         struct phm_clock_voltage_dependency_table *allowed_vdd_mclk_table =
672                 hwmgr->dyn_state.vddc_dependency_on_mclk;
673         struct phm_cac_leakage_table *std_voltage_table =
674                 hwmgr->dyn_state.cac_leakage_table;
675         uint32_t i;
676
677         PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
678                 "SCLK dependency table is missing. This table is mandatory", return -EINVAL);
679         PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1,
680                 "SCLK dependency table has to have is missing. This table is mandatory", return -EINVAL);
681
682         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
683                 "MCLK dependency table is missing. This table is mandatory", return -EINVAL);
684         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1,
685                 "VMCLK dependency table has to have is missing. This table is mandatory", return -EINVAL);
686
687
688         /* Initialize Sclk DPM table based on allow Sclk values*/
689         data->dpm_table.sclk_table.count = 0;
690
691         for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
692                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value !=
693                                 allowed_vdd_sclk_table->entries[i].clk) {
694                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
695                                 allowed_vdd_sclk_table->entries[i].clk;
696                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0;
697                         data->dpm_table.sclk_table.count++;
698                 }
699         }
700
701         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
702                 "MCLK dependency table is missing. This table is mandatory", return -EINVAL);
703         /* Initialize Mclk DPM table based on allow Mclk values */
704         data->dpm_table.mclk_table.count = 0;
705         for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
706                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value !=
707                         allowed_vdd_mclk_table->entries[i].clk) {
708                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
709                                 allowed_vdd_mclk_table->entries[i].clk;
710                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0;
711                         data->dpm_table.mclk_table.count++;
712                 }
713         }
714
715         /* Initialize Vddc DPM table based on allow Vddc values.  And populate corresponding std values. */
716         for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
717                 data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
718                 data->dpm_table.vddc_table.dpm_levels[i].param1 = std_voltage_table->entries[i].Leakage;
719                 /* param1 is for corresponding std voltage */
720                 data->dpm_table.vddc_table.dpm_levels[i].enabled = 1;
721         }
722
723         data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count;
724         allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
725
726         if (NULL != allowed_vdd_mclk_table) {
727                 /* Initialize Vddci DPM table based on allow Mclk values */
728                 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
729                         data->dpm_table.vddci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
730                         data->dpm_table.vddci_table.dpm_levels[i].enabled = 1;
731                 }
732                 data->dpm_table.vddci_table.count = allowed_vdd_mclk_table->count;
733         }
734
735         allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk;
736
737         if (NULL != allowed_vdd_mclk_table) {
738                 /*
739                  * Initialize MVDD DPM table based on allow Mclk
740                  * values
741                  */
742                 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
743                         data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
744                         data->dpm_table.mvdd_table.dpm_levels[i].enabled = 1;
745                 }
746                 data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count;
747         }
748
749         return 0;
750 }
751
752 static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr)
753 {
754         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
755         struct phm_ppt_v1_information *table_info =
756                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
757         uint32_t i;
758
759         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
760         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
761
762         if (table_info == NULL)
763                 return -EINVAL;
764
765         dep_sclk_table = table_info->vdd_dep_on_sclk;
766         dep_mclk_table = table_info->vdd_dep_on_mclk;
767
768         PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
769                         "SCLK dependency table is missing.",
770                         return -EINVAL);
771         PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
772                         "SCLK dependency table count is 0.",
773                         return -EINVAL);
774
775         PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
776                         "MCLK dependency table is missing.",
777                         return -EINVAL);
778         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
779                         "MCLK dependency table count is 0",
780                         return -EINVAL);
781
782         /* Initialize Sclk DPM table based on allow Sclk values */
783         data->dpm_table.sclk_table.count = 0;
784         for (i = 0; i < dep_sclk_table->count; i++) {
785                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
786                                                 dep_sclk_table->entries[i].clk) {
787
788                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
789                                         dep_sclk_table->entries[i].clk;
790
791                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
792                                         (i == 0) ? true : false;
793                         data->dpm_table.sclk_table.count++;
794                 }
795         }
796         if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0)
797                 hwmgr->platform_descriptor.overdriveLimit.engineClock = dep_sclk_table->entries[i-1].clk;
798         /* Initialize Mclk DPM table based on allow Mclk values */
799         data->dpm_table.mclk_table.count = 0;
800         for (i = 0; i < dep_mclk_table->count; i++) {
801                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
802                                 [data->dpm_table.mclk_table.count - 1].value !=
803                                                 dep_mclk_table->entries[i].clk) {
804                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
805                                                         dep_mclk_table->entries[i].clk;
806                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
807                                                         (i == 0) ? true : false;
808                         data->dpm_table.mclk_table.count++;
809                 }
810         }
811
812         if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0)
813                 hwmgr->platform_descriptor.overdriveLimit.memoryClock = dep_mclk_table->entries[i-1].clk;
814         return 0;
815 }
816
817 static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
818 {
819         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
820         struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
821         struct phm_ppt_v1_information *table_info =
822                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
823         uint32_t i;
824
825         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
826         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
827         struct phm_odn_performance_level *entries;
828
829         if (table_info == NULL)
830                 return -EINVAL;
831
832         dep_sclk_table = table_info->vdd_dep_on_sclk;
833         dep_mclk_table = table_info->vdd_dep_on_mclk;
834
835         odn_table->odn_core_clock_dpm_levels.num_of_pl =
836                                                 data->golden_dpm_table.sclk_table.count;
837         entries = odn_table->odn_core_clock_dpm_levels.entries;
838         for (i=0; i<data->golden_dpm_table.sclk_table.count; i++) {
839                 entries[i].clock = data->golden_dpm_table.sclk_table.dpm_levels[i].value;
840                 entries[i].enabled = true;
841                 entries[i].vddc = dep_sclk_table->entries[i].vddc;
842         }
843
844         smu_get_voltage_dependency_table_ppt_v1(dep_sclk_table,
845                 (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk));
846
847         odn_table->odn_memory_clock_dpm_levels.num_of_pl =
848                                                 data->golden_dpm_table.mclk_table.count;
849         entries = odn_table->odn_memory_clock_dpm_levels.entries;
850         for (i=0; i<data->golden_dpm_table.mclk_table.count; i++) {
851                 entries[i].clock = data->golden_dpm_table.mclk_table.dpm_levels[i].value;
852                 entries[i].enabled = true;
853                 entries[i].vddc = dep_mclk_table->entries[i].vddc;
854         }
855
856         smu_get_voltage_dependency_table_ppt_v1(dep_mclk_table,
857                 (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk));
858
859         return 0;
860 }
861
862 static void smu7_setup_voltage_range_from_vbios(struct pp_hwmgr *hwmgr)
863 {
864         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
865         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
866         struct phm_ppt_v1_information *table_info =
867                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
868         uint32_t min_vddc = 0;
869         uint32_t max_vddc = 0;
870
871         if (!table_info)
872                 return;
873
874         dep_sclk_table = table_info->vdd_dep_on_sclk;
875
876         atomctrl_get_voltage_range(hwmgr, &max_vddc, &min_vddc);
877
878         if (min_vddc == 0 || min_vddc > 2000
879                 || min_vddc > dep_sclk_table->entries[0].vddc)
880                 min_vddc = dep_sclk_table->entries[0].vddc;
881
882         if (max_vddc == 0 || max_vddc > 2000
883                 || max_vddc < dep_sclk_table->entries[dep_sclk_table->count-1].vddc)
884                 max_vddc = dep_sclk_table->entries[dep_sclk_table->count-1].vddc;
885
886         data->odn_dpm_table.min_vddc = min_vddc;
887         data->odn_dpm_table.max_vddc = max_vddc;
888 }
889
890 static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
891 {
892         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
893         struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
894         struct phm_ppt_v1_information *table_info =
895                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
896         uint32_t i;
897
898         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
899         struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table;
900
901         if (table_info == NULL)
902                 return;
903
904         for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
905                 if (odn_table->odn_core_clock_dpm_levels.entries[i].clock !=
906                                         data->dpm_table.sclk_table.dpm_levels[i].value) {
907                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
908                         break;
909                 }
910         }
911
912         for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
913                 if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock !=
914                                         data->dpm_table.mclk_table.dpm_levels[i].value) {
915                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
916                         break;
917                 }
918         }
919
920         dep_table = table_info->vdd_dep_on_mclk;
921         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk);
922
923         for (i = 0; i < dep_table->count; i++) {
924                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
925                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK;
926                         return;
927                 }
928         }
929
930         dep_table = table_info->vdd_dep_on_sclk;
931         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk);
932         for (i = 0; i < dep_table->count; i++) {
933                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
934                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK;
935                         return;
936                 }
937         }
938         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
939                 data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC;
940                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK;
941         }
942 }
943
944 static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
945 {
946         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
947
948         smu7_reset_dpm_tables(hwmgr);
949
950         if (hwmgr->pp_table_version == PP_TABLE_V1)
951                 smu7_setup_dpm_tables_v1(hwmgr);
952         else if (hwmgr->pp_table_version == PP_TABLE_V0)
953                 smu7_setup_dpm_tables_v0(hwmgr);
954
955         smu7_setup_default_pcie_table(hwmgr);
956
957         /* save a copy of the default DPM table */
958         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
959                         sizeof(struct smu7_dpm_table));
960
961         /* initialize ODN table */
962         if (hwmgr->od_enabled) {
963                 if (data->odn_dpm_table.max_vddc) {
964                         smu7_check_dpm_table_updated(hwmgr);
965                 } else {
966                         smu7_setup_voltage_range_from_vbios(hwmgr);
967                         smu7_odn_initial_default_setting(hwmgr);
968                 }
969         }
970         return 0;
971 }
972
973 static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
974 {
975
976         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
977                         PHM_PlatformCaps_RegulatorHot))
978                 return smum_send_msg_to_smc(hwmgr,
979                                 PPSMC_MSG_EnableVRHotGPIOInterrupt);
980
981         return 0;
982 }
983
984 static int smu7_enable_sclk_control(struct pp_hwmgr *hwmgr)
985 {
986         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
987                         SCLK_PWRMGT_OFF, 0);
988         return 0;
989 }
990
991 static int smu7_enable_ulv(struct pp_hwmgr *hwmgr)
992 {
993         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
994
995         if (data->ulv_supported)
996                 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableULV);
997
998         return 0;
999 }
1000
1001 static int smu7_disable_ulv(struct pp_hwmgr *hwmgr)
1002 {
1003         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1004
1005         if (data->ulv_supported)
1006                 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableULV);
1007
1008         return 0;
1009 }
1010
1011 static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
1012 {
1013         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1014                         PHM_PlatformCaps_SclkDeepSleep)) {
1015                 if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MASTER_DeepSleep_ON))
1016                         PP_ASSERT_WITH_CODE(false,
1017                                         "Attempt to enable Master Deep Sleep switch failed!",
1018                                         return -EINVAL);
1019         } else {
1020                 if (smum_send_msg_to_smc(hwmgr,
1021                                 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
1022                         PP_ASSERT_WITH_CODE(false,
1023                                         "Attempt to disable Master Deep Sleep switch failed!",
1024                                         return -EINVAL);
1025                 }
1026         }
1027
1028         return 0;
1029 }
1030
1031 static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
1032 {
1033         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1034                         PHM_PlatformCaps_SclkDeepSleep)) {
1035                 if (smum_send_msg_to_smc(hwmgr,
1036                                 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
1037                         PP_ASSERT_WITH_CODE(false,
1038                                         "Attempt to disable Master Deep Sleep switch failed!",
1039                                         return -EINVAL);
1040                 }
1041         }
1042
1043         return 0;
1044 }
1045
1046 static int smu7_disable_sclk_vce_handshake(struct pp_hwmgr *hwmgr)
1047 {
1048         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1049         uint32_t soft_register_value = 0;
1050         uint32_t handshake_disables_offset = data->soft_regs_start
1051                                 + smum_get_offsetof(hwmgr,
1052                                         SMU_SoftRegisters, HandshakeDisables);
1053
1054         soft_register_value = cgs_read_ind_register(hwmgr->device,
1055                                 CGS_IND_REG__SMC, handshake_disables_offset);
1056         soft_register_value |= SMU7_VCE_SCLK_HANDSHAKE_DISABLE;
1057         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1058                         handshake_disables_offset, soft_register_value);
1059         return 0;
1060 }
1061
1062 static int smu7_disable_handshake_uvd(struct pp_hwmgr *hwmgr)
1063 {
1064         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1065         uint32_t soft_register_value = 0;
1066         uint32_t handshake_disables_offset = data->soft_regs_start
1067                                 + smum_get_offsetof(hwmgr,
1068                                         SMU_SoftRegisters, HandshakeDisables);
1069
1070         soft_register_value = cgs_read_ind_register(hwmgr->device,
1071                                 CGS_IND_REG__SMC, handshake_disables_offset);
1072         soft_register_value |= smum_get_mac_definition(hwmgr,
1073                                         SMU_UVD_MCLK_HANDSHAKE_DISABLE);
1074         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1075                         handshake_disables_offset, soft_register_value);
1076         return 0;
1077 }
1078
1079 static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
1080 {
1081         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1082
1083         /* enable SCLK dpm */
1084         if (!data->sclk_dpm_key_disabled) {
1085                 if (hwmgr->chip_id == CHIP_VEGAM)
1086                         smu7_disable_sclk_vce_handshake(hwmgr);
1087
1088                 PP_ASSERT_WITH_CODE(
1089                 (0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Enable)),
1090                 "Failed to enable SCLK DPM during DPM Start Function!",
1091                 return -EINVAL);
1092         }
1093
1094         /* enable MCLK dpm */
1095         if (0 == data->mclk_dpm_key_disabled) {
1096                 if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK))
1097                         smu7_disable_handshake_uvd(hwmgr);
1098
1099                 PP_ASSERT_WITH_CODE(
1100                                 (0 == smum_send_msg_to_smc(hwmgr,
1101                                                 PPSMC_MSG_MCLKDPM_Enable)),
1102                                 "Failed to enable MCLK DPM during DPM Start Function!",
1103                                 return -EINVAL);
1104
1105                 if (hwmgr->chip_family != CHIP_VEGAM)
1106                         PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
1107
1108
1109                 if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
1110                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x5);
1111                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x5);
1112                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x100005);
1113                         udelay(10);
1114                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x400005);
1115                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x400005);
1116                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x500005);
1117                 } else {
1118                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
1119                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
1120                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
1121                         udelay(10);
1122                         if (hwmgr->chip_id == CHIP_VEGAM) {
1123                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400009);
1124                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400009);
1125                         } else {
1126                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
1127                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
1128                         }
1129                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
1130                 }
1131         }
1132
1133         return 0;
1134 }
1135
1136 static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
1137 {
1138         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1139
1140         /*enable general power management */
1141
1142         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1143                         GLOBAL_PWRMGT_EN, 1);
1144
1145         /* enable sclk deep sleep */
1146
1147         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1148                         DYNAMIC_PM_EN, 1);
1149
1150         /* prepare for PCIE DPM */
1151
1152         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1153                         data->soft_regs_start +
1154                         smum_get_offsetof(hwmgr, SMU_SoftRegisters,
1155                                                 VoltageChangeTimeout), 0x1000);
1156         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
1157                         SWRST_COMMAND_1, RESETLC, 0x0);
1158
1159         if (hwmgr->chip_family == AMDGPU_FAMILY_CI)
1160                 cgs_write_register(hwmgr->device, 0x1488,
1161                         (cgs_read_register(hwmgr->device, 0x1488) & ~0x1));
1162
1163         if (smu7_enable_sclk_mclk_dpm(hwmgr)) {
1164                 pr_err("Failed to enable Sclk DPM and Mclk DPM!");
1165                 return -EINVAL;
1166         }
1167
1168         /* enable PCIE dpm */
1169         if (0 == data->pcie_dpm_key_disabled) {
1170                 PP_ASSERT_WITH_CODE(
1171                                 (0 == smum_send_msg_to_smc(hwmgr,
1172                                                 PPSMC_MSG_PCIeDPM_Enable)),
1173                                 "Failed to enable pcie DPM during DPM Start Function!",
1174                                 return -EINVAL);
1175         }
1176
1177         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1178                                 PHM_PlatformCaps_Falcon_QuickTransition)) {
1179                 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr,
1180                                 PPSMC_MSG_EnableACDCGPIOInterrupt)),
1181                                 "Failed to enable AC DC GPIO Interrupt!",
1182                                 );
1183         }
1184
1185         return 0;
1186 }
1187
1188 static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
1189 {
1190         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1191
1192         /* disable SCLK dpm */
1193         if (!data->sclk_dpm_key_disabled) {
1194                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1195                                 "Trying to disable SCLK DPM when DPM is disabled",
1196                                 return 0);
1197                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Disable);
1198         }
1199
1200         /* disable MCLK dpm */
1201         if (!data->mclk_dpm_key_disabled) {
1202                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1203                                 "Trying to disable MCLK DPM when DPM is disabled",
1204                                 return 0);
1205                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_Disable);
1206         }
1207
1208         return 0;
1209 }
1210
1211 static int smu7_stop_dpm(struct pp_hwmgr *hwmgr)
1212 {
1213         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1214
1215         /* disable general power management */
1216         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1217                         GLOBAL_PWRMGT_EN, 0);
1218         /* disable sclk deep sleep */
1219         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1220                         DYNAMIC_PM_EN, 0);
1221
1222         /* disable PCIE dpm */
1223         if (!data->pcie_dpm_key_disabled) {
1224                 PP_ASSERT_WITH_CODE(
1225                                 (smum_send_msg_to_smc(hwmgr,
1226                                                 PPSMC_MSG_PCIeDPM_Disable) == 0),
1227                                 "Failed to disable pcie DPM during DPM Stop Function!",
1228                                 return -EINVAL);
1229         }
1230
1231         smu7_disable_sclk_mclk_dpm(hwmgr);
1232
1233         PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1234                         "Trying to disable voltage DPM when DPM is disabled",
1235                         return 0);
1236
1237         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Disable);
1238
1239         return 0;
1240 }
1241
1242 static void smu7_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
1243 {
1244         bool protection;
1245         enum DPM_EVENT_SRC src;
1246
1247         switch (sources) {
1248         default:
1249                 pr_err("Unknown throttling event sources.");
1250                 /* fall through */
1251         case 0:
1252                 protection = false;
1253                 /* src is unused */
1254                 break;
1255         case (1 << PHM_AutoThrottleSource_Thermal):
1256                 protection = true;
1257                 src = DPM_EVENT_SRC_DIGITAL;
1258                 break;
1259         case (1 << PHM_AutoThrottleSource_External):
1260                 protection = true;
1261                 src = DPM_EVENT_SRC_EXTERNAL;
1262                 break;
1263         case (1 << PHM_AutoThrottleSource_External) |
1264                         (1 << PHM_AutoThrottleSource_Thermal):
1265                 protection = true;
1266                 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
1267                 break;
1268         }
1269         /* Order matters - don't enable thermal protection for the wrong source. */
1270         if (protection) {
1271                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
1272                                 DPM_EVENT_SRC, src);
1273                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1274                                 THERMAL_PROTECTION_DIS,
1275                                 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1276                                                 PHM_PlatformCaps_ThermalController));
1277         } else
1278                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1279                                 THERMAL_PROTECTION_DIS, 1);
1280 }
1281
1282 static int smu7_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
1283                 PHM_AutoThrottleSource source)
1284 {
1285         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1286
1287         if (!(data->active_auto_throttle_sources & (1 << source))) {
1288                 data->active_auto_throttle_sources |= 1 << source;
1289                 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
1290         }
1291         return 0;
1292 }
1293
1294 static int smu7_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
1295 {
1296         return smu7_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
1297 }
1298
1299 static int smu7_disable_auto_throttle_source(struct pp_hwmgr *hwmgr,
1300                 PHM_AutoThrottleSource source)
1301 {
1302         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1303
1304         if (data->active_auto_throttle_sources & (1 << source)) {
1305                 data->active_auto_throttle_sources &= ~(1 << source);
1306                 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
1307         }
1308         return 0;
1309 }
1310
1311 static int smu7_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
1312 {
1313         return smu7_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
1314 }
1315
1316 static int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr)
1317 {
1318         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1319         data->pcie_performance_request = true;
1320
1321         return 0;
1322 }
1323
1324 static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1325 {
1326         int tmp_result = 0;
1327         int result = 0;
1328
1329         if (smu7_voltage_control(hwmgr)) {
1330                 tmp_result = smu7_enable_voltage_control(hwmgr);
1331                 PP_ASSERT_WITH_CODE(tmp_result == 0,
1332                                 "Failed to enable voltage control!",
1333                                 result = tmp_result);
1334
1335                 tmp_result = smu7_construct_voltage_tables(hwmgr);
1336                 PP_ASSERT_WITH_CODE((0 == tmp_result),
1337                                 "Failed to construct voltage tables!",
1338                                 result = tmp_result);
1339         }
1340         smum_initialize_mc_reg_table(hwmgr);
1341
1342         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1343                         PHM_PlatformCaps_EngineSpreadSpectrumSupport))
1344                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1345                                 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
1346
1347         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1348                         PHM_PlatformCaps_ThermalController))
1349                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1350                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
1351
1352         tmp_result = smu7_program_static_screen_threshold_parameters(hwmgr);
1353         PP_ASSERT_WITH_CODE((0 == tmp_result),
1354                         "Failed to program static screen threshold parameters!",
1355                         result = tmp_result);
1356
1357         tmp_result = smu7_enable_display_gap(hwmgr);
1358         PP_ASSERT_WITH_CODE((0 == tmp_result),
1359                         "Failed to enable display gap!", result = tmp_result);
1360
1361         tmp_result = smu7_program_voting_clients(hwmgr);
1362         PP_ASSERT_WITH_CODE((0 == tmp_result),
1363                         "Failed to program voting clients!", result = tmp_result);
1364
1365         tmp_result = smum_process_firmware_header(hwmgr);
1366         PP_ASSERT_WITH_CODE((0 == tmp_result),
1367                         "Failed to process firmware header!", result = tmp_result);
1368
1369         if (hwmgr->chip_id != CHIP_VEGAM) {
1370                 tmp_result = smu7_initial_switch_from_arbf0_to_f1(hwmgr);
1371                 PP_ASSERT_WITH_CODE((0 == tmp_result),
1372                                 "Failed to initialize switch from ArbF0 to F1!",
1373                                 result = tmp_result);
1374         }
1375
1376         result = smu7_setup_default_dpm_tables(hwmgr);
1377         PP_ASSERT_WITH_CODE(0 == result,
1378                         "Failed to setup default DPM tables!", return result);
1379
1380         tmp_result = smum_init_smc_table(hwmgr);
1381         PP_ASSERT_WITH_CODE((0 == tmp_result),
1382                         "Failed to initialize SMC table!", result = tmp_result);
1383
1384         tmp_result = smu7_enable_vrhot_gpio_interrupt(hwmgr);
1385         PP_ASSERT_WITH_CODE((0 == tmp_result),
1386                         "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
1387
1388         smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay);
1389
1390         tmp_result = smu7_enable_sclk_control(hwmgr);
1391         PP_ASSERT_WITH_CODE((0 == tmp_result),
1392                         "Failed to enable SCLK control!", result = tmp_result);
1393
1394         tmp_result = smu7_enable_smc_voltage_controller(hwmgr);
1395         PP_ASSERT_WITH_CODE((0 == tmp_result),
1396                         "Failed to enable voltage control!", result = tmp_result);
1397
1398         tmp_result = smu7_enable_ulv(hwmgr);
1399         PP_ASSERT_WITH_CODE((0 == tmp_result),
1400                         "Failed to enable ULV!", result = tmp_result);
1401
1402         tmp_result = smu7_enable_deep_sleep_master_switch(hwmgr);
1403         PP_ASSERT_WITH_CODE((0 == tmp_result),
1404                         "Failed to enable deep sleep master switch!", result = tmp_result);
1405
1406         tmp_result = smu7_enable_didt_config(hwmgr);
1407         PP_ASSERT_WITH_CODE((tmp_result == 0),
1408                         "Failed to enable deep sleep master switch!", result = tmp_result);
1409
1410         tmp_result = smu7_start_dpm(hwmgr);
1411         PP_ASSERT_WITH_CODE((0 == tmp_result),
1412                         "Failed to start DPM!", result = tmp_result);
1413
1414         tmp_result = smu7_enable_smc_cac(hwmgr);
1415         PP_ASSERT_WITH_CODE((0 == tmp_result),
1416                         "Failed to enable SMC CAC!", result = tmp_result);
1417
1418         tmp_result = smu7_enable_power_containment(hwmgr);
1419         PP_ASSERT_WITH_CODE((0 == tmp_result),
1420                         "Failed to enable power containment!", result = tmp_result);
1421
1422         tmp_result = smu7_power_control_set_level(hwmgr);
1423         PP_ASSERT_WITH_CODE((0 == tmp_result),
1424                         "Failed to power control set level!", result = tmp_result);
1425
1426         tmp_result = smu7_enable_thermal_auto_throttle(hwmgr);
1427         PP_ASSERT_WITH_CODE((0 == tmp_result),
1428                         "Failed to enable thermal auto throttle!", result = tmp_result);
1429
1430         tmp_result = smu7_pcie_performance_request(hwmgr);
1431         PP_ASSERT_WITH_CODE((0 == tmp_result),
1432                         "pcie performance request failed!", result = tmp_result);
1433
1434         return 0;
1435 }
1436
1437 static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
1438 {
1439         if (!hwmgr->avfs_supported)
1440                 return 0;
1441
1442         if (enable) {
1443                 if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
1444                                 CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
1445                         PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
1446                                         hwmgr, PPSMC_MSG_EnableAvfs),
1447                                         "Failed to enable AVFS!",
1448                                         return -EINVAL);
1449                 }
1450         } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
1451                         CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
1452                 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
1453                                 hwmgr, PPSMC_MSG_DisableAvfs),
1454                                 "Failed to disable AVFS!",
1455                                 return -EINVAL);
1456         }
1457
1458         return 0;
1459 }
1460
1461 static int smu7_update_avfs(struct pp_hwmgr *hwmgr)
1462 {
1463         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1464
1465         if (!hwmgr->avfs_supported)
1466                 return 0;
1467
1468         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
1469                 smu7_avfs_control(hwmgr, false);
1470         } else if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
1471                 smu7_avfs_control(hwmgr, false);
1472                 smu7_avfs_control(hwmgr, true);
1473         } else {
1474                 smu7_avfs_control(hwmgr, true);
1475         }
1476
1477         return 0;
1478 }
1479
1480 int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
1481 {
1482         int tmp_result, result = 0;
1483
1484         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1485                         PHM_PlatformCaps_ThermalController))
1486                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1487                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1);
1488
1489         tmp_result = smu7_disable_power_containment(hwmgr);
1490         PP_ASSERT_WITH_CODE((tmp_result == 0),
1491                         "Failed to disable power containment!", result = tmp_result);
1492
1493         tmp_result = smu7_disable_smc_cac(hwmgr);
1494         PP_ASSERT_WITH_CODE((tmp_result == 0),
1495                         "Failed to disable SMC CAC!", result = tmp_result);
1496
1497         tmp_result = smu7_disable_didt_config(hwmgr);
1498         PP_ASSERT_WITH_CODE((tmp_result == 0),
1499                         "Failed to disable DIDT!", result = tmp_result);
1500
1501         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1502                         CG_SPLL_SPREAD_SPECTRUM, SSEN, 0);
1503         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1504                         GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0);
1505
1506         tmp_result = smu7_disable_thermal_auto_throttle(hwmgr);
1507         PP_ASSERT_WITH_CODE((tmp_result == 0),
1508                         "Failed to disable thermal auto throttle!", result = tmp_result);
1509
1510         tmp_result = smu7_avfs_control(hwmgr, false);
1511         PP_ASSERT_WITH_CODE((tmp_result == 0),
1512                         "Failed to disable AVFS!", result = tmp_result);
1513
1514         tmp_result = smu7_stop_dpm(hwmgr);
1515         PP_ASSERT_WITH_CODE((tmp_result == 0),
1516                         "Failed to stop DPM!", result = tmp_result);
1517
1518         tmp_result = smu7_disable_deep_sleep_master_switch(hwmgr);
1519         PP_ASSERT_WITH_CODE((tmp_result == 0),
1520                         "Failed to disable deep sleep master switch!", result = tmp_result);
1521
1522         tmp_result = smu7_disable_ulv(hwmgr);
1523         PP_ASSERT_WITH_CODE((tmp_result == 0),
1524                         "Failed to disable ULV!", result = tmp_result);
1525
1526         tmp_result = smu7_clear_voting_clients(hwmgr);
1527         PP_ASSERT_WITH_CODE((tmp_result == 0),
1528                         "Failed to clear voting clients!", result = tmp_result);
1529
1530         tmp_result = smu7_reset_to_default(hwmgr);
1531         PP_ASSERT_WITH_CODE((tmp_result == 0),
1532                         "Failed to reset to default!", result = tmp_result);
1533
1534         tmp_result = smu7_force_switch_to_arbf0(hwmgr);
1535         PP_ASSERT_WITH_CODE((tmp_result == 0),
1536                         "Failed to force to switch arbf0!", result = tmp_result);
1537
1538         return result;
1539 }
1540
1541 int smu7_reset_asic_tasks(struct pp_hwmgr *hwmgr)
1542 {
1543
1544         return 0;
1545 }
1546
1547 static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
1548 {
1549         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1550         struct phm_ppt_v1_information *table_info =
1551                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1552         struct amdgpu_device *adev = hwmgr->adev;
1553
1554         data->dll_default_on = false;
1555         data->mclk_dpm0_activity_target = 0xa;
1556         data->vddc_vddgfx_delta = 300;
1557         data->static_screen_threshold = SMU7_STATICSCREENTHRESHOLD_DFLT;
1558         data->static_screen_threshold_unit = SMU7_STATICSCREENTHRESHOLDUNIT_DFLT;
1559         data->voting_rights_clients[0] = SMU7_VOTINGRIGHTSCLIENTS_DFLT0;
1560         data->voting_rights_clients[1]= SMU7_VOTINGRIGHTSCLIENTS_DFLT1;
1561         data->voting_rights_clients[2] = SMU7_VOTINGRIGHTSCLIENTS_DFLT2;
1562         data->voting_rights_clients[3]= SMU7_VOTINGRIGHTSCLIENTS_DFLT3;
1563         data->voting_rights_clients[4]= SMU7_VOTINGRIGHTSCLIENTS_DFLT4;
1564         data->voting_rights_clients[5]= SMU7_VOTINGRIGHTSCLIENTS_DFLT5;
1565         data->voting_rights_clients[6]= SMU7_VOTINGRIGHTSCLIENTS_DFLT6;
1566         data->voting_rights_clients[7]= SMU7_VOTINGRIGHTSCLIENTS_DFLT7;
1567
1568         data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
1569         data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
1570         data->pcie_dpm_key_disabled = hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
1571         /* need to set voltage control types before EVV patching */
1572         data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE;
1573         data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE;
1574         data->mvdd_control = SMU7_VOLTAGE_CONTROL_NONE;
1575         data->enable_tdc_limit_feature = true;
1576         data->enable_pkg_pwr_tracking_feature = true;
1577         data->force_pcie_gen = PP_PCIEGenInvalid;
1578         data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false;
1579         data->current_profile_setting.bupdate_sclk = 1;
1580         data->current_profile_setting.sclk_up_hyst = 0;
1581         data->current_profile_setting.sclk_down_hyst = 100;
1582         data->current_profile_setting.sclk_activity = SMU7_SCLK_TARGETACTIVITY_DFLT;
1583         data->current_profile_setting.bupdate_mclk = 1;
1584         data->current_profile_setting.mclk_up_hyst = 0;
1585         data->current_profile_setting.mclk_down_hyst = 100;
1586         data->current_profile_setting.mclk_activity = SMU7_MCLK_TARGETACTIVITY_DFLT;
1587         hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D];
1588         hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1589         hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1590
1591         if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker) {
1592                 uint8_t tmp1, tmp2;
1593                 uint16_t tmp3 = 0;
1594                 atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2,
1595                                                 &tmp3);
1596                 tmp3 = (tmp3 >> 5) & 0x3;
1597                 data->vddc_phase_shed_control = ((tmp3 << 1) | (tmp3 >> 1)) & 0x3;
1598         } else if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
1599                 data->vddc_phase_shed_control = 1;
1600         } else {
1601                 data->vddc_phase_shed_control = 0;
1602         }
1603
1604         if (hwmgr->chip_id  == CHIP_HAWAII) {
1605                 data->thermal_temp_setting.temperature_low = 94500;
1606                 data->thermal_temp_setting.temperature_high = 95000;
1607                 data->thermal_temp_setting.temperature_shutdown = 104000;
1608         } else {
1609                 data->thermal_temp_setting.temperature_low = 99500;
1610                 data->thermal_temp_setting.temperature_high = 100000;
1611                 data->thermal_temp_setting.temperature_shutdown = 104000;
1612         }
1613
1614         data->fast_watermark_threshold = 100;
1615         if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1616                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
1617                 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1618         else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1619                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
1620                 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1621
1622         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1623                         PHM_PlatformCaps_ControlVDDGFX)) {
1624                 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1625                         VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) {
1626                         data->vdd_gfx_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1627                 }
1628         }
1629
1630         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1631                         PHM_PlatformCaps_EnableMVDDControl)) {
1632                 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1633                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
1634                         data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1635                 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1636                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
1637                         data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1638         }
1639
1640         if (SMU7_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control)
1641                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1642                         PHM_PlatformCaps_ControlVDDGFX);
1643
1644         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1645                         PHM_PlatformCaps_ControlVDDCI)) {
1646                 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1647                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
1648                         data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1649                 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1650                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
1651                         data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1652         }
1653
1654         if (data->mvdd_control == SMU7_VOLTAGE_CONTROL_NONE)
1655                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1656                                 PHM_PlatformCaps_EnableMVDDControl);
1657
1658         if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE)
1659                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1660                                 PHM_PlatformCaps_ControlVDDCI);
1661
1662         if ((hwmgr->pp_table_version != PP_TABLE_V0) && (hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK)
1663                 && (table_info->cac_dtp_table->usClockStretchAmount != 0))
1664                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1665                                         PHM_PlatformCaps_ClockStretcher);
1666
1667         data->pcie_gen_performance.max = PP_PCIEGen1;
1668         data->pcie_gen_performance.min = PP_PCIEGen3;
1669         data->pcie_gen_power_saving.max = PP_PCIEGen1;
1670         data->pcie_gen_power_saving.min = PP_PCIEGen3;
1671         data->pcie_lane_performance.max = 0;
1672         data->pcie_lane_performance.min = 16;
1673         data->pcie_lane_power_saving.max = 0;
1674         data->pcie_lane_power_saving.min = 16;
1675
1676
1677         if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
1678                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1679                               PHM_PlatformCaps_UVDPowerGating);
1680         if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
1681                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1682                               PHM_PlatformCaps_VCEPowerGating);
1683 }
1684
1685 /**
1686 * Get Leakage VDDC based on leakage ID.
1687 *
1688 * @param    hwmgr  the address of the powerplay hardware manager.
1689 * @return   always 0
1690 */
1691 static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr)
1692 {
1693         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1694         uint16_t vv_id;
1695         uint16_t vddc = 0;
1696         uint16_t vddgfx = 0;
1697         uint16_t i, j;
1698         uint32_t sclk = 0;
1699         struct phm_ppt_v1_information *table_info =
1700                         (struct phm_ppt_v1_information *)hwmgr->pptable;
1701         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = NULL;
1702
1703
1704         for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
1705                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1706
1707                 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1708                         if ((hwmgr->pp_table_version == PP_TABLE_V1)
1709                             && !phm_get_sclk_for_voltage_evv(hwmgr,
1710                                                 table_info->vddgfx_lookup_table, vv_id, &sclk)) {
1711                                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1712                                                         PHM_PlatformCaps_ClockStretcher)) {
1713                                         sclk_table = table_info->vdd_dep_on_sclk;
1714
1715                                         for (j = 1; j < sclk_table->count; j++) {
1716                                                 if (sclk_table->entries[j].clk == sclk &&
1717                                                                 sclk_table->entries[j].cks_enable == 0) {
1718                                                         sclk += 5000;
1719                                                         break;
1720                                                 }
1721                                         }
1722                                 }
1723                                 if (0 == atomctrl_get_voltage_evv_on_sclk
1724                                     (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk,
1725                                      vv_id, &vddgfx)) {
1726                                         /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */
1727                                         PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -EINVAL);
1728
1729                                         /* the voltage should not be zero nor equal to leakage ID */
1730                                         if (vddgfx != 0 && vddgfx != vv_id) {
1731                                                 data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx;
1732                                                 data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = vv_id;
1733                                                 data->vddcgfx_leakage.count++;
1734                                         }
1735                                 } else {
1736                                         pr_info("Error retrieving EVV voltage value!\n");
1737                                 }
1738                         }
1739                 } else {
1740                         if ((hwmgr->pp_table_version == PP_TABLE_V0)
1741                                 || !phm_get_sclk_for_voltage_evv(hwmgr,
1742                                         table_info->vddc_lookup_table, vv_id, &sclk)) {
1743                                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1744                                                 PHM_PlatformCaps_ClockStretcher)) {
1745                                         if (table_info == NULL)
1746                                                 return -EINVAL;
1747                                         sclk_table = table_info->vdd_dep_on_sclk;
1748
1749                                         for (j = 1; j < sclk_table->count; j++) {
1750                                                 if (sclk_table->entries[j].clk == sclk &&
1751                                                                 sclk_table->entries[j].cks_enable == 0) {
1752                                                         sclk += 5000;
1753                                                         break;
1754                                                 }
1755                                         }
1756                                 }
1757
1758                                 if (phm_get_voltage_evv_on_sclk(hwmgr,
1759                                                         VOLTAGE_TYPE_VDDC,
1760                                                         sclk, vv_id, &vddc) == 0) {
1761                                         if (vddc >= 2000 || vddc == 0)
1762                                                 return -EINVAL;
1763                                 } else {
1764                                         pr_debug("failed to retrieving EVV voltage!\n");
1765                                         continue;
1766                                 }
1767
1768                                 /* the voltage should not be zero nor equal to leakage ID */
1769                                 if (vddc != 0 && vddc != vv_id) {
1770                                         data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc);
1771                                         data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
1772                                         data->vddc_leakage.count++;
1773                                 }
1774                         }
1775                 }
1776         }
1777
1778         return 0;
1779 }
1780
1781 /**
1782  * Change virtual leakage voltage to actual value.
1783  *
1784  * @param     hwmgr  the address of the powerplay hardware manager.
1785  * @param     pointer to changing voltage
1786  * @param     pointer to leakage table
1787  */
1788 static void smu7_patch_ppt_v1_with_vdd_leakage(struct pp_hwmgr *hwmgr,
1789                 uint16_t *voltage, struct smu7_leakage_voltage *leakage_table)
1790 {
1791         uint32_t index;
1792
1793         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
1794         for (index = 0; index < leakage_table->count; index++) {
1795                 /* if this voltage matches a leakage voltage ID */
1796                 /* patch with actual leakage voltage */
1797                 if (leakage_table->leakage_id[index] == *voltage) {
1798                         *voltage = leakage_table->actual_voltage[index];
1799                         break;
1800                 }
1801         }
1802
1803         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
1804                 pr_err("Voltage value looks like a Leakage ID but it's not patched \n");
1805 }
1806
1807 /**
1808 * Patch voltage lookup table by EVV leakages.
1809 *
1810 * @param     hwmgr  the address of the powerplay hardware manager.
1811 * @param     pointer to voltage lookup table
1812 * @param     pointer to leakage table
1813 * @return     always 0
1814 */
1815 static int smu7_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
1816                 phm_ppt_v1_voltage_lookup_table *lookup_table,
1817                 struct smu7_leakage_voltage *leakage_table)
1818 {
1819         uint32_t i;
1820
1821         for (i = 0; i < lookup_table->count; i++)
1822                 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr,
1823                                 &lookup_table->entries[i].us_vdd, leakage_table);
1824
1825         return 0;
1826 }
1827
1828 static int smu7_patch_clock_voltage_limits_with_vddc_leakage(
1829                 struct pp_hwmgr *hwmgr, struct smu7_leakage_voltage *leakage_table,
1830                 uint16_t *vddc)
1831 {
1832         struct phm_ppt_v1_information *table_info =
1833                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1834         smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
1835         hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
1836                         table_info->max_clock_voltage_on_dc.vddc;
1837         return 0;
1838 }
1839
1840 static int smu7_patch_voltage_dependency_tables_with_lookup_table(
1841                 struct pp_hwmgr *hwmgr)
1842 {
1843         uint8_t entry_id;
1844         uint8_t voltage_id;
1845         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1846         struct phm_ppt_v1_information *table_info =
1847                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1848
1849         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1850                         table_info->vdd_dep_on_sclk;
1851         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
1852                         table_info->vdd_dep_on_mclk;
1853         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1854                         table_info->mm_dep_table;
1855
1856         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1857                 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
1858                         voltage_id = sclk_table->entries[entry_id].vddInd;
1859                         sclk_table->entries[entry_id].vddgfx =
1860                                 table_info->vddgfx_lookup_table->entries[voltage_id].us_vdd;
1861                 }
1862         } else {
1863                 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
1864                         voltage_id = sclk_table->entries[entry_id].vddInd;
1865                         sclk_table->entries[entry_id].vddc =
1866                                 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
1867                 }
1868         }
1869
1870         for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
1871                 voltage_id = mclk_table->entries[entry_id].vddInd;
1872                 mclk_table->entries[entry_id].vddc =
1873                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
1874         }
1875
1876         for (entry_id = 0; entry_id < mm_table->count; ++entry_id) {
1877                 voltage_id = mm_table->entries[entry_id].vddcInd;
1878                 mm_table->entries[entry_id].vddc =
1879                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
1880         }
1881
1882         return 0;
1883
1884 }
1885
1886 static int phm_add_voltage(struct pp_hwmgr *hwmgr,
1887                         phm_ppt_v1_voltage_lookup_table *look_up_table,
1888                         phm_ppt_v1_voltage_lookup_record *record)
1889 {
1890         uint32_t i;
1891
1892         PP_ASSERT_WITH_CODE((NULL != look_up_table),
1893                 "Lookup Table empty.", return -EINVAL);
1894         PP_ASSERT_WITH_CODE((0 != look_up_table->count),
1895                 "Lookup Table empty.", return -EINVAL);
1896
1897         i = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
1898         PP_ASSERT_WITH_CODE((i >= look_up_table->count),
1899                 "Lookup Table is full.", return -EINVAL);
1900
1901         /* This is to avoid entering duplicate calculated records. */
1902         for (i = 0; i < look_up_table->count; i++) {
1903                 if (look_up_table->entries[i].us_vdd == record->us_vdd) {
1904                         if (look_up_table->entries[i].us_calculated == 1)
1905                                 return 0;
1906                         break;
1907                 }
1908         }
1909
1910         look_up_table->entries[i].us_calculated = 1;
1911         look_up_table->entries[i].us_vdd = record->us_vdd;
1912         look_up_table->entries[i].us_cac_low = record->us_cac_low;
1913         look_up_table->entries[i].us_cac_mid = record->us_cac_mid;
1914         look_up_table->entries[i].us_cac_high = record->us_cac_high;
1915         /* Only increment the count when we're appending, not replacing duplicate entry. */
1916         if (i == look_up_table->count)
1917                 look_up_table->count++;
1918
1919         return 0;
1920 }
1921
1922
1923 static int smu7_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
1924 {
1925         uint8_t entry_id;
1926         struct phm_ppt_v1_voltage_lookup_record v_record;
1927         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1928         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1929
1930         phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
1931         phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
1932
1933         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1934                 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
1935                         if (sclk_table->entries[entry_id].vdd_offset & (1 << 15))
1936                                 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx +
1937                                         sclk_table->entries[entry_id].vdd_offset - 0xFFFF;
1938                         else
1939                                 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx +
1940                                         sclk_table->entries[entry_id].vdd_offset;
1941
1942                         sclk_table->entries[entry_id].vddc =
1943                                 v_record.us_cac_low = v_record.us_cac_mid =
1944                                 v_record.us_cac_high = v_record.us_vdd;
1945
1946                         phm_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record);
1947                 }
1948
1949                 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
1950                         if (mclk_table->entries[entry_id].vdd_offset & (1 << 15))
1951                                 v_record.us_vdd = mclk_table->entries[entry_id].vddc +
1952                                         mclk_table->entries[entry_id].vdd_offset - 0xFFFF;
1953                         else
1954                                 v_record.us_vdd = mclk_table->entries[entry_id].vddc +
1955                                         mclk_table->entries[entry_id].vdd_offset;
1956
1957                         mclk_table->entries[entry_id].vddgfx = v_record.us_cac_low =
1958                                 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
1959                         phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
1960                 }
1961         }
1962         return 0;
1963 }
1964
1965 static int smu7_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
1966 {
1967         uint8_t entry_id;
1968         struct phm_ppt_v1_voltage_lookup_record v_record;
1969         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1970         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1971         phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1972
1973         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1974                 for (entry_id = 0; entry_id < mm_table->count; entry_id++) {
1975                         if (mm_table->entries[entry_id].vddgfx_offset & (1 << 15))
1976                                 v_record.us_vdd = mm_table->entries[entry_id].vddc +
1977                                         mm_table->entries[entry_id].vddgfx_offset - 0xFFFF;
1978                         else
1979                                 v_record.us_vdd = mm_table->entries[entry_id].vddc +
1980                                         mm_table->entries[entry_id].vddgfx_offset;
1981
1982                         /* Add the calculated VDDGFX to the VDDGFX lookup table */
1983                         mm_table->entries[entry_id].vddgfx = v_record.us_cac_low =
1984                                 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
1985                         phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
1986                 }
1987         }
1988         return 0;
1989 }
1990
1991 static int smu7_sort_lookup_table(struct pp_hwmgr *hwmgr,
1992                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
1993 {
1994         uint32_t table_size, i, j;
1995         struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
1996         table_size = lookup_table->count;
1997
1998         PP_ASSERT_WITH_CODE(0 != lookup_table->count,
1999                 "Lookup table is empty", return -EINVAL);
2000
2001         /* Sorting voltages */
2002         for (i = 0; i < table_size - 1; i++) {
2003                 for (j = i + 1; j > 0; j--) {
2004                         if (lookup_table->entries[j].us_vdd <
2005                                         lookup_table->entries[j - 1].us_vdd) {
2006                                 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
2007                                 lookup_table->entries[j - 1] = lookup_table->entries[j];
2008                                 lookup_table->entries[j] = tmp_voltage_lookup_record;
2009                         }
2010                 }
2011         }
2012
2013         return 0;
2014 }
2015
2016 static int smu7_complete_dependency_tables(struct pp_hwmgr *hwmgr)
2017 {
2018         int result = 0;
2019         int tmp_result;
2020         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2021         struct phm_ppt_v1_information *table_info =
2022                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2023
2024         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
2025                 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr,
2026                         table_info->vddgfx_lookup_table, &(data->vddcgfx_leakage));
2027                 if (tmp_result != 0)
2028                         result = tmp_result;
2029
2030                 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr,
2031                         &table_info->max_clock_voltage_on_dc.vddgfx, &(data->vddcgfx_leakage));
2032         } else {
2033
2034                 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr,
2035                                 table_info->vddc_lookup_table, &(data->vddc_leakage));
2036                 if (tmp_result)
2037                         result = tmp_result;
2038
2039                 tmp_result = smu7_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
2040                                 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
2041                 if (tmp_result)
2042                         result = tmp_result;
2043         }
2044
2045         tmp_result = smu7_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
2046         if (tmp_result)
2047                 result = tmp_result;
2048
2049         tmp_result = smu7_calc_voltage_dependency_tables(hwmgr);
2050         if (tmp_result)
2051                 result = tmp_result;
2052
2053         tmp_result = smu7_calc_mm_voltage_dependency_table(hwmgr);
2054         if (tmp_result)
2055                 result = tmp_result;
2056
2057         tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddgfx_lookup_table);
2058         if (tmp_result)
2059                 result = tmp_result;
2060
2061         tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
2062         if (tmp_result)
2063                 result = tmp_result;
2064
2065         return result;
2066 }
2067
2068 static int smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr *hwmgr)
2069 {
2070         struct phm_ppt_v1_information *table_info =
2071                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2072
2073         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
2074                                                 table_info->vdd_dep_on_sclk;
2075         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
2076                                                 table_info->vdd_dep_on_mclk;
2077
2078         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
2079                 "VDD dependency on SCLK table is missing.",
2080                 return -EINVAL);
2081         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
2082                 "VDD dependency on SCLK table has to have is missing.",
2083                 return -EINVAL);
2084
2085         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
2086                 "VDD dependency on MCLK table is missing",
2087                 return -EINVAL);
2088         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
2089                 "VDD dependency on MCLK table has to have is missing.",
2090                 return -EINVAL);
2091
2092         table_info->max_clock_voltage_on_ac.sclk =
2093                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
2094         table_info->max_clock_voltage_on_ac.mclk =
2095                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
2096         table_info->max_clock_voltage_on_ac.vddc =
2097                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
2098         table_info->max_clock_voltage_on_ac.vddci =
2099                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
2100
2101         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
2102         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
2103         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
2104         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = table_info->max_clock_voltage_on_ac.vddci;
2105
2106         return 0;
2107 }
2108
2109 static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
2110 {
2111         struct phm_ppt_v1_information *table_info =
2112                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
2113         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
2114         struct phm_ppt_v1_voltage_lookup_table *lookup_table;
2115         uint32_t i;
2116         uint32_t hw_revision, sub_vendor_id, sub_sys_id;
2117         struct amdgpu_device *adev = hwmgr->adev;
2118
2119         if (table_info != NULL) {
2120                 dep_mclk_table = table_info->vdd_dep_on_mclk;
2121                 lookup_table = table_info->vddc_lookup_table;
2122         } else
2123                 return 0;
2124
2125         hw_revision = adev->pdev->revision;
2126         sub_sys_id = adev->pdev->subsystem_device;
2127         sub_vendor_id = adev->pdev->subsystem_vendor;
2128
2129         if (hwmgr->chip_id == CHIP_POLARIS10 && hw_revision == 0xC7 &&
2130                         ((sub_sys_id == 0xb37 && sub_vendor_id == 0x1002) ||
2131                     (sub_sys_id == 0x4a8 && sub_vendor_id == 0x1043) ||
2132                     (sub_sys_id == 0x9480 && sub_vendor_id == 0x1682))) {
2133                 if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000)
2134                         return 0;
2135
2136                 for (i = 0; i < lookup_table->count; i++) {
2137                         if (lookup_table->entries[i].us_vdd < 0xff01 && lookup_table->entries[i].us_vdd >= 1000) {
2138                                 dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i;
2139                                 return 0;
2140                         }
2141                 }
2142         }
2143         return 0;
2144 }
2145
2146 static int smu7_thermal_parameter_init(struct pp_hwmgr *hwmgr)
2147 {
2148         struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2149         uint32_t temp_reg;
2150         struct phm_ppt_v1_information *table_info =
2151                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2152
2153
2154         if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
2155                 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
2156                 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
2157                 case 0:
2158                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
2159                         break;
2160                 case 1:
2161                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
2162                         break;
2163                 case 2:
2164                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
2165                         break;
2166                 case 3:
2167                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
2168                         break;
2169                 case 4:
2170                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
2171                         break;
2172                 default:
2173                         break;
2174                 }
2175                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
2176         }
2177
2178         if (table_info == NULL)
2179                 return 0;
2180
2181         if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
2182                 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
2183                 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
2184                         (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
2185
2186                 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
2187                         (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
2188
2189                 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
2190
2191                 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
2192
2193                 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
2194                         (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
2195
2196                 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
2197
2198                 table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
2199                                                                 (table_info->cac_dtp_table->usDefaultTargetOperatingTemp - 50) : 0;
2200
2201                 table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
2202                 table_info->cac_dtp_table->usOperatingTempStep = 1;
2203                 table_info->cac_dtp_table->usOperatingTempHyst = 1;
2204
2205                 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
2206                                hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
2207
2208                 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
2209                                hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
2210
2211                 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
2212                                table_info->cac_dtp_table->usOperatingTempMinLimit;
2213
2214                 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
2215                                table_info->cac_dtp_table->usOperatingTempMaxLimit;
2216
2217                 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
2218                                table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
2219
2220                 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
2221                                table_info->cac_dtp_table->usOperatingTempStep;
2222
2223                 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
2224                                table_info->cac_dtp_table->usTargetOperatingTemp;
2225                 if (hwmgr->feature_mask & PP_OD_FUZZY_FAN_CONTROL_MASK)
2226                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2227                                         PHM_PlatformCaps_ODFuzzyFanControlSupport);
2228         }
2229
2230         return 0;
2231 }
2232
2233 /**
2234  * Change virtual leakage voltage to actual value.
2235  *
2236  * @param     hwmgr  the address of the powerplay hardware manager.
2237  * @param     pointer to changing voltage
2238  * @param     pointer to leakage table
2239  */
2240 static void smu7_patch_ppt_v0_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2241                 uint32_t *voltage, struct smu7_leakage_voltage *leakage_table)
2242 {
2243         uint32_t index;
2244
2245         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2246         for (index = 0; index < leakage_table->count; index++) {
2247                 /* if this voltage matches a leakage voltage ID */
2248                 /* patch with actual leakage voltage */
2249                 if (leakage_table->leakage_id[index] == *voltage) {
2250                         *voltage = leakage_table->actual_voltage[index];
2251                         break;
2252                 }
2253         }
2254
2255         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2256                 pr_err("Voltage value looks like a Leakage ID but it's not patched \n");
2257 }
2258
2259
2260 static int smu7_patch_vddc(struct pp_hwmgr *hwmgr,
2261                               struct phm_clock_voltage_dependency_table *tab)
2262 {
2263         uint16_t i;
2264         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2265
2266         if (tab)
2267                 for (i = 0; i < tab->count; i++)
2268                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2269                                                 &data->vddc_leakage);
2270
2271         return 0;
2272 }
2273
2274 static int smu7_patch_vddci(struct pp_hwmgr *hwmgr,
2275                                struct phm_clock_voltage_dependency_table *tab)
2276 {
2277         uint16_t i;
2278         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2279
2280         if (tab)
2281                 for (i = 0; i < tab->count; i++)
2282                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2283                                                         &data->vddci_leakage);
2284
2285         return 0;
2286 }
2287
2288 static int smu7_patch_vce_vddc(struct pp_hwmgr *hwmgr,
2289                                   struct phm_vce_clock_voltage_dependency_table *tab)
2290 {
2291         uint16_t i;
2292         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2293
2294         if (tab)
2295                 for (i = 0; i < tab->count; i++)
2296                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2297                                                         &data->vddc_leakage);
2298
2299         return 0;
2300 }
2301
2302
2303 static int smu7_patch_uvd_vddc(struct pp_hwmgr *hwmgr,
2304                                   struct phm_uvd_clock_voltage_dependency_table *tab)
2305 {
2306         uint16_t i;
2307         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2308
2309         if (tab)
2310                 for (i = 0; i < tab->count; i++)
2311                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2312                                                         &data->vddc_leakage);
2313
2314         return 0;
2315 }
2316
2317 static int smu7_patch_vddc_shed_limit(struct pp_hwmgr *hwmgr,
2318                                          struct phm_phase_shedding_limits_table *tab)
2319 {
2320         uint16_t i;
2321         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2322
2323         if (tab)
2324                 for (i = 0; i < tab->count; i++)
2325                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].Voltage,
2326                                                         &data->vddc_leakage);
2327
2328         return 0;
2329 }
2330
2331 static int smu7_patch_samu_vddc(struct pp_hwmgr *hwmgr,
2332                                    struct phm_samu_clock_voltage_dependency_table *tab)
2333 {
2334         uint16_t i;
2335         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2336
2337         if (tab)
2338                 for (i = 0; i < tab->count; i++)
2339                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2340                                                         &data->vddc_leakage);
2341
2342         return 0;
2343 }
2344
2345 static int smu7_patch_acp_vddc(struct pp_hwmgr *hwmgr,
2346                                   struct phm_acp_clock_voltage_dependency_table *tab)
2347 {
2348         uint16_t i;
2349         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2350
2351         if (tab)
2352                 for (i = 0; i < tab->count; i++)
2353                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2354                                         &data->vddc_leakage);
2355
2356         return 0;
2357 }
2358
2359 static int smu7_patch_limits_vddc(struct pp_hwmgr *hwmgr,
2360                                   struct phm_clock_and_voltage_limits *tab)
2361 {
2362         uint32_t vddc, vddci;
2363         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2364
2365         if (tab) {
2366                 vddc = tab->vddc;
2367                 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc,
2368                                                    &data->vddc_leakage);
2369                 tab->vddc = vddc;
2370                 vddci = tab->vddci;
2371                 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddci,
2372                                                    &data->vddci_leakage);
2373                 tab->vddci = vddci;
2374         }
2375
2376         return 0;
2377 }
2378
2379 static int smu7_patch_cac_vddc(struct pp_hwmgr *hwmgr, struct phm_cac_leakage_table *tab)
2380 {
2381         uint32_t i;
2382         uint32_t vddc;
2383         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2384
2385         if (tab) {
2386                 for (i = 0; i < tab->count; i++) {
2387                         vddc = (uint32_t)(tab->entries[i].Vddc);
2388                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, &data->vddc_leakage);
2389                         tab->entries[i].Vddc = (uint16_t)vddc;
2390                 }
2391         }
2392
2393         return 0;
2394 }
2395
2396 static int smu7_patch_dependency_tables_with_leakage(struct pp_hwmgr *hwmgr)
2397 {
2398         int tmp;
2399
2400         tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk);
2401         if (tmp)
2402                 return -EINVAL;
2403
2404         tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_mclk);
2405         if (tmp)
2406                 return -EINVAL;
2407
2408         tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
2409         if (tmp)
2410                 return -EINVAL;
2411
2412         tmp = smu7_patch_vddci(hwmgr, hwmgr->dyn_state.vddci_dependency_on_mclk);
2413         if (tmp)
2414                 return -EINVAL;
2415
2416         tmp = smu7_patch_vce_vddc(hwmgr, hwmgr->dyn_state.vce_clock_voltage_dependency_table);
2417         if (tmp)
2418                 return -EINVAL;
2419
2420         tmp = smu7_patch_uvd_vddc(hwmgr, hwmgr->dyn_state.uvd_clock_voltage_dependency_table);
2421         if (tmp)
2422                 return -EINVAL;
2423
2424         tmp = smu7_patch_samu_vddc(hwmgr, hwmgr->dyn_state.samu_clock_voltage_dependency_table);
2425         if (tmp)
2426                 return -EINVAL;
2427
2428         tmp = smu7_patch_acp_vddc(hwmgr, hwmgr->dyn_state.acp_clock_voltage_dependency_table);
2429         if (tmp)
2430                 return -EINVAL;
2431
2432         tmp = smu7_patch_vddc_shed_limit(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table);
2433         if (tmp)
2434                 return -EINVAL;
2435
2436         tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_ac);
2437         if (tmp)
2438                 return -EINVAL;
2439
2440         tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_dc);
2441         if (tmp)
2442                 return -EINVAL;
2443
2444         tmp = smu7_patch_cac_vddc(hwmgr, hwmgr->dyn_state.cac_leakage_table);
2445         if (tmp)
2446                 return -EINVAL;
2447
2448         return 0;
2449 }
2450
2451
2452 static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr)
2453 {
2454         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2455
2456         struct phm_clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
2457         struct phm_clock_voltage_dependency_table *allowed_mclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
2458         struct phm_clock_voltage_dependency_table *allowed_mclk_vddci_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
2459
2460         PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table != NULL,
2461                 "VDDC dependency on SCLK table is missing. This table is mandatory",
2462                 return -EINVAL);
2463         PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table->count >= 1,
2464                 "VDDC dependency on SCLK table has to have is missing. This table is mandatory",
2465                 return -EINVAL);
2466
2467         PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table != NULL,
2468                 "VDDC dependency on MCLK table is missing. This table is mandatory",
2469                 return -EINVAL);
2470         PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table->count >= 1,
2471                 "VDD dependency on MCLK table has to have is missing. This table is mandatory",
2472                 return -EINVAL);
2473
2474         data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[0].v;
2475         data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
2476
2477         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
2478                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
2479         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
2480                 allowed_mclk_vddc_table->entries[allowed_mclk_vddc_table->count - 1].clk;
2481         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
2482                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
2483
2484         if (allowed_mclk_vddci_table != NULL && allowed_mclk_vddci_table->count >= 1) {
2485                 data->min_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[0].v;
2486                 data->max_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
2487         }
2488
2489         if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk->count >= 1)
2490                 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entries[hwmgr->dyn_state.vddci_dependency_on_mclk->count - 1].v;
2491
2492         return 0;
2493 }
2494
2495 static int smu7_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
2496 {
2497         kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
2498         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
2499         kfree(hwmgr->backend);
2500         hwmgr->backend = NULL;
2501
2502         return 0;
2503 }
2504
2505 static int smu7_get_elb_voltages(struct pp_hwmgr *hwmgr)
2506 {
2507         uint16_t virtual_voltage_id, vddc, vddci, efuse_voltage_id;
2508         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2509         int i;
2510
2511         if (atomctrl_get_leakage_id_from_efuse(hwmgr, &efuse_voltage_id) == 0) {
2512                 for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
2513                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2514                         if (atomctrl_get_leakage_vddc_base_on_leakage(hwmgr, &vddc, &vddci,
2515                                                                 virtual_voltage_id,
2516                                                                 efuse_voltage_id) == 0) {
2517                                 if (vddc != 0 && vddc != virtual_voltage_id) {
2518                                         data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc;
2519                                         data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id;
2520                                         data->vddc_leakage.count++;
2521                                 }
2522                                 if (vddci != 0 && vddci != virtual_voltage_id) {
2523                                         data->vddci_leakage.actual_voltage[data->vddci_leakage.count] = vddci;
2524                                         data->vddci_leakage.leakage_id[data->vddci_leakage.count] = virtual_voltage_id;
2525                                         data->vddci_leakage.count++;
2526                                 }
2527                         }
2528                 }
2529         }
2530         return 0;
2531 }
2532
2533 static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
2534 {
2535         struct smu7_hwmgr *data;
2536         int result = 0;
2537
2538         data = kzalloc(sizeof(struct smu7_hwmgr), GFP_KERNEL);
2539         if (data == NULL)
2540                 return -ENOMEM;
2541
2542         hwmgr->backend = data;
2543         smu7_patch_voltage_workaround(hwmgr);
2544         smu7_init_dpm_defaults(hwmgr);
2545
2546         /* Get leakage voltage based on leakage ID. */
2547         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2548                         PHM_PlatformCaps_EVV)) {
2549                 result = smu7_get_evv_voltages(hwmgr);
2550                 if (result) {
2551                         pr_info("Get EVV Voltage Failed.  Abort Driver loading!\n");
2552                         return -EINVAL;
2553                 }
2554         } else {
2555                 smu7_get_elb_voltages(hwmgr);
2556         }
2557
2558         if (hwmgr->pp_table_version == PP_TABLE_V1) {
2559                 smu7_complete_dependency_tables(hwmgr);
2560                 smu7_set_private_data_based_on_pptable_v1(hwmgr);
2561         } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
2562                 smu7_patch_dependency_tables_with_leakage(hwmgr);
2563                 smu7_set_private_data_based_on_pptable_v0(hwmgr);
2564         }
2565
2566         /* Initalize Dynamic State Adjustment Rule Settings */
2567         result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
2568
2569         if (0 == result) {
2570                 struct amdgpu_device *adev = hwmgr->adev;
2571
2572                 data->is_tlu_enabled = false;
2573
2574                 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
2575                                                         SMU7_MAX_HARDWARE_POWERLEVELS;
2576                 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
2577                 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
2578
2579                 data->pcie_gen_cap = adev->pm.pcie_gen_mask;
2580                 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
2581                         data->pcie_spc_cap = 20;
2582                 data->pcie_lane_cap = adev->pm.pcie_mlw_mask;
2583
2584                 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
2585 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
2586                 hwmgr->platform_descriptor.clockStep.engineClock = 500;
2587                 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
2588                 smu7_thermal_parameter_init(hwmgr);
2589         } else {
2590                 /* Ignore return value in here, we are cleaning up a mess. */
2591                 smu7_hwmgr_backend_fini(hwmgr);
2592         }
2593
2594         return 0;
2595 }
2596
2597 static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr)
2598 {
2599         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2600         uint32_t level, tmp;
2601
2602         if (!data->pcie_dpm_key_disabled) {
2603                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
2604                         level = 0;
2605                         tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
2606                         while (tmp >>= 1)
2607                                 level++;
2608
2609                         if (level)
2610                                 smum_send_msg_to_smc_with_parameter(hwmgr,
2611                                                 PPSMC_MSG_PCIeDPM_ForceLevel, level);
2612                 }
2613         }
2614
2615         if (!data->sclk_dpm_key_disabled) {
2616                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
2617                         level = 0;
2618                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
2619                         while (tmp >>= 1)
2620                                 level++;
2621
2622                         if (level)
2623                                 smum_send_msg_to_smc_with_parameter(hwmgr,
2624                                                 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2625                                                 (1 << level));
2626                 }
2627         }
2628
2629         if (!data->mclk_dpm_key_disabled) {
2630                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
2631                         level = 0;
2632                         tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
2633                         while (tmp >>= 1)
2634                                 level++;
2635
2636                         if (level)
2637                                 smum_send_msg_to_smc_with_parameter(hwmgr,
2638                                                 PPSMC_MSG_MCLKDPM_SetEnabledMask,
2639                                                 (1 << level));
2640                 }
2641         }
2642
2643         return 0;
2644 }
2645
2646 static int smu7_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
2647 {
2648         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2649
2650         if (hwmgr->pp_table_version == PP_TABLE_V1)
2651                 phm_apply_dal_min_voltage_request(hwmgr);
2652 /* TO DO  for v0 iceland and Ci*/
2653
2654         if (!data->sclk_dpm_key_disabled) {
2655                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
2656                         smum_send_msg_to_smc_with_parameter(hwmgr,
2657                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
2658                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask);
2659         }
2660
2661         if (!data->mclk_dpm_key_disabled) {
2662                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
2663                         smum_send_msg_to_smc_with_parameter(hwmgr,
2664                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
2665                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask);
2666         }
2667
2668         return 0;
2669 }
2670
2671 static int smu7_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
2672 {
2673         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2674
2675         if (!smum_is_dpm_running(hwmgr))
2676                 return -EINVAL;
2677
2678         if (!data->pcie_dpm_key_disabled) {
2679                 smum_send_msg_to_smc(hwmgr,
2680                                 PPSMC_MSG_PCIeDPM_UnForceLevel);
2681         }
2682
2683         return smu7_upload_dpm_level_enable_mask(hwmgr);
2684 }
2685
2686 static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2687 {
2688         struct smu7_hwmgr *data =
2689                         (struct smu7_hwmgr *)(hwmgr->backend);
2690         uint32_t level;
2691
2692         if (!data->sclk_dpm_key_disabled)
2693                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
2694                         level = phm_get_lowest_enabled_level(hwmgr,
2695                                                               data->dpm_level_enable_mask.sclk_dpm_enable_mask);
2696                         smum_send_msg_to_smc_with_parameter(hwmgr,
2697                                                             PPSMC_MSG_SCLKDPM_SetEnabledMask,
2698                                                             (1 << level));
2699
2700         }
2701
2702         if (!data->mclk_dpm_key_disabled) {
2703                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
2704                         level = phm_get_lowest_enabled_level(hwmgr,
2705                                                               data->dpm_level_enable_mask.mclk_dpm_enable_mask);
2706                         smum_send_msg_to_smc_with_parameter(hwmgr,
2707                                                             PPSMC_MSG_MCLKDPM_SetEnabledMask,
2708                                                             (1 << level));
2709                 }
2710         }
2711
2712         if (!data->pcie_dpm_key_disabled) {
2713                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
2714                         level = phm_get_lowest_enabled_level(hwmgr,
2715                                                               data->dpm_level_enable_mask.pcie_dpm_enable_mask);
2716                         smum_send_msg_to_smc_with_parameter(hwmgr,
2717                                                             PPSMC_MSG_PCIeDPM_ForceLevel,
2718                                                             (level));
2719                 }
2720         }
2721
2722         return 0;
2723 }
2724
2725 static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
2726                                 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask)
2727 {
2728         uint32_t percentage;
2729         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2730         struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table;
2731         int32_t tmp_mclk;
2732         int32_t tmp_sclk;
2733         int32_t count;
2734
2735         if (golden_dpm_table->mclk_table.count < 1)
2736                 return -EINVAL;
2737
2738         percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value /
2739                         golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
2740
2741         if (golden_dpm_table->mclk_table.count == 1) {
2742                 percentage = 70;
2743                 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
2744                 *mclk_mask = golden_dpm_table->mclk_table.count - 1;
2745         } else {
2746                 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 2].value;
2747                 *mclk_mask = golden_dpm_table->mclk_table.count - 2;
2748         }
2749
2750         tmp_sclk = tmp_mclk * percentage / 100;
2751
2752         if (hwmgr->pp_table_version == PP_TABLE_V0) {
2753                 for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
2754                         count >= 0; count--) {
2755                         if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) {
2756                                 tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk;
2757                                 *sclk_mask = count;
2758                                 break;
2759                         }
2760                 }
2761                 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2762                         *sclk_mask = 0;
2763                         tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].clk;
2764                 }
2765
2766                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2767                         *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
2768         } else if (hwmgr->pp_table_version == PP_TABLE_V1) {
2769                 struct phm_ppt_v1_information *table_info =
2770                                 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2771
2772                 for (count = table_info->vdd_dep_on_sclk->count-1; count >= 0; count--) {
2773                         if (tmp_sclk >= table_info->vdd_dep_on_sclk->entries[count].clk) {
2774                                 tmp_sclk = table_info->vdd_dep_on_sclk->entries[count].clk;
2775                                 *sclk_mask = count;
2776                                 break;
2777                         }
2778                 }
2779                 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2780                         *sclk_mask = 0;
2781                         tmp_sclk =  table_info->vdd_dep_on_sclk->entries[0].clk;
2782                 }
2783
2784                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2785                         *sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
2786         }
2787
2788         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
2789                 *mclk_mask = 0;
2790         else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2791                 *mclk_mask = golden_dpm_table->mclk_table.count - 1;
2792
2793         *pcie_mask = data->dpm_table.pcie_speed_table.count - 1;
2794         hwmgr->pstate_sclk = tmp_sclk;
2795         hwmgr->pstate_mclk = tmp_mclk;
2796
2797         return 0;
2798 }
2799
2800 static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
2801                                 enum amd_dpm_forced_level level)
2802 {
2803         int ret = 0;
2804         uint32_t sclk_mask = 0;
2805         uint32_t mclk_mask = 0;
2806         uint32_t pcie_mask = 0;
2807
2808         if (hwmgr->pstate_sclk == 0)
2809                 smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
2810
2811         switch (level) {
2812         case AMD_DPM_FORCED_LEVEL_HIGH:
2813                 ret = smu7_force_dpm_highest(hwmgr);
2814                 break;
2815         case AMD_DPM_FORCED_LEVEL_LOW:
2816                 ret = smu7_force_dpm_lowest(hwmgr);