Merge branch 'drm-fixes-5.0' of git://people.freedesktop.org/~agd5f/linux into drm...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / powerplay / hwmgr / smu7_hwmgr.c
1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #include "pp_debug.h"
24 #include <linux/delay.h>
25 #include <linux/fb.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
28 #include <asm/div64.h>
29 #include <drm/amdgpu_drm.h>
30 #include "ppatomctrl.h"
31 #include "atombios.h"
32 #include "pptable_v1_0.h"
33 #include "pppcielanes.h"
34 #include "amd_pcie_helpers.h"
35 #include "hardwaremanager.h"
36 #include "process_pptables_v1_0.h"
37 #include "cgs_common.h"
38
39 #include "smu7_common.h"
40
41 #include "hwmgr.h"
42 #include "smu7_hwmgr.h"
43 #include "smu_ucode_xfer_vi.h"
44 #include "smu7_powertune.h"
45 #include "smu7_dyn_defaults.h"
46 #include "smu7_thermal.h"
47 #include "smu7_clockpowergating.h"
48 #include "processpptables.h"
49 #include "pp_thermal.h"
50
51 #include "ivsrcid/ivsrcid_vislands30.h"
52
53 #define MC_CG_ARB_FREQ_F0           0x0a
54 #define MC_CG_ARB_FREQ_F1           0x0b
55 #define MC_CG_ARB_FREQ_F2           0x0c
56 #define MC_CG_ARB_FREQ_F3           0x0d
57
58 #define MC_CG_SEQ_DRAMCONF_S0       0x05
59 #define MC_CG_SEQ_DRAMCONF_S1       0x06
60 #define MC_CG_SEQ_YCLK_SUSPEND      0x04
61 #define MC_CG_SEQ_YCLK_RESUME       0x0a
62
63 #define SMC_CG_IND_START            0xc0030000
64 #define SMC_CG_IND_END              0xc0040000
65
66 #define MEM_FREQ_LOW_LATENCY        25000
67 #define MEM_FREQ_HIGH_LATENCY       80000
68
69 #define MEM_LATENCY_HIGH            45
70 #define MEM_LATENCY_LOW             35
71 #define MEM_LATENCY_ERR             0xFFFF
72
73 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
74 #define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
75 #define MC_SEQ_MISC0_GDDR5_VALUE 5
76
77 #define PCIE_BUS_CLK                10000
78 #define TCLK                        (PCIE_BUS_CLK / 10)
79
80 static const struct profile_mode_setting smu7_profiling[7] =
81                                         {{0, 0, 0, 0, 0, 0, 0, 0},
82                                          {1, 0, 100, 30, 1, 0, 100, 10},
83                                          {1, 10, 0, 30, 0, 0, 0, 0},
84                                          {0, 0, 0, 0, 1, 10, 16, 31},
85                                          {1, 0, 11, 50, 1, 0, 100, 10},
86                                          {1, 0, 5, 30, 0, 0, 0, 0},
87                                          {0, 0, 0, 0, 0, 0, 0, 0},
88                                         };
89
90 #define PPSMC_MSG_SetVBITimeout_VEGAM    ((uint16_t) 0x310)
91
92 #define ixPWR_SVI2_PLANE1_LOAD                     0xC0200280
93 #define PWR_SVI2_PLANE1_LOAD__PSI1_MASK                    0x00000020L
94 #define PWR_SVI2_PLANE1_LOAD__PSI0_EN_MASK                 0x00000040L
95 #define PWR_SVI2_PLANE1_LOAD__PSI1__SHIFT                  0x00000005
96 #define PWR_SVI2_PLANE1_LOAD__PSI0_EN__SHIFT               0x00000006
97
98 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
99 enum DPM_EVENT_SRC {
100         DPM_EVENT_SRC_ANALOG = 0,
101         DPM_EVENT_SRC_EXTERNAL = 1,
102         DPM_EVENT_SRC_DIGITAL = 2,
103         DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
104         DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
105 };
106
107 static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic);
108 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
109                 enum pp_clock_type type, uint32_t mask);
110
111 static struct smu7_power_state *cast_phw_smu7_power_state(
112                                   struct pp_hw_power_state *hw_ps)
113 {
114         PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
115                                 "Invalid Powerstate Type!",
116                                  return NULL);
117
118         return (struct smu7_power_state *)hw_ps;
119 }
120
121 static const struct smu7_power_state *cast_const_phw_smu7_power_state(
122                                  const struct pp_hw_power_state *hw_ps)
123 {
124         PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
125                                 "Invalid Powerstate Type!",
126                                  return NULL);
127
128         return (const struct smu7_power_state *)hw_ps;
129 }
130
131 /**
132  * Find the MC microcode version and store it in the HwMgr struct
133  *
134  * @param    hwmgr  the address of the powerplay hardware manager.
135  * @return   always 0
136  */
137 static int smu7_get_mc_microcode_version(struct pp_hwmgr *hwmgr)
138 {
139         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
140
141         hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
142
143         return 0;
144 }
145
146 static uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
147 {
148         uint32_t speedCntl = 0;
149
150         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
151         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
152                         ixPCIE_LC_SPEED_CNTL);
153         return((uint16_t)PHM_GET_FIELD(speedCntl,
154                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
155 }
156
157 static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
158 {
159         uint32_t link_width;
160
161         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
162         link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
163                         PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
164
165         PP_ASSERT_WITH_CODE((7 >= link_width),
166                         "Invalid PCIe lane width!", return 0);
167
168         return decode_pcie_lane_width(link_width);
169 }
170
171 /**
172 * Enable voltage control
173 *
174 * @param    pHwMgr  the address of the powerplay hardware manager.
175 * @return   always PP_Result_OK
176 */
177 static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
178 {
179         if (hwmgr->chip_id == CHIP_VEGAM) {
180                 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
181                                 CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI1, 0);
182                 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
183                                 CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI0_EN, 0);
184         }
185
186         if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK)
187                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Enable);
188
189         return 0;
190 }
191
192 /**
193 * Checks if we want to support voltage control
194 *
195 * @param    hwmgr  the address of the powerplay hardware manager.
196 */
197 static bool smu7_voltage_control(const struct pp_hwmgr *hwmgr)
198 {
199         const struct smu7_hwmgr *data =
200                         (const struct smu7_hwmgr *)(hwmgr->backend);
201
202         return (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control);
203 }
204
205 /**
206 * Enable voltage control
207 *
208 * @param    hwmgr  the address of the powerplay hardware manager.
209 * @return   always 0
210 */
211 static int smu7_enable_voltage_control(struct pp_hwmgr *hwmgr)
212 {
213         /* enable voltage control */
214         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
215                         GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
216
217         return 0;
218 }
219
220 static int phm_get_svi2_voltage_table_v0(pp_atomctrl_voltage_table *voltage_table,
221                 struct phm_clock_voltage_dependency_table *voltage_dependency_table
222                 )
223 {
224         uint32_t i;
225
226         PP_ASSERT_WITH_CODE((NULL != voltage_table),
227                         "Voltage Dependency Table empty.", return -EINVAL;);
228
229         voltage_table->mask_low = 0;
230         voltage_table->phase_delay = 0;
231         voltage_table->count = voltage_dependency_table->count;
232
233         for (i = 0; i < voltage_dependency_table->count; i++) {
234                 voltage_table->entries[i].value =
235                         voltage_dependency_table->entries[i].v;
236                 voltage_table->entries[i].smio_low = 0;
237         }
238
239         return 0;
240 }
241
242
243 /**
244 * Create Voltage Tables.
245 *
246 * @param    hwmgr  the address of the powerplay hardware manager.
247 * @return   always 0
248 */
249 static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr)
250 {
251         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
252         struct phm_ppt_v1_information *table_info =
253                         (struct phm_ppt_v1_information *)hwmgr->pptable;
254         int result = 0;
255         uint32_t tmp;
256
257         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
258                 result = atomctrl_get_voltage_table_v3(hwmgr,
259                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
260                                 &(data->mvdd_voltage_table));
261                 PP_ASSERT_WITH_CODE((0 == result),
262                                 "Failed to retrieve MVDD table.",
263                                 return result);
264         } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
265                 if (hwmgr->pp_table_version == PP_TABLE_V1)
266                         result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
267                                         table_info->vdd_dep_on_mclk);
268                 else if (hwmgr->pp_table_version == PP_TABLE_V0)
269                         result = phm_get_svi2_voltage_table_v0(&(data->mvdd_voltage_table),
270                                         hwmgr->dyn_state.mvdd_dependency_on_mclk);
271
272                 PP_ASSERT_WITH_CODE((0 == result),
273                                 "Failed to retrieve SVI2 MVDD table from dependency table.",
274                                 return result;);
275         }
276
277         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
278                 result = atomctrl_get_voltage_table_v3(hwmgr,
279                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
280                                 &(data->vddci_voltage_table));
281                 PP_ASSERT_WITH_CODE((0 == result),
282                                 "Failed to retrieve VDDCI table.",
283                                 return result);
284         } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
285                 if (hwmgr->pp_table_version == PP_TABLE_V1)
286                         result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
287                                         table_info->vdd_dep_on_mclk);
288                 else if (hwmgr->pp_table_version == PP_TABLE_V0)
289                         result = phm_get_svi2_voltage_table_v0(&(data->vddci_voltage_table),
290                                         hwmgr->dyn_state.vddci_dependency_on_mclk);
291                 PP_ASSERT_WITH_CODE((0 == result),
292                                 "Failed to retrieve SVI2 VDDCI table from dependency table.",
293                                 return result);
294         }
295
296         if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
297                 /* VDDGFX has only SVI2 voltage control */
298                 result = phm_get_svi2_vdd_voltage_table(&(data->vddgfx_voltage_table),
299                                         table_info->vddgfx_lookup_table);
300                 PP_ASSERT_WITH_CODE((0 == result),
301                         "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;);
302         }
303
304
305         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
306                 result = atomctrl_get_voltage_table_v3(hwmgr,
307                                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT,
308                                         &data->vddc_voltage_table);
309                 PP_ASSERT_WITH_CODE((0 == result),
310                         "Failed to retrieve VDDC table.", return result;);
311         } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
312
313                 if (hwmgr->pp_table_version == PP_TABLE_V0)
314                         result = phm_get_svi2_voltage_table_v0(&data->vddc_voltage_table,
315                                         hwmgr->dyn_state.vddc_dependency_on_mclk);
316                 else if (hwmgr->pp_table_version == PP_TABLE_V1)
317                         result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
318                                 table_info->vddc_lookup_table);
319
320                 PP_ASSERT_WITH_CODE((0 == result),
321                         "Failed to retrieve SVI2 VDDC table from dependency table.", return result;);
322         }
323
324         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDC);
325         PP_ASSERT_WITH_CODE(
326                         (data->vddc_voltage_table.count <= tmp),
327                 "Too many voltage values for VDDC. Trimming to fit state table.",
328                         phm_trim_voltage_table_to_fit_state_table(tmp,
329                                                 &(data->vddc_voltage_table)));
330
331         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
332         PP_ASSERT_WITH_CODE(
333                         (data->vddgfx_voltage_table.count <= tmp),
334                 "Too many voltage values for VDDC. Trimming to fit state table.",
335                         phm_trim_voltage_table_to_fit_state_table(tmp,
336                                                 &(data->vddgfx_voltage_table)));
337
338         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDCI);
339         PP_ASSERT_WITH_CODE(
340                         (data->vddci_voltage_table.count <= tmp),
341                 "Too many voltage values for VDDCI. Trimming to fit state table.",
342                         phm_trim_voltage_table_to_fit_state_table(tmp,
343                                         &(data->vddci_voltage_table)));
344
345         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_MVDD);
346         PP_ASSERT_WITH_CODE(
347                         (data->mvdd_voltage_table.count <= tmp),
348                 "Too many voltage values for MVDD. Trimming to fit state table.",
349                         phm_trim_voltage_table_to_fit_state_table(tmp,
350                                                 &(data->mvdd_voltage_table)));
351
352         return 0;
353 }
354
355 /**
356 * Programs static screed detection parameters
357 *
358 * @param    hwmgr  the address of the powerplay hardware manager.
359 * @return   always 0
360 */
361 static int smu7_program_static_screen_threshold_parameters(
362                                                         struct pp_hwmgr *hwmgr)
363 {
364         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
365
366         /* Set static screen threshold unit */
367         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
368                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
369                         data->static_screen_threshold_unit);
370         /* Set static screen threshold */
371         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
372                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
373                         data->static_screen_threshold);
374
375         return 0;
376 }
377
378 /**
379 * Setup display gap for glitch free memory clock switching.
380 *
381 * @param    hwmgr  the address of the powerplay hardware manager.
382 * @return   always  0
383 */
384 static int smu7_enable_display_gap(struct pp_hwmgr *hwmgr)
385 {
386         uint32_t display_gap =
387                         cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
388                                         ixCG_DISPLAY_GAP_CNTL);
389
390         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
391                         DISP_GAP, DISPLAY_GAP_IGNORE);
392
393         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
394                         DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
395
396         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
397                         ixCG_DISPLAY_GAP_CNTL, display_gap);
398
399         return 0;
400 }
401
402 /**
403 * Programs activity state transition voting clients
404 *
405 * @param    hwmgr  the address of the powerplay hardware manager.
406 * @return   always  0
407 */
408 static int smu7_program_voting_clients(struct pp_hwmgr *hwmgr)
409 {
410         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
411         int i;
412
413         /* Clear reset for voting clients before enabling DPM */
414         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
415                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
416         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
417                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
418
419         for (i = 0; i < 8; i++)
420                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
421                                         ixCG_FREQ_TRAN_VOTING_0 + i * 4,
422                                         data->voting_rights_clients[i]);
423         return 0;
424 }
425
426 static int smu7_clear_voting_clients(struct pp_hwmgr *hwmgr)
427 {
428         int i;
429
430         /* Reset voting clients before disabling DPM */
431         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
432                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1);
433         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
434                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1);
435
436         for (i = 0; i < 8; i++)
437                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
438                                 ixCG_FREQ_TRAN_VOTING_0 + i * 4, 0);
439
440         return 0;
441 }
442
443 /* Copy one arb setting to another and then switch the active set.
444  * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
445  */
446 static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
447                 uint32_t arb_src, uint32_t arb_dest)
448 {
449         uint32_t mc_arb_dram_timing;
450         uint32_t mc_arb_dram_timing2;
451         uint32_t burst_time;
452         uint32_t mc_cg_config;
453
454         switch (arb_src) {
455         case MC_CG_ARB_FREQ_F0:
456                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
457                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
458                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
459                 break;
460         case MC_CG_ARB_FREQ_F1:
461                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
462                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
463                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
464                 break;
465         default:
466                 return -EINVAL;
467         }
468
469         switch (arb_dest) {
470         case MC_CG_ARB_FREQ_F0:
471                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
472                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
473                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
474                 break;
475         case MC_CG_ARB_FREQ_F1:
476                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
477                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
478                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
479                 break;
480         default:
481                 return -EINVAL;
482         }
483
484         mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
485         mc_cg_config |= 0x0000000F;
486         cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
487         PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
488
489         return 0;
490 }
491
492 static int smu7_reset_to_default(struct pp_hwmgr *hwmgr)
493 {
494         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ResetToDefaults);
495 }
496
497 /**
498 * Initial switch from ARB F0->F1
499 *
500 * @param    hwmgr  the address of the powerplay hardware manager.
501 * @return   always 0
502 * This function is to be called from the SetPowerState table.
503 */
504 static int smu7_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
505 {
506         return smu7_copy_and_switch_arb_sets(hwmgr,
507                         MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
508 }
509
510 static int smu7_force_switch_to_arbf0(struct pp_hwmgr *hwmgr)
511 {
512         uint32_t tmp;
513
514         tmp = (cgs_read_ind_register(hwmgr->device,
515                         CGS_IND_REG__SMC, ixSMC_SCRATCH9) &
516                         0x0000ff00) >> 8;
517
518         if (tmp == MC_CG_ARB_FREQ_F0)
519                 return 0;
520
521         return smu7_copy_and_switch_arb_sets(hwmgr,
522                         tmp, MC_CG_ARB_FREQ_F0);
523 }
524
525 static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
526 {
527         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
528
529         struct phm_ppt_v1_information *table_info =
530                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
531         struct phm_ppt_v1_pcie_table *pcie_table = NULL;
532
533         uint32_t i, max_entry;
534         uint32_t tmp;
535
536         PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
537                         data->use_pcie_power_saving_levels), "No pcie performance levels!",
538                         return -EINVAL);
539
540         if (table_info != NULL)
541                 pcie_table = table_info->pcie_table;
542
543         if (data->use_pcie_performance_levels &&
544                         !data->use_pcie_power_saving_levels) {
545                 data->pcie_gen_power_saving = data->pcie_gen_performance;
546                 data->pcie_lane_power_saving = data->pcie_lane_performance;
547         } else if (!data->use_pcie_performance_levels &&
548                         data->use_pcie_power_saving_levels) {
549                 data->pcie_gen_performance = data->pcie_gen_power_saving;
550                 data->pcie_lane_performance = data->pcie_lane_power_saving;
551         }
552         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_LINK);
553         phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
554                                         tmp,
555                                         MAX_REGULAR_DPM_NUMBER);
556
557         if (pcie_table != NULL) {
558                 /* max_entry is used to make sure we reserve one PCIE level
559                  * for boot level (fix for A+A PSPP issue).
560                  * If PCIE table from PPTable have ULV entry + 8 entries,
561                  * then ignore the last entry.*/
562                 max_entry = (tmp < pcie_table->count) ? tmp : pcie_table->count;
563                 for (i = 1; i < max_entry; i++) {
564                         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
565                                         get_pcie_gen_support(data->pcie_gen_cap,
566                                                         pcie_table->entries[i].gen_speed),
567                                         get_pcie_lane_support(data->pcie_lane_cap,
568                                                         pcie_table->entries[i].lane_width));
569                 }
570                 data->dpm_table.pcie_speed_table.count = max_entry - 1;
571                 smum_update_smc_table(hwmgr, SMU_BIF_TABLE);
572         } else {
573                 /* Hardcode Pcie Table */
574                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
575                                 get_pcie_gen_support(data->pcie_gen_cap,
576                                                 PP_Min_PCIEGen),
577                                 get_pcie_lane_support(data->pcie_lane_cap,
578                                                 PP_Max_PCIELane));
579                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
580                                 get_pcie_gen_support(data->pcie_gen_cap,
581                                                 PP_Min_PCIEGen),
582                                 get_pcie_lane_support(data->pcie_lane_cap,
583                                                 PP_Max_PCIELane));
584                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
585                                 get_pcie_gen_support(data->pcie_gen_cap,
586                                                 PP_Max_PCIEGen),
587                                 get_pcie_lane_support(data->pcie_lane_cap,
588                                                 PP_Max_PCIELane));
589                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
590                                 get_pcie_gen_support(data->pcie_gen_cap,
591                                                 PP_Max_PCIEGen),
592                                 get_pcie_lane_support(data->pcie_lane_cap,
593                                                 PP_Max_PCIELane));
594                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
595                                 get_pcie_gen_support(data->pcie_gen_cap,
596                                                 PP_Max_PCIEGen),
597                                 get_pcie_lane_support(data->pcie_lane_cap,
598                                                 PP_Max_PCIELane));
599                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
600                                 get_pcie_gen_support(data->pcie_gen_cap,
601                                                 PP_Max_PCIEGen),
602                                 get_pcie_lane_support(data->pcie_lane_cap,
603                                                 PP_Max_PCIELane));
604
605                 data->dpm_table.pcie_speed_table.count = 6;
606         }
607         /* Populate last level for boot PCIE level, but do not increment count. */
608         if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
609                 for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++)
610                         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i,
611                                 get_pcie_gen_support(data->pcie_gen_cap,
612                                                 PP_Max_PCIEGen),
613                                 data->vbios_boot_state.pcie_lane_bootup_value);
614         } else {
615                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
616                         data->dpm_table.pcie_speed_table.count,
617                         get_pcie_gen_support(data->pcie_gen_cap,
618                                         PP_Min_PCIEGen),
619                         get_pcie_lane_support(data->pcie_lane_cap,
620                                         PP_Max_PCIELane));
621         }
622         return 0;
623 }
624
625 static int smu7_reset_dpm_tables(struct pp_hwmgr *hwmgr)
626 {
627         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
628
629         memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table));
630
631         phm_reset_single_dpm_table(
632                         &data->dpm_table.sclk_table,
633                                 smum_get_mac_definition(hwmgr,
634                                         SMU_MAX_LEVELS_GRAPHICS),
635                                         MAX_REGULAR_DPM_NUMBER);
636         phm_reset_single_dpm_table(
637                         &data->dpm_table.mclk_table,
638                         smum_get_mac_definition(hwmgr,
639                                 SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER);
640
641         phm_reset_single_dpm_table(
642                         &data->dpm_table.vddc_table,
643                                 smum_get_mac_definition(hwmgr,
644                                         SMU_MAX_LEVELS_VDDC),
645                                         MAX_REGULAR_DPM_NUMBER);
646         phm_reset_single_dpm_table(
647                         &data->dpm_table.vddci_table,
648                         smum_get_mac_definition(hwmgr,
649                                 SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER);
650
651         phm_reset_single_dpm_table(
652                         &data->dpm_table.mvdd_table,
653                                 smum_get_mac_definition(hwmgr,
654                                         SMU_MAX_LEVELS_MVDD),
655                                         MAX_REGULAR_DPM_NUMBER);
656         return 0;
657 }
658 /*
659  * This function is to initialize all DPM state tables
660  * for SMU7 based on the dependency table.
661  * Dynamic state patching function will then trim these
662  * state tables to the allowed range based
663  * on the power policy or external client requests,
664  * such as UVD request, etc.
665  */
666
667 static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr)
668 {
669         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
670         struct phm_clock_voltage_dependency_table *allowed_vdd_sclk_table =
671                 hwmgr->dyn_state.vddc_dependency_on_sclk;
672         struct phm_clock_voltage_dependency_table *allowed_vdd_mclk_table =
673                 hwmgr->dyn_state.vddc_dependency_on_mclk;
674         struct phm_cac_leakage_table *std_voltage_table =
675                 hwmgr->dyn_state.cac_leakage_table;
676         uint32_t i;
677
678         PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
679                 "SCLK dependency table is missing. This table is mandatory", return -EINVAL);
680         PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1,
681                 "SCLK dependency table has to have is missing. This table is mandatory", return -EINVAL);
682
683         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
684                 "MCLK dependency table is missing. This table is mandatory", return -EINVAL);
685         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1,
686                 "VMCLK dependency table has to have is missing. This table is mandatory", return -EINVAL);
687
688
689         /* Initialize Sclk DPM table based on allow Sclk values*/
690         data->dpm_table.sclk_table.count = 0;
691
692         for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
693                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value !=
694                                 allowed_vdd_sclk_table->entries[i].clk) {
695                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
696                                 allowed_vdd_sclk_table->entries[i].clk;
697                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0;
698                         data->dpm_table.sclk_table.count++;
699                 }
700         }
701
702         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
703                 "MCLK dependency table is missing. This table is mandatory", return -EINVAL);
704         /* Initialize Mclk DPM table based on allow Mclk values */
705         data->dpm_table.mclk_table.count = 0;
706         for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
707                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value !=
708                         allowed_vdd_mclk_table->entries[i].clk) {
709                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
710                                 allowed_vdd_mclk_table->entries[i].clk;
711                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0;
712                         data->dpm_table.mclk_table.count++;
713                 }
714         }
715
716         /* Initialize Vddc DPM table based on allow Vddc values.  And populate corresponding std values. */
717         for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
718                 data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
719                 data->dpm_table.vddc_table.dpm_levels[i].param1 = std_voltage_table->entries[i].Leakage;
720                 /* param1 is for corresponding std voltage */
721                 data->dpm_table.vddc_table.dpm_levels[i].enabled = 1;
722         }
723
724         data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count;
725         allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
726
727         if (NULL != allowed_vdd_mclk_table) {
728                 /* Initialize Vddci DPM table based on allow Mclk values */
729                 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
730                         data->dpm_table.vddci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
731                         data->dpm_table.vddci_table.dpm_levels[i].enabled = 1;
732                 }
733                 data->dpm_table.vddci_table.count = allowed_vdd_mclk_table->count;
734         }
735
736         allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk;
737
738         if (NULL != allowed_vdd_mclk_table) {
739                 /*
740                  * Initialize MVDD DPM table based on allow Mclk
741                  * values
742                  */
743                 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
744                         data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
745                         data->dpm_table.mvdd_table.dpm_levels[i].enabled = 1;
746                 }
747                 data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count;
748         }
749
750         return 0;
751 }
752
753 static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr)
754 {
755         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
756         struct phm_ppt_v1_information *table_info =
757                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
758         uint32_t i;
759
760         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
761         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
762
763         if (table_info == NULL)
764                 return -EINVAL;
765
766         dep_sclk_table = table_info->vdd_dep_on_sclk;
767         dep_mclk_table = table_info->vdd_dep_on_mclk;
768
769         PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
770                         "SCLK dependency table is missing.",
771                         return -EINVAL);
772         PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
773                         "SCLK dependency table count is 0.",
774                         return -EINVAL);
775
776         PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
777                         "MCLK dependency table is missing.",
778                         return -EINVAL);
779         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
780                         "MCLK dependency table count is 0",
781                         return -EINVAL);
782
783         /* Initialize Sclk DPM table based on allow Sclk values */
784         data->dpm_table.sclk_table.count = 0;
785         for (i = 0; i < dep_sclk_table->count; i++) {
786                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
787                                                 dep_sclk_table->entries[i].clk) {
788
789                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
790                                         dep_sclk_table->entries[i].clk;
791
792                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
793                                         (i == 0) ? true : false;
794                         data->dpm_table.sclk_table.count++;
795                 }
796         }
797         if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0)
798                 hwmgr->platform_descriptor.overdriveLimit.engineClock = dep_sclk_table->entries[i-1].clk;
799         /* Initialize Mclk DPM table based on allow Mclk values */
800         data->dpm_table.mclk_table.count = 0;
801         for (i = 0; i < dep_mclk_table->count; i++) {
802                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
803                                 [data->dpm_table.mclk_table.count - 1].value !=
804                                                 dep_mclk_table->entries[i].clk) {
805                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
806                                                         dep_mclk_table->entries[i].clk;
807                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
808                                                         (i == 0) ? true : false;
809                         data->dpm_table.mclk_table.count++;
810                 }
811         }
812
813         if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0)
814                 hwmgr->platform_descriptor.overdriveLimit.memoryClock = dep_mclk_table->entries[i-1].clk;
815         return 0;
816 }
817
818 static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
819 {
820         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
821         struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
822         struct phm_ppt_v1_information *table_info =
823                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
824         uint32_t i;
825
826         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
827         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
828         struct phm_odn_performance_level *entries;
829
830         if (table_info == NULL)
831                 return -EINVAL;
832
833         dep_sclk_table = table_info->vdd_dep_on_sclk;
834         dep_mclk_table = table_info->vdd_dep_on_mclk;
835
836         odn_table->odn_core_clock_dpm_levels.num_of_pl =
837                                                 data->golden_dpm_table.sclk_table.count;
838         entries = odn_table->odn_core_clock_dpm_levels.entries;
839         for (i=0; i<data->golden_dpm_table.sclk_table.count; i++) {
840                 entries[i].clock = data->golden_dpm_table.sclk_table.dpm_levels[i].value;
841                 entries[i].enabled = true;
842                 entries[i].vddc = dep_sclk_table->entries[i].vddc;
843         }
844
845         smu_get_voltage_dependency_table_ppt_v1(dep_sclk_table,
846                 (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk));
847
848         odn_table->odn_memory_clock_dpm_levels.num_of_pl =
849                                                 data->golden_dpm_table.mclk_table.count;
850         entries = odn_table->odn_memory_clock_dpm_levels.entries;
851         for (i=0; i<data->golden_dpm_table.mclk_table.count; i++) {
852                 entries[i].clock = data->golden_dpm_table.mclk_table.dpm_levels[i].value;
853                 entries[i].enabled = true;
854                 entries[i].vddc = dep_mclk_table->entries[i].vddc;
855         }
856
857         smu_get_voltage_dependency_table_ppt_v1(dep_mclk_table,
858                 (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk));
859
860         return 0;
861 }
862
863 static void smu7_setup_voltage_range_from_vbios(struct pp_hwmgr *hwmgr)
864 {
865         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
866         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
867         struct phm_ppt_v1_information *table_info =
868                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
869         uint32_t min_vddc = 0;
870         uint32_t max_vddc = 0;
871
872         if (!table_info)
873                 return;
874
875         dep_sclk_table = table_info->vdd_dep_on_sclk;
876
877         atomctrl_get_voltage_range(hwmgr, &max_vddc, &min_vddc);
878
879         if (min_vddc == 0 || min_vddc > 2000
880                 || min_vddc > dep_sclk_table->entries[0].vddc)
881                 min_vddc = dep_sclk_table->entries[0].vddc;
882
883         if (max_vddc == 0 || max_vddc > 2000
884                 || max_vddc < dep_sclk_table->entries[dep_sclk_table->count-1].vddc)
885                 max_vddc = dep_sclk_table->entries[dep_sclk_table->count-1].vddc;
886
887         data->odn_dpm_table.min_vddc = min_vddc;
888         data->odn_dpm_table.max_vddc = max_vddc;
889 }
890
891 static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
892 {
893         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
894         struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
895         struct phm_ppt_v1_information *table_info =
896                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
897         uint32_t i;
898
899         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
900         struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table;
901
902         if (table_info == NULL)
903                 return;
904
905         for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
906                 if (odn_table->odn_core_clock_dpm_levels.entries[i].clock !=
907                                         data->dpm_table.sclk_table.dpm_levels[i].value) {
908                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
909                         break;
910                 }
911         }
912
913         for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
914                 if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock !=
915                                         data->dpm_table.mclk_table.dpm_levels[i].value) {
916                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
917                         break;
918                 }
919         }
920
921         dep_table = table_info->vdd_dep_on_mclk;
922         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk);
923
924         for (i = 0; i < dep_table->count; i++) {
925                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
926                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK;
927                         return;
928                 }
929         }
930
931         dep_table = table_info->vdd_dep_on_sclk;
932         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk);
933         for (i = 0; i < dep_table->count; i++) {
934                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
935                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK;
936                         return;
937                 }
938         }
939         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
940                 data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC;
941                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK;
942         }
943 }
944
945 static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
946 {
947         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
948
949         smu7_reset_dpm_tables(hwmgr);
950
951         if (hwmgr->pp_table_version == PP_TABLE_V1)
952                 smu7_setup_dpm_tables_v1(hwmgr);
953         else if (hwmgr->pp_table_version == PP_TABLE_V0)
954                 smu7_setup_dpm_tables_v0(hwmgr);
955
956         smu7_setup_default_pcie_table(hwmgr);
957
958         /* save a copy of the default DPM table */
959         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
960                         sizeof(struct smu7_dpm_table));
961
962         /* initialize ODN table */
963         if (hwmgr->od_enabled) {
964                 if (data->odn_dpm_table.max_vddc) {
965                         smu7_check_dpm_table_updated(hwmgr);
966                 } else {
967                         smu7_setup_voltage_range_from_vbios(hwmgr);
968                         smu7_odn_initial_default_setting(hwmgr);
969                 }
970         }
971         return 0;
972 }
973
974 static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
975 {
976
977         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
978                         PHM_PlatformCaps_RegulatorHot))
979                 return smum_send_msg_to_smc(hwmgr,
980                                 PPSMC_MSG_EnableVRHotGPIOInterrupt);
981
982         return 0;
983 }
984
985 static int smu7_enable_sclk_control(struct pp_hwmgr *hwmgr)
986 {
987         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
988                         SCLK_PWRMGT_OFF, 0);
989         return 0;
990 }
991
992 static int smu7_enable_ulv(struct pp_hwmgr *hwmgr)
993 {
994         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
995
996         if (data->ulv_supported)
997                 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableULV);
998
999         return 0;
1000 }
1001
1002 static int smu7_disable_ulv(struct pp_hwmgr *hwmgr)
1003 {
1004         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1005
1006         if (data->ulv_supported)
1007                 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableULV);
1008
1009         return 0;
1010 }
1011
1012 static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
1013 {
1014         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1015                         PHM_PlatformCaps_SclkDeepSleep)) {
1016                 if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MASTER_DeepSleep_ON))
1017                         PP_ASSERT_WITH_CODE(false,
1018                                         "Attempt to enable Master Deep Sleep switch failed!",
1019                                         return -EINVAL);
1020         } else {
1021                 if (smum_send_msg_to_smc(hwmgr,
1022                                 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
1023                         PP_ASSERT_WITH_CODE(false,
1024                                         "Attempt to disable Master Deep Sleep switch failed!",
1025                                         return -EINVAL);
1026                 }
1027         }
1028
1029         return 0;
1030 }
1031
1032 static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
1033 {
1034         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1035                         PHM_PlatformCaps_SclkDeepSleep)) {
1036                 if (smum_send_msg_to_smc(hwmgr,
1037                                 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
1038                         PP_ASSERT_WITH_CODE(false,
1039                                         "Attempt to disable Master Deep Sleep switch failed!",
1040                                         return -EINVAL);
1041                 }
1042         }
1043
1044         return 0;
1045 }
1046
1047 static int smu7_disable_sclk_vce_handshake(struct pp_hwmgr *hwmgr)
1048 {
1049         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1050         uint32_t soft_register_value = 0;
1051         uint32_t handshake_disables_offset = data->soft_regs_start
1052                                 + smum_get_offsetof(hwmgr,
1053                                         SMU_SoftRegisters, HandshakeDisables);
1054
1055         soft_register_value = cgs_read_ind_register(hwmgr->device,
1056                                 CGS_IND_REG__SMC, handshake_disables_offset);
1057         soft_register_value |= SMU7_VCE_SCLK_HANDSHAKE_DISABLE;
1058         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1059                         handshake_disables_offset, soft_register_value);
1060         return 0;
1061 }
1062
1063 static int smu7_disable_handshake_uvd(struct pp_hwmgr *hwmgr)
1064 {
1065         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1066         uint32_t soft_register_value = 0;
1067         uint32_t handshake_disables_offset = data->soft_regs_start
1068                                 + smum_get_offsetof(hwmgr,
1069                                         SMU_SoftRegisters, HandshakeDisables);
1070
1071         soft_register_value = cgs_read_ind_register(hwmgr->device,
1072                                 CGS_IND_REG__SMC, handshake_disables_offset);
1073         soft_register_value |= smum_get_mac_definition(hwmgr,
1074                                         SMU_UVD_MCLK_HANDSHAKE_DISABLE);
1075         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1076                         handshake_disables_offset, soft_register_value);
1077         return 0;
1078 }
1079
1080 static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
1081 {
1082         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1083
1084         /* enable SCLK dpm */
1085         if (!data->sclk_dpm_key_disabled) {
1086                 if (hwmgr->chip_id == CHIP_VEGAM)
1087                         smu7_disable_sclk_vce_handshake(hwmgr);
1088
1089                 PP_ASSERT_WITH_CODE(
1090                 (0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Enable)),
1091                 "Failed to enable SCLK DPM during DPM Start Function!",
1092                 return -EINVAL);
1093         }
1094
1095         /* enable MCLK dpm */
1096         if (0 == data->mclk_dpm_key_disabled) {
1097                 if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK))
1098                         smu7_disable_handshake_uvd(hwmgr);
1099
1100                 PP_ASSERT_WITH_CODE(
1101                                 (0 == smum_send_msg_to_smc(hwmgr,
1102                                                 PPSMC_MSG_MCLKDPM_Enable)),
1103                                 "Failed to enable MCLK DPM during DPM Start Function!",
1104                                 return -EINVAL);
1105
1106                 if (hwmgr->chip_family != CHIP_VEGAM)
1107                         PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
1108
1109
1110                 if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
1111                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x5);
1112                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x5);
1113                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x100005);
1114                         udelay(10);
1115                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x400005);
1116                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x400005);
1117                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x500005);
1118                 } else {
1119                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
1120                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
1121                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
1122                         udelay(10);
1123                         if (hwmgr->chip_id == CHIP_VEGAM) {
1124                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400009);
1125                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400009);
1126                         } else {
1127                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
1128                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
1129                         }
1130                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
1131                 }
1132         }
1133
1134         return 0;
1135 }
1136
1137 static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
1138 {
1139         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1140
1141         /*enable general power management */
1142
1143         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1144                         GLOBAL_PWRMGT_EN, 1);
1145
1146         /* enable sclk deep sleep */
1147
1148         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1149                         DYNAMIC_PM_EN, 1);
1150
1151         /* prepare for PCIE DPM */
1152
1153         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1154                         data->soft_regs_start +
1155                         smum_get_offsetof(hwmgr, SMU_SoftRegisters,
1156                                                 VoltageChangeTimeout), 0x1000);
1157         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
1158                         SWRST_COMMAND_1, RESETLC, 0x0);
1159
1160         if (hwmgr->chip_family == AMDGPU_FAMILY_CI)
1161                 cgs_write_register(hwmgr->device, 0x1488,
1162                         (cgs_read_register(hwmgr->device, 0x1488) & ~0x1));
1163
1164         if (smu7_enable_sclk_mclk_dpm(hwmgr)) {
1165                 pr_err("Failed to enable Sclk DPM and Mclk DPM!");
1166                 return -EINVAL;
1167         }
1168
1169         /* enable PCIE dpm */
1170         if (0 == data->pcie_dpm_key_disabled) {
1171                 PP_ASSERT_WITH_CODE(
1172                                 (0 == smum_send_msg_to_smc(hwmgr,
1173                                                 PPSMC_MSG_PCIeDPM_Enable)),
1174                                 "Failed to enable pcie DPM during DPM Start Function!",
1175                                 return -EINVAL);
1176         }
1177
1178         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1179                                 PHM_PlatformCaps_Falcon_QuickTransition)) {
1180                 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr,
1181                                 PPSMC_MSG_EnableACDCGPIOInterrupt)),
1182                                 "Failed to enable AC DC GPIO Interrupt!",
1183                                 );
1184         }
1185
1186         return 0;
1187 }
1188
1189 static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
1190 {
1191         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1192
1193         /* disable SCLK dpm */
1194         if (!data->sclk_dpm_key_disabled) {
1195                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1196                                 "Trying to disable SCLK DPM when DPM is disabled",
1197                                 return 0);
1198                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Disable);
1199         }
1200
1201         /* disable MCLK dpm */
1202         if (!data->mclk_dpm_key_disabled) {
1203                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1204                                 "Trying to disable MCLK DPM when DPM is disabled",
1205                                 return 0);
1206                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_Disable);
1207         }
1208
1209         return 0;
1210 }
1211
1212 static int smu7_stop_dpm(struct pp_hwmgr *hwmgr)
1213 {
1214         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1215
1216         /* disable general power management */
1217         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1218                         GLOBAL_PWRMGT_EN, 0);
1219         /* disable sclk deep sleep */
1220         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1221                         DYNAMIC_PM_EN, 0);
1222
1223         /* disable PCIE dpm */
1224         if (!data->pcie_dpm_key_disabled) {
1225                 PP_ASSERT_WITH_CODE(
1226                                 (smum_send_msg_to_smc(hwmgr,
1227                                                 PPSMC_MSG_PCIeDPM_Disable) == 0),
1228                                 "Failed to disable pcie DPM during DPM Stop Function!",
1229                                 return -EINVAL);
1230         }
1231
1232         smu7_disable_sclk_mclk_dpm(hwmgr);
1233
1234         PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1235                         "Trying to disable voltage DPM when DPM is disabled",
1236                         return 0);
1237
1238         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Disable);
1239
1240         return 0;
1241 }
1242
1243 static void smu7_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
1244 {
1245         bool protection;
1246         enum DPM_EVENT_SRC src;
1247
1248         switch (sources) {
1249         default:
1250                 pr_err("Unknown throttling event sources.");
1251                 /* fall through */
1252         case 0:
1253                 protection = false;
1254                 /* src is unused */
1255                 break;
1256         case (1 << PHM_AutoThrottleSource_Thermal):
1257                 protection = true;
1258                 src = DPM_EVENT_SRC_DIGITAL;
1259                 break;
1260         case (1 << PHM_AutoThrottleSource_External):
1261                 protection = true;
1262                 src = DPM_EVENT_SRC_EXTERNAL;
1263                 break;
1264         case (1 << PHM_AutoThrottleSource_External) |
1265                         (1 << PHM_AutoThrottleSource_Thermal):
1266                 protection = true;
1267                 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
1268                 break;
1269         }
1270         /* Order matters - don't enable thermal protection for the wrong source. */
1271         if (protection) {
1272                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
1273                                 DPM_EVENT_SRC, src);
1274                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1275                                 THERMAL_PROTECTION_DIS,
1276                                 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1277                                                 PHM_PlatformCaps_ThermalController));
1278         } else
1279                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1280                                 THERMAL_PROTECTION_DIS, 1);
1281 }
1282
1283 static int smu7_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
1284                 PHM_AutoThrottleSource source)
1285 {
1286         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1287
1288         if (!(data->active_auto_throttle_sources & (1 << source))) {
1289                 data->active_auto_throttle_sources |= 1 << source;
1290                 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
1291         }
1292         return 0;
1293 }
1294
1295 static int smu7_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
1296 {
1297         return smu7_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
1298 }
1299
1300 static int smu7_disable_auto_throttle_source(struct pp_hwmgr *hwmgr,
1301                 PHM_AutoThrottleSource source)
1302 {
1303         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1304
1305         if (data->active_auto_throttle_sources & (1 << source)) {
1306                 data->active_auto_throttle_sources &= ~(1 << source);
1307                 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
1308         }
1309         return 0;
1310 }
1311
1312 static int smu7_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
1313 {
1314         return smu7_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
1315 }
1316
1317 static int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr)
1318 {
1319         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1320         data->pcie_performance_request = true;
1321
1322         return 0;
1323 }
1324
1325 static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1326 {
1327         int tmp_result = 0;
1328         int result = 0;
1329
1330         if (smu7_voltage_control(hwmgr)) {
1331                 tmp_result = smu7_enable_voltage_control(hwmgr);
1332                 PP_ASSERT_WITH_CODE(tmp_result == 0,
1333                                 "Failed to enable voltage control!",
1334                                 result = tmp_result);
1335
1336                 tmp_result = smu7_construct_voltage_tables(hwmgr);
1337                 PP_ASSERT_WITH_CODE((0 == tmp_result),
1338                                 "Failed to construct voltage tables!",
1339                                 result = tmp_result);
1340         }
1341         smum_initialize_mc_reg_table(hwmgr);
1342
1343         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1344                         PHM_PlatformCaps_EngineSpreadSpectrumSupport))
1345                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1346                                 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
1347
1348         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1349                         PHM_PlatformCaps_ThermalController))
1350                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1351                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
1352
1353         tmp_result = smu7_program_static_screen_threshold_parameters(hwmgr);
1354         PP_ASSERT_WITH_CODE((0 == tmp_result),
1355                         "Failed to program static screen threshold parameters!",
1356                         result = tmp_result);
1357
1358         tmp_result = smu7_enable_display_gap(hwmgr);
1359         PP_ASSERT_WITH_CODE((0 == tmp_result),
1360                         "Failed to enable display gap!", result = tmp_result);
1361
1362         tmp_result = smu7_program_voting_clients(hwmgr);
1363         PP_ASSERT_WITH_CODE((0 == tmp_result),
1364                         "Failed to program voting clients!", result = tmp_result);
1365
1366         tmp_result = smum_process_firmware_header(hwmgr);
1367         PP_ASSERT_WITH_CODE((0 == tmp_result),
1368                         "Failed to process firmware header!", result = tmp_result);
1369
1370         if (hwmgr->chip_id != CHIP_VEGAM) {
1371                 tmp_result = smu7_initial_switch_from_arbf0_to_f1(hwmgr);
1372                 PP_ASSERT_WITH_CODE((0 == tmp_result),
1373                                 "Failed to initialize switch from ArbF0 to F1!",
1374                                 result = tmp_result);
1375         }
1376
1377         result = smu7_setup_default_dpm_tables(hwmgr);
1378         PP_ASSERT_WITH_CODE(0 == result,
1379                         "Failed to setup default DPM tables!", return result);
1380
1381         tmp_result = smum_init_smc_table(hwmgr);
1382         PP_ASSERT_WITH_CODE((0 == tmp_result),
1383                         "Failed to initialize SMC table!", result = tmp_result);
1384
1385         tmp_result = smu7_enable_vrhot_gpio_interrupt(hwmgr);
1386         PP_ASSERT_WITH_CODE((0 == tmp_result),
1387                         "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
1388
1389         smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay);
1390
1391         tmp_result = smu7_enable_sclk_control(hwmgr);
1392         PP_ASSERT_WITH_CODE((0 == tmp_result),
1393                         "Failed to enable SCLK control!", result = tmp_result);
1394
1395         tmp_result = smu7_enable_smc_voltage_controller(hwmgr);
1396         PP_ASSERT_WITH_CODE((0 == tmp_result),
1397                         "Failed to enable voltage control!", result = tmp_result);
1398
1399         tmp_result = smu7_enable_ulv(hwmgr);
1400         PP_ASSERT_WITH_CODE((0 == tmp_result),
1401                         "Failed to enable ULV!", result = tmp_result);
1402
1403         tmp_result = smu7_enable_deep_sleep_master_switch(hwmgr);
1404         PP_ASSERT_WITH_CODE((0 == tmp_result),
1405                         "Failed to enable deep sleep master switch!", result = tmp_result);
1406
1407         tmp_result = smu7_enable_didt_config(hwmgr);
1408         PP_ASSERT_WITH_CODE((tmp_result == 0),
1409                         "Failed to enable deep sleep master switch!", result = tmp_result);
1410
1411         tmp_result = smu7_start_dpm(hwmgr);
1412         PP_ASSERT_WITH_CODE((0 == tmp_result),
1413                         "Failed to start DPM!", result = tmp_result);
1414
1415         tmp_result = smu7_enable_smc_cac(hwmgr);
1416         PP_ASSERT_WITH_CODE((0 == tmp_result),
1417                         "Failed to enable SMC CAC!", result = tmp_result);
1418
1419         tmp_result = smu7_enable_power_containment(hwmgr);
1420         PP_ASSERT_WITH_CODE((0 == tmp_result),
1421                         "Failed to enable power containment!", result = tmp_result);
1422
1423         tmp_result = smu7_power_control_set_level(hwmgr);
1424         PP_ASSERT_WITH_CODE((0 == tmp_result),
1425                         "Failed to power control set level!", result = tmp_result);
1426
1427         tmp_result = smu7_enable_thermal_auto_throttle(hwmgr);
1428         PP_ASSERT_WITH_CODE((0 == tmp_result),
1429                         "Failed to enable thermal auto throttle!", result = tmp_result);
1430
1431         tmp_result = smu7_pcie_performance_request(hwmgr);
1432         PP_ASSERT_WITH_CODE((0 == tmp_result),
1433                         "pcie performance request failed!", result = tmp_result);
1434
1435         return 0;
1436 }
1437
1438 static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
1439 {
1440         if (!hwmgr->avfs_supported)
1441                 return 0;
1442
1443         if (enable) {
1444                 if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
1445                                 CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
1446                         PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
1447                                         hwmgr, PPSMC_MSG_EnableAvfs),
1448                                         "Failed to enable AVFS!",
1449                                         return -EINVAL);
1450                 }
1451         } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
1452                         CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
1453                 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
1454                                 hwmgr, PPSMC_MSG_DisableAvfs),
1455                                 "Failed to disable AVFS!",
1456                                 return -EINVAL);
1457         }
1458
1459         return 0;
1460 }
1461
1462 static int smu7_update_avfs(struct pp_hwmgr *hwmgr)
1463 {
1464         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1465
1466         if (!hwmgr->avfs_supported)
1467                 return 0;
1468
1469         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
1470                 smu7_avfs_control(hwmgr, false);
1471         } else if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
1472                 smu7_avfs_control(hwmgr, false);
1473                 smu7_avfs_control(hwmgr, true);
1474         } else {
1475                 smu7_avfs_control(hwmgr, true);
1476         }
1477
1478         return 0;
1479 }
1480
1481 int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
1482 {
1483         int tmp_result, result = 0;
1484
1485         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1486                         PHM_PlatformCaps_ThermalController))
1487                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1488                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1);
1489
1490         tmp_result = smu7_disable_power_containment(hwmgr);
1491         PP_ASSERT_WITH_CODE((tmp_result == 0),
1492                         "Failed to disable power containment!", result = tmp_result);
1493
1494         tmp_result = smu7_disable_smc_cac(hwmgr);
1495         PP_ASSERT_WITH_CODE((tmp_result == 0),
1496                         "Failed to disable SMC CAC!", result = tmp_result);
1497
1498         tmp_result = smu7_disable_didt_config(hwmgr);
1499         PP_ASSERT_WITH_CODE((tmp_result == 0),
1500                         "Failed to disable DIDT!", result = tmp_result);
1501
1502         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1503                         CG_SPLL_SPREAD_SPECTRUM, SSEN, 0);
1504         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1505                         GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0);
1506
1507         tmp_result = smu7_disable_thermal_auto_throttle(hwmgr);
1508         PP_ASSERT_WITH_CODE((tmp_result == 0),
1509                         "Failed to disable thermal auto throttle!", result = tmp_result);
1510
1511         tmp_result = smu7_avfs_control(hwmgr, false);
1512         PP_ASSERT_WITH_CODE((tmp_result == 0),
1513                         "Failed to disable AVFS!", result = tmp_result);
1514
1515         tmp_result = smu7_stop_dpm(hwmgr);
1516         PP_ASSERT_WITH_CODE((tmp_result == 0),
1517                         "Failed to stop DPM!", result = tmp_result);
1518
1519         tmp_result = smu7_disable_deep_sleep_master_switch(hwmgr);
1520         PP_ASSERT_WITH_CODE((tmp_result == 0),
1521                         "Failed to disable deep sleep master switch!", result = tmp_result);
1522
1523         tmp_result = smu7_disable_ulv(hwmgr);
1524         PP_ASSERT_WITH_CODE((tmp_result == 0),
1525                         "Failed to disable ULV!", result = tmp_result);
1526
1527         tmp_result = smu7_clear_voting_clients(hwmgr);
1528         PP_ASSERT_WITH_CODE((tmp_result == 0),
1529                         "Failed to clear voting clients!", result = tmp_result);
1530
1531         tmp_result = smu7_reset_to_default(hwmgr);
1532         PP_ASSERT_WITH_CODE((tmp_result == 0),
1533                         "Failed to reset to default!", result = tmp_result);
1534
1535         tmp_result = smu7_force_switch_to_arbf0(hwmgr);
1536         PP_ASSERT_WITH_CODE((tmp_result == 0),
1537                         "Failed to force to switch arbf0!", result = tmp_result);
1538
1539         return result;
1540 }
1541
1542 int smu7_reset_asic_tasks(struct pp_hwmgr *hwmgr)
1543 {
1544
1545         return 0;
1546 }
1547
1548 static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
1549 {
1550         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1551         struct phm_ppt_v1_information *table_info =
1552                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1553         struct amdgpu_device *adev = hwmgr->adev;
1554
1555         data->dll_default_on = false;
1556         data->mclk_dpm0_activity_target = 0xa;
1557         data->vddc_vddgfx_delta = 300;
1558         data->static_screen_threshold = SMU7_STATICSCREENTHRESHOLD_DFLT;
1559         data->static_screen_threshold_unit = SMU7_STATICSCREENTHRESHOLDUNIT_DFLT;
1560         data->voting_rights_clients[0] = SMU7_VOTINGRIGHTSCLIENTS_DFLT0;
1561         data->voting_rights_clients[1]= SMU7_VOTINGRIGHTSCLIENTS_DFLT1;
1562         data->voting_rights_clients[2] = SMU7_VOTINGRIGHTSCLIENTS_DFLT2;
1563         data->voting_rights_clients[3]= SMU7_VOTINGRIGHTSCLIENTS_DFLT3;
1564         data->voting_rights_clients[4]= SMU7_VOTINGRIGHTSCLIENTS_DFLT4;
1565         data->voting_rights_clients[5]= SMU7_VOTINGRIGHTSCLIENTS_DFLT5;
1566         data->voting_rights_clients[6]= SMU7_VOTINGRIGHTSCLIENTS_DFLT6;
1567         data->voting_rights_clients[7]= SMU7_VOTINGRIGHTSCLIENTS_DFLT7;
1568
1569         data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
1570         data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
1571         data->pcie_dpm_key_disabled = hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
1572         /* need to set voltage control types before EVV patching */
1573         data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE;
1574         data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE;
1575         data->mvdd_control = SMU7_VOLTAGE_CONTROL_NONE;
1576         data->enable_tdc_limit_feature = true;
1577         data->enable_pkg_pwr_tracking_feature = true;
1578         data->force_pcie_gen = PP_PCIEGenInvalid;
1579         data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false;
1580         data->current_profile_setting.bupdate_sclk = 1;
1581         data->current_profile_setting.sclk_up_hyst = 0;
1582         data->current_profile_setting.sclk_down_hyst = 100;
1583         data->current_profile_setting.sclk_activity = SMU7_SCLK_TARGETACTIVITY_DFLT;
1584         data->current_profile_setting.bupdate_mclk = 1;
1585         data->current_profile_setting.mclk_up_hyst = 0;
1586         data->current_profile_setting.mclk_down_hyst = 100;
1587         data->current_profile_setting.mclk_activity = SMU7_MCLK_TARGETACTIVITY_DFLT;
1588         hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D];
1589         hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1590         hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1591
1592         if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker) {
1593                 uint8_t tmp1, tmp2;
1594                 uint16_t tmp3 = 0;
1595                 atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2,
1596                                                 &tmp3);
1597                 tmp3 = (tmp3 >> 5) & 0x3;
1598                 data->vddc_phase_shed_control = ((tmp3 << 1) | (tmp3 >> 1)) & 0x3;
1599         } else if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
1600                 data->vddc_phase_shed_control = 1;
1601         } else {
1602                 data->vddc_phase_shed_control = 0;
1603         }
1604
1605         if (hwmgr->chip_id  == CHIP_HAWAII) {
1606                 data->thermal_temp_setting.temperature_low = 94500;
1607                 data->thermal_temp_setting.temperature_high = 95000;
1608                 data->thermal_temp_setting.temperature_shutdown = 104000;
1609         } else {
1610                 data->thermal_temp_setting.temperature_low = 99500;
1611                 data->thermal_temp_setting.temperature_high = 100000;
1612                 data->thermal_temp_setting.temperature_shutdown = 104000;
1613         }
1614
1615         data->fast_watermark_threshold = 100;
1616         if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1617                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
1618                 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1619         else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1620                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
1621                 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1622
1623         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1624                         PHM_PlatformCaps_ControlVDDGFX)) {
1625                 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1626                         VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) {
1627                         data->vdd_gfx_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1628                 }
1629         }
1630
1631         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1632                         PHM_PlatformCaps_EnableMVDDControl)) {
1633                 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1634                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
1635                         data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1636                 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1637                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
1638                         data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1639         }
1640
1641         if (SMU7_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control)
1642                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1643                         PHM_PlatformCaps_ControlVDDGFX);
1644
1645         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1646                         PHM_PlatformCaps_ControlVDDCI)) {
1647                 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1648                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
1649                         data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1650                 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1651                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
1652                         data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1653         }
1654
1655         if (data->mvdd_control == SMU7_VOLTAGE_CONTROL_NONE)
1656                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1657                                 PHM_PlatformCaps_EnableMVDDControl);
1658
1659         if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE)
1660                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1661                                 PHM_PlatformCaps_ControlVDDCI);
1662
1663         if ((hwmgr->pp_table_version != PP_TABLE_V0) && (hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK)
1664                 && (table_info->cac_dtp_table->usClockStretchAmount != 0))
1665                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1666                                         PHM_PlatformCaps_ClockStretcher);
1667
1668         data->pcie_gen_performance.max = PP_PCIEGen1;
1669         data->pcie_gen_performance.min = PP_PCIEGen3;
1670         data->pcie_gen_power_saving.max = PP_PCIEGen1;
1671         data->pcie_gen_power_saving.min = PP_PCIEGen3;
1672         data->pcie_lane_performance.max = 0;
1673         data->pcie_lane_performance.min = 16;
1674         data->pcie_lane_power_saving.max = 0;
1675         data->pcie_lane_power_saving.min = 16;
1676
1677
1678         if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
1679                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1680                               PHM_PlatformCaps_UVDPowerGating);
1681         if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
1682                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1683                               PHM_PlatformCaps_VCEPowerGating);
1684 }
1685
1686 /**
1687 * Get Leakage VDDC based on leakage ID.
1688 *
1689 * @param    hwmgr  the address of the powerplay hardware manager.
1690 * @return   always 0
1691 */
1692 static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr)
1693 {
1694         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1695         uint16_t vv_id;
1696         uint16_t vddc = 0;
1697         uint16_t vddgfx = 0;
1698         uint16_t i, j;
1699         uint32_t sclk = 0;
1700         struct phm_ppt_v1_information *table_info =
1701                         (struct phm_ppt_v1_information *)hwmgr->pptable;
1702         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = NULL;
1703
1704
1705         for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
1706                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1707
1708                 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1709                         if ((hwmgr->pp_table_version == PP_TABLE_V1)
1710                             && !phm_get_sclk_for_voltage_evv(hwmgr,
1711                                                 table_info->vddgfx_lookup_table, vv_id, &sclk)) {
1712                                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1713                                                         PHM_PlatformCaps_ClockStretcher)) {
1714                                         sclk_table = table_info->vdd_dep_on_sclk;
1715
1716                                         for (j = 1; j < sclk_table->count; j++) {
1717                                                 if (sclk_table->entries[j].clk == sclk &&
1718                                                                 sclk_table->entries[j].cks_enable == 0) {
1719                                                         sclk += 5000;
1720                                                         break;
1721                                                 }
1722                                         }
1723                                 }
1724                                 if (0 == atomctrl_get_voltage_evv_on_sclk
1725                                     (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk,
1726                                      vv_id, &vddgfx)) {
1727                                         /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */
1728                                         PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -EINVAL);
1729
1730                                         /* the voltage should not be zero nor equal to leakage ID */
1731                                         if (vddgfx != 0 && vddgfx != vv_id) {
1732                                                 data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx;
1733                                                 data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = vv_id;
1734                                                 data->vddcgfx_leakage.count++;
1735                                         }
1736                                 } else {
1737                                         pr_info("Error retrieving EVV voltage value!\n");
1738                                 }
1739                         }
1740                 } else {
1741                         if ((hwmgr->pp_table_version == PP_TABLE_V0)
1742                                 || !phm_get_sclk_for_voltage_evv(hwmgr,
1743                                         table_info->vddc_lookup_table, vv_id, &sclk)) {
1744                                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1745                                                 PHM_PlatformCaps_ClockStretcher)) {
1746                                         if (table_info == NULL)
1747                                                 return -EINVAL;
1748                                         sclk_table = table_info->vdd_dep_on_sclk;
1749
1750                                         for (j = 1; j < sclk_table->count; j++) {
1751                                                 if (sclk_table->entries[j].clk == sclk &&
1752                                                                 sclk_table->entries[j].cks_enable == 0) {
1753                                                         sclk += 5000;
1754                                                         break;
1755                                                 }
1756                                         }
1757                                 }
1758
1759                                 if (phm_get_voltage_evv_on_sclk(hwmgr,
1760                                                         VOLTAGE_TYPE_VDDC,
1761                                                         sclk, vv_id, &vddc) == 0) {
1762                                         if (vddc >= 2000 || vddc == 0)
1763                                                 return -EINVAL;
1764                                 } else {
1765                                         pr_debug("failed to retrieving EVV voltage!\n");
1766                                         continue;
1767                                 }
1768
1769                                 /* the voltage should not be zero nor equal to leakage ID */
1770                                 if (vddc != 0 && vddc != vv_id) {
1771                                         data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc);
1772                                         data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
1773                                         data->vddc_leakage.count++;
1774                                 }
1775                         }
1776                 }
1777         }
1778
1779         return 0;
1780 }
1781
1782 /**
1783  * Change virtual leakage voltage to actual value.
1784  *
1785  * @param     hwmgr  the address of the powerplay hardware manager.
1786  * @param     pointer to changing voltage
1787  * @param     pointer to leakage table
1788  */
1789 static void smu7_patch_ppt_v1_with_vdd_leakage(struct pp_hwmgr *hwmgr,
1790                 uint16_t *voltage, struct smu7_leakage_voltage *leakage_table)
1791 {
1792         uint32_t index;
1793
1794         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
1795         for (index = 0; index < leakage_table->count; index++) {
1796                 /* if this voltage matches a leakage voltage ID */
1797                 /* patch with actual leakage voltage */
1798                 if (leakage_table->leakage_id[index] == *voltage) {
1799                         *voltage = leakage_table->actual_voltage[index];
1800                         break;
1801                 }
1802         }
1803
1804         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
1805                 pr_err("Voltage value looks like a Leakage ID but it's not patched \n");
1806 }
1807
1808 /**
1809 * Patch voltage lookup table by EVV leakages.
1810 *
1811 * @param     hwmgr  the address of the powerplay hardware manager.
1812 * @param     pointer to voltage lookup table
1813 * @param     pointer to leakage table
1814 * @return     always 0
1815 */
1816 static int smu7_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
1817                 phm_ppt_v1_voltage_lookup_table *lookup_table,
1818                 struct smu7_leakage_voltage *leakage_table)
1819 {
1820         uint32_t i;
1821
1822         for (i = 0; i < lookup_table->count; i++)
1823                 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr,
1824                                 &lookup_table->entries[i].us_vdd, leakage_table);
1825
1826         return 0;
1827 }
1828
1829 static int smu7_patch_clock_voltage_limits_with_vddc_leakage(
1830                 struct pp_hwmgr *hwmgr, struct smu7_leakage_voltage *leakage_table,
1831                 uint16_t *vddc)
1832 {
1833         struct phm_ppt_v1_information *table_info =
1834                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1835         smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
1836         hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
1837                         table_info->max_clock_voltage_on_dc.vddc;
1838         return 0;
1839 }
1840
1841 static int smu7_patch_voltage_dependency_tables_with_lookup_table(
1842                 struct pp_hwmgr *hwmgr)
1843 {
1844         uint8_t entry_id;
1845         uint8_t voltage_id;
1846         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1847         struct phm_ppt_v1_information *table_info =
1848                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1849
1850         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1851                         table_info->vdd_dep_on_sclk;
1852         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
1853                         table_info->vdd_dep_on_mclk;
1854         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1855                         table_info->mm_dep_table;
1856
1857         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1858                 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
1859                         voltage_id = sclk_table->entries[entry_id].vddInd;
1860                         sclk_table->entries[entry_id].vddgfx =
1861                                 table_info->vddgfx_lookup_table->entries[voltage_id].us_vdd;
1862                 }
1863         } else {
1864                 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
1865                         voltage_id = sclk_table->entries[entry_id].vddInd;
1866                         sclk_table->entries[entry_id].vddc =
1867                                 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
1868                 }
1869         }
1870
1871         for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
1872                 voltage_id = mclk_table->entries[entry_id].vddInd;
1873                 mclk_table->entries[entry_id].vddc =
1874                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
1875         }
1876
1877         for (entry_id = 0; entry_id < mm_table->count; ++entry_id) {
1878                 voltage_id = mm_table->entries[entry_id].vddcInd;
1879                 mm_table->entries[entry_id].vddc =
1880                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
1881         }
1882
1883         return 0;
1884
1885 }
1886
1887 static int phm_add_voltage(struct pp_hwmgr *hwmgr,
1888                         phm_ppt_v1_voltage_lookup_table *look_up_table,
1889                         phm_ppt_v1_voltage_lookup_record *record)
1890 {
1891         uint32_t i;
1892
1893         PP_ASSERT_WITH_CODE((NULL != look_up_table),
1894                 "Lookup Table empty.", return -EINVAL);
1895         PP_ASSERT_WITH_CODE((0 != look_up_table->count),
1896                 "Lookup Table empty.", return -EINVAL);
1897
1898         i = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
1899         PP_ASSERT_WITH_CODE((i >= look_up_table->count),
1900                 "Lookup Table is full.", return -EINVAL);
1901
1902         /* This is to avoid entering duplicate calculated records. */
1903         for (i = 0; i < look_up_table->count; i++) {
1904                 if (look_up_table->entries[i].us_vdd == record->us_vdd) {
1905                         if (look_up_table->entries[i].us_calculated == 1)
1906                                 return 0;
1907                         break;
1908                 }
1909         }
1910
1911         look_up_table->entries[i].us_calculated = 1;
1912         look_up_table->entries[i].us_vdd = record->us_vdd;
1913         look_up_table->entries[i].us_cac_low = record->us_cac_low;
1914         look_up_table->entries[i].us_cac_mid = record->us_cac_mid;
1915         look_up_table->entries[i].us_cac_high = record->us_cac_high;
1916         /* Only increment the count when we're appending, not replacing duplicate entry. */
1917         if (i == look_up_table->count)
1918                 look_up_table->count++;
1919
1920         return 0;
1921 }
1922
1923
1924 static int smu7_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
1925 {
1926         uint8_t entry_id;
1927         struct phm_ppt_v1_voltage_lookup_record v_record;
1928         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1929         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1930
1931         phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
1932         phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
1933
1934         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1935                 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
1936                         if (sclk_table->entries[entry_id].vdd_offset & (1 << 15))
1937                                 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx +
1938                                         sclk_table->entries[entry_id].vdd_offset - 0xFFFF;
1939                         else
1940                                 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx +
1941                                         sclk_table->entries[entry_id].vdd_offset;
1942
1943                         sclk_table->entries[entry_id].vddc =
1944                                 v_record.us_cac_low = v_record.us_cac_mid =
1945                                 v_record.us_cac_high = v_record.us_vdd;
1946
1947                         phm_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record);
1948                 }
1949
1950                 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
1951                         if (mclk_table->entries[entry_id].vdd_offset & (1 << 15))
1952                                 v_record.us_vdd = mclk_table->entries[entry_id].vddc +
1953                                         mclk_table->entries[entry_id].vdd_offset - 0xFFFF;
1954                         else
1955                                 v_record.us_vdd = mclk_table->entries[entry_id].vddc +
1956                                         mclk_table->entries[entry_id].vdd_offset;
1957
1958                         mclk_table->entries[entry_id].vddgfx = v_record.us_cac_low =
1959                                 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
1960                         phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
1961                 }
1962         }
1963         return 0;
1964 }
1965
1966 static int smu7_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
1967 {
1968         uint8_t entry_id;
1969         struct phm_ppt_v1_voltage_lookup_record v_record;
1970         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1971         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1972         phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1973
1974         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1975                 for (entry_id = 0; entry_id < mm_table->count; entry_id++) {
1976                         if (mm_table->entries[entry_id].vddgfx_offset & (1 << 15))
1977                                 v_record.us_vdd = mm_table->entries[entry_id].vddc +
1978                                         mm_table->entries[entry_id].vddgfx_offset - 0xFFFF;
1979                         else
1980                                 v_record.us_vdd = mm_table->entries[entry_id].vddc +
1981                                         mm_table->entries[entry_id].vddgfx_offset;
1982
1983                         /* Add the calculated VDDGFX to the VDDGFX lookup table */
1984                         mm_table->entries[entry_id].vddgfx = v_record.us_cac_low =
1985                                 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
1986                         phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
1987                 }
1988         }
1989         return 0;
1990 }
1991
1992 static int smu7_sort_lookup_table(struct pp_hwmgr *hwmgr,
1993                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
1994 {
1995         uint32_t table_size, i, j;
1996         struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
1997         table_size = lookup_table->count;
1998
1999         PP_ASSERT_WITH_CODE(0 != lookup_table->count,
2000                 "Lookup table is empty", return -EINVAL);
2001
2002         /* Sorting voltages */
2003         for (i = 0; i < table_size - 1; i++) {
2004                 for (j = i + 1; j > 0; j--) {
2005                         if (lookup_table->entries[j].us_vdd <
2006                                         lookup_table->entries[j - 1].us_vdd) {
2007                                 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
2008                                 lookup_table->entries[j - 1] = lookup_table->entries[j];
2009                                 lookup_table->entries[j] = tmp_voltage_lookup_record;
2010                         }
2011                 }
2012         }
2013
2014         return 0;
2015 }
2016
2017 static int smu7_complete_dependency_tables(struct pp_hwmgr *hwmgr)
2018 {
2019         int result = 0;
2020         int tmp_result;
2021         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2022         struct phm_ppt_v1_information *table_info =
2023                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2024
2025         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
2026                 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr,
2027                         table_info->vddgfx_lookup_table, &(data->vddcgfx_leakage));
2028                 if (tmp_result != 0)
2029                         result = tmp_result;
2030
2031                 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr,
2032                         &table_info->max_clock_voltage_on_dc.vddgfx, &(data->vddcgfx_leakage));
2033         } else {
2034
2035                 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr,
2036                                 table_info->vddc_lookup_table, &(data->vddc_leakage));
2037                 if (tmp_result)
2038                         result = tmp_result;
2039
2040                 tmp_result = smu7_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
2041                                 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
2042                 if (tmp_result)
2043                         result = tmp_result;
2044         }
2045
2046         tmp_result = smu7_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
2047         if (tmp_result)
2048                 result = tmp_result;
2049
2050         tmp_result = smu7_calc_voltage_dependency_tables(hwmgr);
2051         if (tmp_result)
2052                 result = tmp_result;
2053
2054         tmp_result = smu7_calc_mm_voltage_dependency_table(hwmgr);
2055         if (tmp_result)
2056                 result = tmp_result;
2057
2058         tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddgfx_lookup_table);
2059         if (tmp_result)
2060                 result = tmp_result;
2061
2062         tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
2063         if (tmp_result)
2064                 result = tmp_result;
2065
2066         return result;
2067 }
2068
2069 static int smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr *hwmgr)
2070 {
2071         struct phm_ppt_v1_information *table_info =
2072                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2073
2074         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
2075                                                 table_info->vdd_dep_on_sclk;
2076         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
2077                                                 table_info->vdd_dep_on_mclk;
2078
2079         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
2080                 "VDD dependency on SCLK table is missing.",
2081                 return -EINVAL);
2082         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
2083                 "VDD dependency on SCLK table has to have is missing.",
2084                 return -EINVAL);
2085
2086         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
2087                 "VDD dependency on MCLK table is missing",
2088                 return -EINVAL);
2089         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
2090                 "VDD dependency on MCLK table has to have is missing.",
2091                 return -EINVAL);
2092
2093         table_info->max_clock_voltage_on_ac.sclk =
2094                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
2095         table_info->max_clock_voltage_on_ac.mclk =
2096                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
2097         table_info->max_clock_voltage_on_ac.vddc =
2098                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
2099         table_info->max_clock_voltage_on_ac.vddci =
2100                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
2101
2102         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
2103         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
2104         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
2105         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = table_info->max_clock_voltage_on_ac.vddci;
2106
2107         return 0;
2108 }
2109
2110 static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
2111 {
2112         struct phm_ppt_v1_information *table_info =
2113                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
2114         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
2115         struct phm_ppt_v1_voltage_lookup_table *lookup_table;
2116         uint32_t i;
2117         uint32_t hw_revision, sub_vendor_id, sub_sys_id;
2118         struct amdgpu_device *adev = hwmgr->adev;
2119
2120         if (table_info != NULL) {
2121                 dep_mclk_table = table_info->vdd_dep_on_mclk;
2122                 lookup_table = table_info->vddc_lookup_table;
2123         } else
2124                 return 0;
2125
2126         hw_revision = adev->pdev->revision;
2127         sub_sys_id = adev->pdev->subsystem_device;
2128         sub_vendor_id = adev->pdev->subsystem_vendor;
2129
2130         if (hwmgr->chip_id == CHIP_POLARIS10 && hw_revision == 0xC7 &&
2131                         ((sub_sys_id == 0xb37 && sub_vendor_id == 0x1002) ||
2132                     (sub_sys_id == 0x4a8 && sub_vendor_id == 0x1043) ||
2133                     (sub_sys_id == 0x9480 && sub_vendor_id == 0x1682))) {
2134                 if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000)
2135                         return 0;
2136
2137                 for (i = 0; i < lookup_table->count; i++) {
2138                         if (lookup_table->entries[i].us_vdd < 0xff01 && lookup_table->entries[i].us_vdd >= 1000) {
2139                                 dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i;
2140                                 return 0;
2141                         }
2142                 }
2143         }
2144         return 0;
2145 }
2146
2147 static int smu7_thermal_parameter_init(struct pp_hwmgr *hwmgr)
2148 {
2149         struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2150         uint32_t temp_reg;
2151         struct phm_ppt_v1_information *table_info =
2152                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2153
2154
2155         if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
2156                 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
2157                 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
2158                 case 0:
2159                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
2160                         break;
2161                 case 1:
2162                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
2163                         break;
2164                 case 2:
2165                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
2166                         break;
2167                 case 3:
2168                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
2169                         break;
2170                 case 4:
2171                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
2172                         break;
2173                 default:
2174                         break;
2175                 }
2176                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
2177         }
2178
2179         if (table_info == NULL)
2180                 return 0;
2181
2182         if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
2183                 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
2184                 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
2185                         (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
2186
2187                 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
2188                         (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
2189
2190                 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
2191
2192                 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
2193
2194                 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
2195                         (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
2196
2197                 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
2198
2199                 table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
2200                                                                 (table_info->cac_dtp_table->usDefaultTargetOperatingTemp - 50) : 0;
2201
2202                 table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
2203                 table_info->cac_dtp_table->usOperatingTempStep = 1;
2204                 table_info->cac_dtp_table->usOperatingTempHyst = 1;
2205
2206                 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
2207                                hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
2208
2209                 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
2210                                hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
2211
2212                 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
2213                                table_info->cac_dtp_table->usOperatingTempMinLimit;
2214
2215                 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
2216                                table_info->cac_dtp_table->usOperatingTempMaxLimit;
2217
2218                 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
2219                                table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
2220
2221                 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
2222                                table_info->cac_dtp_table->usOperatingTempStep;
2223
2224                 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
2225                                table_info->cac_dtp_table->usTargetOperatingTemp;
2226                 if (hwmgr->feature_mask & PP_OD_FUZZY_FAN_CONTROL_MASK)
2227                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2228                                         PHM_PlatformCaps_ODFuzzyFanControlSupport);
2229         }
2230
2231         return 0;
2232 }
2233
2234 /**
2235  * Change virtual leakage voltage to actual value.
2236  *
2237  * @param     hwmgr  the address of the powerplay hardware manager.
2238  * @param     pointer to changing voltage
2239  * @param     pointer to leakage table
2240  */
2241 static void smu7_patch_ppt_v0_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2242                 uint32_t *voltage, struct smu7_leakage_voltage *leakage_table)
2243 {
2244         uint32_t index;
2245
2246         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2247         for (index = 0; index < leakage_table->count; index++) {
2248                 /* if this voltage matches a leakage voltage ID */
2249                 /* patch with actual leakage voltage */
2250                 if (leakage_table->leakage_id[index] == *voltage) {
2251                         *voltage = leakage_table->actual_voltage[index];
2252                         break;
2253                 }
2254         }
2255
2256         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2257                 pr_err("Voltage value looks like a Leakage ID but it's not patched \n");
2258 }
2259
2260
2261 static int smu7_patch_vddc(struct pp_hwmgr *hwmgr,
2262                               struct phm_clock_voltage_dependency_table *tab)
2263 {
2264         uint16_t i;
2265         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2266
2267         if (tab)
2268                 for (i = 0; i < tab->count; i++)
2269                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2270                                                 &data->vddc_leakage);
2271
2272         return 0;
2273 }
2274
2275 static int smu7_patch_vddci(struct pp_hwmgr *hwmgr,
2276                                struct phm_clock_voltage_dependency_table *tab)
2277 {
2278         uint16_t i;
2279         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2280
2281         if (tab)
2282                 for (i = 0; i < tab->count; i++)
2283                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2284                                                         &data->vddci_leakage);
2285
2286         return 0;
2287 }
2288
2289 static int smu7_patch_vce_vddc(struct pp_hwmgr *hwmgr,
2290                                   struct phm_vce_clock_voltage_dependency_table *tab)
2291 {
2292         uint16_t i;
2293         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2294
2295         if (tab)
2296                 for (i = 0; i < tab->count; i++)
2297                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2298                                                         &data->vddc_leakage);
2299
2300         return 0;
2301 }
2302
2303
2304 static int smu7_patch_uvd_vddc(struct pp_hwmgr *hwmgr,
2305                                   struct phm_uvd_clock_voltage_dependency_table *tab)
2306 {
2307         uint16_t i;
2308         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2309
2310         if (tab)
2311                 for (i = 0; i < tab->count; i++)
2312                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2313                                                         &data->vddc_leakage);
2314
2315         return 0;
2316 }
2317
2318 static int smu7_patch_vddc_shed_limit(struct pp_hwmgr *hwmgr,
2319                                          struct phm_phase_shedding_limits_table *tab)
2320 {
2321         uint16_t i;
2322         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2323
2324         if (tab)
2325                 for (i = 0; i < tab->count; i++)
2326                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].Voltage,
2327                                                         &data->vddc_leakage);
2328
2329         return 0;
2330 }
2331
2332 static int smu7_patch_samu_vddc(struct pp_hwmgr *hwmgr,
2333                                    struct phm_samu_clock_voltage_dependency_table *tab)
2334 {
2335         uint16_t i;
2336         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2337
2338         if (tab)
2339                 for (i = 0; i < tab->count; i++)
2340                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2341                                                         &data->vddc_leakage);
2342
2343         return 0;
2344 }
2345
2346 static int smu7_patch_acp_vddc(struct pp_hwmgr *hwmgr,
2347                                   struct phm_acp_clock_voltage_dependency_table *tab)
2348 {
2349         uint16_t i;
2350         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2351
2352         if (tab)
2353                 for (i = 0; i < tab->count; i++)
2354                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2355                                         &data->vddc_leakage);
2356
2357         return 0;
2358 }
2359
2360 static int smu7_patch_limits_vddc(struct pp_hwmgr *hwmgr,
2361                                   struct phm_clock_and_voltage_limits *tab)
2362 {
2363         uint32_t vddc, vddci;
2364         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2365
2366         if (tab) {
2367                 vddc = tab->vddc;
2368                 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc,
2369                                                    &data->vddc_leakage);
2370                 tab->vddc = vddc;
2371                 vddci = tab->vddci;
2372                 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddci,
2373                                                    &data->vddci_leakage);
2374                 tab->vddci = vddci;
2375         }
2376
2377         return 0;
2378 }
2379
2380 static int smu7_patch_cac_vddc(struct pp_hwmgr *hwmgr, struct phm_cac_leakage_table *tab)
2381 {
2382         uint32_t i;
2383         uint32_t vddc;
2384         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2385
2386         if (tab) {
2387                 for (i = 0; i < tab->count; i++) {
2388                         vddc = (uint32_t)(tab->entries[i].Vddc);
2389                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, &data->vddc_leakage);
2390                         tab->entries[i].Vddc = (uint16_t)vddc;
2391                 }
2392         }
2393
2394         return 0;
2395 }
2396
2397 static int smu7_patch_dependency_tables_with_leakage(struct pp_hwmgr *hwmgr)
2398 {
2399         int tmp;
2400
2401         tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk);
2402         if (tmp)
2403                 return -EINVAL;
2404
2405         tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_mclk);
2406         if (tmp)
2407                 return -EINVAL;
2408
2409         tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
2410         if (tmp)
2411                 return -EINVAL;
2412
2413         tmp = smu7_patch_vddci(hwmgr, hwmgr->dyn_state.vddci_dependency_on_mclk);
2414         if (tmp)
2415                 return -EINVAL;
2416
2417         tmp = smu7_patch_vce_vddc(hwmgr, hwmgr->dyn_state.vce_clock_voltage_dependency_table);
2418         if (tmp)
2419                 return -EINVAL;
2420
2421         tmp = smu7_patch_uvd_vddc(hwmgr, hwmgr->dyn_state.uvd_clock_voltage_dependency_table);
2422         if (tmp)
2423                 return -EINVAL;
2424
2425         tmp = smu7_patch_samu_vddc(hwmgr, hwmgr->dyn_state.samu_clock_voltage_dependency_table);
2426         if (tmp)
2427                 return -EINVAL;
2428
2429         tmp = smu7_patch_acp_vddc(hwmgr, hwmgr->dyn_state.acp_clock_voltage_dependency_table);
2430         if (tmp)
2431                 return -EINVAL;
2432
2433         tmp = smu7_patch_vddc_shed_limit(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table);
2434         if (tmp)
2435                 return -EINVAL;
2436
2437         tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_ac);
2438         if (tmp)
2439                 return -EINVAL;
2440
2441         tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_dc);
2442         if (tmp)
2443                 return -EINVAL;
2444
2445         tmp = smu7_patch_cac_vddc(hwmgr, hwmgr->dyn_state.cac_leakage_table);
2446         if (tmp)
2447                 return -EINVAL;
2448
2449         return 0;
2450 }
2451
2452
2453 static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr)
2454 {
2455         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2456
2457         struct phm_clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
2458         struct phm_clock_voltage_dependency_table *allowed_mclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
2459         struct phm_clock_voltage_dependency_table *allowed_mclk_vddci_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
2460
2461         PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table != NULL,
2462                 "VDDC dependency on SCLK table is missing. This table is mandatory",
2463                 return -EINVAL);
2464         PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table->count >= 1,
2465                 "VDDC dependency on SCLK table has to have is missing. This table is mandatory",
2466                 return -EINVAL);
2467
2468         PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table != NULL,
2469                 "VDDC dependency on MCLK table is missing. This table is mandatory",
2470                 return -EINVAL);
2471         PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table->count >= 1,
2472                 "VDD dependency on MCLK table has to have is missing. This table is mandatory",
2473                 return -EINVAL);
2474
2475         data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[0].v;
2476         data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
2477
2478         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
2479                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
2480         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
2481                 allowed_mclk_vddc_table->entries[allowed_mclk_vddc_table->count - 1].clk;
2482         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
2483                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
2484
2485         if (allowed_mclk_vddci_table != NULL && allowed_mclk_vddci_table->count >= 1) {
2486                 data->min_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[0].v;
2487                 data->max_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
2488         }
2489
2490         if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk->count >= 1)
2491                 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entries[hwmgr->dyn_state.vddci_dependency_on_mclk->count - 1].v;
2492
2493         return 0;
2494 }
2495
2496 static int smu7_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
2497 {
2498         kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
2499         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
2500         kfree(hwmgr->backend);
2501         hwmgr->backend = NULL;
2502
2503         return 0;
2504 }
2505
2506 static int smu7_get_elb_voltages(struct pp_hwmgr *hwmgr)
2507 {
2508         uint16_t virtual_voltage_id, vddc, vddci, efuse_voltage_id;
2509         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2510         int i;
2511
2512         if (atomctrl_get_leakage_id_from_efuse(hwmgr, &efuse_voltage_id) == 0) {
2513                 for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
2514                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2515                         if (atomctrl_get_leakage_vddc_base_on_leakage(hwmgr, &vddc, &vddci,
2516                                                                 virtual_voltage_id,
2517                                                                 efuse_voltage_id) == 0) {
2518                                 if (vddc != 0 && vddc != virtual_voltage_id) {
2519                                         data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc;
2520                                         data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id;
2521                                         data->vddc_leakage.count++;
2522                                 }
2523                                 if (vddci != 0 && vddci != virtual_voltage_id) {
2524                                         data->vddci_leakage.actual_voltage[data->vddci_leakage.count] = vddci;
2525                                         data->vddci_leakage.leakage_id[data->vddci_leakage.count] = virtual_voltage_id;
2526                                         data->vddci_leakage.count++;
2527                                 }
2528                         }
2529                 }
2530         }
2531         return 0;
2532 }
2533
2534 static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
2535 {
2536         struct smu7_hwmgr *data;
2537         int result = 0;
2538
2539         data = kzalloc(sizeof(struct smu7_hwmgr), GFP_KERNEL);
2540         if (data == NULL)
2541                 return -ENOMEM;
2542
2543         hwmgr->backend = data;
2544         smu7_patch_voltage_workaround(hwmgr);
2545         smu7_init_dpm_defaults(hwmgr);
2546
2547         /* Get leakage voltage based on leakage ID. */
2548         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2549                         PHM_PlatformCaps_EVV)) {
2550                 result = smu7_get_evv_voltages(hwmgr);
2551                 if (result) {
2552                         pr_info("Get EVV Voltage Failed.  Abort Driver loading!\n");
2553                         return -EINVAL;
2554                 }
2555         } else {
2556                 smu7_get_elb_voltages(hwmgr);
2557         }
2558
2559         if (hwmgr->pp_table_version == PP_TABLE_V1) {
2560                 smu7_complete_dependency_tables(hwmgr);
2561                 smu7_set_private_data_based_on_pptable_v1(hwmgr);
2562         } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
2563                 smu7_patch_dependency_tables_with_leakage(hwmgr);
2564                 smu7_set_private_data_based_on_pptable_v0(hwmgr);
2565         }
2566
2567         /* Initalize Dynamic State Adjustment Rule Settings */
2568         result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
2569
2570         if (0 == result) {
2571                 struct amdgpu_device *adev = hwmgr->adev;
2572
2573                 data->is_tlu_enabled = false;
2574
2575                 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
2576                                                         SMU7_MAX_HARDWARE_POWERLEVELS;
2577                 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
2578                 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
2579
2580                 data->pcie_gen_cap = adev->pm.pcie_gen_mask;
2581                 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
2582                         data->pcie_spc_cap = 20;
2583                 data->pcie_lane_cap = adev->pm.pcie_mlw_mask;
2584
2585                 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
2586 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
2587                 hwmgr->platform_descriptor.clockStep.engineClock = 500;
2588                 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
2589                 smu7_thermal_parameter_init(hwmgr);
2590         } else {
2591                 /* Ignore return value in here, we are cleaning up a mess. */
2592                 smu7_hwmgr_backend_fini(hwmgr);
2593         }
2594
2595         return 0;
2596 }
2597
2598 static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr)
2599 {
2600         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2601         uint32_t level, tmp;
2602
2603         if (!data->pcie_dpm_key_disabled) {
2604                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
2605                         level = 0;
2606                         tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
2607                         while (tmp >>= 1)
2608                                 level++;
2609
2610                         if (level)
2611                                 smum_send_msg_to_smc_with_parameter(hwmgr,
2612                                                 PPSMC_MSG_PCIeDPM_ForceLevel, level);
2613                 }
2614         }
2615
2616         if (!data->sclk_dpm_key_disabled) {
2617                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
2618                         level = 0;
2619                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
2620                         while (tmp >>= 1)
2621                                 level++;
2622
2623                         if (level)
2624                                 smum_send_msg_to_smc_with_parameter(hwmgr,
2625                                                 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2626                                                 (1 << level));
2627                 }
2628         }
2629
2630         if (!data->mclk_dpm_key_disabled) {
2631                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
2632                         level = 0;
2633                         tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
2634                         while (tmp >>= 1)
2635                                 level++;
2636
2637                         if (level)
2638                                 smum_send_msg_to_smc_with_parameter(hwmgr,
2639                                                 PPSMC_MSG_MCLKDPM_SetEnabledMask,
2640                                                 (1 << level));
2641                 }
2642         }
2643
2644         return 0;
2645 }
2646
2647 static int smu7_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
2648 {
2649         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2650
2651         if (hwmgr->pp_table_version == PP_TABLE_V1)
2652                 phm_apply_dal_min_voltage_request(hwmgr);
2653 /* TO DO  for v0 iceland and Ci*/
2654
2655         if (!data->sclk_dpm_key_disabled) {
2656                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
2657                         smum_send_msg_to_smc_with_parameter(hwmgr,
2658                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
2659                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask);
2660         }
2661
2662         if (!data->mclk_dpm_key_disabled) {
2663                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
2664                         smum_send_msg_to_smc_with_parameter(hwmgr,
2665                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
2666                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask);
2667         }
2668
2669         return 0;
2670 }
2671
2672 static int smu7_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
2673 {
2674         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2675
2676         if (!smum_is_dpm_running(hwmgr))
2677                 return -EINVAL;
2678
2679         if (!data->pcie_dpm_key_disabled) {
2680                 smum_send_msg_to_smc(hwmgr,
2681                                 PPSMC_MSG_PCIeDPM_UnForceLevel);
2682         }
2683
2684         return smu7_upload_dpm_level_enable_mask(hwmgr);
2685 }
2686
2687 static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2688 {
2689         struct smu7_hwmgr *data =
2690                         (struct smu7_hwmgr *)(hwmgr->backend);
2691         uint32_t level;
2692
2693         if (!data->sclk_dpm_key_disabled)
2694                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
2695                         level = phm_get_lowest_enabled_level(hwmgr,
2696                                                               data->dpm_level_enable_mask.sclk_dpm_enable_mask);
2697                         smum_send_msg_to_smc_with_parameter(hwmgr,
2698                                                             PPSMC_MSG_SCLKDPM_SetEnabledMask,
2699                                                             (1 << level));
2700
2701         }
2702
2703         if (!data->mclk_dpm_key_disabled) {
2704                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
2705                         level = phm_get_lowest_enabled_level(hwmgr,
2706                                                               data->dpm_level_enable_mask.mclk_dpm_enable_mask);
2707                         smum_send_msg_to_smc_with_parameter(hwmgr,
2708                                                             PPSMC_MSG_MCLKDPM_SetEnabledMask,
2709                                                             (1 << level));
2710                 }
2711         }
2712
2713         if (!data->pcie_dpm_key_disabled) {
2714                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
2715                         level = phm_get_lowest_enabled_level(hwmgr,
2716                                                               data->dpm_level_enable_mask.pcie_dpm_enable_mask);
2717                         smum_send_msg_to_smc_with_parameter(hwmgr,
2718                                                             PPSMC_MSG_PCIeDPM_ForceLevel,
2719                                                             (level));
2720                 }
2721         }
2722
2723         return 0;
2724 }
2725
2726 static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
2727                                 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask)
2728 {
2729         uint32_t percentage;
2730         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2731         struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table;
2732         int32_t tmp_mclk;
2733         int32_t tmp_sclk;
2734         int32_t count;
2735
2736         if (golden_dpm_table->mclk_table.count < 1)
2737                 return -EINVAL;
2738
2739         percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value /
2740                         golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
2741
2742         if (golden_dpm_table->mclk_table.count == 1) {
2743                 percentage = 70;
2744                 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
2745                 *mclk_mask = golden_dpm_table->mclk_table.count - 1;
2746         } else {
2747                 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 2].value;
2748                 *mclk_mask = golden_dpm_table->mclk_table.count - 2;
2749         }
2750
2751         tmp_sclk = tmp_mclk * percentage / 100;
2752
2753         if (hwmgr->pp_table_version == PP_TABLE_V0) {
2754                 for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
2755                         count >= 0; count--) {
2756                         if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) {
2757                                 tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk;
2758                                 *sclk_mask = count;
2759                                 break;
2760                         }
2761                 }
2762                 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2763                         *sclk_mask = 0;
2764                         tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].clk;
2765                 }
2766
2767                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2768                         *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
2769         } else if (hwmgr->pp_table_version == PP_TABLE_V1) {
2770                 struct phm_ppt_v1_information *table_info =
2771                                 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2772
2773                 for (count = table_info->vdd_dep_on_sclk->count-1; count >= 0; count--) {
2774                         if (tmp_sclk >= table_info->vdd_dep_on_sclk->entries[count].clk) {
2775                                 tmp_sclk = table_info->vdd_dep_on_sclk->entries[count].clk;
2776                                 *sclk_mask = count;
2777                                 break;
2778                         }
2779                 }
2780                 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2781                         *sclk_mask = 0;
2782                         tmp_sclk =  table_info->vdd_dep_on_sclk->entries[0].clk;
2783                 }
2784
2785                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2786                         *sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
2787         }
2788
2789         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
2790                 *mclk_mask = 0;
2791         else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2792                 *mclk_mask = golden_dpm_table->mclk_table.count - 1;
2793
2794         *pcie_mask = data->dpm_table.pcie_speed_table.count - 1;
2795         hwmgr->pstate_sclk = tmp_sclk;
2796         hwmgr->pstate_mclk = tmp_mclk;
2797
2798         return 0;
2799 }
2800
2801 static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
2802                                 enum amd_dpm_forced_level level)
2803 {
2804         int ret = 0;
2805         uint32_t sclk_mask = 0;
2806         uint32_t mclk_mask = 0;
2807         uint32_t pcie_mask = 0;
2808
2809         if (hwmgr->pstate_sclk == 0)
2810                 smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
2811
2812         switch (level) {
2813         case AMD_DPM_FORCED_LEVEL_HIGH:
2814                 ret = smu7_force_dpm_highest(hwmgr);
2815                 break;
2816         case AMD_DPM_FORCED_LEVEL_LOW: