2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
28 #include <asm/div64.h>
29 #include <drm/amdgpu_drm.h>
30 #include "ppatomctrl.h"
32 #include "pptable_v1_0.h"
33 #include "pppcielanes.h"
34 #include "amd_pcie_helpers.h"
35 #include "hardwaremanager.h"
36 #include "process_pptables_v1_0.h"
37 #include "cgs_common.h"
39 #include "smu7_common.h"
42 #include "smu7_hwmgr.h"
43 #include "smu_ucode_xfer_vi.h"
44 #include "smu7_powertune.h"
45 #include "smu7_dyn_defaults.h"
46 #include "smu7_thermal.h"
47 #include "smu7_clockpowergating.h"
48 #include "processpptables.h"
49 #include "pp_thermal.h"
51 #include "ivsrcid/ivsrcid_vislands30.h"
53 #define MC_CG_ARB_FREQ_F0 0x0a
54 #define MC_CG_ARB_FREQ_F1 0x0b
55 #define MC_CG_ARB_FREQ_F2 0x0c
56 #define MC_CG_ARB_FREQ_F3 0x0d
58 #define MC_CG_SEQ_DRAMCONF_S0 0x05
59 #define MC_CG_SEQ_DRAMCONF_S1 0x06
60 #define MC_CG_SEQ_YCLK_SUSPEND 0x04
61 #define MC_CG_SEQ_YCLK_RESUME 0x0a
63 #define SMC_CG_IND_START 0xc0030000
64 #define SMC_CG_IND_END 0xc0040000
66 #define MEM_FREQ_LOW_LATENCY 25000
67 #define MEM_FREQ_HIGH_LATENCY 80000
69 #define MEM_LATENCY_HIGH 45
70 #define MEM_LATENCY_LOW 35
71 #define MEM_LATENCY_ERR 0xFFFF
73 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
74 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
75 #define MC_SEQ_MISC0_GDDR5_VALUE 5
77 #define PCIE_BUS_CLK 10000
78 #define TCLK (PCIE_BUS_CLK / 10)
80 static const struct profile_mode_setting smu7_profiling[7] =
81 {{0, 0, 0, 0, 0, 0, 0, 0},
82 {1, 0, 100, 30, 1, 0, 100, 10},
83 {1, 10, 0, 30, 0, 0, 0, 0},
84 {0, 0, 0, 0, 1, 10, 16, 31},
85 {1, 0, 11, 50, 1, 0, 100, 10},
86 {1, 0, 5, 30, 0, 0, 0, 0},
87 {0, 0, 0, 0, 0, 0, 0, 0},
90 #define PPSMC_MSG_SetVBITimeout_VEGAM ((uint16_t) 0x310)
92 #define ixPWR_SVI2_PLANE1_LOAD 0xC0200280
93 #define PWR_SVI2_PLANE1_LOAD__PSI1_MASK 0x00000020L
94 #define PWR_SVI2_PLANE1_LOAD__PSI0_EN_MASK 0x00000040L
95 #define PWR_SVI2_PLANE1_LOAD__PSI1__SHIFT 0x00000005
96 #define PWR_SVI2_PLANE1_LOAD__PSI0_EN__SHIFT 0x00000006
98 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
100 DPM_EVENT_SRC_ANALOG = 0,
101 DPM_EVENT_SRC_EXTERNAL = 1,
102 DPM_EVENT_SRC_DIGITAL = 2,
103 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
104 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
107 static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic);
108 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
109 enum pp_clock_type type, uint32_t mask);
111 static struct smu7_power_state *cast_phw_smu7_power_state(
112 struct pp_hw_power_state *hw_ps)
114 PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
115 "Invalid Powerstate Type!",
118 return (struct smu7_power_state *)hw_ps;
121 static const struct smu7_power_state *cast_const_phw_smu7_power_state(
122 const struct pp_hw_power_state *hw_ps)
124 PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
125 "Invalid Powerstate Type!",
128 return (const struct smu7_power_state *)hw_ps;
132 * Find the MC microcode version and store it in the HwMgr struct
134 * @param hwmgr the address of the powerplay hardware manager.
137 static int smu7_get_mc_microcode_version(struct pp_hwmgr *hwmgr)
139 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
141 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
146 static uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
148 uint32_t speedCntl = 0;
150 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
151 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
152 ixPCIE_LC_SPEED_CNTL);
153 return((uint16_t)PHM_GET_FIELD(speedCntl,
154 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
157 static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
161 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
162 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
163 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
165 PP_ASSERT_WITH_CODE((7 >= link_width),
166 "Invalid PCIe lane width!", return 0);
168 return decode_pcie_lane_width(link_width);
172 * Enable voltage control
174 * @param pHwMgr the address of the powerplay hardware manager.
175 * @return always PP_Result_OK
177 static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
179 if (hwmgr->chip_id == CHIP_VEGAM) {
180 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
181 CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI1, 0);
182 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
183 CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI0_EN, 0);
186 if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK)
187 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Enable);
193 * Checks if we want to support voltage control
195 * @param hwmgr the address of the powerplay hardware manager.
197 static bool smu7_voltage_control(const struct pp_hwmgr *hwmgr)
199 const struct smu7_hwmgr *data =
200 (const struct smu7_hwmgr *)(hwmgr->backend);
202 return (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control);
206 * Enable voltage control
208 * @param hwmgr the address of the powerplay hardware manager.
211 static int smu7_enable_voltage_control(struct pp_hwmgr *hwmgr)
213 /* enable voltage control */
214 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
215 GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
220 static int phm_get_svi2_voltage_table_v0(pp_atomctrl_voltage_table *voltage_table,
221 struct phm_clock_voltage_dependency_table *voltage_dependency_table
226 PP_ASSERT_WITH_CODE((NULL != voltage_table),
227 "Voltage Dependency Table empty.", return -EINVAL;);
229 voltage_table->mask_low = 0;
230 voltage_table->phase_delay = 0;
231 voltage_table->count = voltage_dependency_table->count;
233 for (i = 0; i < voltage_dependency_table->count; i++) {
234 voltage_table->entries[i].value =
235 voltage_dependency_table->entries[i].v;
236 voltage_table->entries[i].smio_low = 0;
244 * Create Voltage Tables.
246 * @param hwmgr the address of the powerplay hardware manager.
249 static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr)
251 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
252 struct phm_ppt_v1_information *table_info =
253 (struct phm_ppt_v1_information *)hwmgr->pptable;
257 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
258 result = atomctrl_get_voltage_table_v3(hwmgr,
259 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
260 &(data->mvdd_voltage_table));
261 PP_ASSERT_WITH_CODE((0 == result),
262 "Failed to retrieve MVDD table.",
264 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
265 if (hwmgr->pp_table_version == PP_TABLE_V1)
266 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
267 table_info->vdd_dep_on_mclk);
268 else if (hwmgr->pp_table_version == PP_TABLE_V0)
269 result = phm_get_svi2_voltage_table_v0(&(data->mvdd_voltage_table),
270 hwmgr->dyn_state.mvdd_dependency_on_mclk);
272 PP_ASSERT_WITH_CODE((0 == result),
273 "Failed to retrieve SVI2 MVDD table from dependency table.",
277 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
278 result = atomctrl_get_voltage_table_v3(hwmgr,
279 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
280 &(data->vddci_voltage_table));
281 PP_ASSERT_WITH_CODE((0 == result),
282 "Failed to retrieve VDDCI table.",
284 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
285 if (hwmgr->pp_table_version == PP_TABLE_V1)
286 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
287 table_info->vdd_dep_on_mclk);
288 else if (hwmgr->pp_table_version == PP_TABLE_V0)
289 result = phm_get_svi2_voltage_table_v0(&(data->vddci_voltage_table),
290 hwmgr->dyn_state.vddci_dependency_on_mclk);
291 PP_ASSERT_WITH_CODE((0 == result),
292 "Failed to retrieve SVI2 VDDCI table from dependency table.",
296 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
297 /* VDDGFX has only SVI2 voltage control */
298 result = phm_get_svi2_vdd_voltage_table(&(data->vddgfx_voltage_table),
299 table_info->vddgfx_lookup_table);
300 PP_ASSERT_WITH_CODE((0 == result),
301 "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;);
305 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
306 result = atomctrl_get_voltage_table_v3(hwmgr,
307 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT,
308 &data->vddc_voltage_table);
309 PP_ASSERT_WITH_CODE((0 == result),
310 "Failed to retrieve VDDC table.", return result;);
311 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
313 if (hwmgr->pp_table_version == PP_TABLE_V0)
314 result = phm_get_svi2_voltage_table_v0(&data->vddc_voltage_table,
315 hwmgr->dyn_state.vddc_dependency_on_mclk);
316 else if (hwmgr->pp_table_version == PP_TABLE_V1)
317 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
318 table_info->vddc_lookup_table);
320 PP_ASSERT_WITH_CODE((0 == result),
321 "Failed to retrieve SVI2 VDDC table from dependency table.", return result;);
324 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDC);
326 (data->vddc_voltage_table.count <= tmp),
327 "Too many voltage values for VDDC. Trimming to fit state table.",
328 phm_trim_voltage_table_to_fit_state_table(tmp,
329 &(data->vddc_voltage_table)));
331 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
333 (data->vddgfx_voltage_table.count <= tmp),
334 "Too many voltage values for VDDC. Trimming to fit state table.",
335 phm_trim_voltage_table_to_fit_state_table(tmp,
336 &(data->vddgfx_voltage_table)));
338 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDCI);
340 (data->vddci_voltage_table.count <= tmp),
341 "Too many voltage values for VDDCI. Trimming to fit state table.",
342 phm_trim_voltage_table_to_fit_state_table(tmp,
343 &(data->vddci_voltage_table)));
345 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_MVDD);
347 (data->mvdd_voltage_table.count <= tmp),
348 "Too many voltage values for MVDD. Trimming to fit state table.",
349 phm_trim_voltage_table_to_fit_state_table(tmp,
350 &(data->mvdd_voltage_table)));
356 * Programs static screed detection parameters
358 * @param hwmgr the address of the powerplay hardware manager.
361 static int smu7_program_static_screen_threshold_parameters(
362 struct pp_hwmgr *hwmgr)
364 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
366 /* Set static screen threshold unit */
367 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
368 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
369 data->static_screen_threshold_unit);
370 /* Set static screen threshold */
371 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
372 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
373 data->static_screen_threshold);
379 * Setup display gap for glitch free memory clock switching.
381 * @param hwmgr the address of the powerplay hardware manager.
384 static int smu7_enable_display_gap(struct pp_hwmgr *hwmgr)
386 uint32_t display_gap =
387 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
388 ixCG_DISPLAY_GAP_CNTL);
390 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
391 DISP_GAP, DISPLAY_GAP_IGNORE);
393 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
394 DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
396 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
397 ixCG_DISPLAY_GAP_CNTL, display_gap);
403 * Programs activity state transition voting clients
405 * @param hwmgr the address of the powerplay hardware manager.
408 static int smu7_program_voting_clients(struct pp_hwmgr *hwmgr)
410 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
413 /* Clear reset for voting clients before enabling DPM */
414 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
415 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
416 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
417 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
419 for (i = 0; i < 8; i++)
420 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
421 ixCG_FREQ_TRAN_VOTING_0 + i * 4,
422 data->voting_rights_clients[i]);
426 static int smu7_clear_voting_clients(struct pp_hwmgr *hwmgr)
430 /* Reset voting clients before disabling DPM */
431 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
432 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1);
433 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
434 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1);
436 for (i = 0; i < 8; i++)
437 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
438 ixCG_FREQ_TRAN_VOTING_0 + i * 4, 0);
443 /* Copy one arb setting to another and then switch the active set.
444 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
446 static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
447 uint32_t arb_src, uint32_t arb_dest)
449 uint32_t mc_arb_dram_timing;
450 uint32_t mc_arb_dram_timing2;
452 uint32_t mc_cg_config;
455 case MC_CG_ARB_FREQ_F0:
456 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
457 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
458 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
460 case MC_CG_ARB_FREQ_F1:
461 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
462 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
463 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
470 case MC_CG_ARB_FREQ_F0:
471 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
472 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
473 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
475 case MC_CG_ARB_FREQ_F1:
476 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
477 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
478 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
484 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
485 mc_cg_config |= 0x0000000F;
486 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
487 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
492 static int smu7_reset_to_default(struct pp_hwmgr *hwmgr)
494 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ResetToDefaults);
498 * Initial switch from ARB F0->F1
500 * @param hwmgr the address of the powerplay hardware manager.
502 * This function is to be called from the SetPowerState table.
504 static int smu7_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
506 return smu7_copy_and_switch_arb_sets(hwmgr,
507 MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
510 static int smu7_force_switch_to_arbf0(struct pp_hwmgr *hwmgr)
514 tmp = (cgs_read_ind_register(hwmgr->device,
515 CGS_IND_REG__SMC, ixSMC_SCRATCH9) &
518 if (tmp == MC_CG_ARB_FREQ_F0)
521 return smu7_copy_and_switch_arb_sets(hwmgr,
522 tmp, MC_CG_ARB_FREQ_F0);
525 static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
527 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
529 struct phm_ppt_v1_information *table_info =
530 (struct phm_ppt_v1_information *)(hwmgr->pptable);
531 struct phm_ppt_v1_pcie_table *pcie_table = NULL;
533 uint32_t i, max_entry;
536 PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
537 data->use_pcie_power_saving_levels), "No pcie performance levels!",
540 if (table_info != NULL)
541 pcie_table = table_info->pcie_table;
543 if (data->use_pcie_performance_levels &&
544 !data->use_pcie_power_saving_levels) {
545 data->pcie_gen_power_saving = data->pcie_gen_performance;
546 data->pcie_lane_power_saving = data->pcie_lane_performance;
547 } else if (!data->use_pcie_performance_levels &&
548 data->use_pcie_power_saving_levels) {
549 data->pcie_gen_performance = data->pcie_gen_power_saving;
550 data->pcie_lane_performance = data->pcie_lane_power_saving;
552 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_LINK);
553 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
555 MAX_REGULAR_DPM_NUMBER);
557 if (pcie_table != NULL) {
558 /* max_entry is used to make sure we reserve one PCIE level
559 * for boot level (fix for A+A PSPP issue).
560 * If PCIE table from PPTable have ULV entry + 8 entries,
561 * then ignore the last entry.*/
562 max_entry = (tmp < pcie_table->count) ? tmp : pcie_table->count;
563 for (i = 1; i < max_entry; i++) {
564 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
565 get_pcie_gen_support(data->pcie_gen_cap,
566 pcie_table->entries[i].gen_speed),
567 get_pcie_lane_support(data->pcie_lane_cap,
568 pcie_table->entries[i].lane_width));
570 data->dpm_table.pcie_speed_table.count = max_entry - 1;
571 smum_update_smc_table(hwmgr, SMU_BIF_TABLE);
573 /* Hardcode Pcie Table */
574 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
575 get_pcie_gen_support(data->pcie_gen_cap,
577 get_pcie_lane_support(data->pcie_lane_cap,
579 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
580 get_pcie_gen_support(data->pcie_gen_cap,
582 get_pcie_lane_support(data->pcie_lane_cap,
584 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
585 get_pcie_gen_support(data->pcie_gen_cap,
587 get_pcie_lane_support(data->pcie_lane_cap,
589 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
590 get_pcie_gen_support(data->pcie_gen_cap,
592 get_pcie_lane_support(data->pcie_lane_cap,
594 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
595 get_pcie_gen_support(data->pcie_gen_cap,
597 get_pcie_lane_support(data->pcie_lane_cap,
599 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
600 get_pcie_gen_support(data->pcie_gen_cap,
602 get_pcie_lane_support(data->pcie_lane_cap,
605 data->dpm_table.pcie_speed_table.count = 6;
607 /* Populate last level for boot PCIE level, but do not increment count. */
608 if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
609 for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++)
610 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i,
611 get_pcie_gen_support(data->pcie_gen_cap,
613 data->vbios_boot_state.pcie_lane_bootup_value);
615 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
616 data->dpm_table.pcie_speed_table.count,
617 get_pcie_gen_support(data->pcie_gen_cap,
619 get_pcie_lane_support(data->pcie_lane_cap,
625 static int smu7_reset_dpm_tables(struct pp_hwmgr *hwmgr)
627 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
629 memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table));
631 phm_reset_single_dpm_table(
632 &data->dpm_table.sclk_table,
633 smum_get_mac_definition(hwmgr,
634 SMU_MAX_LEVELS_GRAPHICS),
635 MAX_REGULAR_DPM_NUMBER);
636 phm_reset_single_dpm_table(
637 &data->dpm_table.mclk_table,
638 smum_get_mac_definition(hwmgr,
639 SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER);
641 phm_reset_single_dpm_table(
642 &data->dpm_table.vddc_table,
643 smum_get_mac_definition(hwmgr,
644 SMU_MAX_LEVELS_VDDC),
645 MAX_REGULAR_DPM_NUMBER);
646 phm_reset_single_dpm_table(
647 &data->dpm_table.vddci_table,
648 smum_get_mac_definition(hwmgr,
649 SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER);
651 phm_reset_single_dpm_table(
652 &data->dpm_table.mvdd_table,
653 smum_get_mac_definition(hwmgr,
654 SMU_MAX_LEVELS_MVDD),
655 MAX_REGULAR_DPM_NUMBER);
659 * This function is to initialize all DPM state tables
660 * for SMU7 based on the dependency table.
661 * Dynamic state patching function will then trim these
662 * state tables to the allowed range based
663 * on the power policy or external client requests,
664 * such as UVD request, etc.
667 static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr)
669 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
670 struct phm_clock_voltage_dependency_table *allowed_vdd_sclk_table =
671 hwmgr->dyn_state.vddc_dependency_on_sclk;
672 struct phm_clock_voltage_dependency_table *allowed_vdd_mclk_table =
673 hwmgr->dyn_state.vddc_dependency_on_mclk;
674 struct phm_cac_leakage_table *std_voltage_table =
675 hwmgr->dyn_state.cac_leakage_table;
678 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
679 "SCLK dependency table is missing. This table is mandatory", return -EINVAL);
680 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1,
681 "SCLK dependency table has to have is missing. This table is mandatory", return -EINVAL);
683 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
684 "MCLK dependency table is missing. This table is mandatory", return -EINVAL);
685 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1,
686 "VMCLK dependency table has to have is missing. This table is mandatory", return -EINVAL);
689 /* Initialize Sclk DPM table based on allow Sclk values*/
690 data->dpm_table.sclk_table.count = 0;
692 for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
693 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value !=
694 allowed_vdd_sclk_table->entries[i].clk) {
695 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
696 allowed_vdd_sclk_table->entries[i].clk;
697 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0;
698 data->dpm_table.sclk_table.count++;
702 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
703 "MCLK dependency table is missing. This table is mandatory", return -EINVAL);
704 /* Initialize Mclk DPM table based on allow Mclk values */
705 data->dpm_table.mclk_table.count = 0;
706 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
707 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value !=
708 allowed_vdd_mclk_table->entries[i].clk) {
709 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
710 allowed_vdd_mclk_table->entries[i].clk;
711 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0;
712 data->dpm_table.mclk_table.count++;
716 /* Initialize Vddc DPM table based on allow Vddc values. And populate corresponding std values. */
717 for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
718 data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
719 data->dpm_table.vddc_table.dpm_levels[i].param1 = std_voltage_table->entries[i].Leakage;
720 /* param1 is for corresponding std voltage */
721 data->dpm_table.vddc_table.dpm_levels[i].enabled = 1;
724 data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count;
725 allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
727 if (NULL != allowed_vdd_mclk_table) {
728 /* Initialize Vddci DPM table based on allow Mclk values */
729 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
730 data->dpm_table.vddci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
731 data->dpm_table.vddci_table.dpm_levels[i].enabled = 1;
733 data->dpm_table.vddci_table.count = allowed_vdd_mclk_table->count;
736 allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk;
738 if (NULL != allowed_vdd_mclk_table) {
740 * Initialize MVDD DPM table based on allow Mclk
743 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
744 data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
745 data->dpm_table.mvdd_table.dpm_levels[i].enabled = 1;
747 data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count;
753 static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr)
755 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
756 struct phm_ppt_v1_information *table_info =
757 (struct phm_ppt_v1_information *)(hwmgr->pptable);
760 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
761 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
763 if (table_info == NULL)
766 dep_sclk_table = table_info->vdd_dep_on_sclk;
767 dep_mclk_table = table_info->vdd_dep_on_mclk;
769 PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
770 "SCLK dependency table is missing.",
772 PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
773 "SCLK dependency table count is 0.",
776 PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
777 "MCLK dependency table is missing.",
779 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
780 "MCLK dependency table count is 0",
783 /* Initialize Sclk DPM table based on allow Sclk values */
784 data->dpm_table.sclk_table.count = 0;
785 for (i = 0; i < dep_sclk_table->count; i++) {
786 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
787 dep_sclk_table->entries[i].clk) {
789 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
790 dep_sclk_table->entries[i].clk;
792 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
793 (i == 0) ? true : false;
794 data->dpm_table.sclk_table.count++;
797 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0)
798 hwmgr->platform_descriptor.overdriveLimit.engineClock = dep_sclk_table->entries[i-1].clk;
799 /* Initialize Mclk DPM table based on allow Mclk values */
800 data->dpm_table.mclk_table.count = 0;
801 for (i = 0; i < dep_mclk_table->count; i++) {
802 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
803 [data->dpm_table.mclk_table.count - 1].value !=
804 dep_mclk_table->entries[i].clk) {
805 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
806 dep_mclk_table->entries[i].clk;
807 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
808 (i == 0) ? true : false;
809 data->dpm_table.mclk_table.count++;
813 if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0)
814 hwmgr->platform_descriptor.overdriveLimit.memoryClock = dep_mclk_table->entries[i-1].clk;
818 static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
820 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
821 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
822 struct phm_ppt_v1_information *table_info =
823 (struct phm_ppt_v1_information *)(hwmgr->pptable);
826 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
827 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
828 struct phm_odn_performance_level *entries;
830 if (table_info == NULL)
833 dep_sclk_table = table_info->vdd_dep_on_sclk;
834 dep_mclk_table = table_info->vdd_dep_on_mclk;
836 odn_table->odn_core_clock_dpm_levels.num_of_pl =
837 data->golden_dpm_table.sclk_table.count;
838 entries = odn_table->odn_core_clock_dpm_levels.entries;
839 for (i=0; i<data->golden_dpm_table.sclk_table.count; i++) {
840 entries[i].clock = data->golden_dpm_table.sclk_table.dpm_levels[i].value;
841 entries[i].enabled = true;
842 entries[i].vddc = dep_sclk_table->entries[i].vddc;
845 smu_get_voltage_dependency_table_ppt_v1(dep_sclk_table,
846 (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk));
848 odn_table->odn_memory_clock_dpm_levels.num_of_pl =
849 data->golden_dpm_table.mclk_table.count;
850 entries = odn_table->odn_memory_clock_dpm_levels.entries;
851 for (i=0; i<data->golden_dpm_table.mclk_table.count; i++) {
852 entries[i].clock = data->golden_dpm_table.mclk_table.dpm_levels[i].value;
853 entries[i].enabled = true;
854 entries[i].vddc = dep_mclk_table->entries[i].vddc;
857 smu_get_voltage_dependency_table_ppt_v1(dep_mclk_table,
858 (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk));
863 static void smu7_setup_voltage_range_from_vbios(struct pp_hwmgr *hwmgr)
865 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
866 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
867 struct phm_ppt_v1_information *table_info =
868 (struct phm_ppt_v1_information *)(hwmgr->pptable);
869 uint32_t min_vddc = 0;
870 uint32_t max_vddc = 0;
875 dep_sclk_table = table_info->vdd_dep_on_sclk;
877 atomctrl_get_voltage_range(hwmgr, &max_vddc, &min_vddc);
879 if (min_vddc == 0 || min_vddc > 2000
880 || min_vddc > dep_sclk_table->entries[0].vddc)
881 min_vddc = dep_sclk_table->entries[0].vddc;
883 if (max_vddc == 0 || max_vddc > 2000
884 || max_vddc < dep_sclk_table->entries[dep_sclk_table->count-1].vddc)
885 max_vddc = dep_sclk_table->entries[dep_sclk_table->count-1].vddc;
887 data->odn_dpm_table.min_vddc = min_vddc;
888 data->odn_dpm_table.max_vddc = max_vddc;
891 static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
893 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
894 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
895 struct phm_ppt_v1_information *table_info =
896 (struct phm_ppt_v1_information *)(hwmgr->pptable);
899 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
900 struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table;
902 if (table_info == NULL)
905 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
906 if (odn_table->odn_core_clock_dpm_levels.entries[i].clock !=
907 data->dpm_table.sclk_table.dpm_levels[i].value) {
908 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
913 for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
914 if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock !=
915 data->dpm_table.mclk_table.dpm_levels[i].value) {
916 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
921 dep_table = table_info->vdd_dep_on_mclk;
922 odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk);
924 for (i = 0; i < dep_table->count; i++) {
925 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
926 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK;
931 dep_table = table_info->vdd_dep_on_sclk;
932 odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk);
933 for (i = 0; i < dep_table->count; i++) {
934 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
935 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK;
939 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
940 data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC;
941 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK;
945 static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
947 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
949 smu7_reset_dpm_tables(hwmgr);
951 if (hwmgr->pp_table_version == PP_TABLE_V1)
952 smu7_setup_dpm_tables_v1(hwmgr);
953 else if (hwmgr->pp_table_version == PP_TABLE_V0)
954 smu7_setup_dpm_tables_v0(hwmgr);
956 smu7_setup_default_pcie_table(hwmgr);
958 /* save a copy of the default DPM table */
959 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
960 sizeof(struct smu7_dpm_table));
962 /* initialize ODN table */
963 if (hwmgr->od_enabled) {
964 if (data->odn_dpm_table.max_vddc) {
965 smu7_check_dpm_table_updated(hwmgr);
967 smu7_setup_voltage_range_from_vbios(hwmgr);
968 smu7_odn_initial_default_setting(hwmgr);
974 static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
977 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
978 PHM_PlatformCaps_RegulatorHot))
979 return smum_send_msg_to_smc(hwmgr,
980 PPSMC_MSG_EnableVRHotGPIOInterrupt);
985 static int smu7_enable_sclk_control(struct pp_hwmgr *hwmgr)
987 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
992 static int smu7_enable_ulv(struct pp_hwmgr *hwmgr)
994 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
996 if (data->ulv_supported)
997 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableULV);
1002 static int smu7_disable_ulv(struct pp_hwmgr *hwmgr)
1004 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1006 if (data->ulv_supported)
1007 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableULV);
1012 static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
1014 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1015 PHM_PlatformCaps_SclkDeepSleep)) {
1016 if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MASTER_DeepSleep_ON))
1017 PP_ASSERT_WITH_CODE(false,
1018 "Attempt to enable Master Deep Sleep switch failed!",
1021 if (smum_send_msg_to_smc(hwmgr,
1022 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
1023 PP_ASSERT_WITH_CODE(false,
1024 "Attempt to disable Master Deep Sleep switch failed!",
1032 static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
1034 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1035 PHM_PlatformCaps_SclkDeepSleep)) {
1036 if (smum_send_msg_to_smc(hwmgr,
1037 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
1038 PP_ASSERT_WITH_CODE(false,
1039 "Attempt to disable Master Deep Sleep switch failed!",
1047 static int smu7_disable_sclk_vce_handshake(struct pp_hwmgr *hwmgr)
1049 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1050 uint32_t soft_register_value = 0;
1051 uint32_t handshake_disables_offset = data->soft_regs_start
1052 + smum_get_offsetof(hwmgr,
1053 SMU_SoftRegisters, HandshakeDisables);
1055 soft_register_value = cgs_read_ind_register(hwmgr->device,
1056 CGS_IND_REG__SMC, handshake_disables_offset);
1057 soft_register_value |= SMU7_VCE_SCLK_HANDSHAKE_DISABLE;
1058 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1059 handshake_disables_offset, soft_register_value);
1063 static int smu7_disable_handshake_uvd(struct pp_hwmgr *hwmgr)
1065 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1066 uint32_t soft_register_value = 0;
1067 uint32_t handshake_disables_offset = data->soft_regs_start
1068 + smum_get_offsetof(hwmgr,
1069 SMU_SoftRegisters, HandshakeDisables);
1071 soft_register_value = cgs_read_ind_register(hwmgr->device,
1072 CGS_IND_REG__SMC, handshake_disables_offset);
1073 soft_register_value |= smum_get_mac_definition(hwmgr,
1074 SMU_UVD_MCLK_HANDSHAKE_DISABLE);
1075 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1076 handshake_disables_offset, soft_register_value);
1080 static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
1082 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1084 /* enable SCLK dpm */
1085 if (!data->sclk_dpm_key_disabled) {
1086 if (hwmgr->chip_id == CHIP_VEGAM)
1087 smu7_disable_sclk_vce_handshake(hwmgr);
1089 PP_ASSERT_WITH_CODE(
1090 (0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Enable)),
1091 "Failed to enable SCLK DPM during DPM Start Function!",
1095 /* enable MCLK dpm */
1096 if (0 == data->mclk_dpm_key_disabled) {
1097 if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK))
1098 smu7_disable_handshake_uvd(hwmgr);
1100 PP_ASSERT_WITH_CODE(
1101 (0 == smum_send_msg_to_smc(hwmgr,
1102 PPSMC_MSG_MCLKDPM_Enable)),
1103 "Failed to enable MCLK DPM during DPM Start Function!",
1106 if (hwmgr->chip_family != CHIP_VEGAM)
1107 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
1110 if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
1111 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x5);
1112 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x5);
1113 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x100005);
1115 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x400005);
1116 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x400005);
1117 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x500005);
1119 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
1120 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
1121 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
1123 if (hwmgr->chip_id == CHIP_VEGAM) {
1124 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400009);
1125 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400009);
1127 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
1128 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
1130 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
1137 static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
1139 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1141 /*enable general power management */
1143 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1144 GLOBAL_PWRMGT_EN, 1);
1146 /* enable sclk deep sleep */
1148 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1151 /* prepare for PCIE DPM */
1153 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1154 data->soft_regs_start +
1155 smum_get_offsetof(hwmgr, SMU_SoftRegisters,
1156 VoltageChangeTimeout), 0x1000);
1157 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
1158 SWRST_COMMAND_1, RESETLC, 0x0);
1160 if (hwmgr->chip_family == AMDGPU_FAMILY_CI)
1161 cgs_write_register(hwmgr->device, 0x1488,
1162 (cgs_read_register(hwmgr->device, 0x1488) & ~0x1));
1164 if (smu7_enable_sclk_mclk_dpm(hwmgr)) {
1165 pr_err("Failed to enable Sclk DPM and Mclk DPM!");
1169 /* enable PCIE dpm */
1170 if (0 == data->pcie_dpm_key_disabled) {
1171 PP_ASSERT_WITH_CODE(
1172 (0 == smum_send_msg_to_smc(hwmgr,
1173 PPSMC_MSG_PCIeDPM_Enable)),
1174 "Failed to enable pcie DPM during DPM Start Function!",
1178 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1179 PHM_PlatformCaps_Falcon_QuickTransition)) {
1180 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr,
1181 PPSMC_MSG_EnableACDCGPIOInterrupt)),
1182 "Failed to enable AC DC GPIO Interrupt!",
1189 static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
1191 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1193 /* disable SCLK dpm */
1194 if (!data->sclk_dpm_key_disabled) {
1195 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1196 "Trying to disable SCLK DPM when DPM is disabled",
1198 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Disable);
1201 /* disable MCLK dpm */
1202 if (!data->mclk_dpm_key_disabled) {
1203 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1204 "Trying to disable MCLK DPM when DPM is disabled",
1206 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_Disable);
1212 static int smu7_stop_dpm(struct pp_hwmgr *hwmgr)
1214 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1216 /* disable general power management */
1217 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1218 GLOBAL_PWRMGT_EN, 0);
1219 /* disable sclk deep sleep */
1220 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1223 /* disable PCIE dpm */
1224 if (!data->pcie_dpm_key_disabled) {
1225 PP_ASSERT_WITH_CODE(
1226 (smum_send_msg_to_smc(hwmgr,
1227 PPSMC_MSG_PCIeDPM_Disable) == 0),
1228 "Failed to disable pcie DPM during DPM Stop Function!",
1232 smu7_disable_sclk_mclk_dpm(hwmgr);
1234 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1235 "Trying to disable voltage DPM when DPM is disabled",
1238 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Disable);
1243 static void smu7_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
1246 enum DPM_EVENT_SRC src;
1250 pr_err("Unknown throttling event sources.");
1256 case (1 << PHM_AutoThrottleSource_Thermal):
1258 src = DPM_EVENT_SRC_DIGITAL;
1260 case (1 << PHM_AutoThrottleSource_External):
1262 src = DPM_EVENT_SRC_EXTERNAL;
1264 case (1 << PHM_AutoThrottleSource_External) |
1265 (1 << PHM_AutoThrottleSource_Thermal):
1267 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
1270 /* Order matters - don't enable thermal protection for the wrong source. */
1272 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
1273 DPM_EVENT_SRC, src);
1274 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1275 THERMAL_PROTECTION_DIS,
1276 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1277 PHM_PlatformCaps_ThermalController));
1279 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1280 THERMAL_PROTECTION_DIS, 1);
1283 static int smu7_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
1284 PHM_AutoThrottleSource source)
1286 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1288 if (!(data->active_auto_throttle_sources & (1 << source))) {
1289 data->active_auto_throttle_sources |= 1 << source;
1290 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
1295 static int smu7_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
1297 return smu7_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
1300 static int smu7_disable_auto_throttle_source(struct pp_hwmgr *hwmgr,
1301 PHM_AutoThrottleSource source)
1303 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1305 if (data->active_auto_throttle_sources & (1 << source)) {
1306 data->active_auto_throttle_sources &= ~(1 << source);
1307 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
1312 static int smu7_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
1314 return smu7_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
1317 static int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr)
1319 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1320 data->pcie_performance_request = true;
1325 static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1330 if (smu7_voltage_control(hwmgr)) {
1331 tmp_result = smu7_enable_voltage_control(hwmgr);
1332 PP_ASSERT_WITH_CODE(tmp_result == 0,
1333 "Failed to enable voltage control!",
1334 result = tmp_result);
1336 tmp_result = smu7_construct_voltage_tables(hwmgr);
1337 PP_ASSERT_WITH_CODE((0 == tmp_result),
1338 "Failed to construct voltage tables!",
1339 result = tmp_result);
1341 smum_initialize_mc_reg_table(hwmgr);
1343 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1344 PHM_PlatformCaps_EngineSpreadSpectrumSupport))
1345 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1346 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
1348 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1349 PHM_PlatformCaps_ThermalController))
1350 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1351 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
1353 tmp_result = smu7_program_static_screen_threshold_parameters(hwmgr);
1354 PP_ASSERT_WITH_CODE((0 == tmp_result),
1355 "Failed to program static screen threshold parameters!",
1356 result = tmp_result);
1358 tmp_result = smu7_enable_display_gap(hwmgr);
1359 PP_ASSERT_WITH_CODE((0 == tmp_result),
1360 "Failed to enable display gap!", result = tmp_result);
1362 tmp_result = smu7_program_voting_clients(hwmgr);
1363 PP_ASSERT_WITH_CODE((0 == tmp_result),
1364 "Failed to program voting clients!", result = tmp_result);
1366 tmp_result = smum_process_firmware_header(hwmgr);
1367 PP_ASSERT_WITH_CODE((0 == tmp_result),
1368 "Failed to process firmware header!", result = tmp_result);
1370 if (hwmgr->chip_id != CHIP_VEGAM) {
1371 tmp_result = smu7_initial_switch_from_arbf0_to_f1(hwmgr);
1372 PP_ASSERT_WITH_CODE((0 == tmp_result),
1373 "Failed to initialize switch from ArbF0 to F1!",
1374 result = tmp_result);
1377 result = smu7_setup_default_dpm_tables(hwmgr);
1378 PP_ASSERT_WITH_CODE(0 == result,
1379 "Failed to setup default DPM tables!", return result);
1381 tmp_result = smum_init_smc_table(hwmgr);
1382 PP_ASSERT_WITH_CODE((0 == tmp_result),
1383 "Failed to initialize SMC table!", result = tmp_result);
1385 tmp_result = smu7_enable_vrhot_gpio_interrupt(hwmgr);
1386 PP_ASSERT_WITH_CODE((0 == tmp_result),
1387 "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
1389 smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay);
1391 tmp_result = smu7_enable_sclk_control(hwmgr);
1392 PP_ASSERT_WITH_CODE((0 == tmp_result),
1393 "Failed to enable SCLK control!", result = tmp_result);
1395 tmp_result = smu7_enable_smc_voltage_controller(hwmgr);
1396 PP_ASSERT_WITH_CODE((0 == tmp_result),
1397 "Failed to enable voltage control!", result = tmp_result);
1399 tmp_result = smu7_enable_ulv(hwmgr);
1400 PP_ASSERT_WITH_CODE((0 == tmp_result),
1401 "Failed to enable ULV!", result = tmp_result);
1403 tmp_result = smu7_enable_deep_sleep_master_switch(hwmgr);
1404 PP_ASSERT_WITH_CODE((0 == tmp_result),
1405 "Failed to enable deep sleep master switch!", result = tmp_result);
1407 tmp_result = smu7_enable_didt_config(hwmgr);
1408 PP_ASSERT_WITH_CODE((tmp_result == 0),
1409 "Failed to enable deep sleep master switch!", result = tmp_result);
1411 tmp_result = smu7_start_dpm(hwmgr);
1412 PP_ASSERT_WITH_CODE((0 == tmp_result),
1413 "Failed to start DPM!", result = tmp_result);
1415 tmp_result = smu7_enable_smc_cac(hwmgr);
1416 PP_ASSERT_WITH_CODE((0 == tmp_result),
1417 "Failed to enable SMC CAC!", result = tmp_result);
1419 tmp_result = smu7_enable_power_containment(hwmgr);
1420 PP_ASSERT_WITH_CODE((0 == tmp_result),
1421 "Failed to enable power containment!", result = tmp_result);
1423 tmp_result = smu7_power_control_set_level(hwmgr);
1424 PP_ASSERT_WITH_CODE((0 == tmp_result),
1425 "Failed to power control set level!", result = tmp_result);
1427 tmp_result = smu7_enable_thermal_auto_throttle(hwmgr);
1428 PP_ASSERT_WITH_CODE((0 == tmp_result),
1429 "Failed to enable thermal auto throttle!", result = tmp_result);
1431 tmp_result = smu7_pcie_performance_request(hwmgr);
1432 PP_ASSERT_WITH_CODE((0 == tmp_result),
1433 "pcie performance request failed!", result = tmp_result);
1438 static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
1440 if (!hwmgr->avfs_supported)
1444 if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
1445 CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
1446 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
1447 hwmgr, PPSMC_MSG_EnableAvfs),
1448 "Failed to enable AVFS!",
1451 } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
1452 CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
1453 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
1454 hwmgr, PPSMC_MSG_DisableAvfs),
1455 "Failed to disable AVFS!",
1462 static int smu7_update_avfs(struct pp_hwmgr *hwmgr)
1464 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1466 if (!hwmgr->avfs_supported)
1469 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
1470 smu7_avfs_control(hwmgr, false);
1471 } else if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
1472 smu7_avfs_control(hwmgr, false);
1473 smu7_avfs_control(hwmgr, true);
1475 smu7_avfs_control(hwmgr, true);
1481 int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
1483 int tmp_result, result = 0;
1485 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1486 PHM_PlatformCaps_ThermalController))
1487 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1488 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1);
1490 tmp_result = smu7_disable_power_containment(hwmgr);
1491 PP_ASSERT_WITH_CODE((tmp_result == 0),
1492 "Failed to disable power containment!", result = tmp_result);
1494 tmp_result = smu7_disable_smc_cac(hwmgr);
1495 PP_ASSERT_WITH_CODE((tmp_result == 0),
1496 "Failed to disable SMC CAC!", result = tmp_result);
1498 tmp_result = smu7_disable_didt_config(hwmgr);
1499 PP_ASSERT_WITH_CODE((tmp_result == 0),
1500 "Failed to disable DIDT!", result = tmp_result);
1502 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1503 CG_SPLL_SPREAD_SPECTRUM, SSEN, 0);
1504 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1505 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0);
1507 tmp_result = smu7_disable_thermal_auto_throttle(hwmgr);
1508 PP_ASSERT_WITH_CODE((tmp_result == 0),
1509 "Failed to disable thermal auto throttle!", result = tmp_result);
1511 tmp_result = smu7_avfs_control(hwmgr, false);
1512 PP_ASSERT_WITH_CODE((tmp_result == 0),
1513 "Failed to disable AVFS!", result = tmp_result);
1515 tmp_result = smu7_stop_dpm(hwmgr);
1516 PP_ASSERT_WITH_CODE((tmp_result == 0),
1517 "Failed to stop DPM!", result = tmp_result);
1519 tmp_result = smu7_disable_deep_sleep_master_switch(hwmgr);
1520 PP_ASSERT_WITH_CODE((tmp_result == 0),
1521 "Failed to disable deep sleep master switch!", result = tmp_result);
1523 tmp_result = smu7_disable_ulv(hwmgr);
1524 PP_ASSERT_WITH_CODE((tmp_result == 0),
1525 "Failed to disable ULV!", result = tmp_result);
1527 tmp_result = smu7_clear_voting_clients(hwmgr);
1528 PP_ASSERT_WITH_CODE((tmp_result == 0),
1529 "Failed to clear voting clients!", result = tmp_result);
1531 tmp_result = smu7_reset_to_default(hwmgr);
1532 PP_ASSERT_WITH_CODE((tmp_result == 0),
1533 "Failed to reset to default!", result = tmp_result);
1535 tmp_result = smu7_force_switch_to_arbf0(hwmgr);
1536 PP_ASSERT_WITH_CODE((tmp_result == 0),
1537 "Failed to force to switch arbf0!", result = tmp_result);
1542 int smu7_reset_asic_tasks(struct pp_hwmgr *hwmgr)
1548 static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
1550 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1551 struct phm_ppt_v1_information *table_info =
1552 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1553 struct amdgpu_device *adev = hwmgr->adev;
1555 data->dll_default_on = false;
1556 data->mclk_dpm0_activity_target = 0xa;
1557 data->vddc_vddgfx_delta = 300;
1558 data->static_screen_threshold = SMU7_STATICSCREENTHRESHOLD_DFLT;
1559 data->static_screen_threshold_unit = SMU7_STATICSCREENTHRESHOLDUNIT_DFLT;
1560 data->voting_rights_clients[0] = SMU7_VOTINGRIGHTSCLIENTS_DFLT0;
1561 data->voting_rights_clients[1]= SMU7_VOTINGRIGHTSCLIENTS_DFLT1;
1562 data->voting_rights_clients[2] = SMU7_VOTINGRIGHTSCLIENTS_DFLT2;
1563 data->voting_rights_clients[3]= SMU7_VOTINGRIGHTSCLIENTS_DFLT3;
1564 data->voting_rights_clients[4]= SMU7_VOTINGRIGHTSCLIENTS_DFLT4;
1565 data->voting_rights_clients[5]= SMU7_VOTINGRIGHTSCLIENTS_DFLT5;
1566 data->voting_rights_clients[6]= SMU7_VOTINGRIGHTSCLIENTS_DFLT6;
1567 data->voting_rights_clients[7]= SMU7_VOTINGRIGHTSCLIENTS_DFLT7;
1569 data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
1570 data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
1571 data->pcie_dpm_key_disabled = hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
1572 /* need to set voltage control types before EVV patching */
1573 data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE;
1574 data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE;
1575 data->mvdd_control = SMU7_VOLTAGE_CONTROL_NONE;
1576 data->enable_tdc_limit_feature = true;
1577 data->enable_pkg_pwr_tracking_feature = true;
1578 data->force_pcie_gen = PP_PCIEGenInvalid;
1579 data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false;
1580 data->current_profile_setting.bupdate_sclk = 1;
1581 data->current_profile_setting.sclk_up_hyst = 0;
1582 data->current_profile_setting.sclk_down_hyst = 100;
1583 data->current_profile_setting.sclk_activity = SMU7_SCLK_TARGETACTIVITY_DFLT;
1584 data->current_profile_setting.bupdate_mclk = 1;
1585 data->current_profile_setting.mclk_up_hyst = 0;
1586 data->current_profile_setting.mclk_down_hyst = 100;
1587 data->current_profile_setting.mclk_activity = SMU7_MCLK_TARGETACTIVITY_DFLT;
1588 hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D];
1589 hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1590 hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1592 if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker) {
1595 atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2,
1597 tmp3 = (tmp3 >> 5) & 0x3;
1598 data->vddc_phase_shed_control = ((tmp3 << 1) | (tmp3 >> 1)) & 0x3;
1599 } else if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
1600 data->vddc_phase_shed_control = 1;
1602 data->vddc_phase_shed_control = 0;
1605 if (hwmgr->chip_id == CHIP_HAWAII) {
1606 data->thermal_temp_setting.temperature_low = 94500;
1607 data->thermal_temp_setting.temperature_high = 95000;
1608 data->thermal_temp_setting.temperature_shutdown = 104000;
1610 data->thermal_temp_setting.temperature_low = 99500;
1611 data->thermal_temp_setting.temperature_high = 100000;
1612 data->thermal_temp_setting.temperature_shutdown = 104000;
1615 data->fast_watermark_threshold = 100;
1616 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1617 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
1618 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1619 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1620 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
1621 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1623 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1624 PHM_PlatformCaps_ControlVDDGFX)) {
1625 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1626 VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) {
1627 data->vdd_gfx_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1631 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1632 PHM_PlatformCaps_EnableMVDDControl)) {
1633 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1634 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
1635 data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1636 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1637 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
1638 data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1641 if (SMU7_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control)
1642 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1643 PHM_PlatformCaps_ControlVDDGFX);
1645 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1646 PHM_PlatformCaps_ControlVDDCI)) {
1647 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1648 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
1649 data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1650 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1651 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
1652 data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1655 if (data->mvdd_control == SMU7_VOLTAGE_CONTROL_NONE)
1656 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1657 PHM_PlatformCaps_EnableMVDDControl);
1659 if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE)
1660 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1661 PHM_PlatformCaps_ControlVDDCI);
1663 if ((hwmgr->pp_table_version != PP_TABLE_V0) && (hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK)
1664 && (table_info->cac_dtp_table->usClockStretchAmount != 0))
1665 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1666 PHM_PlatformCaps_ClockStretcher);
1668 data->pcie_gen_performance.max = PP_PCIEGen1;
1669 data->pcie_gen_performance.min = PP_PCIEGen3;
1670 data->pcie_gen_power_saving.max = PP_PCIEGen1;
1671 data->pcie_gen_power_saving.min = PP_PCIEGen3;
1672 data->pcie_lane_performance.max = 0;
1673 data->pcie_lane_performance.min = 16;
1674 data->pcie_lane_power_saving.max = 0;
1675 data->pcie_lane_power_saving.min = 16;
1678 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
1679 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1680 PHM_PlatformCaps_UVDPowerGating);
1681 if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
1682 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1683 PHM_PlatformCaps_VCEPowerGating);
1687 * Get Leakage VDDC based on leakage ID.
1689 * @param hwmgr the address of the powerplay hardware manager.
1692 static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr)
1694 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1697 uint16_t vddgfx = 0;
1700 struct phm_ppt_v1_information *table_info =
1701 (struct phm_ppt_v1_information *)hwmgr->pptable;
1702 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = NULL;
1705 for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
1706 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1708 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1709 if ((hwmgr->pp_table_version == PP_TABLE_V1)
1710 && !phm_get_sclk_for_voltage_evv(hwmgr,
1711 table_info->vddgfx_lookup_table, vv_id, &sclk)) {
1712 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1713 PHM_PlatformCaps_ClockStretcher)) {
1714 sclk_table = table_info->vdd_dep_on_sclk;
1716 for (j = 1; j < sclk_table->count; j++) {
1717 if (sclk_table->entries[j].clk == sclk &&
1718 sclk_table->entries[j].cks_enable == 0) {
1724 if (0 == atomctrl_get_voltage_evv_on_sclk
1725 (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk,
1727 /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */
1728 PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -EINVAL);
1730 /* the voltage should not be zero nor equal to leakage ID */
1731 if (vddgfx != 0 && vddgfx != vv_id) {
1732 data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx;
1733 data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = vv_id;
1734 data->vddcgfx_leakage.count++;
1737 pr_info("Error retrieving EVV voltage value!\n");
1741 if ((hwmgr->pp_table_version == PP_TABLE_V0)
1742 || !phm_get_sclk_for_voltage_evv(hwmgr,
1743 table_info->vddc_lookup_table, vv_id, &sclk)) {
1744 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1745 PHM_PlatformCaps_ClockStretcher)) {
1746 if (table_info == NULL)
1748 sclk_table = table_info->vdd_dep_on_sclk;
1750 for (j = 1; j < sclk_table->count; j++) {
1751 if (sclk_table->entries[j].clk == sclk &&
1752 sclk_table->entries[j].cks_enable == 0) {
1759 if (phm_get_voltage_evv_on_sclk(hwmgr,
1761 sclk, vv_id, &vddc) == 0) {
1762 if (vddc >= 2000 || vddc == 0)
1765 pr_debug("failed to retrieving EVV voltage!\n");
1769 /* the voltage should not be zero nor equal to leakage ID */
1770 if (vddc != 0 && vddc != vv_id) {
1771 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc);
1772 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
1773 data->vddc_leakage.count++;
1783 * Change virtual leakage voltage to actual value.
1785 * @param hwmgr the address of the powerplay hardware manager.
1786 * @param pointer to changing voltage
1787 * @param pointer to leakage table
1789 static void smu7_patch_ppt_v1_with_vdd_leakage(struct pp_hwmgr *hwmgr,
1790 uint16_t *voltage, struct smu7_leakage_voltage *leakage_table)
1794 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
1795 for (index = 0; index < leakage_table->count; index++) {
1796 /* if this voltage matches a leakage voltage ID */
1797 /* patch with actual leakage voltage */
1798 if (leakage_table->leakage_id[index] == *voltage) {
1799 *voltage = leakage_table->actual_voltage[index];
1804 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
1805 pr_err("Voltage value looks like a Leakage ID but it's not patched \n");
1809 * Patch voltage lookup table by EVV leakages.
1811 * @param hwmgr the address of the powerplay hardware manager.
1812 * @param pointer to voltage lookup table
1813 * @param pointer to leakage table
1816 static int smu7_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
1817 phm_ppt_v1_voltage_lookup_table *lookup_table,
1818 struct smu7_leakage_voltage *leakage_table)
1822 for (i = 0; i < lookup_table->count; i++)
1823 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr,
1824 &lookup_table->entries[i].us_vdd, leakage_table);
1829 static int smu7_patch_clock_voltage_limits_with_vddc_leakage(
1830 struct pp_hwmgr *hwmgr, struct smu7_leakage_voltage *leakage_table,
1833 struct phm_ppt_v1_information *table_info =
1834 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1835 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
1836 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
1837 table_info->max_clock_voltage_on_dc.vddc;
1841 static int smu7_patch_voltage_dependency_tables_with_lookup_table(
1842 struct pp_hwmgr *hwmgr)
1846 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1847 struct phm_ppt_v1_information *table_info =
1848 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1850 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1851 table_info->vdd_dep_on_sclk;
1852 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
1853 table_info->vdd_dep_on_mclk;
1854 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1855 table_info->mm_dep_table;
1857 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1858 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
1859 voltage_id = sclk_table->entries[entry_id].vddInd;
1860 sclk_table->entries[entry_id].vddgfx =
1861 table_info->vddgfx_lookup_table->entries[voltage_id].us_vdd;
1864 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
1865 voltage_id = sclk_table->entries[entry_id].vddInd;
1866 sclk_table->entries[entry_id].vddc =
1867 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
1871 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
1872 voltage_id = mclk_table->entries[entry_id].vddInd;
1873 mclk_table->entries[entry_id].vddc =
1874 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
1877 for (entry_id = 0; entry_id < mm_table->count; ++entry_id) {
1878 voltage_id = mm_table->entries[entry_id].vddcInd;
1879 mm_table->entries[entry_id].vddc =
1880 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
1887 static int phm_add_voltage(struct pp_hwmgr *hwmgr,
1888 phm_ppt_v1_voltage_lookup_table *look_up_table,
1889 phm_ppt_v1_voltage_lookup_record *record)
1893 PP_ASSERT_WITH_CODE((NULL != look_up_table),
1894 "Lookup Table empty.", return -EINVAL);
1895 PP_ASSERT_WITH_CODE((0 != look_up_table->count),
1896 "Lookup Table empty.", return -EINVAL);
1898 i = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
1899 PP_ASSERT_WITH_CODE((i >= look_up_table->count),
1900 "Lookup Table is full.", return -EINVAL);
1902 /* This is to avoid entering duplicate calculated records. */
1903 for (i = 0; i < look_up_table->count; i++) {
1904 if (look_up_table->entries[i].us_vdd == record->us_vdd) {
1905 if (look_up_table->entries[i].us_calculated == 1)
1911 look_up_table->entries[i].us_calculated = 1;
1912 look_up_table->entries[i].us_vdd = record->us_vdd;
1913 look_up_table->entries[i].us_cac_low = record->us_cac_low;
1914 look_up_table->entries[i].us_cac_mid = record->us_cac_mid;
1915 look_up_table->entries[i].us_cac_high = record->us_cac_high;
1916 /* Only increment the count when we're appending, not replacing duplicate entry. */
1917 if (i == look_up_table->count)
1918 look_up_table->count++;
1924 static int smu7_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
1927 struct phm_ppt_v1_voltage_lookup_record v_record;
1928 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1929 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1931 phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
1932 phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
1934 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1935 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
1936 if (sclk_table->entries[entry_id].vdd_offset & (1 << 15))
1937 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx +
1938 sclk_table->entries[entry_id].vdd_offset - 0xFFFF;
1940 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx +
1941 sclk_table->entries[entry_id].vdd_offset;
1943 sclk_table->entries[entry_id].vddc =
1944 v_record.us_cac_low = v_record.us_cac_mid =
1945 v_record.us_cac_high = v_record.us_vdd;
1947 phm_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record);
1950 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
1951 if (mclk_table->entries[entry_id].vdd_offset & (1 << 15))
1952 v_record.us_vdd = mclk_table->entries[entry_id].vddc +
1953 mclk_table->entries[entry_id].vdd_offset - 0xFFFF;
1955 v_record.us_vdd = mclk_table->entries[entry_id].vddc +
1956 mclk_table->entries[entry_id].vdd_offset;
1958 mclk_table->entries[entry_id].vddgfx = v_record.us_cac_low =
1959 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
1960 phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
1966 static int smu7_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
1969 struct phm_ppt_v1_voltage_lookup_record v_record;
1970 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1971 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1972 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1974 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1975 for (entry_id = 0; entry_id < mm_table->count; entry_id++) {
1976 if (mm_table->entries[entry_id].vddgfx_offset & (1 << 15))
1977 v_record.us_vdd = mm_table->entries[entry_id].vddc +
1978 mm_table->entries[entry_id].vddgfx_offset - 0xFFFF;
1980 v_record.us_vdd = mm_table->entries[entry_id].vddc +
1981 mm_table->entries[entry_id].vddgfx_offset;
1983 /* Add the calculated VDDGFX to the VDDGFX lookup table */
1984 mm_table->entries[entry_id].vddgfx = v_record.us_cac_low =
1985 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
1986 phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
1992 static int smu7_sort_lookup_table(struct pp_hwmgr *hwmgr,
1993 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
1995 uint32_t table_size, i, j;
1996 struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
1997 table_size = lookup_table->count;
1999 PP_ASSERT_WITH_CODE(0 != lookup_table->count,
2000 "Lookup table is empty", return -EINVAL);
2002 /* Sorting voltages */
2003 for (i = 0; i < table_size - 1; i++) {
2004 for (j = i + 1; j > 0; j--) {
2005 if (lookup_table->entries[j].us_vdd <
2006 lookup_table->entries[j - 1].us_vdd) {
2007 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
2008 lookup_table->entries[j - 1] = lookup_table->entries[j];
2009 lookup_table->entries[j] = tmp_voltage_lookup_record;
2017 static int smu7_complete_dependency_tables(struct pp_hwmgr *hwmgr)
2021 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2022 struct phm_ppt_v1_information *table_info =
2023 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2025 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
2026 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr,
2027 table_info->vddgfx_lookup_table, &(data->vddcgfx_leakage));
2028 if (tmp_result != 0)
2029 result = tmp_result;
2031 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr,
2032 &table_info->max_clock_voltage_on_dc.vddgfx, &(data->vddcgfx_leakage));
2035 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr,
2036 table_info->vddc_lookup_table, &(data->vddc_leakage));
2038 result = tmp_result;
2040 tmp_result = smu7_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
2041 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
2043 result = tmp_result;
2046 tmp_result = smu7_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
2048 result = tmp_result;
2050 tmp_result = smu7_calc_voltage_dependency_tables(hwmgr);
2052 result = tmp_result;
2054 tmp_result = smu7_calc_mm_voltage_dependency_table(hwmgr);
2056 result = tmp_result;
2058 tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddgfx_lookup_table);
2060 result = tmp_result;
2062 tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
2064 result = tmp_result;
2069 static int smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr *hwmgr)
2071 struct phm_ppt_v1_information *table_info =
2072 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2074 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
2075 table_info->vdd_dep_on_sclk;
2076 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
2077 table_info->vdd_dep_on_mclk;
2079 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
2080 "VDD dependency on SCLK table is missing.",
2082 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
2083 "VDD dependency on SCLK table has to have is missing.",
2086 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
2087 "VDD dependency on MCLK table is missing",
2089 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
2090 "VDD dependency on MCLK table has to have is missing.",
2093 table_info->max_clock_voltage_on_ac.sclk =
2094 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
2095 table_info->max_clock_voltage_on_ac.mclk =
2096 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
2097 table_info->max_clock_voltage_on_ac.vddc =
2098 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
2099 table_info->max_clock_voltage_on_ac.vddci =
2100 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
2102 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
2103 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
2104 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
2105 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = table_info->max_clock_voltage_on_ac.vddci;
2110 static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
2112 struct phm_ppt_v1_information *table_info =
2113 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2114 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
2115 struct phm_ppt_v1_voltage_lookup_table *lookup_table;
2117 uint32_t hw_revision, sub_vendor_id, sub_sys_id;
2118 struct amdgpu_device *adev = hwmgr->adev;
2120 if (table_info != NULL) {
2121 dep_mclk_table = table_info->vdd_dep_on_mclk;
2122 lookup_table = table_info->vddc_lookup_table;
2126 hw_revision = adev->pdev->revision;
2127 sub_sys_id = adev->pdev->subsystem_device;
2128 sub_vendor_id = adev->pdev->subsystem_vendor;
2130 if (hwmgr->chip_id == CHIP_POLARIS10 && hw_revision == 0xC7 &&
2131 ((sub_sys_id == 0xb37 && sub_vendor_id == 0x1002) ||
2132 (sub_sys_id == 0x4a8 && sub_vendor_id == 0x1043) ||
2133 (sub_sys_id == 0x9480 && sub_vendor_id == 0x1682))) {
2134 if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000)
2137 for (i = 0; i < lookup_table->count; i++) {
2138 if (lookup_table->entries[i].us_vdd < 0xff01 && lookup_table->entries[i].us_vdd >= 1000) {
2139 dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i;
2147 static int smu7_thermal_parameter_init(struct pp_hwmgr *hwmgr)
2149 struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2151 struct phm_ppt_v1_information *table_info =
2152 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2155 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
2156 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
2157 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
2159 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
2162 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
2165 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
2168 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
2171 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
2176 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
2179 if (table_info == NULL)
2182 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
2183 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
2184 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
2185 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
2187 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
2188 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
2190 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
2192 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
2194 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
2195 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
2197 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
2199 table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
2200 (table_info->cac_dtp_table->usDefaultTargetOperatingTemp - 50) : 0;
2202 table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
2203 table_info->cac_dtp_table->usOperatingTempStep = 1;
2204 table_info->cac_dtp_table->usOperatingTempHyst = 1;
2206 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
2207 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
2209 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
2210 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
2212 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
2213 table_info->cac_dtp_table->usOperatingTempMinLimit;
2215 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
2216 table_info->cac_dtp_table->usOperatingTempMaxLimit;
2218 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
2219 table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
2221 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
2222 table_info->cac_dtp_table->usOperatingTempStep;
2224 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
2225 table_info->cac_dtp_table->usTargetOperatingTemp;
2226 if (hwmgr->feature_mask & PP_OD_FUZZY_FAN_CONTROL_MASK)
2227 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2228 PHM_PlatformCaps_ODFuzzyFanControlSupport);
2235 * Change virtual leakage voltage to actual value.
2237 * @param hwmgr the address of the powerplay hardware manager.
2238 * @param pointer to changing voltage
2239 * @param pointer to leakage table
2241 static void smu7_patch_ppt_v0_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2242 uint32_t *voltage, struct smu7_leakage_voltage *leakage_table)
2246 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2247 for (index = 0; index < leakage_table->count; index++) {
2248 /* if this voltage matches a leakage voltage ID */
2249 /* patch with actual leakage voltage */
2250 if (leakage_table->leakage_id[index] == *voltage) {
2251 *voltage = leakage_table->actual_voltage[index];
2256 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2257 pr_err("Voltage value looks like a Leakage ID but it's not patched \n");
2261 static int smu7_patch_vddc(struct pp_hwmgr *hwmgr,
2262 struct phm_clock_voltage_dependency_table *tab)
2265 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2268 for (i = 0; i < tab->count; i++)
2269 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2270 &data->vddc_leakage);
2275 static int smu7_patch_vddci(struct pp_hwmgr *hwmgr,
2276 struct phm_clock_voltage_dependency_table *tab)
2279 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2282 for (i = 0; i < tab->count; i++)
2283 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2284 &data->vddci_leakage);
2289 static int smu7_patch_vce_vddc(struct pp_hwmgr *hwmgr,
2290 struct phm_vce_clock_voltage_dependency_table *tab)
2293 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2296 for (i = 0; i < tab->count; i++)
2297 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2298 &data->vddc_leakage);
2304 static int smu7_patch_uvd_vddc(struct pp_hwmgr *hwmgr,
2305 struct phm_uvd_clock_voltage_dependency_table *tab)
2308 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2311 for (i = 0; i < tab->count; i++)
2312 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2313 &data->vddc_leakage);
2318 static int smu7_patch_vddc_shed_limit(struct pp_hwmgr *hwmgr,
2319 struct phm_phase_shedding_limits_table *tab)
2322 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2325 for (i = 0; i < tab->count; i++)
2326 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].Voltage,
2327 &data->vddc_leakage);
2332 static int smu7_patch_samu_vddc(struct pp_hwmgr *hwmgr,
2333 struct phm_samu_clock_voltage_dependency_table *tab)
2336 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2339 for (i = 0; i < tab->count; i++)
2340 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2341 &data->vddc_leakage);
2346 static int smu7_patch_acp_vddc(struct pp_hwmgr *hwmgr,
2347 struct phm_acp_clock_voltage_dependency_table *tab)
2350 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2353 for (i = 0; i < tab->count; i++)
2354 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2355 &data->vddc_leakage);
2360 static int smu7_patch_limits_vddc(struct pp_hwmgr *hwmgr,
2361 struct phm_clock_and_voltage_limits *tab)
2363 uint32_t vddc, vddci;
2364 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2368 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc,
2369 &data->vddc_leakage);
2372 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddci,
2373 &data->vddci_leakage);
2380 static int smu7_patch_cac_vddc(struct pp_hwmgr *hwmgr, struct phm_cac_leakage_table *tab)
2384 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2387 for (i = 0; i < tab->count; i++) {
2388 vddc = (uint32_t)(tab->entries[i].Vddc);
2389 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, &data->vddc_leakage);
2390 tab->entries[i].Vddc = (uint16_t)vddc;
2397 static int smu7_patch_dependency_tables_with_leakage(struct pp_hwmgr *hwmgr)
2401 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk);
2405 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_mclk);
2409 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
2413 tmp = smu7_patch_vddci(hwmgr, hwmgr->dyn_state.vddci_dependency_on_mclk);
2417 tmp = smu7_patch_vce_vddc(hwmgr, hwmgr->dyn_state.vce_clock_voltage_dependency_table);
2421 tmp = smu7_patch_uvd_vddc(hwmgr, hwmgr->dyn_state.uvd_clock_voltage_dependency_table);
2425 tmp = smu7_patch_samu_vddc(hwmgr, hwmgr->dyn_state.samu_clock_voltage_dependency_table);
2429 tmp = smu7_patch_acp_vddc(hwmgr, hwmgr->dyn_state.acp_clock_voltage_dependency_table);
2433 tmp = smu7_patch_vddc_shed_limit(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table);
2437 tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_ac);
2441 tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_dc);
2445 tmp = smu7_patch_cac_vddc(hwmgr, hwmgr->dyn_state.cac_leakage_table);
2453 static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr)
2455 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2457 struct phm_clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
2458 struct phm_clock_voltage_dependency_table *allowed_mclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
2459 struct phm_clock_voltage_dependency_table *allowed_mclk_vddci_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
2461 PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table != NULL,
2462 "VDDC dependency on SCLK table is missing. This table is mandatory",
2464 PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table->count >= 1,
2465 "VDDC dependency on SCLK table has to have is missing. This table is mandatory",
2468 PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table != NULL,
2469 "VDDC dependency on MCLK table is missing. This table is mandatory",
2471 PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table->count >= 1,
2472 "VDD dependency on MCLK table has to have is missing. This table is mandatory",
2475 data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[0].v;
2476 data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
2478 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
2479 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
2480 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
2481 allowed_mclk_vddc_table->entries[allowed_mclk_vddc_table->count - 1].clk;
2482 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
2483 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
2485 if (allowed_mclk_vddci_table != NULL && allowed_mclk_vddci_table->count >= 1) {
2486 data->min_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[0].v;
2487 data->max_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
2490 if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk->count >= 1)
2491 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entries[hwmgr->dyn_state.vddci_dependency_on_mclk->count - 1].v;
2496 static int smu7_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
2498 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
2499 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
2500 kfree(hwmgr->backend);
2501 hwmgr->backend = NULL;
2506 static int smu7_get_elb_voltages(struct pp_hwmgr *hwmgr)
2508 uint16_t virtual_voltage_id, vddc, vddci, efuse_voltage_id;
2509 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2512 if (atomctrl_get_leakage_id_from_efuse(hwmgr, &efuse_voltage_id) == 0) {
2513 for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
2514 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2515 if (atomctrl_get_leakage_vddc_base_on_leakage(hwmgr, &vddc, &vddci,
2517 efuse_voltage_id) == 0) {
2518 if (vddc != 0 && vddc != virtual_voltage_id) {
2519 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc;
2520 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id;
2521 data->vddc_leakage.count++;
2523 if (vddci != 0 && vddci != virtual_voltage_id) {
2524 data->vddci_leakage.actual_voltage[data->vddci_leakage.count] = vddci;
2525 data->vddci_leakage.leakage_id[data->vddci_leakage.count] = virtual_voltage_id;
2526 data->vddci_leakage.count++;
2534 static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
2536 struct smu7_hwmgr *data;
2539 data = kzalloc(sizeof(struct smu7_hwmgr), GFP_KERNEL);
2543 hwmgr->backend = data;
2544 smu7_patch_voltage_workaround(hwmgr);
2545 smu7_init_dpm_defaults(hwmgr);
2547 /* Get leakage voltage based on leakage ID. */
2548 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2549 PHM_PlatformCaps_EVV)) {
2550 result = smu7_get_evv_voltages(hwmgr);
2552 pr_info("Get EVV Voltage Failed. Abort Driver loading!\n");
2556 smu7_get_elb_voltages(hwmgr);
2559 if (hwmgr->pp_table_version == PP_TABLE_V1) {
2560 smu7_complete_dependency_tables(hwmgr);
2561 smu7_set_private_data_based_on_pptable_v1(hwmgr);
2562 } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
2563 smu7_patch_dependency_tables_with_leakage(hwmgr);
2564 smu7_set_private_data_based_on_pptable_v0(hwmgr);
2567 /* Initalize Dynamic State Adjustment Rule Settings */
2568 result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
2571 struct amdgpu_device *adev = hwmgr->adev;
2573 data->is_tlu_enabled = false;
2575 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
2576 SMU7_MAX_HARDWARE_POWERLEVELS;
2577 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
2578 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
2580 data->pcie_gen_cap = adev->pm.pcie_gen_mask;
2581 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
2582 data->pcie_spc_cap = 20;
2583 data->pcie_lane_cap = adev->pm.pcie_mlw_mask;
2585 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
2586 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
2587 hwmgr->platform_descriptor.clockStep.engineClock = 500;
2588 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
2589 smu7_thermal_parameter_init(hwmgr);
2591 /* Ignore return value in here, we are cleaning up a mess. */
2592 smu7_hwmgr_backend_fini(hwmgr);
2598 static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr)
2600 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2601 uint32_t level, tmp;
2603 if (!data->pcie_dpm_key_disabled) {
2604 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
2606 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
2611 smum_send_msg_to_smc_with_parameter(hwmgr,
2612 PPSMC_MSG_PCIeDPM_ForceLevel, level);
2616 if (!data->sclk_dpm_key_disabled) {
2617 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
2619 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
2624 smum_send_msg_to_smc_with_parameter(hwmgr,
2625 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2630 if (!data->mclk_dpm_key_disabled) {
2631 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
2633 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
2638 smum_send_msg_to_smc_with_parameter(hwmgr,
2639 PPSMC_MSG_MCLKDPM_SetEnabledMask,
2647 static int smu7_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
2649 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2651 if (hwmgr->pp_table_version == PP_TABLE_V1)
2652 phm_apply_dal_min_voltage_request(hwmgr);
2653 /* TO DO for v0 iceland and Ci*/
2655 if (!data->sclk_dpm_key_disabled) {
2656 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
2657 smum_send_msg_to_smc_with_parameter(hwmgr,
2658 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2659 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
2662 if (!data->mclk_dpm_key_disabled) {
2663 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
2664 smum_send_msg_to_smc_with_parameter(hwmgr,
2665 PPSMC_MSG_MCLKDPM_SetEnabledMask,
2666 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
2672 static int smu7_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
2674 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2676 if (!smum_is_dpm_running(hwmgr))
2679 if (!data->pcie_dpm_key_disabled) {
2680 smum_send_msg_to_smc(hwmgr,
2681 PPSMC_MSG_PCIeDPM_UnForceLevel);
2684 return smu7_upload_dpm_level_enable_mask(hwmgr);
2687 static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2689 struct smu7_hwmgr *data =
2690 (struct smu7_hwmgr *)(hwmgr->backend);
2693 if (!data->sclk_dpm_key_disabled)
2694 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
2695 level = phm_get_lowest_enabled_level(hwmgr,
2696 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
2697 smum_send_msg_to_smc_with_parameter(hwmgr,
2698 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2703 if (!data->mclk_dpm_key_disabled) {
2704 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
2705 level = phm_get_lowest_enabled_level(hwmgr,
2706 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
2707 smum_send_msg_to_smc_with_parameter(hwmgr,
2708 PPSMC_MSG_MCLKDPM_SetEnabledMask,
2713 if (!data->pcie_dpm_key_disabled) {
2714 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
2715 level = phm_get_lowest_enabled_level(hwmgr,
2716 data->dpm_level_enable_mask.pcie_dpm_enable_mask);
2717 smum_send_msg_to_smc_with_parameter(hwmgr,
2718 PPSMC_MSG_PCIeDPM_ForceLevel,
2726 static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
2727 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask)
2729 uint32_t percentage;
2730 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2731 struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table;
2736 if (golden_dpm_table->mclk_table.count < 1)
2739 percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value /
2740 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
2742 if (golden_dpm_table->mclk_table.count == 1) {
2744 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
2745 *mclk_mask = golden_dpm_table->mclk_table.count - 1;
2747 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 2].value;
2748 *mclk_mask = golden_dpm_table->mclk_table.count - 2;
2751 tmp_sclk = tmp_mclk * percentage / 100;
2753 if (hwmgr->pp_table_version == PP_TABLE_V0) {
2754 for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
2755 count >= 0; count--) {
2756 if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) {
2757 tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk;
2762 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2764 tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].clk;
2767 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2768 *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
2769 } else if (hwmgr->pp_table_version == PP_TABLE_V1) {
2770 struct phm_ppt_v1_information *table_info =
2771 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2773 for (count = table_info->vdd_dep_on_sclk->count-1; count >= 0; count--) {
2774 if (tmp_sclk >= table_info->vdd_dep_on_sclk->entries[count].clk) {
2775 tmp_sclk = table_info->vdd_dep_on_sclk->entries[count].clk;
2780 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2782 tmp_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
2785 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2786 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
2789 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
2791 else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2792 *mclk_mask = golden_dpm_table->mclk_table.count - 1;
2794 *pcie_mask = data->dpm_table.pcie_speed_table.count - 1;
2795 hwmgr->pstate_sclk = tmp_sclk;
2796 hwmgr->pstate_mclk = tmp_mclk;
2801 static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
2802 enum amd_dpm_forced_level level)
2805 uint32_t sclk_mask = 0;
2806 uint32_t mclk_mask = 0;
2807 uint32_t pcie_mask = 0;
2809 if (hwmgr->pstate_sclk == 0)
2810 smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
2813 case AMD_DPM_FORCED_LEVEL_HIGH:
2814 ret = smu7_force_dpm_highest(hwmgr);
2816 case AMD_DPM_FORCED_LEVEL_LOW:
2817 ret = smu7_force_dpm_lowest(hwmgr);
2819 case AMD_DPM_FORCED_LEVEL_AUTO:
2820 ret = smu7_unforce_dpm_levels(hwmgr);
2822 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
2823 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
2824 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
2825 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
2826 ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
2829 smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
2830 smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
2831 smu7_force_clock_level(hwmgr, PP_PCIE, 1<<pcie_mask);
2833 case AMD_DPM_FORCED_LEVEL_MANUAL:
2834 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
2840 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2841 smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
2842 else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2843 smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr);
2848 static int smu7_get_power_state_size(struct pp_hwmgr *hwmgr)
2850 return sizeof(struct smu7_power_state);
2853 static int smu7_vblank_too_short(struct pp_hwmgr *hwmgr,
2854 uint32_t vblank_time_us)
2856 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2857 uint32_t switch_limit_us;
2859 switch (hwmgr->chip_id) {
2860 case CHIP_POLARIS10:
2861 case CHIP_POLARIS11:
2862 case CHIP_POLARIS12:
2863 if (hwmgr->is_kicker)
2864 switch_limit_us = data->is_memory_gddr5 ? 450 : 150;
2866 switch_limit_us = data->is_memory_gddr5 ? 190 : 150;
2869 switch_limit_us = 30;
2872 switch_limit_us = data->is_memory_gddr5 ? 450 : 150;
2876 if (vblank_time_us < switch_limit_us)
2882 static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
2883 struct pp_power_state *request_ps,
2884 const struct pp_power_state *current_ps)
2886 struct amdgpu_device *adev = hwmgr->adev;
2887 struct smu7_power_state *smu7_ps =
2888 cast_phw_smu7_power_state(&request_ps->hardware);
2891 struct PP_Clocks minimum_clocks = {0};
2892 bool disable_mclk_switching;
2893 bool disable_mclk_switching_for_frame_lock;
2894 const struct phm_clock_and_voltage_limits *max_limits;
2896 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2897 struct phm_ppt_v1_information *table_info =
2898 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2900 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
2902 data->battery_state = (PP_StateUILabel_Battery ==
2903 request_ps->classification.ui_label);
2905 PP_ASSERT_WITH_CODE(smu7_ps->performance_level_count == 2,
2906 "VI should always have 2 performance levels",
2909 max_limits = adev->pm.ac_power ?
2910 &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
2911 &(hwmgr->dyn_state.max_clock_voltage_on_dc);
2913 /* Cap clock DPM tables at DC MAX if it is in DC. */
2914 if (!adev->pm.ac_power) {
2915 for (i = 0; i < smu7_ps->performance_level_count; i++) {
2916 if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk)
2917 smu7_ps->performance_levels[i].memory_clock = max_limits->mclk;
2918 if (smu7_ps->performance_levels[i].engine_clock > max_limits->sclk)
2919 smu7_ps->performance_levels[i].engine_clock = max_limits->sclk;
2923 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
2924 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
2926 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2927 PHM_PlatformCaps_StablePState)) {
2928 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
2929 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
2931 for (count = table_info->vdd_dep_on_sclk->count - 1;
2932 count >= 0; count--) {
2933 if (stable_pstate_sclk >=
2934 table_info->vdd_dep_on_sclk->entries[count].clk) {
2935 stable_pstate_sclk =
2936 table_info->vdd_dep_on_sclk->entries[count].clk;
2942 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
2944 stable_pstate_mclk = max_limits->mclk;
2946 minimum_clocks.engineClock = stable_pstate_sclk;
2947 minimum_clocks.memoryClock = stable_pstate_mclk;
2950 disable_mclk_switching_for_frame_lock = phm_cap_enabled(
2951 hwmgr->platform_descriptor.platformCaps,
2952 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
2955 if (hwmgr->display_config->num_display == 0)
2956 disable_mclk_switching = false;
2958 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) ||
2959 disable_mclk_switching_for_frame_lock ||
2960 smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time));
2962 sclk = smu7_ps->performance_levels[0].engine_clock;
2963 mclk = smu7_ps->performance_levels[0].memory_clock;
2965 if (disable_mclk_switching)
2966 mclk = smu7_ps->performance_levels
2967 [smu7_ps->performance_level_count - 1].memory_clock;
2969 if (sclk < minimum_clocks.engineClock)
2970 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
2971 max_limits->sclk : minimum_clocks.engineClock;
2973 if (mclk < minimum_clocks.memoryClock)
2974 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
2975 max_limits->mclk : minimum_clocks.memoryClock;
2977 smu7_ps->performance_levels[0].engine_clock = sclk;
2978 smu7_ps->performance_levels[0].memory_clock = mclk;
2980 smu7_ps->performance_levels[1].engine_clock =
2981 (smu7_ps->performance_levels[1].engine_clock >=
2982 smu7_ps->performance_levels[0].engine_clock) ?
2983 smu7_ps->performance_levels[1].engine_clock :
2984 smu7_ps->performance_levels[0].engine_clock;
2986 if (disable_mclk_switching) {
2987 if (mclk < smu7_ps->performance_levels[1].memory_clock)
2988 mclk = smu7_ps->performance_levels[1].memory_clock;
2990 smu7_ps->performance_levels[0].memory_clock = mclk;
2991 smu7_ps->performance_levels[1].memory_clock = mclk;
2993 if (smu7_ps->performance_levels[1].memory_clock <
2994 smu7_ps->performance_levels[0].memory_clock)
2995 smu7_ps->performance_levels[1].memory_clock =
2996 smu7_ps->performance_levels[0].memory_clock;
2999 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3000 PHM_PlatformCaps_StablePState)) {
3001 for (i = 0; i < smu7_ps->performance_level_count; i++) {
3002 smu7_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3003 smu7_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3004 smu7_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3005 smu7_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
3012 static uint32_t smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3014 struct pp_power_state *ps;
3015 struct smu7_power_state *smu7_ps;
3020 ps = hwmgr->request_ps;
3025 smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
3028 return smu7_ps->performance_levels[0].memory_clock;
3030 return smu7_ps->performance_levels
3031 [smu7_ps->performance_level_count-1].memory_clock;
3034 static uint32_t smu7_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3036 struct pp_power_state *ps;
3037 struct smu7_power_state *smu7_ps;
3042 ps = hwmgr->request_ps;
3047 smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
3050 return smu7_ps->performance_levels[0].engine_clock;
3052 return smu7_ps->performance_levels
3053 [smu7_ps->performance_level_count-1].engine_clock;
3056 static int smu7_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
3057 struct pp_hw_power_state *hw_ps)
3059 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3060 struct smu7_power_state *ps = (struct smu7_power_state *)hw_ps;
3061 ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3064 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3066 /* First retrieve the Boot clocks and VDDC from the firmware info table.
3067 * We assume here that fw_info is unchanged if this call fails.
3069 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)smu_atom_get_data_table(hwmgr->adev, index,
3070 &size, &frev, &crev);
3072 /* During a test, there is no firmware info table. */
3075 /* Patch the state. */
3076 data->vbios_boot_state.sclk_bootup_value =
3077 le32_to_cpu(fw_info->ulDefaultEngineClock);
3078 data->vbios_boot_state.mclk_bootup_value =
3079 le32_to_cpu(fw_info->ulDefaultMemoryClock);
3080 data->vbios_boot_state.mvdd_bootup_value =
3081 le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3082 data->vbios_boot_state.vddc_bootup_value =
3083 le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3084 data->vbios_boot_state.vddci_bootup_value =
3085 le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3086 data->vbios_boot_state.pcie_gen_bootup_value =
3087 smu7_get_current_pcie_speed(hwmgr);
3089 data->vbios_boot_state.pcie_lane_bootup_value =
3090 (uint16_t)smu7_get_current_pcie_lane_number(hwmgr);
3092 /* set boot power state */
3093 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3094 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3095 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3096 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3101 static int smu7_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr)
3104 unsigned long ret = 0;
3106 if (hwmgr->pp_table_version == PP_TABLE_V0) {
3107 result = pp_tables_get_num_of_entries(hwmgr, &ret);
3108 return result ? 0 : ret;
3109 } else if (hwmgr->pp_table_version == PP_TABLE_V1) {
3110 result = get_number_of_powerplay_table_entries_v1_0(hwmgr);
3116 static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr,
3117 void *state, struct pp_power_state *power_state,
3118 void *pp_table, uint32_t classification_flag)
3120 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3121 struct smu7_power_state *smu7_power_state =
3122 (struct smu7_power_state *)(&(power_state->hardware));
3123 struct smu7_performance_level *performance_level;
3124 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3125 ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3126 (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3127 PPTable_Generic_SubTable_Header *sclk_dep_table =
3128 (PPTable_Generic_SubTable_Header *)
3129 (((unsigned long)powerplay_table) +
3130 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3132 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3133 (ATOM_Tonga_MCLK_Dependency_Table *)
3134 (((unsigned long)powerplay_table) +
3135 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3137 /* The following fields are not initialized here: id orderedList allStatesList */
3138 power_state->classification.ui_label =
3139 (le16_to_cpu(state_entry->usClassification) &
3140 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3141 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3142 power_state->classification.flags = classification_flag;
3143 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3145 power_state->classification.temporary_state = false;
3146 power_state->classification.to_be_deleted = false;
3148 power_state->validation.disallowOnDC =
3149 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3150 ATOM_Tonga_DISALLOW_ON_DC));
3152 power_state->pcie.lanes = 0;
3154 power_state->display.disableFrameModulation = false;
3155 power_state->display.limitRefreshrate = false;
3156 power_state->display.enableVariBright =
3157 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3158 ATOM_Tonga_ENABLE_VARIBRIGHT));
3160 power_state->validation.supportedPowerLevels = 0;
3161 power_state->uvd_clocks.VCLK = 0;
3162 power_state->uvd_clocks.DCLK = 0;
3163 power_state->temperatures.min = 0;
3164 power_state->temperatures.max = 0;
3166 performance_level = &(smu7_power_state->performance_levels
3167 [smu7_power_state->performance_level_count++]);
3169 PP_ASSERT_WITH_CODE(
3170 (smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)),
3171 "Performance levels exceeds SMC limit!",
3174 PP_ASSERT_WITH_CODE(
3175 (smu7_power_state->performance_level_count <=
3176 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3177 "Performance levels exceeds Driver limit!",
3180 /* Performance levels are arranged from low to high. */
3181 performance_level->memory_clock = mclk_dep_table->entries
3182 [state_entry->ucMemoryClockIndexLow].ulMclk;
3183 if (sclk_dep_table->ucRevId == 0)
3184 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3185 [state_entry->ucEngineClockIndexLow].ulSclk;
3186 else if (sclk_dep_table->ucRevId == 1)
3187 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3188 [state_entry->ucEngineClockIndexLow].ulSclk;
3189 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3190 state_entry->ucPCIEGenLow);
3191 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3192 state_entry->ucPCIELaneLow);
3194 performance_level = &(smu7_power_state->performance_levels
3195 [smu7_power_state->performance_level_count++]);
3196 performance_level->memory_clock = mclk_dep_table->entries
3197 [state_entry->ucMemoryClockIndexHigh].ulMclk;
3199 if (sclk_dep_table->ucRevId == 0)
3200 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3201 [state_entry->ucEngineClockIndexHigh].ulSclk;
3202 else if (sclk_dep_table->ucRevId == 1)
3203 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3204 [state_entry->ucEngineClockIndexHigh].ulSclk;
3206 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3207 state_entry->ucPCIEGenHigh);
3208 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3209 state_entry->ucPCIELaneHigh);
3214 static int smu7_get_pp_table_entry_v1(struct pp_hwmgr *hwmgr,
3215 unsigned long entry_index, struct pp_power_state *state)
3218 struct smu7_power_state *ps;
3219 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3220 struct phm_ppt_v1_information *table_info =
3221 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3222 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3223 table_info->vdd_dep_on_mclk;
3225 state->hardware.magic = PHM_VIslands_Magic;
3227 ps = (struct smu7_power_state *)(&state->hardware);
3229 result = get_powerplay_table_entry_v1_0(hwmgr, entry_index, state,
3230 smu7_get_pp_table_entry_callback_func_v1);
3232 /* This is the earliest time we have all the dependency table and the VBIOS boot state
3233 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3234 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3236 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3237 if (dep_mclk_table->entries[0].clk !=
3238 data->vbios_boot_state.mclk_bootup_value)
3239 pr_debug("Single MCLK entry VDDCI/MCLK dependency table "
3240 "does not match VBIOS boot MCLK level");
3241 if (dep_mclk_table->entries[0].vddci !=
3242 data->vbios_boot_state.vddci_bootup_value)
3243 pr_debug("Single VDDCI entry VDDCI/MCLK dependency table "
3244 "does not match VBIOS boot VDDCI level");
3247 /* set DC compatible flag if this state supports DC */
3248 if (!state->validation.disallowOnDC)
3249 ps->dc_compatible = true;
3251 if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3252 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3254 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3255 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3260 switch (state->classification.ui_label) {
3261 case PP_StateUILabel_Performance:
3262 data->use_pcie_performance_levels = true;
3263 for (i = 0; i < ps->performance_level_count; i++) {
3264 if (data->pcie_gen_performance.max <
3265 ps->performance_levels[i].pcie_gen)
3266 data->pcie_gen_performance.max =
3267 ps->performance_levels[i].pcie_gen;
3269 if (data->pcie_gen_performance.min >
3270 ps->performance_levels[i].pcie_gen)
3271 data->pcie_gen_performance.min =
3272 ps->performance_levels[i].pcie_gen;
3274 if (data->pcie_lane_performance.max <
3275 ps->performance_levels[i].pcie_lane)
3276 data->pcie_lane_performance.max =
3277 ps->performance_levels[i].pcie_lane;
3278 if (data->pcie_lane_performance.min >
3279 ps->performance_levels[i].pcie_lane)
3280 data->pcie_lane_performance.min =
3281 ps->performance_levels[i].pcie_lane;
3284 case PP_StateUILabel_Battery:
3285 data->use_pcie_power_saving_levels = true;
3287 for (i = 0; i < ps->performance_level_count; i++) {
3288 if (data->pcie_gen_power_saving.max <
3289 ps->performance_levels[i].pcie_gen)
3290 data->pcie_gen_power_saving.max =
3291 ps->performance_levels[i].pcie_gen;
3293 if (data->pcie_gen_power_saving.min >
3294 ps->performance_levels[i].pcie_gen)
3295 data->pcie_gen_power_saving.min =
3296 ps->performance_levels[i].pcie_gen;
3298 if (data->pcie_lane_power_saving.max <
3299 ps->performance_levels[i].pcie_lane)
3300 data->pcie_lane_power_saving.max =
3301 ps->performance_levels[i].pcie_lane;
3303 if (data->pcie_lane_power_saving.min >
3304 ps->performance_levels[i].pcie_lane)
3305 data->pcie_lane_power_saving.min =
3306 ps->performance_levels[i].pcie_lane;
3316 static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr,
3317 struct pp_hw_power_state *power_state,
3318 unsigned int index, const void *clock_info)
3320 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3321 struct smu7_power_state *ps = cast_phw_smu7_power_state(power_state);
3322 const ATOM_PPLIB_CI_CLOCK_INFO *visland_clk_info = clock_info;
3323 struct smu7_performance_level *performance_level;
3324 uint32_t engine_clock, memory_clock;
3325 uint16_t pcie_gen_from_bios;
3327 engine_clock = visland_clk_info->ucEngineClockHigh << 16 | visland_clk_info->usEngineClockLow;
3328 memory_clock = visland_clk_info->ucMemoryClockHigh << 16 | visland_clk_info->usMemoryClockLow;
3330 if (!(data->mc_micro_code_feature & DISABLE_MC_LOADMICROCODE) && memory_clock > data->highest_mclk)
3331 data->highest_mclk = memory_clock;
3333 PP_ASSERT_WITH_CODE(
3334 (ps->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)),
3335 "Performance levels exceeds SMC limit!",
3338 PP_ASSERT_WITH_CODE(
3339 (ps->performance_level_count <
3340 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3341 "Performance levels exceeds Driver limit, Skip!",
3344 performance_level = &(ps->performance_levels
3345 [ps->performance_level_count++]);
3347 /* Performance levels are arranged from low to high. */
3348 performance_level->memory_clock = memory_clock;
3349 performance_level->engine_clock = engine_clock;
3351 pcie_gen_from_bios = visland_clk_info->ucPCIEGen;
3353 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, pcie_gen_from_bios);
3354 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, visland_clk_info->usPCIELane);
3359 static int smu7_get_pp_table_entry_v0(struct pp_hwmgr *hwmgr,
3360 unsigned long entry_index, struct pp_power_state *state)
3363 struct smu7_power_state *ps;
3364 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3365 struct phm_clock_voltage_dependency_table *dep_mclk_table =
3366 hwmgr->dyn_state.vddci_dependency_on_mclk;
3368 memset(&state->hardware, 0x00, sizeof(struct pp_hw_power_state));
3370 state->hardware.magic = PHM_VIslands_Magic;
3372 ps = (struct smu7_power_state *)(&state->hardware);
3374 result = pp_tables_get_entry(hwmgr, entry_index, state,
3375 smu7_get_pp_table_entry_callback_func_v0);
3378 * This is the earliest time we have all the dependency table
3379 * and the VBIOS boot state as
3380 * PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot
3381 * state if there is only one VDDCI/MCLK level, check if it's
3382 * the same as VBIOS boot state
3384 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3385 if (dep_mclk_table->entries[0].clk !=
3386 data->vbios_boot_state.mclk_bootup_value)
3387 pr_debug("Single MCLK entry VDDCI/MCLK dependency table "
3388 "does not match VBIOS boot MCLK level");
3389 if (dep_mclk_table->entries[0].v !=
3390 data->vbios_boot_state.vddci_bootup_value)
3391 pr_debug("Single VDDCI entry VDDCI/MCLK dependency table "
3392 "does not match VBIOS boot VDDCI level");
3395 /* set DC compatible flag if this state supports DC */
3396 if (!state->validation.disallowOnDC)
3397 ps->dc_compatible = true;
3399 if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3400 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3402 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3403 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3408 switch (state->classification.ui_label) {
3409 case PP_StateUILabel_Performance:
3410 data->use_pcie_performance_levels = true;
3412 for (i = 0; i < ps->performance_level_count; i++) {
3413 if (data->pcie_gen_performance.max <
3414 ps->performance_levels[i].pcie_gen)
3415 data->pcie_gen_performance.max =
3416 ps->performance_levels[i].pcie_gen;
3418 if (data->pcie_gen_performance.min >
3419 ps->performance_levels[i].pcie_gen)
3420 data->pcie_gen_performance.min =
3421 ps->performance_levels[i].pcie_gen;
3423 if (data->pcie_lane_performance.max <
3424 ps->performance_levels[i].pcie_lane)
3425 data->pcie_lane_performance.max =
3426 ps->performance_levels[i].pcie_lane;
3428 if (data->pcie_lane_performance.min >
3429 ps->performance_levels[i].pcie_lane)
3430 data->pcie_lane_performance.min =
3431 ps->performance_levels[i].pcie_lane;
3434 case PP_StateUILabel_Battery:
3435 data->use_pcie_power_saving_levels = true;
3437 for (i = 0; i < ps->performance_level_count; i++) {
3438 if (data->pcie_gen_power_saving.max <
3439 ps->performance_levels[i].pcie_gen)
3440 data->pcie_gen_power_saving.max =
3441 ps->performance_levels[i].pcie_gen;
3443 if (data->pcie_gen_power_saving.min >
3444 ps->performance_levels[i].pcie_gen)
3445 data->pcie_gen_power_saving.min =
3446 ps->performance_levels[i].pcie_gen;
3448 if (data->pcie_lane_power_saving.max <
3449 ps->performance_levels[i].pcie_lane)
3450 data->pcie_lane_power_saving.max =
3451 ps->performance_levels[i].pcie_lane;
3453 if (data->pcie_lane_power_saving.min >
3454 ps->performance_levels[i].pcie_lane)
3455 data->pcie_lane_power_saving.min =
3456 ps->performance_levels[i].pcie_lane;
3466 static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3467 unsigned long entry_index, struct pp_power_state *state)
3469 if (hwmgr->pp_table_version == PP_TABLE_V0)
3470 return smu7_get_pp_table_entry_v0(hwmgr, entry_index, state);
3471 else if (hwmgr->pp_table_version == PP_TABLE_V1)
3472 return smu7_get_pp_table_entry_v1(hwmgr, entry_index, state);
3477 static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, u32 *query)
3485 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetCurrPkgPwr, 0);
3486 tmp = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3492 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart);
3493 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3494 ixSMU_PM_STATUS_94, 0);
3496 for (i = 0; i < 10; i++) {
3498 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample);
3499 tmp = cgs_read_ind_register(hwmgr->device,
3501 ixSMU_PM_STATUS_94);
3510 static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx,
3511 void *value, int *size)
3513 uint32_t sclk, mclk, activity_percent;
3514 uint32_t offset, val_vid;
3515 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3517 /* size must be at least 4 bytes for all sensors */
3522 case AMDGPU_PP_SENSOR_GFX_SCLK:
3523 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency);
3524 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3525 *((uint32_t *)value) = sclk;
3528 case AMDGPU_PP_SENSOR_GFX_MCLK:
3529 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency);
3530 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3531 *((uint32_t *)value) = mclk;
3534 case AMDGPU_PP_SENSOR_GPU_LOAD:
3535 offset = data->soft_regs_start + smum_get_offsetof(hwmgr,
3537 AverageGraphicsActivity);
3539 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
3540 activity_percent += 0x80;
3541 activity_percent >>= 8;
3542 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
3545 case AMDGPU_PP_SENSOR_GPU_TEMP:
3546 *((uint32_t *)value) = smu7_thermal_get_temperature(hwmgr);
3549 case AMDGPU_PP_SENSOR_UVD_POWER:
3550 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
3553 case AMDGPU_PP_SENSOR_VCE_POWER:
3554 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
3557 case AMDGPU_PP_SENSOR_GPU_POWER:
3558 return smu7_get_gpu_power(hwmgr, (uint32_t *)value);
3559 case AMDGPU_PP_SENSOR_VDDGFX:
3560 if ((data->vr_config & 0xff) == 0x2)
3561 val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device,
3562 CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE2_VID);
3564 val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device,
3565 CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE1_VID);
3567 *((uint32_t *)value) = (uint32_t)convert_to_vddc(val_vid);
3574 static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3576 const struct phm_set_power_state_input *states =
3577 (const struct phm_set_power_state_input *)input;
3578 const struct smu7_power_state *smu7_ps =
3579 cast_const_phw_smu7_power_state(states->pnew_state);
3580 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3581 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
3582 uint32_t sclk = smu7_ps->performance_levels
3583 [smu7_ps->performance_level_count - 1].engine_clock;
3584 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
3585 uint32_t mclk = smu7_ps->performance_levels
3586 [smu7_ps->performance_level_count - 1].memory_clock;
3587 struct PP_Clocks min_clocks = {0};
3590 for (i = 0; i < sclk_table->count; i++) {
3591 if (sclk == sclk_table->dpm_levels[i].value)
3595 if (i >= sclk_table->count) {
3596 if (sclk > sclk_table->dpm_levels[i-1].value) {
3597 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3598 sclk_table->dpm_levels[i-1].value = sclk;
3601 /* TODO: Check SCLK in DAL's minimum clocks
3602 * in case DeepSleep divider update is required.
3604 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
3605 (min_clocks.engineClockInSR >= SMU7_MINIMUM_ENGINE_CLOCK ||
3606 data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))
3607 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3610 for (i = 0; i < mclk_table->count; i++) {
3611 if (mclk == mclk_table->dpm_levels[i].value)
3615 if (i >= mclk_table->count) {
3616 if (mclk > mclk_table->dpm_levels[i-1].value) {
3617 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3618 mclk_table->dpm_levels[i-1].value = mclk;
3622 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
3623 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3628 static uint16_t smu7_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
3629 const struct smu7_power_state *smu7_ps)
3632 uint32_t sclk, max_sclk = 0;
3633 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3634 struct smu7_dpm_table *dpm_table = &data->dpm_table;
3636 for (i = 0; i < smu7_ps->performance_level_count; i++) {
3637 sclk = smu7_ps->performance_levels[i].engine_clock;
3638 if (max_sclk < sclk)
3642 for (i = 0; i < dpm_table->sclk_table.count; i++) {
3643 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
3644 return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
3645 dpm_table->pcie_speed_table.dpm_levels
3646 [dpm_table->pcie_speed_table.count - 1].value :
3647 dpm_table->pcie_speed_table.dpm_levels[i].value);
3653 static int smu7_request_link_speed_change_before_state_change(
3654 struct pp_hwmgr *hwmgr, const void *input)
3656 const struct phm_set_power_state_input *states =
3657 (const struct phm_set_power_state_input *)input;
3658 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3659 const struct smu7_power_state *smu7_nps =
3660 cast_const_phw_smu7_power_state(states->pnew_state);
3661 const struct smu7_power_state *polaris10_cps =
3662 cast_const_phw_smu7_power_state(states->pcurrent_state);
3664 uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_nps);
3665 uint16_t current_link_speed;
3667 if (data->force_pcie_gen == PP_PCIEGenInvalid)
3668 current_link_speed = smu7_get_maximum_link_speed(hwmgr, polaris10_cps);
3670 current_link_speed = data->force_pcie_gen;
3672 data->force_pcie_gen = PP_PCIEGenInvalid;
3673 data->pspp_notify_required = false;
3675 if (target_link_speed > current_link_speed) {
3676 switch (target_link_speed) {
3679 if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN3, false))
3681 data->force_pcie_gen = PP_PCIEGen2;
3682 if (current_link_speed == PP_PCIEGen2)
3685 if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN2, false))
3689 data->force_pcie_gen = smu7_get_current_pcie_speed(hwmgr);
3693 if (target_link_speed < current_link_speed)
3694 data->pspp_notify_required = true;
3700 static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3702 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3704 if (0 == data->need_update_smu7_dpm_table)
3707 if ((0 == data->sclk_dpm_key_disabled) &&
3708 (data->need_update_smu7_dpm_table &
3709 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
3710 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3711 "Trying to freeze SCLK DPM when DPM is disabled",
3713 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
3714 PPSMC_MSG_SCLKDPM_FreezeLevel),
3715 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
3719 if ((0 == data->mclk_dpm_key_disabled) &&
3720 (data->need_update_smu7_dpm_table &
3721 DPMTABLE_OD_UPDATE_MCLK)) {
3722 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3723 "Trying to freeze MCLK DPM when DPM is disabled",
3725 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
3726 PPSMC_MSG_MCLKDPM_FreezeLevel),
3727 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
3734 static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
3735 struct pp_hwmgr *hwmgr, const void *input)
3738 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3739 struct smu7_dpm_table *dpm_table = &data->dpm_table;
3741 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
3742 struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);
3743 struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);
3745 if (0 == data->need_update_smu7_dpm_table)
3748 if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
3749 for (count = 0; count < dpm_table->sclk_table.count; count++) {
3750 dpm_table->sclk_table.dpm_levels[count].enabled = odn_sclk_table->entries[count].enabled;
3751 dpm_table->sclk_table.dpm_levels[count].value = odn_sclk_table->entries[count].clock;
3755 if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
3756 for (count = 0; count < dpm_table->mclk_table.count; count++) {
3757 dpm_table->mclk_table.dpm_levels[count].enabled = odn_mclk_table->entries[count].enabled;
3758 dpm_table->mclk_table.dpm_levels[count].value = odn_mclk_table->entries[count].clock;
3762 if (data->need_update_smu7_dpm_table &
3763 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
3764 result = smum_populate_all_graphic_levels(hwmgr);
3765 PP_ASSERT_WITH_CODE((0 == result),
3766 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
3770 if (data->need_update_smu7_dpm_table &
3771 (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
3772 /*populate MCLK dpm table to SMU7 */
3773 result = smum_populate_all_memory_levels(hwmgr);
3774 PP_ASSERT_WITH_CODE((0 == result),
3775 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
3782 static int smu7_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
3783 struct smu7_single_dpm_table *dpm_table,
3784 uint32_t low_limit, uint32_t high_limit)
3788 for (i = 0; i < dpm_table->count; i++) {
3789 /*skip the trim if od is enabled*/
3790 if (!hwmgr->od_enabled && (dpm_table->dpm_levels[i].value < low_limit
3791 || dpm_table->dpm_levels[i].value > high_limit))
3792 dpm_table->dpm_levels[i].enabled = false;
3794 dpm_table->dpm_levels[i].enabled = true;
3800 static int smu7_trim_dpm_states(struct pp_hwmgr *hwmgr,
3801 const struct smu7_power_state *smu7_ps)
3803 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3804 uint32_t high_limit_count;
3806 PP_ASSERT_WITH_CODE((smu7_ps->performance_level_count >= 1),
3807 "power state did not have any performance level",
3810 high_limit_count = (1 == smu7_ps->performance_level_count) ? 0 : 1;
3812 smu7_trim_single_dpm_states(hwmgr,
3813 &(data->dpm_table.sclk_table),
3814 smu7_ps->performance_levels[0].engine_clock,
3815 smu7_ps->performance_levels[high_limit_count].engine_clock);
3817 smu7_trim_single_dpm_states(hwmgr,
3818 &(data->dpm_table.mclk_table),
3819 smu7_ps->performance_levels[0].memory_clock,
3820 smu7_ps->performance_levels[high_limit_count].memory_clock);
3825 static int smu7_generate_dpm_level_enable_mask(
3826 struct pp_hwmgr *hwmgr, const void *input)
3829 const struct phm_set_power_state_input *states =
3830 (const struct phm_set_power_state_input *)input;
3831 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3832 const struct smu7_power_state *smu7_ps =
3833 cast_const_phw_smu7_power_state(states->pnew_state);
3836 result = smu7_trim_dpm_states(hwmgr, smu7_ps);
3840 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
3841 phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
3842 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
3843 phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
3844 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
3845 phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
3850 static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3852 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3854 if (0 == data->need_update_smu7_dpm_table)
3857 if ((0 == data->sclk_dpm_key_disabled) &&
3858 (data->need_update_smu7_dpm_table &
3859 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
3861 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3862 "Trying to Unfreeze SCLK DPM when DPM is disabled",
3864 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
3865 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
3866 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
3870 if ((0 == data->mclk_dpm_key_disabled) &&
3871 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
3873 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3874 "Trying to Unfreeze MCLK DPM when DPM is disabled",
3876 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
3877 PPSMC_MSG_MCLKDPM_UnfreezeLevel),
3878 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
3882 data->need_update_smu7_dpm_table &= DPMTABLE_OD_UPDATE_VDDC;
3887 static int smu7_notify_link_speed_change_after_state_change(
3888 struct pp_hwmgr *hwmgr, const void *input)
3890 const struct phm_set_power_state_input *states =
3891 (const struct phm_set_power_state_input *)input;
3892 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3893 const struct smu7_power_state *smu7_ps =
3894 cast_const_phw_smu7_power_state(states->pnew_state);
3895 uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_ps);
3898 if (data->pspp_notify_required) {
3899 if (target_link_speed == PP_PCIEGen3)
3900 request = PCIE_PERF_REQ_GEN3;
3901 else if (target_link_speed == PP_PCIEGen2)
3902 request = PCIE_PERF_REQ_GEN2;
3904 request = PCIE_PERF_REQ_GEN1;
3906 if (request == PCIE_PERF_REQ_GEN1 &&
3907 smu7_get_current_pcie_speed(hwmgr) > 0)
3911 if (amdgpu_acpi_pcie_performance_request(hwmgr->adev, request, false)) {
3912 if (PP_PCIEGen2 == target_link_speed)
3913 pr_info("PSPP request to switch to Gen2 from Gen3 Failed!");
3915 pr_info("PSPP request to switch to Gen1 from Gen2 Failed!");
3923 static int smu7_notify_smc_display(struct pp_hwmgr *hwmgr)
3925 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3927 if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK) {
3928 if (hwmgr->chip_id == CHIP_VEGAM)
3929 smum_send_msg_to_smc_with_parameter(hwmgr,
3930 (PPSMC_Msg)PPSMC_MSG_SetVBITimeout_VEGAM, data->frame_time_x2);
3932 smum_send_msg_to_smc_with_parameter(hwmgr,
3933 (PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2);
3935 return (smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ? 0 : -EINVAL;
3938 static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
3940 int tmp_result, result = 0;
3941 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3943 tmp_result = smu7_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
3944 PP_ASSERT_WITH_CODE((0 == tmp_result),
3945 "Failed to find DPM states clocks in DPM table!",
3946 result = tmp_result);
3948 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3949 PHM_PlatformCaps_PCIEPerformanceRequest)) {
3951 smu7_request_link_speed_change_before_state_change(hwmgr, input);
3952 PP_ASSERT_WITH_CODE((0 == tmp_result),
3953 "Failed to request link speed change before state change!",
3954 result = tmp_result);
3957 tmp_result = smu7_freeze_sclk_mclk_dpm(hwmgr);
3958 PP_ASSERT_WITH_CODE((0 == tmp_result),
3959 "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
3961 tmp_result = smu7_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
3962 PP_ASSERT_WITH_CODE((0 == tmp_result),
3963 "Failed to populate and upload SCLK MCLK DPM levels!",
3964 result = tmp_result);
3966 tmp_result = smu7_update_avfs(hwmgr);
3967 PP_ASSERT_WITH_CODE((0 == tmp_result),
3968 "Failed to update avfs voltages!",
3969 result = tmp_result);
3971 tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input);
3972 PP_ASSERT_WITH_CODE((0 == tmp_result),
3973 "Failed to generate DPM level enabled mask!",
3974 result = tmp_result);
3976 tmp_result = smum_update_sclk_threshold(hwmgr);
3977 PP_ASSERT_WITH_CODE((0 == tmp_result),
3978 "Failed to update SCLK threshold!",
3979 result = tmp_result);
3981 tmp_result = smu7_notify_smc_display(hwmgr);
3982 PP_ASSERT_WITH_CODE((0 == tmp_result),
3983 "Failed to notify smc display settings!",
3984 result = tmp_result);
3986 tmp_result = smu7_unfreeze_sclk_mclk_dpm(hwmgr);
3987 PP_ASSERT_WITH_CODE((0 == tmp_result),
3988 "Failed to unfreeze SCLK MCLK DPM!",
3989 result = tmp_result);
3991 tmp_result = smu7_upload_dpm_level_enable_mask(hwmgr);
3992 PP_ASSERT_WITH_CODE((0 == tmp_result),
3993 "Failed to upload DPM level enabled mask!",
3994 result = tmp_result);
3996 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3997 PHM_PlatformCaps_PCIEPerformanceRequest)) {
3999 smu7_notify_link_speed_change_after_state_change(hwmgr, input);
4000 PP_ASSERT_WITH_CODE((0 == tmp_result),
4001 "Failed to notify link speed change after state change!",
4002 result = tmp_result);
4004 data->apply_optimized_settings = false;
4008 static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
4010 hwmgr->thermal_controller.
4011 advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4013 return smum_send_msg_to_smc_with_parameter(hwmgr,
4014 PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
4018 smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
4020 PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
4022 return (smum_send_msg_to_smc(hwmgr, msg) == 0) ? 0 : -1;
4026 smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
4028 if (hwmgr->display_config->num_display > 1 &&
4029 !hwmgr->display_config->multi_monitor_in_sync)
4030 smu7_notify_smc_display_change(hwmgr, false);
4036 * Programs the display gap
4038 * @param hwmgr the address of the powerplay hardware manager.
4041 static int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
4043 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4044 uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4045 uint32_t display_gap2;
4046 uint32_t pre_vbi_time_in_us;
4047 uint32_t frame_time_in_us;
4048 uint32_t ref_clock, refresh_rate;
4050 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->num_display > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4051 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4053 ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
4054 refresh_rate = hwmgr->display_config->vrefresh;
4056 if (0 == refresh_rate)
4059 frame_time_in_us = 1000000 / refresh_rate;
4061 pre_vbi_time_in_us = frame_time_in_us - 200 - hwmgr->display_config->min_vblank_time;
4063 data->frame_time_x2 = frame_time_in_us * 2 / 100;
4065 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4067 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4069 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4070 data->soft_regs_start + smum_get_offsetof(hwmgr,
4072 PreVBlankGap), 0x64);
4074 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4075 data->soft_regs_start + smum_get_offsetof(hwmgr,
4078 (frame_time_in_us - pre_vbi_time_in_us));
4083 static int smu7_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4085 return smu7_program_display_gap(hwmgr);
4089 * Set maximum target operating fan output RPM
4091 * @param hwmgr: the address of the powerplay hardware manager.
4092 * @param usMaxFanRpm: max operating fan RPM value.
4093 * @return The response that came from the SMC.
4095 static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
4097 hwmgr->thermal_controller.
4098 advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4100 return smum_send_msg_to_smc_with_parameter(hwmgr,
4101 PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
4104 static const struct amdgpu_irq_src_funcs smu7_irq_funcs = {
4105 .process = phm_irq_process,
4108 static int smu7_register_irq_handlers(struct pp_hwmgr *hwmgr)
4110 struct amdgpu_irq_src *source =
4111 kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
4116 source->funcs = &smu7_irq_funcs;
4118 amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
4119 AMDGPU_IRQ_CLIENTID_LEGACY,
4120 VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH,
4122 amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
4123 AMDGPU_IRQ_CLIENTID_LEGACY,
4124 VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW,
4127 /* Register CTF(GPIO_19) interrupt */
4128 amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
4129 AMDGPU_IRQ_CLIENTID_LEGACY,
4130 VISLANDS30_IV_SRCID_GPIO_19,
4137 smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4139 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4140 bool is_update_required = false;
4142 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
4143 is_update_required = true;
4145 if (data->display_timing.vrefresh != hwmgr->display_config->vrefresh)
4146 is_update_required = true;
4148 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4149 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr &&
4150 (data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK ||
4151 hwmgr->display_config->min_core_set_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))
4152 is_update_required = true;
4154 return is_update_required;
4157 static inline bool smu7_are_power_levels_equal(const struct smu7_performance_level *pl1,
4158 const struct smu7_performance_level *pl2)
4160 return ((pl1->memory_clock == pl2->memory_clock) &&
4161 (pl1->engine_clock == pl2->engine_clock) &&
4162 (pl1->pcie_gen == pl2->pcie_gen) &&
4163 (pl1->pcie_lane == pl2->pcie_lane));
4166 static int smu7_check_states_equal(struct pp_hwmgr *hwmgr,
4167 const struct pp_hw_power_state *pstate1,
4168 const struct pp_hw_power_state *pstate2, bool *equal)
4170 const struct smu7_power_state *psa;
4171 const struct smu7_power_state *psb;
4173 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4175 if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4178 psa = cast_const_phw_smu7_power_state(pstate1);
4179 psb = cast_const_phw_smu7_power_state(pstate2);
4180 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4181 if (psa->performance_level_count != psb->performance_level_count) {
4186 for (i = 0; i < psa->performance_level_count; i++) {
4187 if (!smu7_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4188 /* If we have found even one performance level pair that is different the states are different. */
4194 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4195 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4196 *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4197 *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4198 /* For OD call, set value based on flag */
4199 *equal &= !(data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK |
4200 DPMTABLE_OD_UPDATE_MCLK |
4201 DPMTABLE_OD_UPDATE_VDDC));
4206 static int smu7_check_mc_firmware(struct pp_hwmgr *hwmgr)
4208 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4210 uint32_t vbios_version;
4213 /* Read MC indirect register offset 0x9F bits [3:0] to see
4214 * if VBIOS has already loaded a full version of MC ucode
4218 smu7_get_mc_microcode_version(hwmgr);
4219 vbios_version = hwmgr->microcode_version_info.MC & 0xf;
4221 data->need_long_memory_training = false;
4223 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX,
4224 ixMC_IO_DEBUG_UP_13);
4225 tmp = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
4227 if (tmp & (1 << 23)) {
4228 data->mem_latency_high = MEM_LATENCY_HIGH;
4229 data->mem_latency_low = MEM_LATENCY_LOW;
4230 if ((hwmgr->chip_id == CHIP_POLARIS10) ||
4231 (hwmgr->chip_id == CHIP_POLARIS11) ||
4232 (hwmgr->chip_id == CHIP_POLARIS12))
4233 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableFFC);
4235 data->mem_latency_high = 330;
4236 data->mem_latency_low = 330;
4237 if ((hwmgr->chip_id == CHIP_POLARIS10) ||
4238 (hwmgr->chip_id == CHIP_POLARIS11) ||
4239 (hwmgr->chip_id == CHIP_POLARIS12))
4240 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableFFC);
4246 static int smu7_read_clock_registers(struct pp_hwmgr *hwmgr)
4248 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4250 data->clock_registers.vCG_SPLL_FUNC_CNTL =
4251 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL);
4252 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 =
4253 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2);
4254 data->clock_registers.vCG_SPLL_FUNC_CNTL_3 =
4255 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3);
4256 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 =
4257 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4);
4258 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM =
4259 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM);
4260 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
4261 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2);
4262 data->clock_registers.vDLL_CNTL =
4263 cgs_read_register(hwmgr->device, mmDLL_CNTL);
4264 data->clock_registers.vMCLK_PWRMGT_CNTL =
4265 cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL);
4266 data->clock_registers.vMPLL_AD_FUNC_CNTL =
4267 cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL);
4268 data->clock_registers.vMPLL_DQ_FUNC_CNTL =
4269 cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL);
4270 data->clock_registers.vMPLL_FUNC_CNTL =
4271 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL);
4272 data->clock_registers.vMPLL_FUNC_CNTL_1 =
4273 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1);
4274 data->clock_registers.vMPLL_FUNC_CNTL_2 =
4275 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2);
4276 data->clock_registers.vMPLL_SS1 =
4277 cgs_read_register(hwmgr->device, mmMPLL_SS1);
4278 data->clock_registers.vMPLL_SS2 =
4279 cgs_read_register(hwmgr->device, mmMPLL_SS2);
4285 * Find out if memory is GDDR5.
4287 * @param hwmgr the address of the powerplay hardware manager.
4290 static int smu7_get_memory_type(struct pp_hwmgr *hwmgr)
4292 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4293 struct amdgpu_device *adev = hwmgr->adev;
4295 data->is_memory_gddr5 = (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5);
4301 * Enables Dynamic Power Management by SMC
4303 * @param hwmgr the address of the powerplay hardware manager.
4306 static int smu7_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
4308 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4309 GENERAL_PWRMGT, STATIC_PM_EN, 1);
4315 * Initialize PowerGating States for different engines
4317 * @param hwmgr the address of the powerplay hardware manager.
4320 static int smu7_init_power_gate_state(struct pp_hwmgr *hwmgr)
4322 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4324 data->uvd_power_gated = false;
4325 data->vce_power_gated = false;
4330 static int smu7_init_sclk_threshold(struct pp_hwmgr *hwmgr)
4332 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4334 data->low_sclk_interrupt_threshold = 0;
4338 static int smu7_setup_asic_task(struct pp_hwmgr *hwmgr)
4340 int tmp_result, result = 0;
4342 smu7_check_mc_firmware(hwmgr);
4344 tmp_result = smu7_read_clock_registers(hwmgr);
4345 PP_ASSERT_WITH_CODE((0 == tmp_result),
4346 "Failed to read clock registers!", result = tmp_result);
4348 tmp_result = smu7_get_memory_type(hwmgr);
4349 PP_ASSERT_WITH_CODE((0 == tmp_result),
4350 "Failed to get memory type!", result = tmp_result);
4352 tmp_result = smu7_enable_acpi_power_management(hwmgr);
4353 PP_ASSERT_WITH_CODE((0 == tmp_result),
4354 "Failed to enable ACPI power management!", result = tmp_result);
4356 tmp_result = smu7_init_power_gate_state(hwmgr);
4357 PP_ASSERT_WITH_CODE((0 == tmp_result),
4358 "Failed to init power gate state!", result = tmp_result);
4360 tmp_result = smu7_get_mc_microcode_version(hwmgr);
4361 PP_ASSERT_WITH_CODE((0 == tmp_result),
4362 "Failed to get MC microcode version!", result = tmp_result);
4364 tmp_result = smu7_init_sclk_threshold(hwmgr);
4365 PP_ASSERT_WITH_CODE((0 == tmp_result),
4366 "Failed to init sclk threshold!", result = tmp_result);
4371 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
4372 enum pp_clock_type type, uint32_t mask)
4374 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4381 if (!data->sclk_dpm_key_disabled)
4382 smum_send_msg_to_smc_with_parameter(hwmgr,
4383 PPSMC_MSG_SCLKDPM_SetEnabledMask,
4384 data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
4387 if (!data->mclk_dpm_key_disabled)
4388 smum_send_msg_to_smc_with_parameter(hwmgr,
4389 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4390 data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
4394 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
4396 if (!data->pcie_dpm_key_disabled) {
4397 if (fls(tmp) != ffs(tmp))
4398 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PCIeDPM_UnForceLevel);
4400 smum_send_msg_to_smc_with_parameter(hwmgr,
4401 PPSMC_MSG_PCIeDPM_ForceLevel,
4413 static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
4414 enum pp_clock_type type, char *buf)
4416 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4417 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4418 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4419 struct smu7_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
4420 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
4421 struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);
4422 struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);
4423 int i, now, size = 0;
4424 uint32_t clock, pcie_speed;
4428 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency);
4429 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4431 for (i = 0; i < sclk_table->count; i++) {
4432 if (clock > sclk_table->dpm_levels[i].value)
4438 for (i = 0; i < sclk_table->count; i++)
4439 size += sprintf(buf + size, "%d: %uMhz %s\n",
4440 i, sclk_table->dpm_levels[i].value / 100,
4441 (i == now) ? "*" : "");
4444 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency);
4445 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4447 for (i = 0; i < mclk_table->count; i++) {
4448 if (clock > mclk_table->dpm_levels[i].value)
4454 for (i = 0; i < mclk_table->count; i++)
4455 size += sprintf(buf + size, "%d: %uMhz %s\n",
4456 i, mclk_table->dpm_levels[i].value / 100,
4457 (i == now) ? "*" : "");
4460 pcie_speed = smu7_get_current_pcie_speed(hwmgr);
4461 for (i = 0; i < pcie_table->count; i++) {
4462 if (pcie_speed != pcie_table->dpm_levels[i].value)
4468 for (i = 0; i < pcie_table->count; i++)
4469 size += sprintf(buf + size, "%d: %s %s\n", i,
4470 (pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x8" :
4471 (pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" :
4472 (pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "",
4473 (i == now) ? "*" : "");
4476 if (hwmgr->od_enabled) {
4477 size = sprintf(buf, "%s:\n", "OD_SCLK");
4478 for (i = 0; i < odn_sclk_table->num_of_pl; i++)
4479 size += sprintf(buf + size, "%d: %10uMHz %10umV\n",
4480 i, odn_sclk_table->entries[i].clock/100,
4481 odn_sclk_table->entries[i].vddc);
4485 if (hwmgr->od_enabled) {
4486 size = sprintf(buf, "%s:\n", "OD_MCLK");
4487 for (i = 0; i < odn_mclk_table->num_of_pl; i++)
4488 size += sprintf(buf + size, "%d: %10uMHz %10umV\n",
4489 i, odn_mclk_table->entries[i].clock/100,
4490 odn_mclk_table->entries[i].vddc);
4494 if (hwmgr->od_enabled) {
4495 size = sprintf(buf, "%s:\n", "OD_RANGE");
4496 size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",
4497 data->golden_dpm_table.sclk_table.dpm_levels[0].value/100,
4498 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
4499 size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n",
4500 data->golden_dpm_table.mclk_table.dpm_levels[0].value/100,
4501 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
4502 size += sprintf(buf + size, "VDDC: %7umV %11umV\n",
4503 data->odn_dpm_table.min_vddc,
4504 data->odn_dpm_table.max_vddc);
4513 static void smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
4516 case AMD_FAN_CTRL_NONE:
4517 smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
4519 case AMD_FAN_CTRL_MANUAL:
4520 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4521 PHM_PlatformCaps_MicrocodeFanControl))
4522 smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
4524 case AMD_FAN_CTRL_AUTO:
4525 if (!smu7_fan_ctrl_set_static_mode(hwmgr, mode))
4526 smu7_fan_ctrl_start_smc_fan_control(hwmgr);
4533 static uint32_t smu7_get_fan_control_mode(struct pp_hwmgr *hwmgr)
4535 return hwmgr->fan_ctrl_enabled ? AMD_FAN_CTRL_AUTO : AMD_FAN_CTRL_MANUAL;
4538 static int smu7_get_sclk_od(struct pp_hwmgr *hwmgr)
4540 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4541 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4542 struct smu7_single_dpm_table *golden_sclk_table =
4543 &(data->golden_dpm_table.sclk_table);
4544 int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
4545 int golden_value = golden_sclk_table->dpm_levels
4546 [golden_sclk_table->count - 1].value;
4548 value -= golden_value;
4549 value = DIV_ROUND_UP(value * 100, golden_value);
4554 static int smu7_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
4556 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4557 struct smu7_single_dpm_table *golden_sclk_table =
4558 &(data->golden_dpm_table.sclk_table);
4559 struct pp_power_state *ps;
4560 struct smu7_power_state *smu7_ps;
4565 ps = hwmgr->request_ps;
4570 smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
4572 smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].engine_clock =
4573 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
4575 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
4580 static int smu7_get_mclk_od(struct pp_hwmgr *hwmgr)
4582 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4583 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4584 struct smu7_single_dpm_table *golden_mclk_table =
4585 &(data->golden_dpm_table.mclk_table);
4586 int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
4587 int golden_value = golden_mclk_table->dpm_levels
4588 [golden_mclk_table->count - 1].value;
4590 value -= golden_value;
4591 value = DIV_ROUND_UP(value * 100, golden_value);
4596 static int smu7_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
4598 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4599 struct smu7_single_dpm_table *golden_mclk_table =
4600 &(data->golden_dpm_table.mclk_table);
4601 struct pp_power_state *ps;
4602 struct smu7_power_state *smu7_ps;
4607 ps = hwmgr->request_ps;
4612 smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
4614 smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].memory_clock =
4615 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value *
4617 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
4623 static int smu7_get_sclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks)
4625 struct phm_ppt_v1_information *table_info =
4626 (struct phm_ppt_v1_information *)hwmgr->pptable;
4627 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = NULL;
4628 struct phm_clock_voltage_dependency_table *sclk_table;
4631 if (hwmgr->pp_table_version == PP_TABLE_V1) {
4632 if (table_info == NULL || table_info->vdd_dep_on_sclk == NULL)
4634 dep_sclk_table = table_info->vdd_dep_on_sclk;
4635 for (i = 0; i < dep_sclk_table->count; i++)
4636 clocks->clock[i] = dep_sclk_table->entries[i].clk * 10;
4637 clocks->count = dep_sclk_table->count;
4638 } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
4639 sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
4640 for (i = 0; i < sclk_table->count; i++)
4641 clocks->clock[i] = sclk_table->entries[i].clk * 10;
4642 clocks->count = sclk_table->count;
4648 static uint32_t smu7_get_mem_latency(struct pp_hwmgr *hwmgr, uint32_t clk)
4650 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4652 if (clk >= MEM_FREQ_LOW_LATENCY && clk < MEM_FREQ_HIGH_LATENCY)
4653 return data->mem_latency_high;
4654 else if (clk >= MEM_FREQ_HIGH_LATENCY)
4655 return data->mem_latency_low;
4657 return MEM_LATENCY_ERR;
4660 static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks)
4662 struct phm_ppt_v1_information *table_info =
4663 (struct phm_ppt_v1_information *)hwmgr->pptable;
4664 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
4666 struct phm_clock_voltage_dependency_table *mclk_table;
4668 if (hwmgr->pp_table_version == PP_TABLE_V1) {
4669 if (table_info == NULL)
4671 dep_mclk_table = table_info->vdd_dep_on_mclk;
4672 for (i = 0; i < dep_mclk_table->count; i++) {
4673 clocks->clock[i] = dep_mclk_table->entries[i].clk * 10;
4674 clocks->latency[i] = smu7_get_mem_latency(hwmgr,
4675 dep_mclk_table->entries[i].clk);
4677 clocks->count = dep_mclk_table->count;
4678 } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
4679 mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
4680 for (i = 0; i < mclk_table->count; i++)
4681 clocks->clock[i] = mclk_table->entries[i].clk * 10;
4682 clocks->count = mclk_table->count;
4687 static int smu7_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type,
4688 struct amd_pp_clocks *clocks)
4691 case amd_pp_sys_clock:
4692 smu7_get_sclks(hwmgr, clocks);
4694 case amd_pp_mem_clock:
4695 smu7_get_mclks(hwmgr, clocks);
4704 static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
4705 uint32_t virtual_addr_low,
4706 uint32_t virtual_addr_hi,
4707 uint32_t mc_addr_low,
4708 uint32_t mc_addr_hi,
4711 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4713 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4714 data->soft_regs_start +
4715 smum_get_offsetof(hwmgr,
4716 SMU_SoftRegisters, DRAM_LOG_ADDR_H),
4719 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4720 data->soft_regs_start +
4721 smum_get_offsetof(hwmgr,
4722 SMU_SoftRegisters, DRAM_LOG_ADDR_L),
4725 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4726 data->soft_regs_start +
4727 smum_get_offsetof(hwmgr,
4728 SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_H),
4731 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4732 data->soft_regs_start +
4733 smum_get_offsetof(hwmgr,
4734 SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_L),
4737 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4738 data->soft_regs_start +
4739 smum_get_offsetof(hwmgr,
4740 SMU_SoftRegisters, DRAM_LOG_BUFF_SIZE),
4745 static int smu7_get_max_high_clocks(struct pp_hwmgr *hwmgr,
4746 struct amd_pp_simple_clock_info *clocks)
4748 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4749 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4750 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4755 clocks->memory_max_clock = mclk_table->count > 1 ?
4756 mclk_table->dpm_levels[mclk_table->count-1].value :
4757 mclk_table->dpm_levels[0].value;
4758 clocks->engine_max_clock = sclk_table->count > 1 ?
4759 sclk_table->dpm_levels[sclk_table->count-1].value :
4760 sclk_table->dpm_levels[0].value;
4764 static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
4765 struct PP_TemperatureRange *thermal_data)
4767 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4768 struct phm_ppt_v1_information *table_info =
4769 (struct phm_ppt_v1_information *)hwmgr->pptable;
4771 memcpy(thermal_data, &SMU7ThermalPolicy[0], sizeof(struct PP_TemperatureRange));
4773 if (hwmgr->pp_table_version == PP_TABLE_V1)
4774 thermal_data->max = table_info->cac_dtp_table->usSoftwareShutdownTemp *
4775 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4776 else if (hwmgr->pp_table_version == PP_TABLE_V0)
4777 thermal_data->max = data->thermal_temp_setting.temperature_shutdown *
4778 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4783 static bool smu7_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
4784 enum PP_OD_DPM_TABLE_COMMAND type,
4788 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4790 if (voltage < data->odn_dpm_table.min_vddc || voltage > data->odn_dpm_table.max_vddc) {
4791 pr_info("OD voltage is out of range [%d - %d] mV\n",
4792 data->odn_dpm_table.min_vddc,
4793 data->odn_dpm_table.max_vddc);
4797 if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
4798 if (data->golden_dpm_table.sclk_table.dpm_levels[0].value > clk ||
4799 hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) {
4800 pr_info("OD engine clock is out of range [%d - %d] MHz\n",
4801 data->golden_dpm_table.sclk_table.dpm_levels[0].value/100,
4802 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
4805 } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
4806 if (data->golden_dpm_table.mclk_table.dpm_levels[0].value > clk ||
4807 hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) {
4808 pr_info("OD memory clock is out of range [%d - %d] MHz\n",
4809 data->golden_dpm_table.mclk_table.dpm_levels[0].value/100,
4810 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
4820 static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
4821 enum PP_OD_DPM_TABLE_COMMAND type,
4822 long *input, uint32_t size)
4825 struct phm_odn_clock_levels *podn_dpm_table_in_backend = NULL;
4826 struct smu7_odn_clock_voltage_dependency_table *podn_vdd_dep_in_backend = NULL;
4827 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4831 uint32_t input_level;
4833 PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
4836 if (!hwmgr->od_enabled) {
4837 pr_info("OverDrive feature not enabled\n");
4841 if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) {
4842 podn_dpm_table_in_backend = &data->odn_dpm_table.odn_core_clock_dpm_levels;
4843 podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_sclk;
4844 PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
4845 "Failed to get ODN SCLK and Voltage tables",
4847 } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) {
4848 podn_dpm_table_in_backend = &data->odn_dpm_table.odn_memory_clock_dpm_levels;
4849 podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_mclk;
4851 PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
4852 "Failed to get ODN MCLK and Voltage tables",
4854 } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) {
4855 smu7_odn_initial_default_setting(hwmgr);
4857 } else if (PP_OD_COMMIT_DPM_TABLE == type) {
4858 smu7_check_dpm_table_updated(hwmgr);
4864 for (i = 0; i < size; i += 3) {
4865 if (i + 3 > size || input[i] >= podn_dpm_table_in_backend->num_of_pl) {
4866 pr_info("invalid clock voltage input \n");
4869 input_level = input[i];
4870 input_clk = input[i+1] * 100;
4871 input_vol = input[i+2];
4873 if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
4874 podn_dpm_table_in_backend->entries[input_level].clock = input_clk;
4875 podn_vdd_dep_in_backend->entries[input_level].clk = input_clk;
4876 podn_dpm_table_in_backend->entries[input_level].vddc = input_vol;
4877 podn_vdd_dep_in_backend->entries[input_level].vddc = input_vol;
4878 podn_vdd_dep_in_backend->entries[input_level].vddgfx = input_vol;
4887 static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
4889 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4890 uint32_t i, size = 0;
4893 static const char *profile_name[7] = {"BOOTUP_DEFAULT",
4901 static const char *title[8] = {"NUM",
4905 "SCLK_ACTIVE_LEVEL",
4908 "MCLK_ACTIVE_LEVEL"};
4913 size += sprintf(buf + size, "%s %16s %16s %16s %16s %16s %16s %16s\n",
4914 title[0], title[1], title[2], title[3],
4915 title[4], title[5], title[6], title[7]);
4917 len = sizeof(smu7_profiling) / sizeof(struct profile_mode_setting);
4919 for (i = 0; i < len; i++) {
4920 if (i == hwmgr->power_profile_mode) {
4921 size += sprintf(buf + size, "%3d %14s %s: %8d %16d %16d %16d %16d %16d\n",
4922 i, profile_name[i], "*",
4923 data->current_profile_setting.sclk_up_hyst,
4924 data->current_profile_setting.sclk_down_hyst,
4925 data->current_profile_setting.sclk_activity,
4926 data->current_profile_setting.mclk_up_hyst,
4927 data->current_profile_setting.mclk_down_hyst,
4928 data->current_profile_setting.mclk_activity);
4931 if (smu7_profiling[i].bupdate_sclk)
4932 size += sprintf(buf + size, "%3d %16s: %8d %16d %16d ",
4933 i, profile_name[i], smu7_profiling[i].sclk_up_hyst,
4934 smu7_profiling[i].sclk_down_hyst,
4935 smu7_profiling[i].sclk_activity);
4937 size += sprintf(buf + size, "%3d %16s: %8s %16s %16s ",
4938 i, profile_name[i], "-", "-", "-");
4940 if (smu7_profiling[i].bupdate_mclk)
4941 size += sprintf(buf + size, "%16d %16d %16d\n",
4942 smu7_profiling[i].mclk_up_hyst,
4943 smu7_profiling[i].mclk_down_hyst,
4944 smu7_profiling[i].mclk_activity);
4946 size += sprintf(buf + size, "%16s %16s %16s\n",
4953 static void smu7_patch_compute_profile_mode(struct pp_hwmgr *hwmgr,
4954 enum PP_SMC_POWER_PROFILE requst)
4956 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4957 uint32_t tmp, level;
4959 if (requst == PP_SMC_POWER_PROFILE_COMPUTE) {
4960 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4962 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
4966 smu7_force_clock_level(hwmgr, PP_SCLK, 3 << (level-1));
4968 } else if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE) {
4969 smu7_force_clock_level(hwmgr, PP_SCLK, data->dpm_level_enable_mask.sclk_dpm_enable_mask);
4973 static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
4975 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4976 struct profile_mode_setting tmp;
4977 enum PP_SMC_POWER_PROFILE mode;
4984 case PP_SMC_POWER_PROFILE_CUSTOM:
4988 tmp.bupdate_sclk = input[0];
4989 tmp.sclk_up_hyst = input[1];
4990 tmp.sclk_down_hyst = input[2];
4991 tmp.sclk_activity = input[3];
4992 tmp.bupdate_mclk = input[4];
4993 tmp.mclk_up_hyst = input[5];
4994 tmp.mclk_down_hyst = input[6];
4995 tmp.mclk_activity = input[7];
4996 if (!smum_update_dpm_settings(hwmgr, &tmp)) {
4997 memcpy(&data->current_profile_setting, &tmp, sizeof(struct profile_mode_setting));
4998 hwmgr->power_profile_mode = mode;
5001 case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
5002 case PP_SMC_POWER_PROFILE_POWERSAVING:
5003 case PP_SMC_POWER_PROFILE_VIDEO:
5004 case PP_SMC_POWER_PROFILE_VR:
5005 case PP_SMC_POWER_PROFILE_COMPUTE:
5006 if (mode == hwmgr->power_profile_mode)
5009 memcpy(&tmp, &smu7_profiling[mode], sizeof(struct profile_mode_setting));
5010 if (!smum_update_dpm_settings(hwmgr, &tmp)) {
5011 if (tmp.bupdate_sclk) {
5012 data->current_profile_setting.bupdate_sclk = tmp.bupdate_sclk;
5013 data->current_profile_setting.sclk_up_hyst = tmp.sclk_up_hyst;
5014 data->current_profile_setting.sclk_down_hyst = tmp.sclk_down_hyst;
5015 data->current_profile_setting.sclk_activity = tmp.sclk_activity;
5017 if (tmp.bupdate_mclk) {
5018 data->current_profile_setting.bupdate_mclk = tmp.bupdate_mclk;
5019 data->current_profile_setting.mclk_up_hyst = tmp.mclk_up_hyst;
5020 data->current_profile_setting.mclk_down_hyst = tmp.mclk_down_hyst;
5021 data->current_profile_setting.mclk_activity = tmp.mclk_activity;
5023 smu7_patch_compute_profile_mode(hwmgr, mode);
5024 hwmgr->power_profile_mode = mode;
5034 static int smu7_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
5035 PHM_PerformanceLevelDesignation designation, uint32_t index,
5036 PHM_PerformanceLevel *level)
5038 const struct smu7_power_state *ps;
5039 struct smu7_hwmgr *data;
5042 if (level == NULL || hwmgr == NULL || state == NULL)
5045 data = hwmgr->backend;
5046 ps = cast_const_phw_smu7_power_state(state);
5048 i = index > ps->performance_level_count - 1 ?
5049 ps->performance_level_count - 1 : index;
5051 level->coreClock = ps->performance_levels[i].engine_clock;
5052 level->memory_clock = ps->performance_levels[i].memory_clock;
5057 static int smu7_power_off_asic(struct pp_hwmgr *hwmgr)
5061 result = smu7_disable_dpm_tasks(hwmgr);
5062 PP_ASSERT_WITH_CODE((0 == result),
5063 "[disable_dpm_tasks] Failed to disable DPM!",
5069 static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
5070 .backend_init = &smu7_hwmgr_backend_init,
5071 .backend_fini = &smu7_hwmgr_backend_fini,
5072 .asic_setup = &smu7_setup_asic_task,
5073 .dynamic_state_management_enable = &smu7_enable_dpm_tasks,
5074 .apply_state_adjust_rules = smu7_apply_state_adjust_rules,
5075 .force_dpm_level = &smu7_force_dpm_level,
5076 .power_state_set = smu7_set_power_state_tasks,
5077 .get_power_state_size = smu7_get_power_state_size,
5078 .get_mclk = smu7_dpm_get_mclk,
5079 .get_sclk = smu7_dpm_get_sclk,
5080 .patch_boot_state = smu7_dpm_patch_boot_state,
5081 .get_pp_table_entry = smu7_get_pp_table_entry,
5082 .get_num_of_pp_table_entries = smu7_get_number_of_powerplay_table_entries,
5083 .powerdown_uvd = smu7_powerdown_uvd,
5084 .powergate_uvd = smu7_powergate_uvd,
5085 .powergate_vce = smu7_powergate_vce,
5086 .disable_clock_power_gating = smu7_disable_clock_power_gating,
5087 .update_clock_gatings = smu7_update_clock_gatings,
5088 .notify_smc_display_config_after_ps_adjustment = smu7_notify_smc_display_config_after_ps_adjustment,
5089 .display_config_changed = smu7_display_configuration_changed_task,
5090 .set_max_fan_pwm_output = smu7_set_max_fan_pwm_output,
5091 .set_max_fan_rpm_output = smu7_set_max_fan_rpm_output,
5092 .stop_thermal_controller = smu7_thermal_stop_thermal_controller,
5093 .get_fan_speed_info = smu7_fan_ctrl_get_fan_speed_info,
5094 .get_fan_speed_percent = smu7_fan_ctrl_get_fan_speed_percent,
5095 .set_fan_speed_percent = smu7_fan_ctrl_set_fan_speed_percent,
5096 .reset_fan_speed_to_default = smu7_fan_ctrl_reset_fan_speed_to_default,
5097 .get_fan_speed_rpm = smu7_fan_ctrl_get_fan_speed_rpm,
5098 .set_fan_speed_rpm = smu7_fan_ctrl_set_fan_speed_rpm,
5099 .uninitialize_thermal_controller = smu7_thermal_ctrl_uninitialize_thermal_controller,
5100 .register_irq_handlers = smu7_register_irq_handlers,
5101 .check_smc_update_required_for_display_configuration = smu7_check_smc_update_required_for_display_configuration,
5102 .check_states_equal = smu7_check_states_equal,
5103 .set_fan_control_mode = smu7_set_fan_control_mode,
5104 .get_fan_control_mode = smu7_get_fan_control_mode,
5105 .force_clock_level = smu7_force_clock_level,
5106 .print_clock_levels = smu7_print_clock_levels,
5107 .powergate_gfx = smu7_powergate_gfx,
5108 .get_sclk_od = smu7_get_sclk_od,
5109 .set_sclk_od = smu7_set_sclk_od,
5110 .get_mclk_od = smu7_get_mclk_od,
5111 .set_mclk_od = smu7_set_mclk_od,
5112 .get_clock_by_type = smu7_get_clock_by_type,
5113 .read_sensor = smu7_read_sensor,
5114 .dynamic_state_management_disable = smu7_disable_dpm_tasks,
5115 .avfs_control = smu7_avfs_control,
5116 .disable_smc_firmware_ctf = smu7_thermal_disable_alert,
5117 .start_thermal_controller = smu7_start_thermal_controller,
5118 .notify_cac_buffer_info = smu7_notify_cac_buffer_info,
5119 .get_max_high_clocks = smu7_get_max_high_clocks,
5120 .get_thermal_temperature_range = smu7_get_thermal_temperature_range,
5121 .odn_edit_dpm_table = smu7_odn_edit_dpm_table,
5122 .set_power_limit = smu7_set_power_limit,
5123 .get_power_profile_mode = smu7_get_power_profile_mode,
5124 .set_power_profile_mode = smu7_set_power_profile_mode,
5125 .get_performance_level = smu7_get_performance_level,
5126 .power_off_asic = smu7_power_off_asic,
5129 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
5130 uint32_t clock_insr)
5134 uint32_t min = max(clock_insr, (uint32_t)SMU7_MINIMUM_ENGINE_CLOCK);
5136 PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0);
5137 for (i = SMU7_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
5140 if (temp >= min || i == 0)
5146 int smu7_init_function_pointers(struct pp_hwmgr *hwmgr)
5150 hwmgr->hwmgr_func = &smu7_hwmgr_funcs;
5151 if (hwmgr->pp_table_version == PP_TABLE_V0)
5152 hwmgr->pptable_func = &pptable_funcs;
5153 else if (hwmgr->pp_table_version == PP_TABLE_V1)
5154 hwmgr->pptable_func = &pptable_v1_0_funcs;