drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "pp_debug.h"
  24 #include <linux/types.h>
  25 #include <linux/kernel.h>
  26 #include <linux/slab.h>
  27 #include "atom-types.h"
  28 #include "atombios.h"
  29 #include "processpptables.h"
  30 #include "cgs_common.h"
  31 #include "smumgr.h"
  32 #include "hwmgr.h"
  33 #include "hardwaremanager.h"
  34 #include "rv_ppsmc.h"
  35 #include "rv_hwmgr.h"
  36 #include "power_state.h"
  37 #include "rv_smumgr.h"
  38 #include "pp_soc15.h"
  39
  40 #define RAVEN_MAX_DEEPSLEEP_DIVIDER_ID     5
  41 #define RAVEN_MINIMUM_ENGINE_CLOCK         800   //8Mhz, the low boundary of engine clock allowed on this chip
  42 #define SCLK_MIN_DIV_INTV_SHIFT         12
  43 #define RAVEN_DISPCLK_BYPASS_THRESHOLD     10000 //100mhz
  44 #define SMC_RAM_END                     0x40000
  45
  46 static const unsigned long PhwRaven_Magic = (unsigned long) PHM_Rv_Magic;
  47 int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
  48                 struct pp_display_clock_request *clock_req);
  49
  50 struct phm_vq_budgeting_record rv_vqtable[] = {
  51         /* _TBD
  52          * CUs, SSP low, SSP High, Min Sclk Low, Min Sclk, High, AWD/non-AWD, DCLK, ECLK, Sustainable Sclk, Sustainable CUs */
  53         { 8, 0, 45, 0, 0, VQ_DisplayConfig_NoneAWD, 80000, 120000, 4, 0 },
  54 };
  55
  56 static struct rv_power_state *cast_rv_ps(struct pp_hw_power_state *hw_ps)
  57 {
  58         if (PhwRaven_Magic != hw_ps->magic)
  59                 return NULL;
  60
  61         return (struct rv_power_state *)hw_ps;
  62 }
  63
  64 static const struct rv_power_state *cast_const_rv_ps(
  65                                 const struct pp_hw_power_state *hw_ps)
  66 {
  67         if (PhwRaven_Magic != hw_ps->magic)
  68                 return NULL;
  69
  70         return (struct rv_power_state *)hw_ps;
  71 }
  72
  73 static int rv_init_vq_budget_table(struct pp_hwmgr *hwmgr)
  74 {
  75         uint32_t table_size, i;
  76         struct phm_vq_budgeting_table *ptable;
  77         uint32_t num_entries = ARRAY_SIZE(rv_vqtable);
  78
  79         if (hwmgr->dyn_state.vq_budgeting_table != NULL)
  80                 return 0;
  81
  82         table_size = sizeof(struct phm_vq_budgeting_table) +
  83                         sizeof(struct phm_vq_budgeting_record) * (num_entries - 1);
  84
  85         ptable = kzalloc(table_size, GFP_KERNEL);
  86         if (NULL == ptable)
  87                 return -ENOMEM;
  88
  89         ptable->numEntries = (uint8_t) num_entries;
  90
  91         for (i = 0; i < ptable->numEntries; i++) {
  92                 ptable->entries[i].ulCUs = rv_vqtable[i].ulCUs;
  93                 ptable->entries[i].ulSustainableSOCPowerLimitLow = rv_vqtable[i].ulSustainableSOCPowerLimitLow;
  94                 ptable->entries[i].ulSustainableSOCPowerLimitHigh = rv_vqtable[i].ulSustainableSOCPowerLimitHigh;
  95                 ptable->entries[i].ulMinSclkLow = rv_vqtable[i].ulMinSclkLow;
  96                 ptable->entries[i].ulMinSclkHigh = rv_vqtable[i].ulMinSclkHigh;
  97                 ptable->entries[i].ucDispConfig = rv_vqtable[i].ucDispConfig;
  98                 ptable->entries[i].ulDClk = rv_vqtable[i].ulDClk;
  99                 ptable->entries[i].ulEClk = rv_vqtable[i].ulEClk;
 100                 ptable->entries[i].ulSustainableSclk = rv_vqtable[i].ulSustainableSclk;
 101                 ptable->entries[i].ulSustainableCUs = rv_vqtable[i].ulSustainableCUs;
 102         }
 103
 104         hwmgr->dyn_state.vq_budgeting_table = ptable;
 105
 106         return 0;
 107 }
 108
 109 static int rv_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
 110 {
 111         struct rv_hwmgr *rv_hwmgr = (struct rv_hwmgr *)(hwmgr->backend);
 112         struct cgs_system_info sys_info = {0};
 113         int result;
 114
 115         rv_hwmgr->ddi_power_gating_disabled = 0;
 116         rv_hwmgr->bapm_enabled = 1;
 117         rv_hwmgr->dce_slow_sclk_threshold = 30000;
 118         rv_hwmgr->disable_driver_thermal_policy = 1;
 119         rv_hwmgr->thermal_auto_throttling_treshold = 0;
 120         rv_hwmgr->is_nb_dpm_enabled = 1;
 121         rv_hwmgr->dpm_flags = 1;
 122         rv_hwmgr->disable_smu_acp_s3_handshake = 1;
 123         rv_hwmgr->disable_notify_smu_vpu_recovery = 0;
 124         rv_hwmgr->gfx_off_controled_by_driver = false;
 125
 126         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 127                                         PHM_PlatformCaps_DynamicM3Arbiter);
 128
 129         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 130                                         PHM_PlatformCaps_UVDPowerGating);
 131
 132         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 133                                         PHM_PlatformCaps_UVDDynamicPowerGating);
 134
 135         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 136                                         PHM_PlatformCaps_VCEPowerGating);
 137
 138         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 139                                         PHM_PlatformCaps_SamuPowerGating);
 140
 141         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 142                                         PHM_PlatformCaps_ACP);
 143
 144         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 145                                         PHM_PlatformCaps_SclkDeepSleep);
 146
 147         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 148                                 PHM_PlatformCaps_GFXDynamicMGPowerGating);
 149
 150         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 151                                 PHM_PlatformCaps_SclkThrottleLowNotification);
 152
 153         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 154                                 PHM_PlatformCaps_DisableVoltageIsland);
 155
 156         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 157                                         PHM_PlatformCaps_DynamicUVDState);
 158
 159         sys_info.size = sizeof(struct cgs_system_info);
 160         sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
 161         result = cgs_query_system_info(hwmgr->device, &sys_info);
 162         if (!result) {
 163                 if (sys_info.value & AMD_PG_SUPPORT_GFX_DMG)
 164                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 165                                       PHM_PlatformCaps_GFXDynamicMGPowerGating);
 166         }
 167
 168         return 0;
 169 }
 170
 171 static int rv_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
 172                         struct phm_clock_and_voltage_limits *table)
 173 {
 174         return 0;
 175 }
 176
 177 static int rv_init_dynamic_state_adjustment_rule_settings(
 178                                                         struct pp_hwmgr *hwmgr)
 179 {
 180         uint32_t table_size =
 181                 sizeof(struct phm_clock_voltage_dependency_table) +
 182                 (7 * sizeof(struct phm_clock_voltage_dependency_record));
 183
 184         struct phm_clock_voltage_dependency_table *table_clk_vlt =
 185                                         kzalloc(table_size, GFP_KERNEL);
 186
 187         if (NULL == table_clk_vlt) {
 188                 pr_err("Can not allocate memory!\n");
 189                 return -ENOMEM;
 190         }
 191
 192         table_clk_vlt->count = 8;
 193         table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
 194         table_clk_vlt->entries[0].v = 0;
 195         table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
 196         table_clk_vlt->entries[1].v = 1;
 197         table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
 198         table_clk_vlt->entries[2].v = 2;
 199         table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
 200         table_clk_vlt->entries[3].v = 3;
 201         table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
 202         table_clk_vlt->entries[4].v = 4;
 203         table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
 204         table_clk_vlt->entries[5].v = 5;
 205         table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
 206         table_clk_vlt->entries[6].v = 6;
 207         table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
 208         table_clk_vlt->entries[7].v = 7;
 209         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
 210
 211         return 0;
 212 }
 213
 214 static int rv_get_system_info_data(struct pp_hwmgr *hwmgr)
 215 {
 216         struct rv_hwmgr *rv_data = (struct rv_hwmgr *)hwmgr->backend;
 217
 218         rv_data->sys_info.htc_hyst_lmt = 5;
 219         rv_data->sys_info.htc_tmp_lmt = 203;
 220
 221         if (rv_data->thermal_auto_throttling_treshold == 0)
 222                  rv_data->thermal_auto_throttling_treshold = 203;
 223
 224         rv_construct_max_power_limits_table (hwmgr,
 225                                     &hwmgr->dyn_state.max_clock_voltage_on_ac);
 226
 227         rv_init_dynamic_state_adjustment_rule_settings(hwmgr);
 228
 229         return 0;
 230 }
 231
 232 static int rv_construct_boot_state(struct pp_hwmgr *hwmgr)
 233 {
 234         return 0;
 235 }
 236
 237 static int rv_tf_set_clock_limit(struct pp_hwmgr *hwmgr, void *input,
 238                                 void *output, void *storage, int result)
 239 {
 240         struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
 241         struct PP_Clocks clocks = {0};
 242         struct pp_display_clock_request clock_req;
 243
 244         clocks.dcefClock = hwmgr->display_config.min_dcef_set_clk;
 245         clocks.dcefClockInSR = hwmgr->display_config.min_dcef_deep_sleep_set_clk;
 246         clock_req.clock_type = amd_pp_dcf_clock;
 247         clock_req.clock_freq_in_khz = clocks.dcefClock * 10;
 248
 249         if (clocks.dcefClock == 0 && clocks.dcefClockInSR == 0)
 250                 clock_req.clock_freq_in_khz = rv_data->dcf_actual_hard_min_freq;
 251
 252         PP_ASSERT_WITH_CODE(!rv_display_clock_voltage_request(hwmgr, &clock_req),
 253                                 "Attempt to set DCF Clock Failed!", return -EINVAL);
 254
 255         if(rv_data->need_min_deep_sleep_dcefclk && 0 != clocks.dcefClockInSR)
 256                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 257                                         PPSMC_MSG_SetMinDeepSleepDcefclk,
 258                                         clocks.dcefClockInSR / 100);
 259         /*
 260         if(!rv_data->isp_tileA_power_gated || !rv_data->isp_tileB_power_gated) {
 261                 if ((hwmgr->ispArbiter.iclk != 0) && (rv_data->ISPActualHardMinFreq != (hwmgr->ispArbiter.iclk / 100) )) {
 262                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 263                                         PPSMC_MSG_SetHardMinIspclkByFreq, hwmgr->ispArbiter.iclk / 100);
 264                         rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->ISPActualHardMinFreq),
 265                 }
 266         } */
 267
 268         if (((hwmgr->uvd_arbiter.vclk_soft_min / 100) != rv_data->vclk_soft_min) ||
 269             ((hwmgr->uvd_arbiter.dclk_soft_min / 100) != rv_data->dclk_soft_min)) {
 270                 rv_data->vclk_soft_min = hwmgr->uvd_arbiter.vclk_soft_min / 100;
 271                 rv_data->dclk_soft_min = hwmgr->uvd_arbiter.dclk_soft_min / 100;
 272                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 273                         PPSMC_MSG_SetSoftMinVcn,
 274                         (rv_data->vclk_soft_min << 16) | rv_data->vclk_soft_min);
 275         }
 276
 277         if((hwmgr->gfx_arbiter.sclk_hard_min != 0) &&
 278                 ((hwmgr->gfx_arbiter.sclk_hard_min / 100) != rv_data->soc_actual_hard_min_freq)) {
 279                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 280                                         PPSMC_MSG_SetHardMinSocclkByFreq,
 281                                         hwmgr->gfx_arbiter.sclk_hard_min / 100);
 282                         rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->soc_actual_hard_min_freq);
 283         }
 284
 285         if ((hwmgr->gfx_arbiter.gfxclk != 0) &&
 286                 (rv_data->gfx_actual_soft_min_freq != (hwmgr->gfx_arbiter.gfxclk))) {
 287                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 288                                         PPSMC_MSG_SetMinVideoGfxclkFreq,
 289                                         hwmgr->gfx_arbiter.gfxclk / 100);
 290                 rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->gfx_actual_soft_min_freq);
 291         }
 292
 293         if ((hwmgr->gfx_arbiter.fclk != 0) &&
 294                 (rv_data->fabric_actual_soft_min_freq != (hwmgr->gfx_arbiter.fclk / 100))) {
 295                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 296                                         PPSMC_MSG_SetMinVideoFclkFreq,
 297                                         hwmgr->gfx_arbiter.fclk / 100);
 298                 rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->fabric_actual_soft_min_freq);
 299         }
 300
 301         return 0;
 302 }
 303
 304 static int rv_tf_set_num_active_display(struct pp_hwmgr *hwmgr, void *input,
 305                                 void *output, void *storage, int result)
 306 {
 307         uint32_t  num_of_active_displays = 0;
 308         struct cgs_display_info info = {0};
 309
 310         cgs_get_active_displays_info(hwmgr->device, &info);
 311         num_of_active_displays = info.display_count;
 312
 313         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 314                                 PPSMC_MSG_SetDisplayCount,
 315                                 num_of_active_displays);
 316         return 0;
 317 }
 318
 319 static const struct phm_master_table_item rv_set_power_state_list[] = {
 320         { NULL, rv_tf_set_clock_limit },
 321         { NULL, rv_tf_set_num_active_display },
 322         { }
 323 };
 324
 325 static const struct phm_master_table_header rv_set_power_state_master = {
 326         0,
 327         PHM_MasterTableFlag_None,
 328         rv_set_power_state_list
 329 };
 330
 331 static int rv_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input,
 332                                 void *output, void *storage, int result)
 333 {
 334         struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
 335
 336         rv_data->vcn_power_gated = true;
 337         rv_data->isp_tileA_power_gated = true;
 338         rv_data->isp_tileB_power_gated = true;
 339
 340         return 0;
 341 }
 342
 343 static const struct phm_master_table_item rv_setup_asic_list[] = {
 344         { .tableFunction = rv_tf_init_power_gate_state },
 345         { }
 346 };
 347
 348 static const struct phm_master_table_header rv_setup_asic_master = {
 349         0,
 350         PHM_MasterTableFlag_None,
 351         rv_setup_asic_list
 352 };
 353
 354 static int rv_tf_reset_cc6_data(struct pp_hwmgr *hwmgr,
 355                                         void *input, void *output,
 356                                         void *storage, int result)
 357 {
 358         struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
 359
 360         rv_data->separation_time = 0;
 361         rv_data->cc6_disable = false;
 362         rv_data->pstate_disable = false;
 363         rv_data->cc6_setting_changed = false;
 364
 365         return 0;
 366 }
 367
 368 static const struct phm_master_table_item rv_power_down_asic_list[] = {
 369         { .tableFunction = rv_tf_reset_cc6_data },
 370         { }
 371 };
 372
 373 static const struct phm_master_table_header rv_power_down_asic_master = {
 374         0,
 375         PHM_MasterTableFlag_None,
 376         rv_power_down_asic_list
 377 };
 378
 379
 380 static int rv_tf_disable_gfx_off(struct pp_hwmgr *hwmgr,
 381                                                 void *input, void *output,
 382                                                 void *storage, int result)
 383 {
 384         struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
 385
 386         if (rv_data->gfx_off_controled_by_driver)
 387                 smum_send_msg_to_smc(hwmgr->smumgr,
 388                                                 PPSMC_MSG_DisableGfxOff);
 389
 390         return 0;
 391 }
 392
 393 static const struct phm_master_table_item rv_disable_dpm_list[] = {
 394         {NULL, rv_tf_disable_gfx_off},
 395         { },
 396 };
 397
 398
 399 static const struct phm_master_table_header rv_disable_dpm_master = {
 400         0,
 401         PHM_MasterTableFlag_None,
 402         rv_disable_dpm_list
 403 };
 404
 405 static int rv_tf_enable_gfx_off(struct pp_hwmgr *hwmgr,
 406                                                 void *input, void *output,
 407                                                 void *storage, int result)
 408 {
 409         struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
 410
 411         if (rv_data->gfx_off_controled_by_driver)
 412                 smum_send_msg_to_smc(hwmgr->smumgr,
 413                                                 PPSMC_MSG_EnableGfxOff);
 414
 415         return 0;
 416 }
 417
 418 static const struct phm_master_table_item rv_enable_dpm_list[] = {
 419         {NULL, rv_tf_enable_gfx_off},
 420         { },
 421 };
 422
 423 static const struct phm_master_table_header rv_enable_dpm_master = {
 424         0,
 425         PHM_MasterTableFlag_None,
 426         rv_enable_dpm_list
 427 };
 428
 429 static int rv_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
 430                                 struct pp_power_state  *prequest_ps,
 431                         const struct pp_power_state *pcurrent_ps)
 432 {
 433         return 0;
 434 }
 435
 436 /* temporary hardcoded clock voltage breakdown tables */
 437 DpmClock_t VddDcfClk[]= {
 438         { 300, 2600},
 439         { 600, 3200},
 440         { 600, 3600},
 441 };
 442
 443 DpmClock_t VddSocClk[]= {
 444         { 478, 2600},
 445         { 722, 3200},
 446         { 722, 3600},
 447 };
 448
 449 DpmClock_t VddFClk[]= {
 450         { 400, 2600},
 451         {1200, 3200},
 452         {1200, 3600},
 453 };
 454
 455 DpmClock_t VddDispClk[]= {
 456         { 435, 2600},
 457         { 661, 3200},
 458         {1086, 3600},
 459 };
 460
 461 DpmClock_t VddDppClk[]= {
 462         { 435, 2600},
 463         { 661, 3200},
 464         { 661, 3600},
 465 };
 466
 467 DpmClock_t VddPhyClk[]= {
 468         { 540, 2600},
 469         { 810, 3200},
 470         { 810, 3600},
 471 };
 472
 473 static int rv_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
 474                         struct rv_voltage_dependency_table **pptable,
 475                         uint32_t num_entry, DpmClock_t *pclk_dependency_table)
 476 {
 477         uint32_t table_size, i;
 478         struct rv_voltage_dependency_table *ptable;
 479
 480         table_size = sizeof(uint32_t) + sizeof(struct rv_voltage_dependency_table) * num_entry;
 481         ptable = kzalloc(table_size, GFP_KERNEL);
 482
 483         if (NULL == ptable)
 484                 return -ENOMEM;
 485
 486         ptable->count = num_entry;
 487
 488         for (i = 0; i < ptable->count; i++) {
 489                 ptable->entries[i].clk         = pclk_dependency_table->Freq * 100;
 490                 ptable->entries[i].vol         = pclk_dependency_table->Vol;
 491                 pclk_dependency_table++;
 492         }
 493
 494         *pptable = ptable;
 495
 496         return 0;
 497 }
 498
 499
 500 static int rv_populate_clock_table(struct pp_hwmgr *hwmgr)
 501 {
 502         int result;
 503
 504         struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
 505         DpmClocks_t  *table = &(rv_data->clock_table);
 506         struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
 507
 508         result = rv_copy_table_from_smc(hwmgr->smumgr, (uint8_t *)table, CLOCKTABLE);
 509
 510         PP_ASSERT_WITH_CODE((0 == result),
 511                         "Attempt to copy clock table from smc failed",
 512                         return result);
 513
 514         if (0 == result && table->DcefClocks[0].Freq != 0) {
 515                 rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
 516                                                 NUM_DCEFCLK_DPM_LEVELS,
 517                                                 &rv_data->clock_table.DcefClocks[0]);
 518                 rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
 519                                                 NUM_SOCCLK_DPM_LEVELS,
 520                                                 &rv_data->clock_table.SocClocks[0]);
 521                 rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
 522                                                 NUM_FCLK_DPM_LEVELS,
 523                                                 &rv_data->clock_table.FClocks[0]);
 524                 rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_mclk,
 525                                                 NUM_MEMCLK_DPM_LEVELS,
 526                                                 &rv_data->clock_table.MemClocks[0]);
 527         } else {
 528                 rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
 529                                                 ARRAY_SIZE(VddDcfClk),
 530                                                 &VddDcfClk[0]);
 531                 rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
 532                                                 ARRAY_SIZE(VddSocClk),
 533                                                 &VddSocClk[0]);
 534                 rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
 535                                                 ARRAY_SIZE(VddFClk),
 536                                                 &VddFClk[0]);
 537         }
 538         rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dispclk,
 539                                         ARRAY_SIZE(VddDispClk),
 540                                         &VddDispClk[0]);
 541         rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dppclk,
 542                                         ARRAY_SIZE(VddDppClk), &VddDppClk[0]);
 543         rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk,
 544                                         ARRAY_SIZE(VddPhyClk), &VddPhyClk[0]);
 545
 546         return 0;
 547 }
 548
 549 static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 550 {
 551         int result = 0;
 552         struct rv_hwmgr *data;
 553
 554         data = kzalloc(sizeof(struct rv_hwmgr), GFP_KERNEL);
 555         if (data == NULL)
 556                 return -ENOMEM;
 557
 558         hwmgr->backend = data;
 559
 560         result = rv_initialize_dpm_defaults(hwmgr);
 561         if (result != 0) {
 562                 pr_err("rv_initialize_dpm_defaults failed\n");
 563                 return result;
 564         }
 565
 566         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 567                 PHM_PlatformCaps_PowerPlaySupport);
 568
 569         rv_populate_clock_table(hwmgr);
 570
 571         result = rv_get_system_info_data(hwmgr);
 572         if (result != 0) {
 573                 pr_err("rv_get_system_info_data failed\n");
 574                 return result;
 575         }
 576
 577         rv_construct_boot_state(hwmgr);
 578
 579         result = phm_construct_table(hwmgr, &rv_setup_asic_master,
 580                                 &(hwmgr->setup_asic));
 581         if (result != 0) {
 582                 pr_err("Fail to construct setup ASIC\n");
 583                 return result;
 584         }
 585
 586         result = phm_construct_table(hwmgr, &rv_power_down_asic_master,
 587                                 &(hwmgr->power_down_asic));
 588         if (result != 0) {
 589                 pr_err("Fail to construct power down ASIC\n");
 590                 return result;
 591         }
 592
 593         result = phm_construct_table(hwmgr, &rv_set_power_state_master,
 594                                 &(hwmgr->set_power_state));
 595         if (result != 0) {
 596                 pr_err("Fail to construct set_power_state\n");
 597                 return result;
 598         }
 599
 600         result = phm_construct_table(hwmgr, &rv_disable_dpm_master,
 601                                 &(hwmgr->disable_dynamic_state_management));
 602         if (result != 0) {
 603                 pr_err("Fail to disable_dynamic_state\n");
 604                 return result;
 605         }
 606         result = phm_construct_table(hwmgr, &rv_enable_dpm_master,
 607                                 &(hwmgr->enable_dynamic_state_management));
 608         if (result != 0) {
 609                 pr_err("Fail to enable_dynamic_state\n");
 610                 return result;
 611         }
 612
 613         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
 614                                                 RAVEN_MAX_HARDWARE_POWERLEVELS;
 615
 616         hwmgr->platform_descriptor.hardwarePerformanceLevels =
 617                                                 RAVEN_MAX_HARDWARE_POWERLEVELS;
 618
 619         hwmgr->platform_descriptor.vbiosInterruptId = 0;
 620
 621         hwmgr->platform_descriptor.clockStep.engineClock = 500;
 622
 623         hwmgr->platform_descriptor.clockStep.memoryClock = 500;
 624
 625         hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
 626
 627         rv_init_vq_budget_table(hwmgr);
 628
 629         return result;
 630 }
 631
 632 static int rv_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 633 {
 634         struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
 635         struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
 636
 637         phm_destroy_table(hwmgr, &(hwmgr->set_power_state));
 638         phm_destroy_table(hwmgr, &(hwmgr->enable_dynamic_state_management));
 639         phm_destroy_table(hwmgr, &(hwmgr->disable_dynamic_state_management));
 640         phm_destroy_table(hwmgr, &(hwmgr->power_down_asic));
 641         phm_destroy_table(hwmgr, &(hwmgr->setup_asic));
 642
 643         if (pinfo->vdd_dep_on_dcefclk) {
 644                 kfree(pinfo->vdd_dep_on_dcefclk);
 645                 pinfo->vdd_dep_on_dcefclk = NULL;
 646         }
 647         if (pinfo->vdd_dep_on_socclk) {
 648                 kfree(pinfo->vdd_dep_on_socclk);
 649                 pinfo->vdd_dep_on_socclk = NULL;
 650         }
 651         if (pinfo->vdd_dep_on_fclk) {
 652                 kfree(pinfo->vdd_dep_on_fclk);
 653                 pinfo->vdd_dep_on_fclk = NULL;
 654         }
 655         if (pinfo->vdd_dep_on_dispclk) {
 656                 kfree(pinfo->vdd_dep_on_dispclk);
 657                 pinfo->vdd_dep_on_dispclk = NULL;
 658         }
 659         if (pinfo->vdd_dep_on_dppclk) {
 660                 kfree(pinfo->vdd_dep_on_dppclk);
 661                 pinfo->vdd_dep_on_dppclk = NULL;
 662         }
 663         if (pinfo->vdd_dep_on_phyclk) {
 664                 kfree(pinfo->vdd_dep_on_phyclk);
 665                 pinfo->vdd_dep_on_phyclk = NULL;
 666         }
 667
 668         if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) {
 669                 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
 670                 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
 671         }
 672
 673         if (NULL != hwmgr->dyn_state.vq_budgeting_table) {
 674                 kfree(hwmgr->dyn_state.vq_budgeting_table);
 675                 hwmgr->dyn_state.vq_budgeting_table = NULL;
 676         }
 677
 678         kfree(hwmgr->backend);
 679         hwmgr->backend = NULL;
 680
 681         return 0;
 682 }
 683
 684 static int rv_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
 685                                 enum amd_dpm_forced_level level)
 686 {
 687         return 0;
 688 }
 689
 690 static int rv_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
 691 {
 692         return 0;
 693 }
 694
 695 static int rv_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
 696 {
 697         return 0;
 698 }
 699
 700 static int rv_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
 701                                         struct pp_hw_power_state *hw_ps)
 702 {
 703         return 0;
 704 }
 705
 706 static int rv_dpm_get_pp_table_entry_callback(
 707                                                      struct pp_hwmgr *hwmgr,
 708                                            struct pp_hw_power_state *hw_ps,
 709                                                           unsigned int index,
 710                                                      const void *clock_info)
 711 {
 712         struct rv_power_state *rv_ps = cast_rv_ps(hw_ps);
 713
 714         const ATOM_PPLIB_CZ_CLOCK_INFO *rv_clock_info = clock_info;
 715
 716         struct phm_clock_voltage_dependency_table *table =
 717                                     hwmgr->dyn_state.vddc_dependency_on_sclk;
 718         uint8_t clock_info_index = rv_clock_info->index;
 719
 720         if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1))
 721                 clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1);
 722
 723         rv_ps->levels[index].engine_clock = table->entries[clock_info_index].clk;
 724         rv_ps->levels[index].vddc_index = (uint8_t)table->entries[clock_info_index].v;
 725
 726         rv_ps->level = index + 1;
 727
 728         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
 729                 rv_ps->levels[index].ds_divider_index = 5;
 730                 rv_ps->levels[index].ss_divider_index = 5;
 731         }
 732
 733         return 0;
 734 }
 735
 736 static int rv_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
 737 {
 738         int result;
 739         unsigned long ret = 0;
 740
 741         result = pp_tables_get_num_of_entries(hwmgr, &ret);
 742
 743         return result ? 0 : ret;
 744 }
 745
 746 static int rv_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
 747                     unsigned long entry, struct pp_power_state *ps)
 748 {
 749         int result;
 750         struct rv_power_state *rv_ps;
 751
 752         ps->hardware.magic = PhwRaven_Magic;
 753
 754         rv_ps = cast_rv_ps(&(ps->hardware));
 755
 756         result = pp_tables_get_entry(hwmgr, entry, ps,
 757                         rv_dpm_get_pp_table_entry_callback);
 758
 759         rv_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
 760         rv_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
 761
 762         return result;
 763 }
 764
 765 static int rv_get_power_state_size(struct pp_hwmgr *hwmgr)
 766 {
 767         return sizeof(struct rv_power_state);
 768 }
 769
 770 static int rv_set_cpu_power_state(struct pp_hwmgr *hwmgr)
 771 {
 772         return 0;
 773 }
 774
 775
 776 static int rv_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
 777                         bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
 778 {
 779         return 0;
 780 }
 781
 782 static int rv_get_dal_power_level(struct pp_hwmgr *hwmgr,
 783                 struct amd_pp_simple_clock_info *info)
 784 {
 785         return -EINVAL;
 786 }
 787
 788 static int rv_force_clock_level(struct pp_hwmgr *hwmgr,
 789                 enum pp_clock_type type, uint32_t mask)
 790 {
 791         return 0;
 792 }
 793
 794 static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
 795                 enum pp_clock_type type, char *buf)
 796 {
 797         return 0;
 798 }
 799
 800 static int rv_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
 801                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
 802                                 PHM_PerformanceLevel *level)
 803 {
 804         const struct rv_power_state *ps;
 805         struct rv_hwmgr *data;
 806         uint32_t level_index;
 807         uint32_t i;
 808         uint32_t vol_dep_record_index = 0;
 809
 810         if (level == NULL || hwmgr == NULL || state == NULL)
 811                 return -EINVAL;
 812
 813         data = (struct rv_hwmgr *)(hwmgr->backend);
 814         ps = cast_const_rv_ps(state);
 815
 816         level_index = index > ps->level - 1 ? ps->level - 1 : index;
 817         level->coreClock = ps->levels[level_index].engine_clock;
 818
 819         if (designation == PHM_PerformanceLevelDesignation_PowerContainment) {
 820                 for (i = 1; i < ps->level; i++) {
 821                         if (ps->levels[i].engine_clock > data->dce_slow_sclk_threshold) {
 822                                 level->coreClock = ps->levels[i].engine_clock;
 823                                 break;
 824                         }
 825                 }
 826         }
 827
 828         if (level_index == 0) {
 829                 vol_dep_record_index = data->clock_vol_info.vdd_dep_on_fclk->count - 1;
 830                 level->memory_clock =
 831                         data->clock_vol_info.vdd_dep_on_fclk->entries[vol_dep_record_index].clk;
 832         } else
 833                 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
 834
 835         level->nonLocalMemoryFreq = 0;
 836         level->nonLocalMemoryWidth = 0;
 837
 838         return 0;
 839 }
 840
 841 static int rv_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
 842         const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
 843 {
 844         const struct rv_power_state *ps = cast_const_rv_ps(state);
 845
 846         clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index));
 847         clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1].ss_divider_index));
 848
 849         return 0;
 850 }
 851
 852 #define MEM_FREQ_LOW_LATENCY        25000
 853 #define MEM_FREQ_HIGH_LATENCY       80000
 854 #define MEM_LATENCY_HIGH            245
 855 #define MEM_LATENCY_LOW             35
 856 #define MEM_LATENCY_ERR             0xFFFF
 857
 858
 859 static uint32_t rv_get_mem_latency(struct pp_hwmgr *hwmgr,
 860                 uint32_t clock)
 861 {
 862         if (clock >= MEM_FREQ_LOW_LATENCY &&
 863                         clock < MEM_FREQ_HIGH_LATENCY)
 864                 return MEM_LATENCY_HIGH;
 865         else if (clock >= MEM_FREQ_HIGH_LATENCY)
 866                 return MEM_LATENCY_LOW;
 867         else
 868                 return MEM_LATENCY_ERR;
 869 }
 870
 871 static int rv_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
 872                 enum amd_pp_clock_type type,
 873                 struct pp_clock_levels_with_latency *clocks)
 874 {
 875         uint32_t i;
 876         struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
 877         struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
 878         struct rv_voltage_dependency_table *pclk_vol_table;
 879         bool latency_required = false;
 880
 881         if (pinfo == NULL)
 882                 return -EINVAL;
 883
 884         switch (type) {
 885         case amd_pp_mem_clock:
 886                 pclk_vol_table = pinfo->vdd_dep_on_mclk;
 887                 latency_required = true;
 888                 break;
 889         case amd_pp_f_clock:
 890                 pclk_vol_table = pinfo->vdd_dep_on_fclk;
 891                 latency_required = true;
 892                 break;
 893         case amd_pp_dcf_clock:
 894                 pclk_vol_table = pinfo->vdd_dep_on_dcefclk;
 895                 break;
 896         case amd_pp_disp_clock:
 897                 pclk_vol_table = pinfo->vdd_dep_on_dispclk;
 898                 break;
 899         case amd_pp_phy_clock:
 900                 pclk_vol_table = pinfo->vdd_dep_on_phyclk;
 901                 break;
 902         case amd_pp_dpp_clock:
 903                 pclk_vol_table = pinfo->vdd_dep_on_dppclk;
 904         default:
 905                 return -EINVAL;
 906         }
 907
 908         if (pclk_vol_table == NULL || pclk_vol_table->count == 0)
 909                 return -EINVAL;
 910
 911         clocks->num_levels = 0;
 912         for (i = 0; i < pclk_vol_table->count; i++) {
 913                 clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk;
 914                 clocks->data[i].latency_in_us = latency_required ?
 915                                                 rv_get_mem_latency(hwmgr,
 916                                                 pclk_vol_table->entries[i].clk) :
 917                                                 0;
 918                 clocks->num_levels++;
 919         }
 920
 921         return 0;
 922 }
 923
 924 static int rv_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
 925                 enum amd_pp_clock_type type,
 926                 struct pp_clock_levels_with_voltage *clocks)
 927 {
 928         uint32_t i;
 929         struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
 930         struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
 931         struct rv_voltage_dependency_table *pclk_vol_table = NULL;
 932
 933         if (pinfo == NULL)
 934                 return -EINVAL;
 935
 936         switch (type) {
 937         case amd_pp_mem_clock:
 938                 pclk_vol_table = pinfo->vdd_dep_on_mclk;
 939                 break;
 940         case amd_pp_f_clock:
 941                 pclk_vol_table = pinfo->vdd_dep_on_fclk;
 942                 break;
 943         case amd_pp_dcf_clock:
 944                 pclk_vol_table = pinfo->vdd_dep_on_dcefclk;
 945                 break;
 946         case amd_pp_soc_clock:
 947                 pclk_vol_table = pinfo->vdd_dep_on_socclk;
 948                 break;
 949         default:
 950                 return -EINVAL;
 951         }
 952
 953         if (pclk_vol_table == NULL || pclk_vol_table->count == 0)
 954                 return -EINVAL;
 955
 956         clocks->num_levels = 0;
 957         for (i = 0; i < pclk_vol_table->count; i++) {
 958                 clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk;
 959                 clocks->data[i].voltage_in_mv = pclk_vol_table->entries[i].vol;
 960                 clocks->num_levels++;
 961         }
 962
 963         return 0;
 964 }
 965
 966 int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
 967                 struct pp_display_clock_request *clock_req)
 968 {
 969         int result = 0;
 970         struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
 971         enum amd_pp_clock_type clk_type = clock_req->clock_type;
 972         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
 973         PPSMC_Msg        msg;
 974
 975         switch (clk_type) {
 976         case amd_pp_dcf_clock:
 977                 if (clk_freq == rv_data->dcf_actual_hard_min_freq)
 978                         return 0;
 979                 msg =  PPSMC_MSG_SetHardMinDcefclkByFreq;
 980                 rv_data->dcf_actual_hard_min_freq = clk_freq;
 981                 break;
 982         case amd_pp_soc_clock:
 983                  msg = PPSMC_MSG_SetHardMinSocclkByFreq;
 984                 break;
 985         case amd_pp_f_clock:
 986                 if (clk_freq == rv_data->f_actual_hard_min_freq)
 987                         return 0;
 988                 rv_data->f_actual_hard_min_freq = clk_freq;
 989                 msg = PPSMC_MSG_SetHardMinFclkByFreq;
 990                 break;
 991         default:
 992                 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
 993                 return -EINVAL;
 994         }
 995
 996         result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg,
 997                                                         clk_freq);
 998
 999         return result;
1000 }
1001
1002 static int rv_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
1003 {
1004         return -EINVAL;
1005 }
1006
1007 static int rv_thermal_get_temperature(struct pp_hwmgr *hwmgr)
1008 {
1009         uint32_t reg_offset = soc15_get_register_offset(THM_HWID, 0,
1010                         mmTHM_TCON_CUR_TMP_BASE_IDX, mmTHM_TCON_CUR_TMP);
1011         uint32_t reg_value = cgs_read_register(hwmgr->device, reg_offset);
1012         int cur_temp =
1013                 (reg_value & THM_TCON_CUR_TMP__CUR_TEMP_MASK) >> THM_TCON_CUR_TMP__CUR_TEMP__SHIFT;
1014
1015         if (cur_temp & THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK)
1016                 cur_temp = ((cur_temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1017         else
1018                 cur_temp = (cur_temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1019
1020         return cur_temp;
1021 }
1022
1023 static int rv_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1024                           void *value, int *size)
1025 {
1026         switch (idx) {
1027         case AMDGPU_PP_SENSOR_GPU_TEMP:
1028                 *((uint32_t *)value) = rv_thermal_get_temperature(hwmgr);
1029                 return 0;
1030         default:
1031                 return -EINVAL;
1032         }
1033 }
1034
1035 static const struct pp_hwmgr_func rv_hwmgr_funcs = {
1036         .backend_init = rv_hwmgr_backend_init,
1037         .backend_fini = rv_hwmgr_backend_fini,
1038         .asic_setup = NULL,
1039         .apply_state_adjust_rules = rv_apply_state_adjust_rules,
1040         .force_dpm_level = rv_dpm_force_dpm_level,
1041         .get_power_state_size = rv_get_power_state_size,
1042         .powerdown_uvd = NULL,
1043         .powergate_uvd = NULL,
1044         .powergate_vce = NULL,
1045         .get_mclk = rv_dpm_get_mclk,
1046         .get_sclk = rv_dpm_get_sclk,
1047         .patch_boot_state = rv_dpm_patch_boot_state,
1048         .get_pp_table_entry = rv_dpm_get_pp_table_entry,
1049         .get_num_of_pp_table_entries = rv_dpm_get_num_of_pp_table_entries,
1050         .set_cpu_power_state = rv_set_cpu_power_state,
1051         .store_cc6_data = rv_store_cc6_data,
1052         .force_clock_level = rv_force_clock_level,
1053         .print_clock_levels = rv_print_clock_levels,
1054         .get_dal_power_level = rv_get_dal_power_level,
1055         .get_performance_level = rv_get_performance_level,
1056         .get_current_shallow_sleep_clocks = rv_get_current_shallow_sleep_clocks,
1057         .get_clock_by_type_with_latency = rv_get_clock_by_type_with_latency,
1058         .get_clock_by_type_with_voltage = rv_get_clock_by_type_with_voltage,
1059         .get_max_high_clocks = rv_get_max_high_clocks,
1060         .read_sensor = rv_read_sensor,
1061 };
1062
1063 int rv_init_function_pointers(struct pp_hwmgr *hwmgr)
1064 {
1065         hwmgr->hwmgr_func = &rv_hwmgr_funcs;
1066         hwmgr->pptable_func = &pptable_funcs;
1067         return 0;
1068 }