drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/delay.h>
  26 #include <linux/kernel.h>
  27 #include <linux/slab.h>
  28 #include <linux/types.h>
  29 #include <linux/pci.h>
  30 #include <drm/amdgpu_drm.h>
  31 #include "power_state.h"
  32 #include "hwmgr.h"
  33 #include "ppsmc.h"
  34 #include "amd_acpi.h"
  35 #include "pp_psm.h"
  36
  37 extern const struct pp_smumgr_func ci_smu_funcs;
  38 extern const struct pp_smumgr_func smu8_smu_funcs;
  39 extern const struct pp_smumgr_func iceland_smu_funcs;
  40 extern const struct pp_smumgr_func tonga_smu_funcs;
  41 extern const struct pp_smumgr_func fiji_smu_funcs;
  42 extern const struct pp_smumgr_func polaris10_smu_funcs;
  43 extern const struct pp_smumgr_func vegam_smu_funcs;
  44 extern const struct pp_smumgr_func vega10_smu_funcs;
  45 extern const struct pp_smumgr_func vega12_smu_funcs;
  46 extern const struct pp_smumgr_func smu10_smu_funcs;
  47 extern const struct pp_smumgr_func vega20_smu_funcs;
  48
  49 extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
  50 extern int smu8_init_function_pointers(struct pp_hwmgr *hwmgr);
  51 extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
  52 extern int vega12_hwmgr_init(struct pp_hwmgr *hwmgr);
  53 extern int vega20_hwmgr_init(struct pp_hwmgr *hwmgr);
  54 extern int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
  55
  56 static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
  57 static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);
  58 static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr);
  59 static int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr);
  60 static int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr);
  61 static int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr);
  62 static int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr);
  63
  64
  65 static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
  66 {
  67         hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 2;
  68         hwmgr->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 0;
  69         hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 1;
  70         hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VR] = 3;
  71         hwmgr->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 4;
  72
  73         hwmgr->workload_setting[0] = PP_SMC_POWER_PROFILE_POWERSAVING;
  74         hwmgr->workload_setting[1] = PP_SMC_POWER_PROFILE_VIDEO;
  75         hwmgr->workload_setting[2] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
  76         hwmgr->workload_setting[3] = PP_SMC_POWER_PROFILE_VR;
  77         hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_COMPUTE;
  78 }
  79
  80 int hwmgr_early_init(struct pp_hwmgr *hwmgr)
  81 {
  82         if (!hwmgr)
  83                 return -EINVAL;
  84
  85         hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
  86         hwmgr->pp_table_version = PP_TABLE_V1;
  87         hwmgr->dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
  88         hwmgr->request_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
  89         hwmgr_init_default_caps(hwmgr);
  90         hwmgr_set_user_specify_caps(hwmgr);
  91         hwmgr->fan_ctrl_is_in_default_mode = true;
  92         hwmgr_init_workload_prority(hwmgr);
  93
  94         switch (hwmgr->chip_family) {
  95         case AMDGPU_FAMILY_CI:
  96                 hwmgr->smumgr_funcs = &ci_smu_funcs;
  97                 ci_set_asic_special_caps(hwmgr);
  98                 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
  99                                          PP_ENABLE_GFX_CG_THRU_SMU |
 100                                          PP_GFXOFF_MASK);
 101                 hwmgr->pp_table_version = PP_TABLE_V0;
 102                 hwmgr->od_enabled = false;
 103                 smu7_init_function_pointers(hwmgr);
 104                 break;
 105         case AMDGPU_FAMILY_CZ:
 106                 hwmgr->od_enabled = false;
 107                 hwmgr->smumgr_funcs = &smu8_smu_funcs;
 108                 hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
 109                 smu8_init_function_pointers(hwmgr);
 110                 break;
 111         case AMDGPU_FAMILY_VI:
 112                 hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
 113                 switch (hwmgr->chip_id) {
 114                 case CHIP_TOPAZ:
 115                         hwmgr->smumgr_funcs = &iceland_smu_funcs;
 116                         topaz_set_asic_special_caps(hwmgr);
 117                         hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
 118                                                 PP_ENABLE_GFX_CG_THRU_SMU);
 119                         hwmgr->pp_table_version = PP_TABLE_V0;
 120                         hwmgr->od_enabled = false;
 121                         break;
 122                 case CHIP_TONGA:
 123                         hwmgr->smumgr_funcs = &tonga_smu_funcs;
 124                         tonga_set_asic_special_caps(hwmgr);
 125                         hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK;
 126                         break;
 127                 case CHIP_FIJI:
 128                         hwmgr->smumgr_funcs = &fiji_smu_funcs;
 129                         fiji_set_asic_special_caps(hwmgr);
 130                         hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
 131                                                 PP_ENABLE_GFX_CG_THRU_SMU);
 132                         break;
 133                 case CHIP_POLARIS11:
 134                 case CHIP_POLARIS10:
 135                 case CHIP_POLARIS12:
 136                         hwmgr->smumgr_funcs = &polaris10_smu_funcs;
 137                         polaris_set_asic_special_caps(hwmgr);
 138                         hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
 139                         break;
 140                 case CHIP_VEGAM:
 141                         hwmgr->smumgr_funcs = &vegam_smu_funcs;
 142                         polaris_set_asic_special_caps(hwmgr);
 143                         hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
 144                         break;
 145                 default:
 146                         return -EINVAL;
 147                 }
 148                 smu7_init_function_pointers(hwmgr);
 149                 break;
 150         case AMDGPU_FAMILY_AI:
 151                 switch (hwmgr->chip_id) {
 152                 case CHIP_VEGA10:
 153                         hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
 154                         hwmgr->smumgr_funcs = &vega10_smu_funcs;
 155                         vega10_hwmgr_init(hwmgr);
 156                         break;
 157                 case CHIP_VEGA12:
 158                         hwmgr->smumgr_funcs = &vega12_smu_funcs;
 159                         vega12_hwmgr_init(hwmgr);
 160                         break;
 161                 case CHIP_VEGA20:
 162                         hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
 163                         hwmgr->smumgr_funcs = &vega20_smu_funcs;
 164                         vega20_hwmgr_init(hwmgr);
 165                         break;
 166                 default:
 167                         return -EINVAL;
 168                 }
 169                 break;
 170         case AMDGPU_FAMILY_RV:
 171                 switch (hwmgr->chip_id) {
 172                 case CHIP_RAVEN:
 173                         hwmgr->od_enabled = false;
 174                         hwmgr->smumgr_funcs = &smu10_smu_funcs;
 175                         smu10_init_function_pointers(hwmgr);
 176                         break;
 177                 default:
 178                         return -EINVAL;
 179                 }
 180                 break;
 181         default:
 182                 return -EINVAL;
 183         }
 184
 185         return 0;
 186 }
 187
 188 int hwmgr_sw_init(struct pp_hwmgr *hwmgr)
 189 {
 190         if (!hwmgr|| !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->smu_init)
 191                 return -EINVAL;
 192
 193         phm_register_irq_handlers(hwmgr);
 194
 195         return hwmgr->smumgr_funcs->smu_init(hwmgr);
 196 }
 197
 198
 199 int hwmgr_sw_fini(struct pp_hwmgr *hwmgr)
 200 {
 201         if (hwmgr && hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->smu_fini)
 202                 hwmgr->smumgr_funcs->smu_fini(hwmgr);
 203
 204         return 0;
 205 }
 206
 207 int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
 208 {
 209         int ret = 0;
 210
 211         if (!hwmgr->pm_en)
 212                 return 0;
 213
 214         if (!hwmgr->pptable_func ||
 215             !hwmgr->pptable_func->pptable_init ||
 216             !hwmgr->hwmgr_func->backend_init) {
 217                 hwmgr->pm_en = false;
 218                 pr_info("dpm not supported \n");
 219                 return 0;
 220         }
 221
 222         ret = hwmgr->pptable_func->pptable_init(hwmgr);
 223         if (ret)
 224                 goto err;
 225
 226         ((struct amdgpu_device *)hwmgr->adev)->pm.no_fan =
 227                                 hwmgr->thermal_controller.fanInfo.bNoFan;
 228
 229         ret = hwmgr->hwmgr_func->backend_init(hwmgr);
 230         if (ret)
 231                 goto err1;
 232  /* make sure dc limits are valid */
 233         if ((hwmgr->dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
 234                         (hwmgr->dyn_state.max_clock_voltage_on_dc.mclk == 0))
 235                         hwmgr->dyn_state.max_clock_voltage_on_dc =
 236                                         hwmgr->dyn_state.max_clock_voltage_on_ac;
 237
 238         ret = psm_init_power_state_table(hwmgr);
 239         if (ret)
 240                 goto err2;
 241
 242         ret = phm_setup_asic(hwmgr);
 243         if (ret)
 244                 goto err2;
 245
 246         ret = phm_enable_dynamic_state_management(hwmgr);
 247         if (ret)
 248                 goto err2;
 249         ret = phm_start_thermal_controller(hwmgr);
 250         ret |= psm_set_performance_states(hwmgr);
 251         if (ret)
 252                 goto err2;
 253
 254         ((struct amdgpu_device *)hwmgr->adev)->pm.dpm_enabled = true;
 255
 256         return 0;
 257 err2:
 258         if (hwmgr->hwmgr_func->backend_fini)
 259                 hwmgr->hwmgr_func->backend_fini(hwmgr);
 260 err1:
 261         if (hwmgr->pptable_func->pptable_fini)
 262                 hwmgr->pptable_func->pptable_fini(hwmgr);
 263 err:
 264         return ret;
 265 }
 266
 267 int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
 268 {
 269         if (!hwmgr || !hwmgr->pm_en)
 270                 return 0;
 271
 272         phm_stop_thermal_controller(hwmgr);
 273         psm_set_boot_states(hwmgr);
 274         psm_adjust_power_state_dynamic(hwmgr, false, NULL);
 275         phm_disable_dynamic_state_management(hwmgr);
 276         phm_disable_clock_power_gatings(hwmgr);
 277
 278         if (hwmgr->hwmgr_func->backend_fini)
 279                 hwmgr->hwmgr_func->backend_fini(hwmgr);
 280         if (hwmgr->pptable_func->pptable_fini)
 281                 hwmgr->pptable_func->pptable_fini(hwmgr);
 282         return psm_fini_power_state_table(hwmgr);
 283 }
 284
 285 int hwmgr_suspend(struct pp_hwmgr *hwmgr)
 286 {
 287         int ret = 0;
 288
 289         if (!hwmgr || !hwmgr->pm_en)
 290                 return 0;
 291
 292         phm_disable_smc_firmware_ctf(hwmgr);
 293         ret = psm_set_boot_states(hwmgr);
 294         if (ret)
 295                 return ret;
 296         ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
 297         if (ret)
 298                 return ret;
 299         ret = phm_power_down_asic(hwmgr);
 300
 301         return ret;
 302 }
 303
 304 int hwmgr_resume(struct pp_hwmgr *hwmgr)
 305 {
 306         int ret = 0;
 307
 308         if (!hwmgr)
 309                 return -EINVAL;
 310
 311         if (!hwmgr->pm_en)
 312                 return 0;
 313
 314         ret = phm_setup_asic(hwmgr);
 315         if (ret)
 316                 return ret;
 317
 318         ret = phm_enable_dynamic_state_management(hwmgr);
 319         if (ret)
 320                 return ret;
 321         ret = phm_start_thermal_controller(hwmgr);
 322         ret |= psm_set_performance_states(hwmgr);
 323         if (ret)
 324                 return ret;
 325
 326         ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
 327
 328         return ret;
 329 }
 330
 331 static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type  state)
 332 {
 333         switch (state) {
 334         case POWER_STATE_TYPE_BATTERY:
 335                 return PP_StateUILabel_Battery;
 336         case POWER_STATE_TYPE_BALANCED:
 337                 return PP_StateUILabel_Balanced;
 338         case POWER_STATE_TYPE_PERFORMANCE:
 339                 return PP_StateUILabel_Performance;
 340         default:
 341                 return PP_StateUILabel_None;
 342         }
 343 }
 344
 345 int hwmgr_handle_task(struct pp_hwmgr *hwmgr, enum amd_pp_task task_id,
 346                 enum amd_pm_state_type *user_state)
 347 {
 348         int ret = 0;
 349
 350         if (hwmgr == NULL)
 351                 return -EINVAL;
 352
 353         switch (task_id) {
 354         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
 355                 ret = phm_pre_display_configuration_changed(hwmgr);
 356                 if (ret)
 357                         return ret;
 358                 ret = phm_set_cpu_power_state(hwmgr);
 359                 if (ret)
 360                         return ret;
 361                 ret = psm_set_performance_states(hwmgr);
 362                 if (ret)
 363                         return ret;
 364                 ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
 365                 break;
 366         case AMD_PP_TASK_ENABLE_USER_STATE:
 367         {
 368                 enum PP_StateUILabel requested_ui_label;
 369                 struct pp_power_state *requested_ps = NULL;
 370
 371                 if (user_state == NULL) {
 372                         ret = -EINVAL;
 373                         break;
 374                 }
 375
 376                 requested_ui_label = power_state_convert(*user_state);
 377                 ret = psm_set_user_performance_state(hwmgr, requested_ui_label, &requested_ps);
 378                 if (ret)
 379                         return ret;
 380                 ret = psm_adjust_power_state_dynamic(hwmgr, false, requested_ps);
 381                 break;
 382         }
 383         case AMD_PP_TASK_COMPLETE_INIT:
 384         case AMD_PP_TASK_READJUST_POWER_STATE:
 385                 ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
 386                 break;
 387         default:
 388                 break;
 389         }
 390         return ret;
 391 }
 392
 393 void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)
 394 {
 395         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
 396
 397         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM);
 398         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM);
 399
 400 #if defined(CONFIG_ACPI)
 401         if (amdgpu_acpi_is_pcie_performance_request_supported(hwmgr->adev))
 402                 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
 403 #endif
 404
 405         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 406                 PHM_PlatformCaps_DynamicPatchPowerState);
 407
 408         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 409                 PHM_PlatformCaps_EnableSMU7ThermalManagement);
 410
 411         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 412                         PHM_PlatformCaps_DynamicPowerManagement);
 413
 414         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 415                                         PHM_PlatformCaps_SMC);
 416
 417         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 418                                         PHM_PlatformCaps_DynamicUVDState);
 419
 420         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 421                                                 PHM_PlatformCaps_FanSpeedInTableIsRPM);
 422         return;
 423 }
 424
 425 int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
 426 {
 427         if (hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK)
 428                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 429                         PHM_PlatformCaps_SclkDeepSleep);
 430         else
 431                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 432                         PHM_PlatformCaps_SclkDeepSleep);
 433
 434         if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
 435                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 436                             PHM_PlatformCaps_PowerContainment);
 437                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 438                         PHM_PlatformCaps_CAC);
 439         } else {
 440                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 441                             PHM_PlatformCaps_PowerContainment);
 442                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 443                         PHM_PlatformCaps_CAC);
 444         }
 445
 446         if (hwmgr->feature_mask & PP_OVERDRIVE_MASK)
 447                 hwmgr->od_enabled = true;
 448
 449         return 0;
 450 }
 451
 452 int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 453 {
 454         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 455                                                 PHM_PlatformCaps_EVV);
 456         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 457                                                 PHM_PlatformCaps_SQRamping);
 458         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 459                                                 PHM_PlatformCaps_RegulatorHot);
 460
 461         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 462                                         PHM_PlatformCaps_AutomaticDCTransition);
 463
 464         if (hwmgr->chip_id != CHIP_POLARIS10)
 465                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 466                                         PHM_PlatformCaps_SPLLShutdownSupport);
 467
 468         if (hwmgr->chip_id != CHIP_POLARIS11) {
 469                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 470                                                         PHM_PlatformCaps_DBRamping);
 471                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 472                                                         PHM_PlatformCaps_TDRamping);
 473                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 474                                                         PHM_PlatformCaps_TCPRamping);
 475         }
 476         return 0;
 477 }
 478
 479 int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 480 {
 481         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 482                                                 PHM_PlatformCaps_EVV);
 483         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 484                         PHM_PlatformCaps_SQRamping);
 485         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 486                         PHM_PlatformCaps_DBRamping);
 487         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 488                         PHM_PlatformCaps_TDRamping);
 489         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 490                         PHM_PlatformCaps_TCPRamping);
 491         return 0;
 492 }
 493
 494 int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 495 {
 496         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 497                                                 PHM_PlatformCaps_EVV);
 498         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 499                         PHM_PlatformCaps_SQRamping);
 500         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 501                         PHM_PlatformCaps_DBRamping);
 502         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 503                         PHM_PlatformCaps_TDRamping);
 504         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 505                         PHM_PlatformCaps_TCPRamping);
 506
 507         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 508                       PHM_PlatformCaps_UVDPowerGating);
 509         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 510                       PHM_PlatformCaps_VCEPowerGating);
 511         return 0;
 512 }
 513
 514 int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 515 {
 516         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 517                                                 PHM_PlatformCaps_EVV);
 518         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 519                         PHM_PlatformCaps_SQRamping);
 520         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 521                         PHM_PlatformCaps_DBRamping);
 522         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 523                         PHM_PlatformCaps_TDRamping);
 524         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 525                         PHM_PlatformCaps_TCPRamping);
 526         return 0;
 527 }
 528
 529 int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 530 {
 531         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 532                         PHM_PlatformCaps_SQRamping);
 533         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 534                         PHM_PlatformCaps_DBRamping);
 535         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 536                         PHM_PlatformCaps_TDRamping);
 537         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 538                         PHM_PlatformCaps_TCPRamping);
 539         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 540                         PHM_PlatformCaps_MemorySpreadSpectrumSupport);
 541         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 542                         PHM_PlatformCaps_EngineSpreadSpectrumSupport);
 543         return 0;
 544 }