drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/types.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include "atom-types.h"
  27 #include "atombios.h"
  28 #include "processpptables.h"
  29 #include "pp_debug.h"
  30 #include "cgs_common.h"
  31 #include "smu/smu_8_0_d.h"
  32 #include "smu8_fusion.h"
  33 #include "smu/smu_8_0_sh_mask.h"
  34 #include "smumgr.h"
  35 #include "hwmgr.h"
  36 #include "hardwaremanager.h"
  37 #include "cz_ppsmc.h"
  38 #include "cz_hwmgr.h"
  39 #include "power_state.h"
  40 #include "cz_clockpowergating.h"
  41 #include "pp_debug.h"
  42
  43 #define ixSMUSVI_NB_CURRENTVID 0xD8230044
  44 #define CURRENT_NB_VID_MASK 0xff000000
  45 #define CURRENT_NB_VID__SHIFT 24
  46 #define ixSMUSVI_GFX_CURRENTVID  0xD8230048
  47 #define CURRENT_GFX_VID_MASK 0xff000000
  48 #define CURRENT_GFX_VID__SHIFT 24
  49
  50 static const unsigned long PhwCz_Magic = (unsigned long) PHM_Cz_Magic;
  51
  52 static struct cz_power_state *cast_PhwCzPowerState(struct pp_hw_power_state *hw_ps)
  53 {
  54         if (PhwCz_Magic != hw_ps->magic)
  55                 return NULL;
  56
  57         return (struct cz_power_state *)hw_ps;
  58 }
  59
  60 static const struct cz_power_state *cast_const_PhwCzPowerState(
  61                                 const struct pp_hw_power_state *hw_ps)
  62 {
  63         if (PhwCz_Magic != hw_ps->magic)
  64                 return NULL;
  65
  66         return (struct cz_power_state *)hw_ps;
  67 }
  68
  69 uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr,
  70                                         uint32_t clock, uint32_t msg)
  71 {
  72         int i = 0;
  73         struct phm_vce_clock_voltage_dependency_table *ptable =
  74                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
  75
  76         switch (msg) {
  77         case PPSMC_MSG_SetEclkSoftMin:
  78         case PPSMC_MSG_SetEclkHardMin:
  79                 for (i = 0; i < (int)ptable->count; i++) {
  80                         if (clock <= ptable->entries[i].ecclk)
  81                                 break;
  82                 }
  83                 break;
  84
  85         case PPSMC_MSG_SetEclkSoftMax:
  86         case PPSMC_MSG_SetEclkHardMax:
  87                 for (i = ptable->count - 1; i >= 0; i--) {
  88                         if (clock >= ptable->entries[i].ecclk)
  89                                 break;
  90                 }
  91                 break;
  92
  93         default:
  94                 break;
  95         }
  96
  97         return i;
  98 }
  99
 100 static uint32_t cz_get_sclk_level(struct pp_hwmgr *hwmgr,
 101                                 uint32_t clock, uint32_t msg)
 102 {
 103         int i = 0;
 104         struct phm_clock_voltage_dependency_table *table =
 105                                 hwmgr->dyn_state.vddc_dependency_on_sclk;
 106
 107         switch (msg) {
 108         case PPSMC_MSG_SetSclkSoftMin:
 109         case PPSMC_MSG_SetSclkHardMin:
 110                 for (i = 0; i < (int)table->count; i++) {
 111                         if (clock <= table->entries[i].clk)
 112                                 break;
 113                 }
 114                 break;
 115
 116         case PPSMC_MSG_SetSclkSoftMax:
 117         case PPSMC_MSG_SetSclkHardMax:
 118                 for (i = table->count - 1; i >= 0; i--) {
 119                         if (clock >= table->entries[i].clk)
 120                                 break;
 121                 }
 122                 break;
 123
 124         default:
 125                 break;
 126         }
 127         return i;
 128 }
 129
 130 static uint32_t cz_get_uvd_level(struct pp_hwmgr *hwmgr,
 131                                         uint32_t clock, uint32_t msg)
 132 {
 133         int i = 0;
 134         struct phm_uvd_clock_voltage_dependency_table *ptable =
 135                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
 136
 137         switch (msg) {
 138         case PPSMC_MSG_SetUvdSoftMin:
 139         case PPSMC_MSG_SetUvdHardMin:
 140                 for (i = 0; i < (int)ptable->count; i++) {
 141                         if (clock <= ptable->entries[i].vclk)
 142                                 break;
 143                 }
 144                 break;
 145
 146         case PPSMC_MSG_SetUvdSoftMax:
 147         case PPSMC_MSG_SetUvdHardMax:
 148                 for (i = ptable->count - 1; i >= 0; i--) {
 149                         if (clock >= ptable->entries[i].vclk)
 150                                 break;
 151                 }
 152                 break;
 153
 154         default:
 155                 break;
 156         }
 157
 158         return i;
 159 }
 160
 161 static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr)
 162 {
 163         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 164
 165         if (cz_hwmgr->max_sclk_level == 0) {
 166                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxSclkLevel);
 167                 cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr->smumgr) + 1;
 168         }
 169
 170         return cz_hwmgr->max_sclk_level;
 171 }
 172
 173 static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
 174 {
 175         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 176         uint32_t i;
 177         struct cgs_system_info sys_info = {0};
 178         int result;
 179
 180         cz_hwmgr->gfx_ramp_step = 256*25/100;
 181         cz_hwmgr->gfx_ramp_delay = 1; /* by default, we delay 1us */
 182
 183         for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++)
 184                 cz_hwmgr->activity_target[i] = CZ_AT_DFLT;
 185
 186         cz_hwmgr->mgcg_cgtt_local0 = 0x00000000;
 187         cz_hwmgr->mgcg_cgtt_local1 = 0x00000000;
 188         cz_hwmgr->clock_slow_down_freq = 25000;
 189         cz_hwmgr->skip_clock_slow_down = 1;
 190         cz_hwmgr->enable_nb_ps_policy = 1; /* disable until UNB is ready, Enabled */
 191         cz_hwmgr->voltage_drop_in_dce_power_gating = 0; /* disable until fully verified */
 192         cz_hwmgr->voting_rights_clients = 0x00C00033;
 193         cz_hwmgr->static_screen_threshold = 8;
 194         cz_hwmgr->ddi_power_gating_disabled = 0;
 195         cz_hwmgr->bapm_enabled = 1;
 196         cz_hwmgr->voltage_drop_threshold = 0;
 197         cz_hwmgr->gfx_power_gating_threshold = 500;
 198         cz_hwmgr->vce_slow_sclk_threshold = 20000;
 199         cz_hwmgr->dce_slow_sclk_threshold = 30000;
 200         cz_hwmgr->disable_driver_thermal_policy = 1;
 201         cz_hwmgr->disable_nb_ps3_in_battery = 0;
 202
 203         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 204                                                         PHM_PlatformCaps_ABM);
 205
 206         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 207                                     PHM_PlatformCaps_NonABMSupportInPPLib);
 208
 209         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 210                                         PHM_PlatformCaps_DynamicM3Arbiter);
 211
 212         cz_hwmgr->override_dynamic_mgpg = 1;
 213
 214         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 215                                   PHM_PlatformCaps_DynamicPatchPowerState);
 216
 217         cz_hwmgr->thermal_auto_throttling_treshold = 0;
 218         cz_hwmgr->tdr_clock = 0;
 219         cz_hwmgr->disable_gfx_power_gating_in_uvd = 0;
 220
 221         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 222                                         PHM_PlatformCaps_DynamicUVDState);
 223
 224         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 225                         PHM_PlatformCaps_UVDDPM);
 226         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 227                         PHM_PlatformCaps_VCEDPM);
 228
 229         cz_hwmgr->cc6_settings.cpu_cc6_disable = false;
 230         cz_hwmgr->cc6_settings.cpu_pstate_disable = false;
 231         cz_hwmgr->cc6_settings.nb_pstate_switch_disable = false;
 232         cz_hwmgr->cc6_settings.cpu_pstate_separation_time = 0;
 233
 234         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 235                                    PHM_PlatformCaps_DisableVoltageIsland);
 236
 237         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 238                       PHM_PlatformCaps_UVDPowerGating);
 239         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 240                       PHM_PlatformCaps_VCEPowerGating);
 241         sys_info.size = sizeof(struct cgs_system_info);
 242         sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
 243         result = cgs_query_system_info(hwmgr->device, &sys_info);
 244         if (!result) {
 245                 if (sys_info.value & AMD_PG_SUPPORT_UVD)
 246                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 247                                       PHM_PlatformCaps_UVDPowerGating);
 248                 if (sys_info.value & AMD_PG_SUPPORT_VCE)
 249                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 250                                       PHM_PlatformCaps_VCEPowerGating);
 251         }
 252
 253         return 0;
 254 }
 255
 256 static uint32_t cz_convert_8Bit_index_to_voltage(
 257                         struct pp_hwmgr *hwmgr, uint16_t voltage)
 258 {
 259         return 6200 - (voltage * 25);
 260 }
 261
 262 static int cz_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
 263                         struct phm_clock_and_voltage_limits *table)
 264 {
 265         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend;
 266         struct cz_sys_info *sys_info = &cz_hwmgr->sys_info;
 267         struct phm_clock_voltage_dependency_table *dep_table =
 268                                 hwmgr->dyn_state.vddc_dependency_on_sclk;
 269
 270         if (dep_table->count > 0) {
 271                 table->sclk = dep_table->entries[dep_table->count-1].clk;
 272                 table->vddc = cz_convert_8Bit_index_to_voltage(hwmgr,
 273                    (uint16_t)dep_table->entries[dep_table->count-1].v);
 274         }
 275         table->mclk = sys_info->nbp_memory_clock[0];
 276         return 0;
 277 }
 278
 279 static int cz_init_dynamic_state_adjustment_rule_settings(
 280                         struct pp_hwmgr *hwmgr,
 281                         ATOM_CLK_VOLT_CAPABILITY *disp_voltage_table)
 282 {
 283         uint32_t table_size =
 284                 sizeof(struct phm_clock_voltage_dependency_table) +
 285                 (7 * sizeof(struct phm_clock_voltage_dependency_record));
 286
 287         struct phm_clock_voltage_dependency_table *table_clk_vlt =
 288                                         kzalloc(table_size, GFP_KERNEL);
 289
 290         if (NULL == table_clk_vlt) {
 291                 printk(KERN_ERR "[ powerplay ] Can not allocate memory!\n");
 292                 return -ENOMEM;
 293         }
 294
 295         table_clk_vlt->count = 8;
 296         table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
 297         table_clk_vlt->entries[0].v = 0;
 298         table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
 299         table_clk_vlt->entries[1].v = 1;
 300         table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
 301         table_clk_vlt->entries[2].v = 2;
 302         table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
 303         table_clk_vlt->entries[3].v = 3;
 304         table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
 305         table_clk_vlt->entries[4].v = 4;
 306         table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
 307         table_clk_vlt->entries[5].v = 5;
 308         table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
 309         table_clk_vlt->entries[6].v = 6;
 310         table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
 311         table_clk_vlt->entries[7].v = 7;
 312         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
 313
 314         return 0;
 315 }
 316
 317 static int cz_get_system_info_data(struct pp_hwmgr *hwmgr)
 318 {
 319         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend;
 320         ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *info = NULL;
 321         uint32_t i;
 322         int result = 0;
 323         uint8_t frev, crev;
 324         uint16_t size;
 325
 326         info = (ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *) cgs_atom_get_data_table(
 327                         hwmgr->device,
 328                         GetIndexIntoMasterTable(DATA, IntegratedSystemInfo),
 329                         &size, &frev, &crev);
 330
 331         if (crev != 9) {
 332                 printk(KERN_ERR "[ powerplay ] Unsupported IGP table: %d %d\n", frev, crev);
 333                 return -EINVAL;
 334         }
 335
 336         if (info == NULL) {
 337                 printk(KERN_ERR "[ powerplay ] Could not retrieve the Integrated System Info Table!\n");
 338                 return -EINVAL;
 339         }
 340
 341         cz_hwmgr->sys_info.bootup_uma_clock =
 342                                    le32_to_cpu(info->ulBootUpUMAClock);
 343
 344         cz_hwmgr->sys_info.bootup_engine_clock =
 345                                 le32_to_cpu(info->ulBootUpEngineClock);
 346
 347         cz_hwmgr->sys_info.dentist_vco_freq =
 348                                    le32_to_cpu(info->ulDentistVCOFreq);
 349
 350         cz_hwmgr->sys_info.system_config =
 351                                      le32_to_cpu(info->ulSystemConfig);
 352
 353         cz_hwmgr->sys_info.bootup_nb_voltage_index =
 354                                   le16_to_cpu(info->usBootUpNBVoltage);
 355
 356         cz_hwmgr->sys_info.htc_hyst_lmt =
 357                         (info->ucHtcHystLmt == 0) ? 5 : info->ucHtcHystLmt;
 358
 359         cz_hwmgr->sys_info.htc_tmp_lmt =
 360                         (info->ucHtcTmpLmt == 0) ? 203 : info->ucHtcTmpLmt;
 361
 362         if (cz_hwmgr->sys_info.htc_tmp_lmt <=
 363                         cz_hwmgr->sys_info.htc_hyst_lmt) {
 364                 printk(KERN_ERR "[ powerplay ] The htcTmpLmt should be larger than htcHystLmt.\n");
 365                 return -EINVAL;
 366         }
 367
 368         cz_hwmgr->sys_info.nb_dpm_enable =
 369                                 cz_hwmgr->enable_nb_ps_policy &&
 370                                 (le32_to_cpu(info->ulSystemConfig) >> 3 & 0x1);
 371
 372         for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
 373                 if (i < CZ_NUM_NBPMEMORYCLOCK) {
 374                         cz_hwmgr->sys_info.nbp_memory_clock[i] =
 375                           le32_to_cpu(info->ulNbpStateMemclkFreq[i]);
 376                 }
 377                 cz_hwmgr->sys_info.nbp_n_clock[i] =
 378                             le32_to_cpu(info->ulNbpStateNClkFreq[i]);
 379         }
 380
 381         for (i = 0; i < MAX_DISPLAY_CLOCK_LEVEL; i++) {
 382                 cz_hwmgr->sys_info.display_clock[i] =
 383                                         le32_to_cpu(info->sDispClkVoltageMapping[i].ulMaximumSupportedCLK);
 384         }
 385
 386         /* Here use 4 levels, make sure not exceed */
 387         for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
 388                 cz_hwmgr->sys_info.nbp_voltage_index[i] =
 389                              le16_to_cpu(info->usNBPStateVoltage[i]);
 390         }
 391
 392         if (!cz_hwmgr->sys_info.nb_dpm_enable) {
 393                 for (i = 1; i < CZ_NUM_NBPSTATES; i++) {
 394                         if (i < CZ_NUM_NBPMEMORYCLOCK) {
 395                                 cz_hwmgr->sys_info.nbp_memory_clock[i] =
 396                                     cz_hwmgr->sys_info.nbp_memory_clock[0];
 397                         }
 398                         cz_hwmgr->sys_info.nbp_n_clock[i] =
 399                                     cz_hwmgr->sys_info.nbp_n_clock[0];
 400                         cz_hwmgr->sys_info.nbp_voltage_index[i] =
 401                                     cz_hwmgr->sys_info.nbp_voltage_index[0];
 402                 }
 403         }
 404
 405         if (le32_to_cpu(info->ulGPUCapInfo) &
 406                 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) {
 407                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 408                                     PHM_PlatformCaps_EnableDFSBypass);
 409         }
 410
 411         cz_hwmgr->sys_info.uma_channel_number = info->ucUMAChannelNumber;
 412
 413         cz_construct_max_power_limits_table (hwmgr,
 414                                     &hwmgr->dyn_state.max_clock_voltage_on_ac);
 415
 416         cz_init_dynamic_state_adjustment_rule_settings(hwmgr,
 417                                     &info->sDISPCLK_Voltage[0]);
 418
 419         return result;
 420 }
 421
 422 static int cz_construct_boot_state(struct pp_hwmgr *hwmgr)
 423 {
 424         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 425
 426         cz_hwmgr->boot_power_level.engineClock =
 427                                 cz_hwmgr->sys_info.bootup_engine_clock;
 428
 429         cz_hwmgr->boot_power_level.vddcIndex =
 430                         (uint8_t)cz_hwmgr->sys_info.bootup_nb_voltage_index;
 431
 432         cz_hwmgr->boot_power_level.dsDividerIndex = 0;
 433         cz_hwmgr->boot_power_level.ssDividerIndex = 0;
 434         cz_hwmgr->boot_power_level.allowGnbSlow = 1;
 435         cz_hwmgr->boot_power_level.forceNBPstate = 0;
 436         cz_hwmgr->boot_power_level.hysteresis_up = 0;
 437         cz_hwmgr->boot_power_level.numSIMDToPowerDown = 0;
 438         cz_hwmgr->boot_power_level.display_wm = 0;
 439         cz_hwmgr->boot_power_level.vce_wm = 0;
 440
 441         return 0;
 442 }
 443
 444 static int cz_tf_reset_active_process_mask(struct pp_hwmgr *hwmgr, void *input,
 445                                         void *output, void *storage, int result)
 446 {
 447         return 0;
 448 }
 449
 450 static int cz_tf_upload_pptable_to_smu(struct pp_hwmgr *hwmgr, void *input,
 451                                        void *output, void *storage, int result)
 452 {
 453         struct SMU8_Fusion_ClkTable *clock_table;
 454         int ret;
 455         uint32_t i;
 456         void *table = NULL;
 457         pp_atomctrl_clock_dividers_kong dividers;
 458
 459         struct phm_clock_voltage_dependency_table *vddc_table =
 460                 hwmgr->dyn_state.vddc_dependency_on_sclk;
 461         struct phm_clock_voltage_dependency_table *vdd_gfx_table =
 462                 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk;
 463         struct phm_acp_clock_voltage_dependency_table *acp_table =
 464                 hwmgr->dyn_state.acp_clock_voltage_dependency_table;
 465         struct phm_uvd_clock_voltage_dependency_table *uvd_table =
 466                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
 467         struct phm_vce_clock_voltage_dependency_table *vce_table =
 468                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
 469
 470         if (!hwmgr->need_pp_table_upload)
 471                 return 0;
 472
 473         ret = smum_download_powerplay_table(hwmgr->smumgr, &table);
 474
 475         PP_ASSERT_WITH_CODE((0 == ret && NULL != table),
 476                             "Fail to get clock table from SMU!", return -EINVAL;);
 477
 478         clock_table = (struct SMU8_Fusion_ClkTable *)table;
 479
 480         /* patch clock table */
 481         PP_ASSERT_WITH_CODE((vddc_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 482                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 483         PP_ASSERT_WITH_CODE((vdd_gfx_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 484                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 485         PP_ASSERT_WITH_CODE((acp_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 486                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 487         PP_ASSERT_WITH_CODE((uvd_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 488                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 489         PP_ASSERT_WITH_CODE((vce_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 490                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 491
 492         for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++) {
 493
 494                 /* vddc_sclk */
 495                 clock_table->SclkBreakdownTable.ClkLevel[i].GnbVid =
 496                         (i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0;
 497                 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency =
 498                         (i < vddc_table->count) ? vddc_table->entries[i].clk : 0;
 499
 500                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 501                                                       clock_table->SclkBreakdownTable.ClkLevel[i].Frequency,
 502                                                       &dividers);
 503
 504                 clock_table->SclkBreakdownTable.ClkLevel[i].DfsDid =
 505                         (uint8_t)dividers.pll_post_divider;
 506
 507                 /* vddgfx_sclk */
 508                 clock_table->SclkBreakdownTable.ClkLevel[i].GfxVid =
 509                         (i < vdd_gfx_table->count) ? (uint8_t)vdd_gfx_table->entries[i].v : 0;
 510
 511                 /* acp breakdown */
 512                 clock_table->AclkBreakdownTable.ClkLevel[i].GfxVid =
 513                         (i < acp_table->count) ? (uint8_t)acp_table->entries[i].v : 0;
 514                 clock_table->AclkBreakdownTable.ClkLevel[i].Frequency =
 515                         (i < acp_table->count) ? acp_table->entries[i].acpclk : 0;
 516
 517                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 518                                                       clock_table->AclkBreakdownTable.ClkLevel[i].Frequency,
 519                                                       &dividers);
 520
 521                 clock_table->AclkBreakdownTable.ClkLevel[i].DfsDid =
 522                         (uint8_t)dividers.pll_post_divider;
 523
 524
 525                 /* uvd breakdown */
 526                 clock_table->VclkBreakdownTable.ClkLevel[i].GfxVid =
 527                         (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
 528                 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency =
 529                         (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0;
 530
 531                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 532                                                       clock_table->VclkBreakdownTable.ClkLevel[i].Frequency,
 533                                                       &dividers);
 534
 535                 clock_table->VclkBreakdownTable.ClkLevel[i].DfsDid =
 536                         (uint8_t)dividers.pll_post_divider;
 537
 538                 clock_table->DclkBreakdownTable.ClkLevel[i].GfxVid =
 539                         (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
 540                 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency =
 541                         (i < uvd_table->count) ? uvd_table->entries[i].dclk : 0;
 542
 543                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 544                                                       clock_table->DclkBreakdownTable.ClkLevel[i].Frequency,
 545                                                       &dividers);
 546
 547                 clock_table->DclkBreakdownTable.ClkLevel[i].DfsDid =
 548                         (uint8_t)dividers.pll_post_divider;
 549
 550                 /* vce breakdown */
 551                 clock_table->EclkBreakdownTable.ClkLevel[i].GfxVid =
 552                         (i < vce_table->count) ? (uint8_t)vce_table->entries[i].v : 0;
 553                 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency =
 554                         (i < vce_table->count) ? vce_table->entries[i].ecclk : 0;
 555
 556
 557                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 558                                                       clock_table->EclkBreakdownTable.ClkLevel[i].Frequency,
 559                                                       &dividers);
 560
 561                 clock_table->EclkBreakdownTable.ClkLevel[i].DfsDid =
 562                         (uint8_t)dividers.pll_post_divider;
 563
 564         }
 565         ret = smum_upload_powerplay_table(hwmgr->smumgr);
 566
 567         return ret;
 568 }
 569
 570 static int cz_tf_init_sclk_limit(struct pp_hwmgr *hwmgr, void *input,
 571                                  void *output, void *storage, int result)
 572 {
 573         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 574         struct phm_clock_voltage_dependency_table *table =
 575                                         hwmgr->dyn_state.vddc_dependency_on_sclk;
 576         unsigned long clock = 0, level;
 577
 578         if (NULL == table || table->count <= 0)
 579                 return -EINVAL;
 580
 581         cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
 582         cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
 583
 584         level = cz_get_max_sclk_level(hwmgr) - 1;
 585
 586         if (level < table->count)
 587                 clock = table->entries[level].clk;
 588         else
 589                 clock = table->entries[table->count - 1].clk;
 590
 591         cz_hwmgr->sclk_dpm.soft_max_clk = clock;
 592         cz_hwmgr->sclk_dpm.hard_max_clk = clock;
 593
 594         return 0;
 595 }
 596
 597 static int cz_tf_init_uvd_limit(struct pp_hwmgr *hwmgr, void *input,
 598                                 void *output, void *storage, int result)
 599 {
 600         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 601         struct phm_uvd_clock_voltage_dependency_table *table =
 602                                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
 603         unsigned long clock = 0, level;
 604
 605         if (NULL == table || table->count <= 0)
 606                 return -EINVAL;
 607
 608         cz_hwmgr->uvd_dpm.soft_min_clk = 0;
 609         cz_hwmgr->uvd_dpm.hard_min_clk = 0;
 610
 611         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxUvdLevel);
 612         level = smum_get_argument(hwmgr->smumgr);
 613
 614         if (level < table->count)
 615                 clock = table->entries[level].vclk;
 616         else
 617                 clock = table->entries[table->count - 1].vclk;
 618
 619         cz_hwmgr->uvd_dpm.soft_max_clk = clock;
 620         cz_hwmgr->uvd_dpm.hard_max_clk = clock;
 621
 622         return 0;
 623 }
 624
 625 static int cz_tf_init_vce_limit(struct pp_hwmgr *hwmgr, void *input,
 626                                 void *output, void *storage, int result)
 627 {
 628         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 629         struct phm_vce_clock_voltage_dependency_table *table =
 630                                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
 631         unsigned long clock = 0, level;
 632
 633         if (NULL == table || table->count <= 0)
 634                 return -EINVAL;
 635
 636         cz_hwmgr->vce_dpm.soft_min_clk = 0;
 637         cz_hwmgr->vce_dpm.hard_min_clk = 0;
 638
 639         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxEclkLevel);
 640         level = smum_get_argument(hwmgr->smumgr);
 641
 642         if (level < table->count)
 643                 clock = table->entries[level].ecclk;
 644         else
 645                 clock = table->entries[table->count - 1].ecclk;
 646
 647         cz_hwmgr->vce_dpm.soft_max_clk = clock;
 648         cz_hwmgr->vce_dpm.hard_max_clk = clock;
 649
 650         return 0;
 651 }
 652
 653 static int cz_tf_init_acp_limit(struct pp_hwmgr *hwmgr, void *input,
 654                                 void *output, void *storage, int result)
 655 {
 656         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 657         struct phm_acp_clock_voltage_dependency_table *table =
 658                                 hwmgr->dyn_state.acp_clock_voltage_dependency_table;
 659         unsigned long clock = 0, level;
 660
 661         if (NULL == table || table->count <= 0)
 662                 return -EINVAL;
 663
 664         cz_hwmgr->acp_dpm.soft_min_clk = 0;
 665         cz_hwmgr->acp_dpm.hard_min_clk = 0;
 666
 667         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxAclkLevel);
 668         level = smum_get_argument(hwmgr->smumgr);
 669
 670         if (level < table->count)
 671                 clock = table->entries[level].acpclk;
 672         else
 673                 clock = table->entries[table->count - 1].acpclk;
 674
 675         cz_hwmgr->acp_dpm.soft_max_clk = clock;
 676         cz_hwmgr->acp_dpm.hard_max_clk = clock;
 677         return 0;
 678 }
 679
 680 static int cz_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input,
 681                                 void *output, void *storage, int result)
 682 {
 683         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 684
 685         cz_hwmgr->uvd_power_gated = false;
 686         cz_hwmgr->vce_power_gated = false;
 687         cz_hwmgr->samu_power_gated = false;
 688         cz_hwmgr->acp_power_gated = false;
 689         cz_hwmgr->pgacpinit = true;
 690
 691         return 0;
 692 }
 693
 694 static int cz_tf_init_sclk_threshold(struct pp_hwmgr *hwmgr, void *input,
 695                                 void *output, void *storage, int result)
 696 {
 697         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 698
 699         cz_hwmgr->low_sclk_interrupt_threshold = 0;
 700
 701         return 0;
 702 }
 703 static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr,
 704                                         void *input, void *output,
 705                                         void *storage, int result)
 706 {
 707         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 708         struct phm_clock_voltage_dependency_table *table =
 709                                         hwmgr->dyn_state.vddc_dependency_on_sclk;
 710
 711         unsigned long clock = 0;
 712         unsigned long level;
 713         unsigned long stable_pstate_sclk;
 714         unsigned long percentage;
 715
 716         cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
 717         level = cz_get_max_sclk_level(hwmgr) - 1;
 718
 719         if (level < table->count)
 720                 cz_hwmgr->sclk_dpm.soft_max_clk  = table->entries[level].clk;
 721         else
 722                 cz_hwmgr->sclk_dpm.soft_max_clk  = table->entries[table->count - 1].clk;
 723
 724         clock = hwmgr->display_config.min_core_set_clock;
 725         if (clock == 0)
 726                 printk(KERN_INFO "[ powerplay ] min_core_set_clock not set\n");
 727
 728         if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) {
 729                 cz_hwmgr->sclk_dpm.hard_min_clk = clock;
 730
 731                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 732                                                 PPSMC_MSG_SetSclkHardMin,
 733                                                  cz_get_sclk_level(hwmgr,
 734                                         cz_hwmgr->sclk_dpm.hard_min_clk,
 735                                              PPSMC_MSG_SetSclkHardMin));
 736         }
 737
 738         clock = cz_hwmgr->sclk_dpm.soft_min_clk;
 739
 740         /* update minimum clocks for Stable P-State feature */
 741         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 742                                      PHM_PlatformCaps_StablePState)) {
 743                 percentage = 75;
 744                 /*Sclk - calculate sclk value based on percentage and find FLOOR sclk from VddcDependencyOnSCLK table  */
 745                 stable_pstate_sclk = (hwmgr->dyn_state.max_clock_voltage_on_ac.mclk *
 746                                         percentage) / 100;
 747
 748                 if (clock < stable_pstate_sclk)
 749                         clock = stable_pstate_sclk;
 750         } else {
 751                 if (clock < hwmgr->gfx_arbiter.sclk)
 752                         clock = hwmgr->gfx_arbiter.sclk;
 753         }
 754
 755         if (cz_hwmgr->sclk_dpm.soft_min_clk != clock) {
 756                 cz_hwmgr->sclk_dpm.soft_min_clk = clock;
 757                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 758                                                 PPSMC_MSG_SetSclkSoftMin,
 759                                                 cz_get_sclk_level(hwmgr,
 760                                         cz_hwmgr->sclk_dpm.soft_min_clk,
 761                                              PPSMC_MSG_SetSclkSoftMin));
 762         }
 763
 764         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 765                                     PHM_PlatformCaps_StablePState) &&
 766                          cz_hwmgr->sclk_dpm.soft_max_clk != clock) {
 767                 cz_hwmgr->sclk_dpm.soft_max_clk = clock;
 768                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 769                                                 PPSMC_MSG_SetSclkSoftMax,
 770                                                 cz_get_sclk_level(hwmgr,
 771                                         cz_hwmgr->sclk_dpm.soft_max_clk,
 772                                         PPSMC_MSG_SetSclkSoftMax));
 773         }
 774
 775         return 0;
 776 }
 777
 778 static int cz_tf_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr,
 779                                         void *input, void *output,
 780                                         void *storage, int result)
 781 {
 782         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 783                                 PHM_PlatformCaps_SclkDeepSleep)) {
 784                 uint32_t clks = hwmgr->display_config.min_core_set_clock_in_sr;
 785                 if (clks == 0)
 786                         clks = CZ_MIN_DEEP_SLEEP_SCLK;
 787
 788                 PP_DBG_LOG("Setting Deep Sleep Clock: %d\n", clks);
 789
 790                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 791                                 PPSMC_MSG_SetMinDeepSleepSclk,
 792                                 clks);
 793         }
 794
 795         return 0;
 796 }
 797
 798 static int cz_tf_set_watermark_threshold(struct pp_hwmgr *hwmgr,
 799                                         void *input, void *output,
 800                                         void *storage, int result)
 801 {
 802         struct cz_hwmgr *cz_hwmgr =
 803                                   (struct cz_hwmgr *)(hwmgr->backend);
 804
 805         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 806                                         PPSMC_MSG_SetWatermarkFrequency,
 807                                         cz_hwmgr->sclk_dpm.soft_max_clk);
 808
 809         return 0;
 810 }
 811
 812 static int cz_tf_set_enabled_levels(struct pp_hwmgr *hwmgr,
 813                                         void *input, void *output,
 814                                         void *storage, int result)
 815 {
 816         return 0;
 817 }
 818
 819
 820 static int cz_tf_enable_nb_dpm(struct pp_hwmgr *hwmgr,
 821                                         void *input, void *output,
 822                                         void *storage, int result)
 823 {
 824         int ret = 0;
 825
 826         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 827         unsigned long dpm_features = 0;
 828
 829         if (!cz_hwmgr->is_nb_dpm_enabled) {
 830                 PP_DBG_LOG("enabling ALL SMU features.\n");
 831                 dpm_features |= NB_DPM_MASK;
 832                 ret = smum_send_msg_to_smc_with_parameter(
 833                                                           hwmgr->smumgr,
 834                                                           PPSMC_MSG_EnableAllSmuFeatures,
 835                                                           dpm_features);
 836                 if (ret == 0)
 837                         cz_hwmgr->is_nb_dpm_enabled = true;
 838         }
 839
 840         return ret;
 841 }
 842
 843 static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock)
 844 {
 845         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 846
 847         if (hw_data->is_nb_dpm_enabled) {
 848                 if (enable) {
 849                         PP_DBG_LOG("enable Low Memory PState.\n");
 850
 851                         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 852                                                 PPSMC_MSG_EnableLowMemoryPstate,
 853                                                 (lock ? 1 : 0));
 854                 } else {
 855                         PP_DBG_LOG("disable Low Memory PState.\n");
 856
 857                         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 858                                                 PPSMC_MSG_DisableLowMemoryPstate,
 859                                                 (lock ? 1 : 0));
 860                 }
 861         }
 862
 863         return 0;
 864 }
 865
 866 static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr,
 867                                         void *input, void *output,
 868                                         void *storage, int result)
 869 {
 870         bool disable_switch;
 871         bool enable_low_mem_state;
 872         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 873         const struct phm_set_power_state_input *states = (struct phm_set_power_state_input *)input;
 874         const struct cz_power_state *pnew_state = cast_const_PhwCzPowerState(states->pnew_state);
 875
 876         if (hw_data->sys_info.nb_dpm_enable) {
 877                 disable_switch = hw_data->cc6_settings.nb_pstate_switch_disable ? true : false;
 878                 enable_low_mem_state = hw_data->cc6_settings.nb_pstate_switch_disable ? false : true;
 879
 880                 if (pnew_state->action == FORCE_HIGH)
 881                         cz_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch);
 882                 else if (pnew_state->action == CANCEL_FORCE_HIGH)
 883                         cz_nbdpm_pstate_enable_disable(hwmgr, true, disable_switch);
 884                 else
 885                         cz_nbdpm_pstate_enable_disable(hwmgr, enable_low_mem_state, disable_switch);
 886         }
 887         return 0;
 888 }
 889
 890 static const struct phm_master_table_item cz_set_power_state_list[] = {
 891         {NULL, cz_tf_update_sclk_limit},
 892         {NULL, cz_tf_set_deep_sleep_sclk_threshold},
 893         {NULL, cz_tf_set_watermark_threshold},
 894         {NULL, cz_tf_set_enabled_levels},
 895         {NULL, cz_tf_enable_nb_dpm},
 896         {NULL, cz_tf_update_low_mem_pstate},
 897         {NULL, NULL}
 898 };
 899
 900 static const struct phm_master_table_header cz_set_power_state_master = {
 901         0,
 902         PHM_MasterTableFlag_None,
 903         cz_set_power_state_list
 904 };
 905
 906 static const struct phm_master_table_item cz_setup_asic_list[] = {
 907         {NULL, cz_tf_reset_active_process_mask},
 908         {NULL, cz_tf_upload_pptable_to_smu},
 909         {NULL, cz_tf_init_sclk_limit},
 910         {NULL, cz_tf_init_uvd_limit},
 911         {NULL, cz_tf_init_vce_limit},
 912         {NULL, cz_tf_init_acp_limit},
 913         {NULL, cz_tf_init_power_gate_state},
 914         {NULL, cz_tf_init_sclk_threshold},
 915         {NULL, NULL}
 916 };
 917
 918 static const struct phm_master_table_header cz_setup_asic_master = {
 919         0,
 920         PHM_MasterTableFlag_None,
 921         cz_setup_asic_list
 922 };
 923
 924 static int cz_tf_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr,
 925                                         void *input, void *output,
 926                                         void *storage, int result)
 927 {
 928         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 929         hw_data->disp_clk_bypass_pending = false;
 930         hw_data->disp_clk_bypass = false;
 931
 932         return 0;
 933 }
 934
 935 static int cz_tf_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr,
 936                                         void *input, void *output,
 937                                         void *storage, int result)
 938 {
 939         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 940         hw_data->is_nb_dpm_enabled = false;
 941
 942         return 0;
 943 }
 944
 945 static int cz_tf_reset_cc6_data(struct pp_hwmgr *hwmgr,
 946                                         void *input, void *output,
 947                                         void *storage, int result)
 948 {
 949         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 950
 951         hw_data->cc6_settings.cc6_setting_changed = false;
 952         hw_data->cc6_settings.cpu_pstate_separation_time = 0;
 953         hw_data->cc6_settings.cpu_cc6_disable = false;
 954         hw_data->cc6_settings.cpu_pstate_disable = false;
 955
 956         return 0;
 957 }
 958
 959 static const struct phm_master_table_item cz_power_down_asic_list[] = {
 960         {NULL, cz_tf_power_up_display_clock_sys_pll},
 961         {NULL, cz_tf_clear_nb_dpm_flag},
 962         {NULL, cz_tf_reset_cc6_data},
 963         {NULL, NULL}
 964 };
 965
 966 static const struct phm_master_table_header cz_power_down_asic_master = {
 967         0,
 968         PHM_MasterTableFlag_None,
 969         cz_power_down_asic_list
 970 };
 971
 972 static int cz_tf_program_voting_clients(struct pp_hwmgr *hwmgr, void *input,
 973                                 void *output, void *storage, int result)
 974 {
 975         PHMCZ_WRITE_SMC_REGISTER(hwmgr->device, CG_FREQ_TRAN_VOTING_0,
 976                                 PPCZ_VOTINGRIGHTSCLIENTS_DFLT0);
 977         return 0;
 978 }
 979
 980 static int cz_tf_start_dpm(struct pp_hwmgr *hwmgr, void *input, void *output,
 981                            void *storage, int result)
 982 {
 983         int res = 0xff;
 984         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 985         unsigned long dpm_features = 0;
 986
 987         cz_hwmgr->dpm_flags |= DPMFlags_SCLK_Enabled;
 988         dpm_features |= SCLK_DPM_MASK;
 989
 990         res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 991                                 PPSMC_MSG_EnableAllSmuFeatures,
 992                                 dpm_features);
 993
 994         return res;
 995 }
 996
 997 static int cz_tf_program_bootup_state(struct pp_hwmgr *hwmgr, void *input,
 998                                 void *output, void *storage, int result)
 999 {
1000         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1001
1002         cz_hwmgr->sclk_dpm.soft_min_clk = cz_hwmgr->sys_info.bootup_engine_clock;
1003         cz_hwmgr->sclk_dpm.soft_max_clk = cz_hwmgr->sys_info.bootup_engine_clock;
1004
1005         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1006                                 PPSMC_MSG_SetSclkSoftMin,
1007                                 cz_get_sclk_level(hwmgr,
1008                                 cz_hwmgr->sclk_dpm.soft_min_clk,
1009                                 PPSMC_MSG_SetSclkSoftMin));
1010
1011         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1012                                 PPSMC_MSG_SetSclkSoftMax,
1013                                 cz_get_sclk_level(hwmgr,
1014                                 cz_hwmgr->sclk_dpm.soft_max_clk,
1015                                 PPSMC_MSG_SetSclkSoftMax));
1016
1017         return 0;
1018 }
1019
1020 int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *input,
1021                                 void *output, void *storage, int result)
1022 {
1023         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1024
1025         cz_hwmgr->acp_boot_level = 0xff;
1026         return 0;
1027 }
1028
1029 static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
1030                                 unsigned long check_feature)
1031 {
1032         int result;
1033         unsigned long features;
1034
1035         result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_GetFeatureStatus, 0);
1036         if (result == 0) {
1037                 features = smum_get_argument(hwmgr->smumgr);
1038                 if (features & check_feature)
1039                         return true;
1040         }
1041
1042         return result;
1043 }
1044
1045 static int cz_tf_check_for_dpm_disabled(struct pp_hwmgr *hwmgr, void *input,
1046                                 void *output, void *storage, int result)
1047 {
1048         if (cz_dpm_check_smu_features(hwmgr, SMU_EnabledFeatureScoreboard_SclkDpmOn))
1049                 return PP_Result_TableImmediateExit;
1050         return 0;
1051 }
1052
1053 static int cz_tf_enable_didt(struct pp_hwmgr *hwmgr, void *input,
1054                                 void *output, void *storage, int result)
1055 {
1056         /* TO DO */
1057         return 0;
1058 }
1059
1060 static int cz_tf_check_for_dpm_enabled(struct pp_hwmgr *hwmgr,
1061                                                 void *input, void *output,
1062                                                 void *storage, int result)
1063 {
1064         if (!cz_dpm_check_smu_features(hwmgr,
1065                              SMU_EnabledFeatureScoreboard_SclkDpmOn))
1066                 return PP_Result_TableImmediateExit;
1067         return 0;
1068 }
1069
1070 static const struct phm_master_table_item cz_disable_dpm_list[] = {
1071         { NULL, cz_tf_check_for_dpm_enabled},
1072         {NULL, NULL},
1073 };
1074
1075
1076 static const struct phm_master_table_header cz_disable_dpm_master = {
1077         0,
1078         PHM_MasterTableFlag_None,
1079         cz_disable_dpm_list
1080 };
1081
1082 static const struct phm_master_table_item cz_enable_dpm_list[] = {
1083         { NULL, cz_tf_check_for_dpm_disabled },
1084         { NULL, cz_tf_program_voting_clients },
1085         { NULL, cz_tf_start_dpm},
1086         { NULL, cz_tf_program_bootup_state},
1087         { NULL, cz_tf_enable_didt },
1088         { NULL, cz_tf_reset_acp_boot_level },
1089         {NULL, NULL},
1090 };
1091
1092 static const struct phm_master_table_header cz_enable_dpm_master = {
1093         0,
1094         PHM_MasterTableFlag_None,
1095         cz_enable_dpm_list
1096 };
1097
1098 static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
1099                                 struct pp_power_state  *prequest_ps,
1100                         const struct pp_power_state *pcurrent_ps)
1101 {
1102         struct cz_power_state *cz_ps =
1103                                 cast_PhwCzPowerState(&prequest_ps->hardware);
1104
1105         const struct cz_power_state *cz_current_ps =
1106                                 cast_const_PhwCzPowerState(&pcurrent_ps->hardware);
1107
1108         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1109         struct PP_Clocks clocks = {0, 0, 0, 0};
1110         bool force_high;
1111         uint32_t  num_of_active_displays = 0;
1112         struct cgs_display_info info = {0};
1113
1114         cz_ps->evclk = hwmgr->vce_arbiter.evclk;
1115         cz_ps->ecclk = hwmgr->vce_arbiter.ecclk;
1116
1117         cz_ps->need_dfs_bypass = true;
1118
1119         cz_hwmgr->video_start = (hwmgr->uvd_arbiter.vclk != 0 || hwmgr->uvd_arbiter.dclk != 0 ||
1120                                 hwmgr->vce_arbiter.evclk != 0 || hwmgr->vce_arbiter.ecclk != 0);
1121
1122         cz_hwmgr->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
1123
1124         clocks.memoryClock = hwmgr->display_config.min_mem_set_clock != 0 ?
1125                                 hwmgr->display_config.min_mem_set_clock :
1126                                 cz_hwmgr->sys_info.nbp_memory_clock[1];
1127
1128         cgs_get_active_displays_info(hwmgr->device, &info);
1129         num_of_active_displays = info.display_count;
1130
1131         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
1132                 clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk;
1133
1134         if (clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
1135                 clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
1136
1137         force_high = (clocks.memoryClock > cz_hwmgr->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1])
1138                         || (num_of_active_displays >= 3);
1139
1140         cz_ps->action = cz_current_ps->action;
1141
1142         if (!force_high && (cz_ps->action == FORCE_HIGH))
1143                 cz_ps->action = CANCEL_FORCE_HIGH;
1144         else if (force_high && (cz_ps->action != FORCE_HIGH))
1145                 cz_ps->action = FORCE_HIGH;
1146         else
1147                 cz_ps->action = DO_NOTHING;
1148
1149         return 0;
1150 }
1151
1152 static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
1153 {
1154         int result = 0;
1155         struct cz_hwmgr *data;
1156
1157         data = kzalloc(sizeof(struct cz_hwmgr), GFP_KERNEL);
1158         if (data == NULL)
1159                 return -ENOMEM;
1160
1161         hwmgr->backend = data;
1162
1163         result = cz_initialize_dpm_defaults(hwmgr);
1164         if (result != 0) {
1165                 printk(KERN_ERR "[ powerplay ] cz_initialize_dpm_defaults failed\n");
1166                 return result;
1167         }
1168
1169         result = cz_get_system_info_data(hwmgr);
1170         if (result != 0) {
1171                 printk(KERN_ERR "[ powerplay ] cz_get_system_info_data failed\n");
1172                 return result;
1173         }
1174
1175         cz_construct_boot_state(hwmgr);
1176
1177         result = phm_construct_table(hwmgr, &cz_setup_asic_master,
1178                                 &(hwmgr->setup_asic));
1179         if (result != 0) {
1180                 printk(KERN_ERR "[ powerplay ] Fail to construct setup ASIC\n");
1181                 return result;
1182         }
1183
1184         result = phm_construct_table(hwmgr, &cz_power_down_asic_master,
1185                                 &(hwmgr->power_down_asic));
1186         if (result != 0) {
1187                 printk(KERN_ERR "[ powerplay ] Fail to construct power down ASIC\n");
1188                 return result;
1189         }
1190
1191         result = phm_construct_table(hwmgr, &cz_disable_dpm_master,
1192                                 &(hwmgr->disable_dynamic_state_management));
1193         if (result != 0) {
1194                 printk(KERN_ERR "[ powerplay ] Fail to disable_dynamic_state\n");
1195                 return result;
1196         }
1197         result = phm_construct_table(hwmgr, &cz_enable_dpm_master,
1198                                 &(hwmgr->enable_dynamic_state_management));
1199         if (result != 0) {
1200                 printk(KERN_ERR "[ powerplay ] Fail to enable_dynamic_state\n");
1201                 return result;
1202         }
1203         result = phm_construct_table(hwmgr, &cz_set_power_state_master,
1204                                 &(hwmgr->set_power_state));
1205         if (result != 0) {
1206                 printk(KERN_ERR "[ powerplay ] Fail to construct set_power_state\n");
1207                 return result;
1208         }
1209         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =  CZ_MAX_HARDWARE_POWERLEVELS;
1210
1211         result = phm_construct_table(hwmgr, &cz_phm_enable_clock_power_gatings_master, &(hwmgr->enable_clock_power_gatings));
1212         if (result != 0) {
1213                 printk(KERN_ERR "[ powerplay ] Fail to construct enable_clock_power_gatings\n");
1214                 return result;
1215         }
1216         return result;
1217 }
1218
1219 static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
1220 {
1221         if (hwmgr != NULL && hwmgr->backend != NULL) {
1222                 kfree(hwmgr->backend);
1223                 kfree(hwmgr);
1224         }
1225         return 0;
1226 }
1227
1228 int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
1229 {
1230         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1231
1232         if (cz_hwmgr->sclk_dpm.soft_min_clk !=
1233                                 cz_hwmgr->sclk_dpm.soft_max_clk)
1234                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1235                                                 PPSMC_MSG_SetSclkSoftMin,
1236                                                 cz_get_sclk_level(hwmgr,
1237                                                 cz_hwmgr->sclk_dpm.soft_max_clk,
1238                                                 PPSMC_MSG_SetSclkSoftMin));
1239         return 0;
1240 }
1241
1242 int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
1243 {
1244         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1245         struct phm_clock_voltage_dependency_table *table =
1246                                 hwmgr->dyn_state.vddc_dependency_on_sclk;
1247         unsigned long clock = 0, level;
1248
1249         if (NULL == table || table->count <= 0)
1250                 return -EINVAL;
1251
1252         cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
1253         cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
1254
1255         level = cz_get_max_sclk_level(hwmgr) - 1;
1256
1257         if (level < table->count)
1258                 clock = table->entries[level].clk;
1259         else
1260                 clock = table->entries[table->count - 1].clk;
1261
1262         cz_hwmgr->sclk_dpm.soft_max_clk = clock;
1263         cz_hwmgr->sclk_dpm.hard_max_clk = clock;
1264
1265         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1266                                 PPSMC_MSG_SetSclkSoftMin,
1267                                 cz_get_sclk_level(hwmgr,
1268                                 cz_hwmgr->sclk_dpm.soft_min_clk,
1269                                 PPSMC_MSG_SetSclkSoftMin));
1270
1271         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1272                                 PPSMC_MSG_SetSclkSoftMax,
1273                                 cz_get_sclk_level(hwmgr,
1274                                 cz_hwmgr->sclk_dpm.soft_max_clk,
1275                                 PPSMC_MSG_SetSclkSoftMax));
1276
1277         return 0;
1278 }
1279
1280 int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
1281 {
1282         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1283
1284         if (cz_hwmgr->sclk_dpm.soft_min_clk !=
1285                                 cz_hwmgr->sclk_dpm.soft_max_clk) {
1286                 cz_hwmgr->sclk_dpm.soft_max_clk =
1287                         cz_hwmgr->sclk_dpm.soft_min_clk;
1288
1289                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1290                                 PPSMC_MSG_SetSclkSoftMax,
1291                                 cz_get_sclk_level(hwmgr,
1292                                 cz_hwmgr->sclk_dpm.soft_max_clk,
1293                                 PPSMC_MSG_SetSclkSoftMax));
1294         }
1295
1296         return 0;
1297 }
1298
1299 static int cz_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
1300                                 enum amd_dpm_forced_level level)
1301 {
1302         int ret = 0;
1303
1304         switch (level) {
1305         case AMD_DPM_FORCED_LEVEL_HIGH:
1306                 ret = cz_phm_force_dpm_highest(hwmgr);
1307                 if (ret)
1308                         return ret;
1309                 break;
1310         case AMD_DPM_FORCED_LEVEL_LOW:
1311                 ret = cz_phm_force_dpm_lowest(hwmgr);
1312                 if (ret)
1313                         return ret;
1314                 break;
1315         case AMD_DPM_FORCED_LEVEL_AUTO:
1316                 ret = cz_phm_unforce_dpm_levels(hwmgr);
1317                 if (ret)
1318                         return ret;
1319                 break;
1320         default:
1321                 break;
1322         }
1323
1324         hwmgr->dpm_level = level;
1325
1326         return ret;
1327 }
1328
1329 int cz_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
1330 {
1331         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1332                                          PHM_PlatformCaps_UVDPowerGating))
1333                 return smum_send_msg_to_smc(hwmgr->smumgr,
1334                                                      PPSMC_MSG_UVDPowerOFF);
1335         return 0;
1336 }
1337
1338 int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
1339 {
1340         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1341                                          PHM_PlatformCaps_UVDPowerGating)) {
1342                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1343                                   PHM_PlatformCaps_UVDDynamicPowerGating)) {
1344                         return smum_send_msg_to_smc_with_parameter(
1345                                                                 hwmgr->smumgr,
1346                                                    PPSMC_MSG_UVDPowerON, 1);
1347                 } else {
1348                         return smum_send_msg_to_smc_with_parameter(
1349                                                                 hwmgr->smumgr,
1350                                                    PPSMC_MSG_UVDPowerON, 0);
1351                 }
1352         }
1353
1354         return 0;
1355 }
1356
1357 int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
1358 {
1359         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1360         struct phm_uvd_clock_voltage_dependency_table *ptable =
1361                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
1362
1363         if (!bgate) {
1364                 /* Stable Pstate is enabled and we need to set the UVD DPM to highest level */
1365                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1366                                          PHM_PlatformCaps_StablePState)) {
1367                         cz_hwmgr->uvd_dpm.hard_min_clk =
1368                                    ptable->entries[ptable->count - 1].vclk;
1369
1370                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1371                                                      PPSMC_MSG_SetUvdHardMin,
1372                                                       cz_get_uvd_level(hwmgr,
1373                                              cz_hwmgr->uvd_dpm.hard_min_clk,
1374                                                    PPSMC_MSG_SetUvdHardMin));
1375
1376                         cz_enable_disable_uvd_dpm(hwmgr, true);
1377                 } else {
1378                         cz_enable_disable_uvd_dpm(hwmgr, true);
1379                 }
1380         } else {
1381                 cz_enable_disable_uvd_dpm(hwmgr, false);
1382         }
1383
1384         return 0;
1385 }
1386
1387 int  cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
1388 {
1389         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1390         struct phm_vce_clock_voltage_dependency_table *ptable =
1391                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
1392
1393         /* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
1394         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1395                                          PHM_PlatformCaps_StablePState)) {
1396                 cz_hwmgr->vce_dpm.hard_min_clk =
1397                                   ptable->entries[ptable->count - 1].ecclk;
1398
1399                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1400                                         PPSMC_MSG_SetEclkHardMin,
1401                                         cz_get_eclk_level(hwmgr,
1402                                              cz_hwmgr->vce_dpm.hard_min_clk,
1403                                                 PPSMC_MSG_SetEclkHardMin));
1404         } else {
1405                 /*EPR# 419220 -HW limitation to to */
1406                 cz_hwmgr->vce_dpm.hard_min_clk = hwmgr->vce_arbiter.ecclk;
1407                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1408                                             PPSMC_MSG_SetEclkHardMin,
1409                                             cz_get_eclk_level(hwmgr,
1410                                      cz_hwmgr->vce_dpm.hard_min_clk,
1411                                           PPSMC_MSG_SetEclkHardMin));
1412
1413         }
1414         return 0;
1415 }
1416
1417 int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr)
1418 {
1419         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1420                                          PHM_PlatformCaps_VCEPowerGating))
1421                 return smum_send_msg_to_smc(hwmgr->smumgr,
1422                                                      PPSMC_MSG_VCEPowerOFF);
1423         return 0;
1424 }
1425
1426 int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr)
1427 {
1428         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1429                                          PHM_PlatformCaps_VCEPowerGating))
1430                 return smum_send_msg_to_smc(hwmgr->smumgr,
1431                                                      PPSMC_MSG_VCEPowerON);
1432         return 0;
1433 }
1434
1435 static int cz_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1436 {
1437         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1438
1439         return cz_hwmgr->sys_info.bootup_uma_clock;
1440 }
1441
1442 static int cz_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1443 {
1444         struct pp_power_state  *ps;
1445         struct cz_power_state  *cz_ps;
1446
1447         if (hwmgr == NULL)
1448                 return -EINVAL;
1449
1450         ps = hwmgr->request_ps;
1451
1452         if (ps == NULL)
1453                 return -EINVAL;
1454
1455         cz_ps = cast_PhwCzPowerState(&ps->hardware);
1456
1457         if (low)
1458                 return cz_ps->levels[0].engineClock;
1459         else
1460                 return cz_ps->levels[cz_ps->level-1].engineClock;
1461 }
1462
1463 static int cz_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
1464                                         struct pp_hw_power_state *hw_ps)
1465 {
1466         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1467         struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps);
1468
1469         cz_ps->level = 1;
1470         cz_ps->nbps_flags = 0;
1471         cz_ps->bapm_flags = 0;
1472         cz_ps->levels[0] = cz_hwmgr->boot_power_level;
1473
1474         return 0;
1475 }
1476
1477 static int cz_dpm_get_pp_table_entry_callback(
1478                                                      struct pp_hwmgr *hwmgr,
1479                                            struct pp_hw_power_state *hw_ps,
1480                                                           unsigned int index,
1481                                                      const void *clock_info)
1482 {
1483         struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps);
1484
1485         const ATOM_PPLIB_CZ_CLOCK_INFO *cz_clock_info = clock_info;
1486
1487         struct phm_clock_voltage_dependency_table *table =
1488                                     hwmgr->dyn_state.vddc_dependency_on_sclk;
1489         uint8_t clock_info_index = cz_clock_info->index;
1490
1491         if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1))
1492                 clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1);
1493
1494         cz_ps->levels[index].engineClock = table->entries[clock_info_index].clk;
1495         cz_ps->levels[index].vddcIndex = (uint8_t)table->entries[clock_info_index].v;
1496
1497         cz_ps->level = index + 1;
1498
1499         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
1500                 cz_ps->levels[index].dsDividerIndex = 5;
1501                 cz_ps->levels[index].ssDividerIndex = 5;
1502         }
1503
1504         return 0;
1505 }
1506
1507 static int cz_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
1508 {
1509         int result;
1510         unsigned long ret = 0;
1511
1512         result = pp_tables_get_num_of_entries(hwmgr, &ret);
1513
1514         return result ? 0 : ret;
1515 }
1516
1517 static int cz_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
1518                     unsigned long entry, struct pp_power_state *ps)
1519 {
1520         int result;
1521         struct cz_power_state *cz_ps;
1522
1523         ps->hardware.magic = PhwCz_Magic;
1524
1525         cz_ps = cast_PhwCzPowerState(&(ps->hardware));
1526
1527         result = pp_tables_get_entry(hwmgr, entry, ps,
1528                         cz_dpm_get_pp_table_entry_callback);
1529
1530         cz_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
1531         cz_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
1532
1533         return result;
1534 }
1535
1536 int cz_get_power_state_size(struct pp_hwmgr *hwmgr)
1537 {
1538         return sizeof(struct cz_power_state);
1539 }
1540
1541 static void cz_hw_print_display_cfg(
1542         const struct cc6_settings *cc6_settings)
1543 {
1544         PP_DBG_LOG("New Display Configuration:\n");
1545
1546         PP_DBG_LOG("   cpu_cc6_disable: %d\n",
1547                         cc6_settings->cpu_cc6_disable);
1548         PP_DBG_LOG("   cpu_pstate_disable: %d\n",
1549                         cc6_settings->cpu_pstate_disable);
1550         PP_DBG_LOG("   nb_pstate_switch_disable: %d\n",
1551                         cc6_settings->nb_pstate_switch_disable);
1552         PP_DBG_LOG("   cpu_pstate_separation_time: %d\n\n",
1553                         cc6_settings->cpu_pstate_separation_time);
1554 }
1555
1556  static int cz_set_cpu_power_state(struct pp_hwmgr *hwmgr)
1557 {
1558         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
1559         uint32_t data = 0;
1560
1561         if (hw_data->cc6_settings.cc6_setting_changed) {
1562
1563                 hw_data->cc6_settings.cc6_setting_changed = false;
1564
1565                 cz_hw_print_display_cfg(&hw_data->cc6_settings);
1566
1567                 data |= (hw_data->cc6_settings.cpu_pstate_separation_time
1568                         & PWRMGT_SEPARATION_TIME_MASK)
1569                         << PWRMGT_SEPARATION_TIME_SHIFT;
1570
1571                 data |= (hw_data->cc6_settings.cpu_cc6_disable ? 0x1 : 0x0)
1572                         << PWRMGT_DISABLE_CPU_CSTATES_SHIFT;
1573
1574                 data |= (hw_data->cc6_settings.cpu_pstate_disable ? 0x1 : 0x0)
1575                         << PWRMGT_DISABLE_CPU_PSTATES_SHIFT;
1576
1577                 PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n",
1578                         data);
1579
1580                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1581                                                 PPSMC_MSG_SetDisplaySizePowerParams,
1582                                                 data);
1583         }
1584
1585         return 0;
1586 }
1587
1588
1589 static int cz_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
1590                         bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
1591 {
1592         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
1593
1594         if (separation_time !=
1595             hw_data->cc6_settings.cpu_pstate_separation_time ||
1596             cc6_disable != hw_data->cc6_settings.cpu_cc6_disable ||
1597             pstate_disable != hw_data->cc6_settings.cpu_pstate_disable ||
1598             pstate_switch_disable != hw_data->cc6_settings.nb_pstate_switch_disable) {
1599
1600                 hw_data->cc6_settings.cc6_setting_changed = true;
1601
1602                 hw_data->cc6_settings.cpu_pstate_separation_time =
1603                         separation_time;
1604                 hw_data->cc6_settings.cpu_cc6_disable =
1605                         cc6_disable;
1606                 hw_data->cc6_settings.cpu_pstate_disable =
1607                         pstate_disable;
1608                 hw_data->cc6_settings.nb_pstate_switch_disable =
1609                         pstate_switch_disable;
1610
1611         }
1612
1613         return 0;
1614 }
1615
1616 static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr,
1617                 struct amd_pp_simple_clock_info *info)
1618 {
1619         uint32_t i;
1620         const struct phm_clock_voltage_dependency_table *table =
1621                         hwmgr->dyn_state.vddc_dep_on_dal_pwrl;
1622         const struct phm_clock_and_voltage_limits *limits =
1623                         &hwmgr->dyn_state.max_clock_voltage_on_ac;
1624
1625         info->engine_max_clock = limits->sclk;
1626         info->memory_max_clock = limits->mclk;
1627
1628         for (i = table->count - 1; i > 0; i--) {
1629                 if (limits->vddc >= table->entries[i].v) {
1630                         info->level = table->entries[i].clk;
1631                         return 0;
1632                 }
1633         }
1634         return -EINVAL;
1635 }
1636
1637 static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
1638                 enum pp_clock_type type, uint32_t mask)
1639 {
1640         if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1641                 return -EINVAL;
1642
1643         switch (type) {
1644         case PP_SCLK:
1645                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1646                                 PPSMC_MSG_SetSclkSoftMin,
1647                                 mask);
1648                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1649                                 PPSMC_MSG_SetSclkSoftMax,
1650                                 mask);
1651                 break;
1652         default:
1653                 break;
1654         }
1655
1656         return 0;
1657 }
1658
1659 static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
1660                 enum pp_clock_type type, char *buf)
1661 {
1662         struct phm_clock_voltage_dependency_table *sclk_table =
1663                         hwmgr->dyn_state.vddc_dependency_on_sclk;
1664         int i, now, size = 0;
1665
1666         switch (type) {
1667         case PP_SCLK:
1668                 now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
1669                                 CGS_IND_REG__SMC,
1670                                 ixTARGET_AND_CURRENT_PROFILE_INDEX),
1671                                 TARGET_AND_CURRENT_PROFILE_INDEX,
1672                                 CURR_SCLK_INDEX);
1673
1674                 for (i = 0; i < sclk_table->count; i++)
1675                         size += sprintf(buf + size, "%d: %uMhz %s\n",
1676                                         i, sclk_table->entries[i].clk / 100,
1677                                         (i == now) ? "*" : "");
1678                 break;
1679         default:
1680                 break;
1681         }
1682         return size;
1683 }
1684
1685 static int cz_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
1686                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
1687                                 PHM_PerformanceLevel *level)
1688 {
1689         const struct cz_power_state *ps;
1690         struct cz_hwmgr *data;
1691         uint32_t level_index;
1692         uint32_t i;
1693
1694         if (level == NULL || hwmgr == NULL || state == NULL)
1695                 return -EINVAL;
1696
1697         data = (struct cz_hwmgr *)(hwmgr->backend);
1698         ps = cast_const_PhwCzPowerState(state);
1699
1700         level_index = index > ps->level - 1 ? ps->level - 1 : index;
1701         level->coreClock = ps->levels[level_index].engineClock;
1702
1703         if (designation == PHM_PerformanceLevelDesignation_PowerContainment) {
1704                 for (i = 1; i < ps->level; i++) {
1705                         if (ps->levels[i].engineClock > data->dce_slow_sclk_threshold) {
1706                                 level->coreClock = ps->levels[i].engineClock;
1707                                 break;
1708                         }
1709                 }
1710         }
1711
1712         if (level_index == 0)
1713                 level->memory_clock = data->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1];
1714         else
1715                 level->memory_clock = data->sys_info.nbp_memory_clock[0];
1716
1717         level->vddc = (cz_convert_8Bit_index_to_voltage(hwmgr, ps->levels[level_index].vddcIndex) + 2) / 4;
1718         level->nonLocalMemoryFreq = 0;
1719         level->nonLocalMemoryWidth = 0;
1720
1721         return 0;
1722 }
1723
1724 static int cz_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
1725         const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
1726 {
1727         const struct cz_power_state *ps = cast_const_PhwCzPowerState(state);
1728
1729         clock_info->min_eng_clk = ps->levels[0].engineClock / (1 << (ps->levels[0].ssDividerIndex));
1730         clock_info->max_eng_clk = ps->levels[ps->level - 1].engineClock / (1 << (ps->levels[ps->level - 1].ssDividerIndex));
1731
1732         return 0;
1733 }
1734
1735 static int cz_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type,
1736                                                 struct amd_pp_clocks *clocks)
1737 {
1738         struct cz_hwmgr *data = (struct cz_hwmgr *)(hwmgr->backend);
1739         int i;
1740         struct phm_clock_voltage_dependency_table *table;
1741
1742         clocks->count = cz_get_max_sclk_level(hwmgr);
1743         switch (type) {
1744         case amd_pp_disp_clock:
1745                 for (i = 0; i < clocks->count; i++)
1746                         clocks->clock[i] = data->sys_info.display_clock[i];
1747                 break;
1748         case amd_pp_sys_clock:
1749                 table = hwmgr->dyn_state.vddc_dependency_on_sclk;
1750                 for (i = 0; i < clocks->count; i++)
1751                         clocks->clock[i] = table->entries[i].clk;
1752                 break;
1753         case amd_pp_mem_clock:
1754                 clocks->count = CZ_NUM_NBPMEMORYCLOCK;
1755                 for (i = 0; i < clocks->count; i++)
1756                         clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i];
1757                 break;
1758         default:
1759                 return -1;
1760         }
1761
1762         return 0;
1763 }
1764
1765 static int cz_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
1766 {
1767         struct phm_clock_voltage_dependency_table *table =
1768                                         hwmgr->dyn_state.vddc_dependency_on_sclk;
1769         unsigned long level;
1770         const struct phm_clock_and_voltage_limits *limits =
1771                         &hwmgr->dyn_state.max_clock_voltage_on_ac;
1772
1773         if ((NULL == table) || (table->count <= 0) || (clocks == NULL))
1774                 return -EINVAL;
1775
1776         level = cz_get_max_sclk_level(hwmgr) - 1;
1777
1778         if (level < table->count)
1779                 clocks->engine_max_clock = table->entries[level].clk;
1780         else
1781                 clocks->engine_max_clock = table->entries[table->count - 1].clk;
1782
1783         clocks->memory_max_clock = limits->mclk;
1784
1785         return 0;
1786 }
1787
1788 static int cz_thermal_get_temperature(struct pp_hwmgr *hwmgr)
1789 {
1790         int actual_temp = 0;
1791         uint32_t val = cgs_read_ind_register(hwmgr->device,
1792                                              CGS_IND_REG__SMC, ixTHM_TCON_CUR_TMP);
1793         uint32_t temp = PHM_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP);
1794
1795         if (PHM_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP_RANGE_SEL))
1796                 actual_temp = ((temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1797         else
1798                 actual_temp = (temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1799
1800         return actual_temp;
1801 }
1802
1803 static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_t *value)
1804 {
1805         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1806
1807         struct phm_clock_voltage_dependency_table *table =
1808                                 hwmgr->dyn_state.vddc_dependency_on_sclk;
1809
1810         struct phm_vce_clock_voltage_dependency_table *vce_table =
1811                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
1812
1813         struct phm_uvd_clock_voltage_dependency_table *uvd_table =
1814                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
1815
1816         uint32_t sclk_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX),
1817                                         TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX);
1818         uint32_t uvd_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
1819                                         TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX);
1820         uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
1821                                         TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX);
1822
1823         uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent;
1824         uint16_t vddnb, vddgfx;
1825         int result;
1826
1827         switch (idx) {
1828         case AMDGPU_PP_SENSOR_GFX_SCLK:
1829                 if (sclk_index < NUM_SCLK_LEVELS) {
1830                         sclk = table->entries[sclk_index].clk;
1831                         *value = sclk;
1832                         return 0;
1833                 }
1834                 return -EINVAL;
1835         case AMDGPU_PP_SENSOR_VDDNB:
1836                 tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) &
1837                         CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
1838                 vddnb = cz_convert_8Bit_index_to_voltage(hwmgr, tmp);
1839                 *value = vddnb;
1840                 return 0;
1841         case AMDGPU_PP_SENSOR_VDDGFX:
1842                 tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) &
1843                         CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
1844                 vddgfx = cz_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp);
1845                 *value = vddgfx;
1846                 return 0;
1847         case AMDGPU_PP_SENSOR_UVD_VCLK:
1848                 if (!cz_hwmgr->uvd_power_gated) {
1849                         if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
1850                                 return -EINVAL;
1851                         } else {
1852                                 vclk = uvd_table->entries[uvd_index].vclk;
1853                                 *value = vclk;
1854                                 return 0;
1855                         }
1856                 }
1857                 *value = 0;
1858                 return 0;
1859         case AMDGPU_PP_SENSOR_UVD_DCLK:
1860                 if (!cz_hwmgr->uvd_power_gated) {
1861                         if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
1862                                 return -EINVAL;
1863                         } else {
1864                                 dclk = uvd_table->entries[uvd_index].dclk;
1865                                 *value = dclk;
1866                                 return 0;
1867                         }
1868                 }
1869                 *value = 0;
1870                 return 0;
1871         case AMDGPU_PP_SENSOR_VCE_ECCLK:
1872                 if (!cz_hwmgr->vce_power_gated) {
1873                         if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
1874                                 return -EINVAL;
1875                         } else {
1876                                 ecclk = vce_table->entries[vce_index].ecclk;
1877                                 *value = ecclk;
1878                                 return 0;
1879                         }
1880                 }
1881                 *value = 0;
1882                 return 0;
1883         case AMDGPU_PP_SENSOR_GPU_LOAD:
1884                 result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetAverageGraphicsActivity);
1885                 if (0 == result) {
1886                         activity_percent = cgs_read_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0);
1887                         activity_percent = activity_percent > 100 ? 100 : activity_percent;
1888                 } else {
1889                         activity_percent = 50;
1890                 }
1891                 *value = activity_percent;
1892                 return 0;
1893         case AMDGPU_PP_SENSOR_UVD_POWER:
1894                 *value = cz_hwmgr->uvd_power_gated ? 0 : 1;
1895                 return 0;
1896         case AMDGPU_PP_SENSOR_VCE_POWER:
1897                 *value = cz_hwmgr->vce_power_gated ? 0 : 1;
1898                 return 0;
1899         case AMDGPU_PP_SENSOR_GPU_TEMP:
1900                 *value = cz_thermal_get_temperature(hwmgr);
1901                 return 0;
1902         default:
1903                 return -EINVAL;
1904         }
1905 }
1906
1907 static const struct pp_hwmgr_func cz_hwmgr_funcs = {
1908         .backend_init = cz_hwmgr_backend_init,
1909         .backend_fini = cz_hwmgr_backend_fini,
1910         .asic_setup = NULL,
1911         .apply_state_adjust_rules = cz_apply_state_adjust_rules,
1912         .force_dpm_level = cz_dpm_force_dpm_level,
1913         .get_power_state_size = cz_get_power_state_size,
1914         .powerdown_uvd = cz_dpm_powerdown_uvd,
1915         .powergate_uvd = cz_dpm_powergate_uvd,
1916         .powergate_vce = cz_dpm_powergate_vce,
1917         .get_mclk = cz_dpm_get_mclk,
1918         .get_sclk = cz_dpm_get_sclk,
1919         .patch_boot_state = cz_dpm_patch_boot_state,
1920         .get_pp_table_entry = cz_dpm_get_pp_table_entry,
1921         .get_num_of_pp_table_entries = cz_dpm_get_num_of_pp_table_entries,
1922         .set_cpu_power_state = cz_set_cpu_power_state,
1923         .store_cc6_data = cz_store_cc6_data,
1924         .force_clock_level = cz_force_clock_level,
1925         .print_clock_levels = cz_print_clock_levels,
1926         .get_dal_power_level = cz_get_dal_power_level,
1927         .get_performance_level = cz_get_performance_level,
1928         .get_current_shallow_sleep_clocks = cz_get_current_shallow_sleep_clocks,
1929         .get_clock_by_type = cz_get_clock_by_type,
1930         .get_max_high_clocks = cz_get_max_high_clocks,
1931         .read_sensor = cz_read_sensor,
1932 };
1933
1934 int cz_hwmgr_init(struct pp_hwmgr *hwmgr)
1935 {
1936         hwmgr->hwmgr_func = &cz_hwmgr_funcs;
1937         hwmgr->pptable_func = &pptable_funcs;
1938         return 0;
1939 }