drivers/gpu/drm/amd/powerplay/amd_powerplay.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "pp_debug.h"
  24 #include <linux/types.h>
  25 #include <linux/kernel.h>
  26 #include <linux/gfp.h>
  27 #include <linux/slab.h>
  28 #include "amd_shared.h"
  29 #include "amd_powerplay.h"
  30 #include "pp_instance.h"
  31 #include "power_state.h"
  32
  33 #define PP_DPM_DISABLED 0xCCCC
  34
  35 static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
  36                 void *input, void *output);
  37
  38 static inline int pp_check(struct pp_instance *handle)
  39 {
  40         if (handle == NULL)
  41                 return -EINVAL;
  42
  43         if (handle->hwmgr == NULL || handle->hwmgr->smumgr_funcs == NULL)
  44                 return -EINVAL;
  45
  46         if (handle->pm_en == 0)
  47                 return PP_DPM_DISABLED;
  48
  49         if (handle->hwmgr->hwmgr_func == NULL)
  50                 return PP_DPM_DISABLED;
  51
  52         return 0;
  53 }
  54
  55 static int amd_powerplay_create(struct amd_pp_init *pp_init,
  56                                 void **handle)
  57 {
  58         struct pp_instance *instance;
  59
  60         if (pp_init == NULL || handle == NULL)
  61                 return -EINVAL;
  62
  63         instance = kzalloc(sizeof(struct pp_instance), GFP_KERNEL);
  64         if (instance == NULL)
  65                 return -ENOMEM;
  66
  67         instance->chip_family = pp_init->chip_family;
  68         instance->chip_id = pp_init->chip_id;
  69         instance->pm_en = pp_init->pm_en;
  70         instance->feature_mask = pp_init->feature_mask;
  71         instance->device = pp_init->device;
  72         mutex_init(&instance->pp_lock);
  73         *handle = instance;
  74         return 0;
  75 }
  76
  77 static int amd_powerplay_destroy(void *handle)
  78 {
  79         struct pp_instance *instance = (struct pp_instance *)handle;
  80
  81         kfree(instance->hwmgr->hardcode_pp_table);
  82         instance->hwmgr->hardcode_pp_table = NULL;
  83
  84         kfree(instance->hwmgr);
  85         instance->hwmgr = NULL;
  86
  87         kfree(instance);
  88         instance = NULL;
  89         return 0;
  90 }
  91
  92 static int pp_early_init(void *handle)
  93 {
  94         int ret;
  95         struct pp_instance *pp_handle = NULL;
  96
  97         pp_handle = cgs_register_pp_handle(handle, amd_powerplay_create);
  98
  99         if (!pp_handle)
 100                 return -EINVAL;
 101
 102         ret = hwmgr_early_init(pp_handle);
 103         if (ret)
 104                 return -EINVAL;
 105
 106         return 0;
 107 }
 108
 109 static int pp_sw_init(void *handle)
 110 {
 111         struct pp_hwmgr *hwmgr;
 112         int ret = 0;
 113         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 114
 115         ret = pp_check(pp_handle);
 116
 117         if (ret >= 0) {
 118                 hwmgr = pp_handle->hwmgr;
 119
 120                 if (hwmgr->smumgr_funcs->smu_init == NULL)
 121                         return -EINVAL;
 122
 123                 ret = hwmgr->smumgr_funcs->smu_init(hwmgr);
 124
 125                 pr_info("amdgpu: powerplay sw initialized\n");
 126         }
 127         return ret;
 128 }
 129
 130 static int pp_sw_fini(void *handle)
 131 {
 132         struct pp_hwmgr *hwmgr;
 133         int ret = 0;
 134         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 135
 136         ret = pp_check(pp_handle);
 137         if (ret >= 0) {
 138                 hwmgr = pp_handle->hwmgr;
 139
 140                 if (hwmgr->smumgr_funcs->smu_fini == NULL)
 141                         return -EINVAL;
 142
 143                 ret = hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
 144         }
 145         return ret;
 146 }
 147
 148 static int pp_hw_init(void *handle)
 149 {
 150         int ret = 0;
 151         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 152         struct pp_hwmgr *hwmgr;
 153
 154         ret = pp_check(pp_handle);
 155
 156         if (ret >= 0) {
 157                 hwmgr = pp_handle->hwmgr;
 158
 159                 if (hwmgr->smumgr_funcs->start_smu == NULL)
 160                         return -EINVAL;
 161
 162                 if(hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) {
 163                         pr_err("smc start failed\n");
 164                         hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
 165                         return -EINVAL;;
 166                 }
 167                 if (ret == PP_DPM_DISABLED)
 168                         goto exit;
 169                 ret = hwmgr_hw_init(pp_handle);
 170                 if (ret)
 171                         goto exit;
 172         }
 173         return ret;
 174 exit:
 175         pp_handle->pm_en = 0;
 176         cgs_notify_dpm_enabled(hwmgr->device, false);
 177         return 0;
 178
 179 }
 180
 181 static int pp_hw_fini(void *handle)
 182 {
 183         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 184         int ret = 0;
 185
 186         ret = pp_check(pp_handle);
 187         if (ret == 0)
 188                 hwmgr_hw_fini(pp_handle);
 189
 190         return 0;
 191 }
 192
 193 static int pp_late_init(void *handle)
 194 {
 195         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 196         int ret = 0;
 197
 198         ret = pp_check(pp_handle);
 199         if (ret == 0)
 200                 pp_dpm_dispatch_tasks(pp_handle,
 201                                         AMD_PP_TASK_COMPLETE_INIT, NULL, NULL);
 202
 203         return 0;
 204 }
 205
 206 static void pp_late_fini(void *handle)
 207 {
 208         amd_powerplay_destroy(handle);
 209 }
 210
 211
 212 static bool pp_is_idle(void *handle)
 213 {
 214         return false;
 215 }
 216
 217 static int pp_wait_for_idle(void *handle)
 218 {
 219         return 0;
 220 }
 221
 222 static int pp_sw_reset(void *handle)
 223 {
 224         return 0;
 225 }
 226
 227 static int pp_set_powergating_state(void *handle,
 228                                     enum amd_powergating_state state)
 229 {
 230         struct pp_hwmgr  *hwmgr;
 231         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 232         int ret = 0;
 233
 234         ret = pp_check(pp_handle);
 235
 236         if (ret)
 237                 return ret;
 238
 239         hwmgr = pp_handle->hwmgr;
 240
 241         if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
 242                 pr_info("%s was not implemented.\n", __func__);
 243                 return 0;
 244         }
 245
 246         /* Enable/disable GFX per cu powergating through SMU */
 247         return hwmgr->hwmgr_func->enable_per_cu_power_gating(hwmgr,
 248                         state == AMD_PG_STATE_GATE);
 249 }
 250
 251 static int pp_suspend(void *handle)
 252 {
 253         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 254         int ret = 0;
 255
 256         ret = pp_check(pp_handle);
 257         if (ret == 0)
 258                 hwmgr_hw_suspend(pp_handle);
 259         return 0;
 260 }
 261
 262 static int pp_resume(void *handle)
 263 {
 264         struct pp_hwmgr  *hwmgr;
 265         int ret;
 266         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 267
 268         ret = pp_check(pp_handle);
 269
 270         if (ret < 0)
 271                 return ret;
 272
 273         hwmgr = pp_handle->hwmgr;
 274
 275         if (hwmgr->smumgr_funcs->start_smu == NULL)
 276                 return -EINVAL;
 277
 278         if (hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) {
 279                 pr_err("smc start failed\n");
 280                 hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
 281                 return -EINVAL;
 282         }
 283
 284         if (ret == PP_DPM_DISABLED)
 285                 return 0;
 286
 287         return hwmgr_hw_resume(pp_handle);
 288 }
 289
 290 const struct amd_ip_funcs pp_ip_funcs = {
 291         .name = "powerplay",
 292         .early_init = pp_early_init,
 293         .late_init = pp_late_init,
 294         .sw_init = pp_sw_init,
 295         .sw_fini = pp_sw_fini,
 296         .hw_init = pp_hw_init,
 297         .hw_fini = pp_hw_fini,
 298         .late_fini = pp_late_fini,
 299         .suspend = pp_suspend,
 300         .resume = pp_resume,
 301         .is_idle = pp_is_idle,
 302         .wait_for_idle = pp_wait_for_idle,
 303         .soft_reset = pp_sw_reset,
 304         .set_clockgating_state = NULL,
 305         .set_powergating_state = pp_set_powergating_state,
 306 };
 307
 308 static int pp_dpm_load_fw(void *handle)
 309 {
 310         return 0;
 311 }
 312
 313 static int pp_dpm_fw_loading_complete(void *handle)
 314 {
 315         return 0;
 316 }
 317
 318 static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)
 319 {
 320         struct pp_hwmgr  *hwmgr;
 321         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 322         int ret = 0;
 323
 324         ret = pp_check(pp_handle);
 325
 326         if (ret)
 327                 return ret;
 328
 329         hwmgr = pp_handle->hwmgr;
 330
 331         if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
 332                 pr_info("%s was not implemented.\n", __func__);
 333                 return 0;
 334         }
 335
 336         return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 337 }
 338
 339 static void pp_dpm_en_umd_pstate(struct pp_hwmgr  *hwmgr,
 340                                                 enum amd_dpm_forced_level *level)
 341 {
 342         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
 343                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
 344                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
 345                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 346
 347         if (!(hwmgr->dpm_level & profile_mode_mask)) {
 348                 /* enter umd pstate, save current level, disable gfx cg*/
 349                 if (*level & profile_mode_mask) {
 350                         hwmgr->saved_dpm_level = hwmgr->dpm_level;
 351                         hwmgr->en_umd_pstate = true;
 352                         cgs_set_clockgating_state(hwmgr->device,
 353                                                 AMD_IP_BLOCK_TYPE_GFX,
 354                                                 AMD_CG_STATE_UNGATE);
 355                         cgs_set_powergating_state(hwmgr->device,
 356                                         AMD_IP_BLOCK_TYPE_GFX,
 357                                         AMD_PG_STATE_UNGATE);
 358                 }
 359         } else {
 360                 /* exit umd pstate, restore level, enable gfx cg*/
 361                 if (!(*level & profile_mode_mask)) {
 362                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
 363                                 *level = hwmgr->saved_dpm_level;
 364                         hwmgr->en_umd_pstate = false;
 365                         cgs_set_clockgating_state(hwmgr->device,
 366                                         AMD_IP_BLOCK_TYPE_GFX,
 367                                         AMD_CG_STATE_GATE);
 368                         cgs_set_powergating_state(hwmgr->device,
 369                                         AMD_IP_BLOCK_TYPE_GFX,
 370                                         AMD_PG_STATE_GATE);
 371                 }
 372         }
 373 }
 374
 375 static int pp_dpm_force_performance_level(void *handle,
 376                                         enum amd_dpm_forced_level level)
 377 {
 378         struct pp_hwmgr  *hwmgr;
 379         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 380         int ret = 0;
 381
 382         ret = pp_check(pp_handle);
 383
 384         if (ret)
 385                 return ret;
 386
 387         hwmgr = pp_handle->hwmgr;
 388
 389         if (level == hwmgr->dpm_level)
 390                 return 0;
 391
 392         if (hwmgr->hwmgr_func->force_dpm_level == NULL) {
 393                 pr_info("%s was not implemented.\n", __func__);
 394                 return 0;
 395         }
 396
 397         mutex_lock(&pp_handle->pp_lock);
 398         pp_dpm_en_umd_pstate(hwmgr, &level);
 399         hwmgr->request_dpm_level = level;
 400         hwmgr_handle_task(pp_handle, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL);
 401         ret = hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
 402         if (!ret)
 403                 hwmgr->dpm_level = hwmgr->request_dpm_level;
 404
 405         mutex_unlock(&pp_handle->pp_lock);
 406         return 0;
 407 }
 408
 409 static enum amd_dpm_forced_level pp_dpm_get_performance_level(
 410                                                                 void *handle)
 411 {
 412         struct pp_hwmgr  *hwmgr;
 413         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 414         int ret = 0;
 415         enum amd_dpm_forced_level level;
 416
 417         ret = pp_check(pp_handle);
 418
 419         if (ret)
 420                 return ret;
 421
 422         hwmgr = pp_handle->hwmgr;
 423         mutex_lock(&pp_handle->pp_lock);
 424         level = hwmgr->dpm_level;
 425         mutex_unlock(&pp_handle->pp_lock);
 426         return level;
 427 }
 428
 429 static uint32_t pp_dpm_get_sclk(void *handle, bool low)
 430 {
 431         struct pp_hwmgr  *hwmgr;
 432         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 433         int ret = 0;
 434         uint32_t clk = 0;
 435
 436         ret = pp_check(pp_handle);
 437
 438         if (ret)
 439                 return ret;
 440
 441         hwmgr = pp_handle->hwmgr;
 442
 443         if (hwmgr->hwmgr_func->get_sclk == NULL) {
 444                 pr_info("%s was not implemented.\n", __func__);
 445                 return 0;
 446         }
 447         mutex_lock(&pp_handle->pp_lock);
 448         clk = hwmgr->hwmgr_func->get_sclk(hwmgr, low);
 449         mutex_unlock(&pp_handle->pp_lock);
 450         return clk;
 451 }
 452
 453 static uint32_t pp_dpm_get_mclk(void *handle, bool low)
 454 {
 455         struct pp_hwmgr  *hwmgr;
 456         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 457         int ret = 0;
 458         uint32_t clk = 0;
 459
 460         ret = pp_check(pp_handle);
 461
 462         if (ret)
 463                 return ret;
 464
 465         hwmgr = pp_handle->hwmgr;
 466
 467         if (hwmgr->hwmgr_func->get_mclk == NULL) {
 468                 pr_info("%s was not implemented.\n", __func__);
 469                 return 0;
 470         }
 471         mutex_lock(&pp_handle->pp_lock);
 472         clk = hwmgr->hwmgr_func->get_mclk(hwmgr, low);
 473         mutex_unlock(&pp_handle->pp_lock);
 474         return clk;
 475 }
 476
 477 static void pp_dpm_powergate_vce(void *handle, bool gate)
 478 {
 479         struct pp_hwmgr  *hwmgr;
 480         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 481         int ret = 0;
 482
 483         ret = pp_check(pp_handle);
 484
 485         if (ret)
 486                 return;
 487
 488         hwmgr = pp_handle->hwmgr;
 489
 490         if (hwmgr->hwmgr_func->powergate_vce == NULL) {
 491                 pr_info("%s was not implemented.\n", __func__);
 492                 return;
 493         }
 494         mutex_lock(&pp_handle->pp_lock);
 495         hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
 496         mutex_unlock(&pp_handle->pp_lock);
 497 }
 498
 499 static void pp_dpm_powergate_uvd(void *handle, bool gate)
 500 {
 501         struct pp_hwmgr  *hwmgr;
 502         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 503         int ret = 0;
 504
 505         ret = pp_check(pp_handle);
 506
 507         if (ret)
 508                 return;
 509
 510         hwmgr = pp_handle->hwmgr;
 511
 512         if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
 513                 pr_info("%s was not implemented.\n", __func__);
 514                 return;
 515         }
 516         mutex_lock(&pp_handle->pp_lock);
 517         hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
 518         mutex_unlock(&pp_handle->pp_lock);
 519 }
 520
 521 static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
 522                 void *input, void *output)
 523 {
 524         int ret = 0;
 525         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 526
 527         ret = pp_check(pp_handle);
 528
 529         if (ret)
 530                 return ret;
 531
 532         mutex_lock(&pp_handle->pp_lock);
 533         ret = hwmgr_handle_task(pp_handle, task_id, input, output);
 534         mutex_unlock(&pp_handle->pp_lock);
 535
 536         return ret;
 537 }
 538
 539 static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
 540 {
 541         struct pp_hwmgr *hwmgr;
 542         struct pp_power_state *state;
 543         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 544         int ret = 0;
 545         enum amd_pm_state_type pm_type;
 546
 547         ret = pp_check(pp_handle);
 548
 549         if (ret)
 550                 return ret;
 551
 552         hwmgr = pp_handle->hwmgr;
 553
 554         if (hwmgr->current_ps == NULL)
 555                 return -EINVAL;
 556
 557         mutex_lock(&pp_handle->pp_lock);
 558
 559         state = hwmgr->current_ps;
 560
 561         switch (state->classification.ui_label) {
 562         case PP_StateUILabel_Battery:
 563                 pm_type = POWER_STATE_TYPE_BATTERY;
 564                 break;
 565         case PP_StateUILabel_Balanced:
 566                 pm_type = POWER_STATE_TYPE_BALANCED;
 567                 break;
 568         case PP_StateUILabel_Performance:
 569                 pm_type = POWER_STATE_TYPE_PERFORMANCE;
 570                 break;
 571         default:
 572                 if (state->classification.flags & PP_StateClassificationFlag_Boot)
 573                         pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
 574                 else
 575                         pm_type = POWER_STATE_TYPE_DEFAULT;
 576                 break;
 577         }
 578         mutex_unlock(&pp_handle->pp_lock);
 579
 580         return pm_type;
 581 }
 582
 583 static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
 584 {
 585         struct pp_hwmgr  *hwmgr;
 586         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 587         int ret = 0;
 588
 589         ret = pp_check(pp_handle);
 590
 591         if (ret)
 592                 return;
 593
 594         hwmgr = pp_handle->hwmgr;
 595
 596         if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
 597                 pr_info("%s was not implemented.\n", __func__);
 598                 return;
 599         }
 600         mutex_lock(&pp_handle->pp_lock);
 601         hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
 602         mutex_unlock(&pp_handle->pp_lock);
 603 }
 604
 605 static uint32_t pp_dpm_get_fan_control_mode(void *handle)
 606 {
 607         struct pp_hwmgr  *hwmgr;
 608         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 609         int ret = 0;
 610         uint32_t mode = 0;
 611
 612         ret = pp_check(pp_handle);
 613
 614         if (ret)
 615                 return ret;
 616
 617         hwmgr = pp_handle->hwmgr;
 618
 619         if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
 620                 pr_info("%s was not implemented.\n", __func__);
 621                 return 0;
 622         }
 623         mutex_lock(&pp_handle->pp_lock);
 624         mode = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
 625         mutex_unlock(&pp_handle->pp_lock);
 626         return mode;
 627 }
 628
 629 static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
 630 {
 631         struct pp_hwmgr  *hwmgr;
 632         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 633         int ret = 0;
 634
 635         ret = pp_check(pp_handle);
 636
 637         if (ret)
 638                 return ret;
 639
 640         hwmgr = pp_handle->hwmgr;
 641
 642         if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
 643                 pr_info("%s was not implemented.\n", __func__);
 644                 return 0;
 645         }
 646         mutex_lock(&pp_handle->pp_lock);
 647         ret = hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent);
 648         mutex_unlock(&pp_handle->pp_lock);
 649         return ret;
 650 }
 651
 652 static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
 653 {
 654         struct pp_hwmgr  *hwmgr;
 655         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 656         int ret = 0;
 657
 658         ret = pp_check(pp_handle);
 659
 660         if (ret)
 661                 return ret;
 662
 663         hwmgr = pp_handle->hwmgr;
 664
 665         if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
 666                 pr_info("%s was not implemented.\n", __func__);
 667                 return 0;
 668         }
 669
 670         mutex_lock(&pp_handle->pp_lock);
 671         ret = hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed);
 672         mutex_unlock(&pp_handle->pp_lock);
 673         return ret;
 674 }
 675
 676 static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm)
 677 {
 678         struct pp_hwmgr *hwmgr;
 679         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 680         int ret = 0;
 681
 682         ret = pp_check(pp_handle);
 683
 684         if (ret)
 685                 return ret;
 686
 687         hwmgr = pp_handle->hwmgr;
 688
 689         if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL)
 690                 return -EINVAL;
 691
 692         mutex_lock(&pp_handle->pp_lock);
 693         ret = hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm);
 694         mutex_unlock(&pp_handle->pp_lock);
 695         return ret;
 696 }
 697
 698 static int pp_dpm_get_temperature(void *handle)
 699 {
 700         struct pp_hwmgr  *hwmgr;
 701         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 702         int ret = 0;
 703
 704         ret = pp_check(pp_handle);
 705
 706         if (ret)
 707                 return ret;
 708
 709         hwmgr = pp_handle->hwmgr;
 710
 711         if (hwmgr->hwmgr_func->get_temperature == NULL) {
 712                 pr_info("%s was not implemented.\n", __func__);
 713                 return 0;
 714         }
 715         mutex_lock(&pp_handle->pp_lock);
 716         ret = hwmgr->hwmgr_func->get_temperature(hwmgr);
 717         mutex_unlock(&pp_handle->pp_lock);
 718         return ret;
 719 }
 720
 721 static int pp_dpm_get_pp_num_states(void *handle,
 722                 struct pp_states_info *data)
 723 {
 724         struct pp_hwmgr *hwmgr;
 725         int i;
 726         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 727         int ret = 0;
 728
 729         ret = pp_check(pp_handle);
 730
 731         if (ret)
 732                 return ret;
 733
 734         hwmgr = pp_handle->hwmgr;
 735
 736         if (hwmgr->ps == NULL)
 737                 return -EINVAL;
 738
 739         mutex_lock(&pp_handle->pp_lock);
 740
 741         data->nums = hwmgr->num_ps;
 742
 743         for (i = 0; i < hwmgr->num_ps; i++) {
 744                 struct pp_power_state *state = (struct pp_power_state *)
 745                                 ((unsigned long)hwmgr->ps + i * hwmgr->ps_size);
 746                 switch (state->classification.ui_label) {
 747                 case PP_StateUILabel_Battery:
 748                         data->states[i] = POWER_STATE_TYPE_BATTERY;
 749                         break;
 750                 case PP_StateUILabel_Balanced:
 751                         data->states[i] = POWER_STATE_TYPE_BALANCED;
 752                         break;
 753                 case PP_StateUILabel_Performance:
 754                         data->states[i] = POWER_STATE_TYPE_PERFORMANCE;
 755                         break;
 756                 default:
 757                         if (state->classification.flags & PP_StateClassificationFlag_Boot)
 758                                 data->states[i] = POWER_STATE_TYPE_INTERNAL_BOOT;
 759                         else
 760                                 data->states[i] = POWER_STATE_TYPE_DEFAULT;
 761                 }
 762         }
 763         mutex_unlock(&pp_handle->pp_lock);
 764         return 0;
 765 }
 766
 767 static int pp_dpm_get_pp_table(void *handle, char **table)
 768 {
 769         struct pp_hwmgr *hwmgr;
 770         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 771         int ret = 0;
 772         int size = 0;
 773
 774         ret = pp_check(pp_handle);
 775
 776         if (ret)
 777                 return ret;
 778
 779         hwmgr = pp_handle->hwmgr;
 780
 781         if (!hwmgr->soft_pp_table)
 782                 return -EINVAL;
 783
 784         mutex_lock(&pp_handle->pp_lock);
 785         *table = (char *)hwmgr->soft_pp_table;
 786         size = hwmgr->soft_pp_table_size;
 787         mutex_unlock(&pp_handle->pp_lock);
 788         return size;
 789 }
 790
 791 static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
 792 {
 793         struct pp_hwmgr *hwmgr;
 794         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 795         int ret = 0;
 796
 797         ret = pp_check(pp_handle);
 798
 799         if (ret)
 800                 return ret;
 801
 802         hwmgr = pp_handle->hwmgr;
 803         mutex_lock(&pp_handle->pp_lock);
 804         if (!hwmgr->hardcode_pp_table) {
 805                 hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table,
 806                                                    hwmgr->soft_pp_table_size,
 807                                                    GFP_KERNEL);
 808                 if (!hwmgr->hardcode_pp_table) {
 809                         mutex_unlock(&pp_handle->pp_lock);
 810                         return -ENOMEM;
 811                 }
 812         }
 813
 814         memcpy(hwmgr->hardcode_pp_table, buf, size);
 815
 816         hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;
 817         mutex_unlock(&pp_handle->pp_lock);
 818
 819         ret = amd_powerplay_reset(handle);
 820         if (ret)
 821                 return ret;
 822
 823         if (hwmgr->hwmgr_func->avfs_control) {
 824                 ret = hwmgr->hwmgr_func->avfs_control(hwmgr, false);
 825                 if (ret)
 826                         return ret;
 827         }
 828
 829         return 0;
 830 }
 831
 832 static int pp_dpm_force_clock_level(void *handle,
 833                 enum pp_clock_type type, uint32_t mask)
 834 {
 835         struct pp_hwmgr *hwmgr;
 836         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 837         int ret = 0;
 838
 839         ret = pp_check(pp_handle);
 840
 841         if (ret)
 842                 return ret;
 843
 844         hwmgr = pp_handle->hwmgr;
 845
 846         if (hwmgr->hwmgr_func->force_clock_level == NULL) {
 847                 pr_info("%s was not implemented.\n", __func__);
 848                 return 0;
 849         }
 850         mutex_lock(&pp_handle->pp_lock);
 851         hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
 852         mutex_unlock(&pp_handle->pp_lock);
 853         return ret;
 854 }
 855
 856 static int pp_dpm_print_clock_levels(void *handle,
 857                 enum pp_clock_type type, char *buf)
 858 {
 859         struct pp_hwmgr *hwmgr;
 860         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 861         int ret = 0;
 862
 863         ret = pp_check(pp_handle);
 864
 865         if (ret)
 866                 return ret;
 867
 868         hwmgr = pp_handle->hwmgr;
 869
 870         if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
 871                 pr_info("%s was not implemented.\n", __func__);
 872                 return 0;
 873         }
 874         mutex_lock(&pp_handle->pp_lock);
 875         ret = hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
 876         mutex_unlock(&pp_handle->pp_lock);
 877         return ret;
 878 }
 879
 880 static int pp_dpm_get_sclk_od(void *handle)
 881 {
 882         struct pp_hwmgr *hwmgr;
 883         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 884         int ret = 0;
 885
 886         ret = pp_check(pp_handle);
 887
 888         if (ret)
 889                 return ret;
 890
 891         hwmgr = pp_handle->hwmgr;
 892
 893         if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
 894                 pr_info("%s was not implemented.\n", __func__);
 895                 return 0;
 896         }
 897         mutex_lock(&pp_handle->pp_lock);
 898         ret = hwmgr->hwmgr_func->get_sclk_od(hwmgr);
 899         mutex_unlock(&pp_handle->pp_lock);
 900         return ret;
 901 }
 902
 903 static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
 904 {
 905         struct pp_hwmgr *hwmgr;
 906         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 907         int ret = 0;
 908
 909         ret = pp_check(pp_handle);
 910
 911         if (ret)
 912                 return ret;
 913
 914         hwmgr = pp_handle->hwmgr;
 915
 916         if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
 917                 pr_info("%s was not implemented.\n", __func__);
 918                 return 0;
 919         }
 920
 921         mutex_lock(&pp_handle->pp_lock);
 922         ret = hwmgr->hwmgr_func->set_sclk_od(hwmgr, value);
 923         mutex_unlock(&pp_handle->pp_lock);
 924         return ret;
 925 }
 926
 927 static int pp_dpm_get_mclk_od(void *handle)
 928 {
 929         struct pp_hwmgr *hwmgr;
 930         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 931         int ret = 0;
 932
 933         ret = pp_check(pp_handle);
 934
 935         if (ret)
 936                 return ret;
 937
 938         hwmgr = pp_handle->hwmgr;
 939
 940         if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
 941                 pr_info("%s was not implemented.\n", __func__);
 942                 return 0;
 943         }
 944         mutex_lock(&pp_handle->pp_lock);
 945         ret = hwmgr->hwmgr_func->get_mclk_od(hwmgr);
 946         mutex_unlock(&pp_handle->pp_lock);
 947         return ret;
 948 }
 949
 950 static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
 951 {
 952         struct pp_hwmgr *hwmgr;
 953         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 954         int ret = 0;
 955
 956         ret = pp_check(pp_handle);
 957
 958         if (ret)
 959                 return ret;
 960
 961         hwmgr = pp_handle->hwmgr;
 962
 963         if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
 964                 pr_info("%s was not implemented.\n", __func__);
 965                 return 0;
 966         }
 967         mutex_lock(&pp_handle->pp_lock);
 968         ret = hwmgr->hwmgr_func->set_mclk_od(hwmgr, value);
 969         mutex_unlock(&pp_handle->pp_lock);
 970         return ret;
 971 }
 972
 973 static int pp_dpm_read_sensor(void *handle, int idx,
 974                               void *value, int *size)
 975 {
 976         struct pp_hwmgr *hwmgr;
 977         struct pp_instance *pp_handle = (struct pp_instance *)handle;
 978         int ret = 0;
 979
 980         ret = pp_check(pp_handle);
 981
 982         if (ret)
 983                 return ret;
 984
 985         hwmgr = pp_handle->hwmgr;
 986
 987         if (hwmgr->hwmgr_func->read_sensor == NULL) {
 988                 pr_info("%s was not implemented.\n", __func__);
 989                 return 0;
 990         }
 991
 992         mutex_lock(&pp_handle->pp_lock);
 993         ret = hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size);
 994         mutex_unlock(&pp_handle->pp_lock);
 995
 996         return ret;
 997 }
 998
 999 static struct amd_vce_state*
1000 pp_dpm_get_vce_clock_state(void *handle, unsigned idx)
1001 {
1002         struct pp_hwmgr *hwmgr;
1003         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1004         int ret = 0;
1005
1006         ret = pp_check(pp_handle);
1007
1008         if (ret)
1009                 return NULL;
1010
1011         hwmgr = pp_handle->hwmgr;
1012
1013         if (hwmgr && idx < hwmgr->num_vce_state_tables)
1014                 return &hwmgr->vce_states[idx];
1015         return NULL;
1016 }
1017
1018 static int pp_dpm_reset_power_profile_state(void *handle,
1019                 struct amd_pp_profile *request)
1020 {
1021         struct pp_hwmgr *hwmgr;
1022         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1023
1024         if (!request || pp_check(pp_handle))
1025                 return -EINVAL;
1026
1027         hwmgr = pp_handle->hwmgr;
1028
1029         if (hwmgr->hwmgr_func->set_power_profile_state == NULL) {
1030                 pr_info("%s was not implemented.\n", __func__);
1031                 return 0;
1032         }
1033
1034         if (request->type == AMD_PP_GFX_PROFILE) {
1035                 hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
1036                 return hwmgr->hwmgr_func->set_power_profile_state(hwmgr,
1037                                 &hwmgr->gfx_power_profile);
1038         } else if (request->type == AMD_PP_COMPUTE_PROFILE) {
1039                 hwmgr->compute_power_profile =
1040                                 hwmgr->default_compute_power_profile;
1041                 return hwmgr->hwmgr_func->set_power_profile_state(hwmgr,
1042                                 &hwmgr->compute_power_profile);
1043         } else
1044                 return -EINVAL;
1045 }
1046
1047 static int pp_dpm_get_power_profile_state(void *handle,
1048                 struct amd_pp_profile *query)
1049 {
1050         struct pp_hwmgr *hwmgr;
1051         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1052
1053         if (!query || pp_check(pp_handle))
1054                 return -EINVAL;
1055
1056         hwmgr = pp_handle->hwmgr;
1057
1058         if (query->type == AMD_PP_GFX_PROFILE)
1059                 memcpy(query, &hwmgr->gfx_power_profile,
1060                                 sizeof(struct amd_pp_profile));
1061         else if (query->type == AMD_PP_COMPUTE_PROFILE)
1062                 memcpy(query, &hwmgr->compute_power_profile,
1063                                 sizeof(struct amd_pp_profile));
1064         else
1065                 return -EINVAL;
1066
1067         return 0;
1068 }
1069
1070 static int pp_dpm_set_power_profile_state(void *handle,
1071                 struct amd_pp_profile *request)
1072 {
1073         struct pp_hwmgr *hwmgr;
1074         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1075         int ret = -1;
1076
1077         if (!request || pp_check(pp_handle))
1078                 return -EINVAL;
1079
1080         hwmgr = pp_handle->hwmgr;
1081
1082         if (hwmgr->hwmgr_func->set_power_profile_state == NULL) {
1083                 pr_info("%s was not implemented.\n", __func__);
1084                 return 0;
1085         }
1086
1087         if (request->min_sclk ||
1088                 request->min_mclk ||
1089                 request->activity_threshold ||
1090                 request->up_hyst ||
1091                 request->down_hyst) {
1092                 if (request->type == AMD_PP_GFX_PROFILE)
1093                         memcpy(&hwmgr->gfx_power_profile, request,
1094                                         sizeof(struct amd_pp_profile));
1095                 else if (request->type == AMD_PP_COMPUTE_PROFILE)
1096                         memcpy(&hwmgr->compute_power_profile, request,
1097                                         sizeof(struct amd_pp_profile));
1098                 else
1099                         return -EINVAL;
1100
1101                 if (request->type == hwmgr->current_power_profile)
1102                         ret = hwmgr->hwmgr_func->set_power_profile_state(
1103                                         hwmgr,
1104                                         request);
1105         } else {
1106                 /* set power profile if it exists */
1107                 switch (request->type) {
1108                 case AMD_PP_GFX_PROFILE:
1109                         ret = hwmgr->hwmgr_func->set_power_profile_state(
1110                                         hwmgr,
1111                                         &hwmgr->gfx_power_profile);
1112                         break;
1113                 case AMD_PP_COMPUTE_PROFILE:
1114                         ret = hwmgr->hwmgr_func->set_power_profile_state(
1115                                         hwmgr,
1116                                         &hwmgr->compute_power_profile);
1117                         break;
1118                 default:
1119                         return -EINVAL;
1120                 }
1121         }
1122
1123         if (!ret)
1124                 hwmgr->current_power_profile = request->type;
1125
1126         return 0;
1127 }
1128
1129 static int pp_dpm_switch_power_profile(void *handle,
1130                 enum amd_pp_profile_type type)
1131 {
1132         struct pp_hwmgr *hwmgr;
1133         struct amd_pp_profile request = {0};
1134         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1135
1136         if (pp_check(pp_handle))
1137                 return -EINVAL;
1138
1139         hwmgr = pp_handle->hwmgr;
1140
1141         if (hwmgr->current_power_profile != type) {
1142                 request.type = type;
1143                 pp_dpm_set_power_profile_state(handle, &request);
1144         }
1145
1146         return 0;
1147 }
1148
1149 const struct amd_pm_funcs pp_dpm_funcs = {
1150         .get_temperature = pp_dpm_get_temperature,
1151         .load_firmware = pp_dpm_load_fw,
1152         .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
1153         .force_performance_level = pp_dpm_force_performance_level,
1154         .get_performance_level = pp_dpm_get_performance_level,
1155         .get_current_power_state = pp_dpm_get_current_power_state,
1156         .get_sclk = pp_dpm_get_sclk,
1157         .get_mclk = pp_dpm_get_mclk,
1158         .powergate_vce = pp_dpm_powergate_vce,
1159         .powergate_uvd = pp_dpm_powergate_uvd,
1160         .dispatch_tasks = pp_dpm_dispatch_tasks,
1161         .set_fan_control_mode = pp_dpm_set_fan_control_mode,
1162         .get_fan_control_mode = pp_dpm_get_fan_control_mode,
1163         .set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
1164         .get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
1165         .get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm,
1166         .get_pp_num_states = pp_dpm_get_pp_num_states,
1167         .get_pp_table = pp_dpm_get_pp_table,
1168         .set_pp_table = pp_dpm_set_pp_table,
1169         .force_clock_level = pp_dpm_force_clock_level,
1170         .print_clock_levels = pp_dpm_print_clock_levels,
1171         .get_sclk_od = pp_dpm_get_sclk_od,
1172         .set_sclk_od = pp_dpm_set_sclk_od,
1173         .get_mclk_od = pp_dpm_get_mclk_od,
1174         .set_mclk_od = pp_dpm_set_mclk_od,
1175         .read_sensor = pp_dpm_read_sensor,
1176         .get_vce_clock_state = pp_dpm_get_vce_clock_state,
1177         .reset_power_profile_state = pp_dpm_reset_power_profile_state,
1178         .get_power_profile_state = pp_dpm_get_power_profile_state,
1179         .set_power_profile_state = pp_dpm_set_power_profile_state,
1180         .switch_power_profile = pp_dpm_switch_power_profile,
1181         .set_clockgating_by_smu = pp_set_clockgating_by_smu,
1182 };
1183
1184 int amd_powerplay_reset(void *handle)
1185 {
1186         struct pp_instance *instance = (struct pp_instance *)handle;
1187         int ret;
1188
1189         ret = pp_check(instance);
1190         if (ret)
1191                 return ret;
1192
1193         ret = pp_hw_fini(instance);
1194         if (ret)
1195                 return ret;
1196
1197         ret = hwmgr_hw_init(instance);
1198         if (ret)
1199                 return ret;
1200
1201         return hwmgr_handle_task(instance, AMD_PP_TASK_COMPLETE_INIT, NULL, NULL);
1202 }
1203
1204 /* export this function to DAL */
1205
1206 int amd_powerplay_display_configuration_change(void *handle,
1207         const struct amd_pp_display_configuration *display_config)
1208 {
1209         struct pp_hwmgr  *hwmgr;
1210         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1211         int ret = 0;
1212
1213         ret = pp_check(pp_handle);
1214
1215         if (ret)
1216                 return ret;
1217
1218         hwmgr = pp_handle->hwmgr;
1219         mutex_lock(&pp_handle->pp_lock);
1220         phm_store_dal_configuration_data(hwmgr, display_config);
1221         mutex_unlock(&pp_handle->pp_lock);
1222         return 0;
1223 }
1224
1225 int amd_powerplay_get_display_power_level(void *handle,
1226                 struct amd_pp_simple_clock_info *output)
1227 {
1228         struct pp_hwmgr  *hwmgr;
1229         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1230         int ret = 0;
1231
1232         ret = pp_check(pp_handle);
1233
1234         if (ret)
1235                 return ret;
1236
1237         hwmgr = pp_handle->hwmgr;
1238
1239         if (output == NULL)
1240                 return -EINVAL;
1241
1242         mutex_lock(&pp_handle->pp_lock);
1243         ret = phm_get_dal_power_level(hwmgr, output);
1244         mutex_unlock(&pp_handle->pp_lock);
1245         return ret;
1246 }
1247
1248 int amd_powerplay_get_current_clocks(void *handle,
1249                 struct amd_pp_clock_info *clocks)
1250 {
1251         struct amd_pp_simple_clock_info simple_clocks;
1252         struct pp_clock_info hw_clocks;
1253         struct pp_hwmgr  *hwmgr;
1254         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1255         int ret = 0;
1256
1257         ret = pp_check(pp_handle);
1258
1259         if (ret)
1260                 return ret;
1261
1262         hwmgr = pp_handle->hwmgr;
1263
1264         mutex_lock(&pp_handle->pp_lock);
1265
1266         phm_get_dal_power_level(hwmgr, &simple_clocks);
1267
1268         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1269                                         PHM_PlatformCaps_PowerContainment))
1270                 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware,
1271                                         &hw_clocks, PHM_PerformanceLevelDesignation_PowerContainment);
1272         else
1273                 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware,
1274                                         &hw_clocks, PHM_PerformanceLevelDesignation_Activity);
1275
1276         if (ret) {
1277                 pr_info("Error in phm_get_clock_info \n");
1278                 mutex_unlock(&pp_handle->pp_lock);
1279                 return -EINVAL;
1280         }
1281
1282         clocks->min_engine_clock = hw_clocks.min_eng_clk;
1283         clocks->max_engine_clock = hw_clocks.max_eng_clk;
1284         clocks->min_memory_clock = hw_clocks.min_mem_clk;
1285         clocks->max_memory_clock = hw_clocks.max_mem_clk;
1286         clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1287         clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1288
1289         clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1290         clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1291
1292         clocks->max_clocks_state = simple_clocks.level;
1293
1294         if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) {
1295                 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1296                 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1297         }
1298         mutex_unlock(&pp_handle->pp_lock);
1299         return 0;
1300 }
1301
1302 int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
1303 {
1304         struct pp_hwmgr  *hwmgr;
1305         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1306         int ret = 0;
1307
1308         ret = pp_check(pp_handle);
1309
1310         if (ret)
1311                 return ret;
1312
1313         hwmgr = pp_handle->hwmgr;
1314
1315         if (clocks == NULL)
1316                 return -EINVAL;
1317
1318         mutex_lock(&pp_handle->pp_lock);
1319         ret = phm_get_clock_by_type(hwmgr, type, clocks);
1320         mutex_unlock(&pp_handle->pp_lock);
1321         return ret;
1322 }
1323
1324 int amd_powerplay_get_clock_by_type_with_latency(void *handle,
1325                 enum amd_pp_clock_type type,
1326                 struct pp_clock_levels_with_latency *clocks)
1327 {
1328         struct pp_hwmgr *hwmgr;
1329         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1330         int ret = 0;
1331
1332         ret = pp_check(pp_handle);
1333         if (ret)
1334                 return ret;
1335
1336         if (!clocks)
1337                 return -EINVAL;
1338
1339         mutex_lock(&pp_handle->pp_lock);
1340         hwmgr = ((struct pp_instance *)handle)->hwmgr;
1341         ret = phm_get_clock_by_type_with_latency(hwmgr, type, clocks);
1342         mutex_unlock(&pp_handle->pp_lock);
1343         return ret;
1344 }
1345
1346 int amd_powerplay_get_clock_by_type_with_voltage(void *handle,
1347                 enum amd_pp_clock_type type,
1348                 struct pp_clock_levels_with_voltage *clocks)
1349 {
1350         struct pp_hwmgr *hwmgr;
1351         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1352         int ret = 0;
1353
1354         ret = pp_check(pp_handle);
1355         if (ret)
1356                 return ret;
1357
1358         if (!clocks)
1359                 return -EINVAL;
1360
1361         hwmgr = ((struct pp_instance *)handle)->hwmgr;
1362
1363         mutex_lock(&pp_handle->pp_lock);
1364
1365         ret = phm_get_clock_by_type_with_voltage(hwmgr, type, clocks);
1366
1367         mutex_unlock(&pp_handle->pp_lock);
1368         return ret;
1369 }
1370
1371 int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle,
1372                 struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
1373 {
1374         struct pp_hwmgr *hwmgr;
1375         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1376         int ret = 0;
1377
1378         ret = pp_check(pp_handle);
1379         if (ret)
1380                 return ret;
1381
1382         if (!wm_with_clock_ranges)
1383                 return -EINVAL;
1384
1385         hwmgr = ((struct pp_instance *)handle)->hwmgr;
1386
1387         mutex_lock(&pp_handle->pp_lock);
1388         ret = phm_set_watermarks_for_clocks_ranges(hwmgr,
1389                         wm_with_clock_ranges);
1390         mutex_unlock(&pp_handle->pp_lock);
1391
1392         return ret;
1393 }
1394
1395 int amd_powerplay_display_clock_voltage_request(void *handle,
1396                 struct pp_display_clock_request *clock)
1397 {
1398         struct pp_hwmgr *hwmgr;
1399         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1400         int ret = 0;
1401
1402         ret = pp_check(pp_handle);
1403         if (ret)
1404                 return ret;
1405
1406         if (!clock)
1407                 return -EINVAL;
1408
1409         hwmgr = ((struct pp_instance *)handle)->hwmgr;
1410
1411         mutex_lock(&pp_handle->pp_lock);
1412         ret = phm_display_clock_voltage_request(hwmgr, clock);
1413         mutex_unlock(&pp_handle->pp_lock);
1414
1415         return ret;
1416 }
1417
1418 int amd_powerplay_get_display_mode_validation_clocks(void *handle,
1419                 struct amd_pp_simple_clock_info *clocks)
1420 {
1421         struct pp_hwmgr  *hwmgr;
1422         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1423         int ret = 0;
1424
1425         ret = pp_check(pp_handle);
1426
1427         if (ret)
1428                 return ret;
1429
1430         hwmgr = pp_handle->hwmgr;
1431
1432         if (clocks == NULL)
1433                 return -EINVAL;
1434
1435         mutex_lock(&pp_handle->pp_lock);
1436
1437         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
1438                 ret = phm_get_max_high_clocks(hwmgr, clocks);
1439
1440         mutex_unlock(&pp_handle->pp_lock);
1441         return ret;
1442 }
1443