2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/gfp.h>
27 #include <linux/slab.h>
28 #include "amd_shared.h"
29 #include "amd_powerplay.h"
30 #include "pp_instance.h"
31 #include "power_state.h"
33 #define PP_DPM_DISABLED 0xCCCC
35 static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
36 void *input, void *output);
38 static inline int pp_check(struct pp_instance *handle)
43 if (handle->hwmgr == NULL || handle->hwmgr->smumgr_funcs == NULL)
46 if (handle->pm_en == 0)
47 return PP_DPM_DISABLED;
49 if (handle->hwmgr->hwmgr_func == NULL)
50 return PP_DPM_DISABLED;
55 static int amd_powerplay_create(struct amd_pp_init *pp_init,
58 struct pp_instance *instance;
60 if (pp_init == NULL || handle == NULL)
63 instance = kzalloc(sizeof(struct pp_instance), GFP_KERNEL);
67 instance->chip_family = pp_init->chip_family;
68 instance->chip_id = pp_init->chip_id;
69 instance->pm_en = pp_init->pm_en;
70 instance->feature_mask = pp_init->feature_mask;
71 instance->device = pp_init->device;
72 mutex_init(&instance->pp_lock);
77 static int amd_powerplay_destroy(void *handle)
79 struct pp_instance *instance = (struct pp_instance *)handle;
81 kfree(instance->hwmgr->hardcode_pp_table);
82 instance->hwmgr->hardcode_pp_table = NULL;
84 kfree(instance->hwmgr);
85 instance->hwmgr = NULL;
92 static int pp_early_init(void *handle)
95 struct pp_instance *pp_handle = NULL;
97 pp_handle = cgs_register_pp_handle(handle, amd_powerplay_create);
102 ret = hwmgr_early_init(pp_handle);
109 static int pp_sw_init(void *handle)
111 struct pp_hwmgr *hwmgr;
113 struct pp_instance *pp_handle = (struct pp_instance *)handle;
115 ret = pp_check(pp_handle);
118 hwmgr = pp_handle->hwmgr;
120 if (hwmgr->smumgr_funcs->smu_init == NULL)
123 ret = hwmgr->smumgr_funcs->smu_init(hwmgr);
125 pr_debug("amdgpu: powerplay sw initialized\n");
130 static int pp_sw_fini(void *handle)
132 struct pp_hwmgr *hwmgr;
134 struct pp_instance *pp_handle = (struct pp_instance *)handle;
136 ret = pp_check(pp_handle);
138 hwmgr = pp_handle->hwmgr;
140 if (hwmgr->smumgr_funcs->smu_fini == NULL)
143 ret = hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
148 static int pp_hw_init(void *handle)
151 struct pp_instance *pp_handle = (struct pp_instance *)handle;
152 struct pp_hwmgr *hwmgr;
154 ret = pp_check(pp_handle);
157 hwmgr = pp_handle->hwmgr;
159 if (hwmgr->smumgr_funcs->start_smu == NULL)
162 if(hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) {
163 pr_err("smc start failed\n");
164 hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
167 if (ret == PP_DPM_DISABLED)
169 ret = hwmgr_hw_init(pp_handle);
175 pp_handle->pm_en = 0;
176 cgs_notify_dpm_enabled(hwmgr->device, false);
181 static int pp_hw_fini(void *handle)
183 struct pp_instance *pp_handle = (struct pp_instance *)handle;
186 ret = pp_check(pp_handle);
188 hwmgr_hw_fini(pp_handle);
193 static int pp_late_init(void *handle)
195 struct pp_instance *pp_handle = (struct pp_instance *)handle;
198 ret = pp_check(pp_handle);
200 pp_dpm_dispatch_tasks(pp_handle,
201 AMD_PP_TASK_COMPLETE_INIT, NULL, NULL);
206 static void pp_late_fini(void *handle)
208 amd_powerplay_destroy(handle);
212 static bool pp_is_idle(void *handle)
217 static int pp_wait_for_idle(void *handle)
222 static int pp_sw_reset(void *handle)
227 static int pp_set_powergating_state(void *handle,
228 enum amd_powergating_state state)
230 struct pp_hwmgr *hwmgr;
231 struct pp_instance *pp_handle = (struct pp_instance *)handle;
234 ret = pp_check(pp_handle);
239 hwmgr = pp_handle->hwmgr;
241 if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
242 pr_info("%s was not implemented.\n", __func__);
246 /* Enable/disable GFX per cu powergating through SMU */
247 return hwmgr->hwmgr_func->enable_per_cu_power_gating(hwmgr,
248 state == AMD_PG_STATE_GATE);
251 static int pp_suspend(void *handle)
253 struct pp_instance *pp_handle = (struct pp_instance *)handle;
256 ret = pp_check(pp_handle);
258 hwmgr_hw_suspend(pp_handle);
262 static int pp_resume(void *handle)
264 struct pp_hwmgr *hwmgr;
266 struct pp_instance *pp_handle = (struct pp_instance *)handle;
268 ret = pp_check(pp_handle);
273 hwmgr = pp_handle->hwmgr;
275 if (hwmgr->smumgr_funcs->start_smu == NULL)
278 if (hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) {
279 pr_err("smc start failed\n");
280 hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
284 if (ret == PP_DPM_DISABLED)
287 return hwmgr_hw_resume(pp_handle);
290 const struct amd_ip_funcs pp_ip_funcs = {
292 .early_init = pp_early_init,
293 .late_init = pp_late_init,
294 .sw_init = pp_sw_init,
295 .sw_fini = pp_sw_fini,
296 .hw_init = pp_hw_init,
297 .hw_fini = pp_hw_fini,
298 .late_fini = pp_late_fini,
299 .suspend = pp_suspend,
301 .is_idle = pp_is_idle,
302 .wait_for_idle = pp_wait_for_idle,
303 .soft_reset = pp_sw_reset,
304 .set_clockgating_state = NULL,
305 .set_powergating_state = pp_set_powergating_state,
308 static int pp_dpm_load_fw(void *handle)
313 static int pp_dpm_fw_loading_complete(void *handle)
318 static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)
320 struct pp_hwmgr *hwmgr;
321 struct pp_instance *pp_handle = (struct pp_instance *)handle;
324 ret = pp_check(pp_handle);
329 hwmgr = pp_handle->hwmgr;
331 if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
332 pr_info("%s was not implemented.\n", __func__);
336 return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
339 static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr,
340 enum amd_dpm_forced_level *level)
342 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
343 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
344 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
345 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
347 if (!(hwmgr->dpm_level & profile_mode_mask)) {
348 /* enter umd pstate, save current level, disable gfx cg*/
349 if (*level & profile_mode_mask) {
350 hwmgr->saved_dpm_level = hwmgr->dpm_level;
351 hwmgr->en_umd_pstate = true;
352 cgs_set_clockgating_state(hwmgr->device,
353 AMD_IP_BLOCK_TYPE_GFX,
354 AMD_CG_STATE_UNGATE);
355 cgs_set_powergating_state(hwmgr->device,
356 AMD_IP_BLOCK_TYPE_GFX,
357 AMD_PG_STATE_UNGATE);
360 /* exit umd pstate, restore level, enable gfx cg*/
361 if (!(*level & profile_mode_mask)) {
362 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
363 *level = hwmgr->saved_dpm_level;
364 hwmgr->en_umd_pstate = false;
365 cgs_set_clockgating_state(hwmgr->device,
366 AMD_IP_BLOCK_TYPE_GFX,
368 cgs_set_powergating_state(hwmgr->device,
369 AMD_IP_BLOCK_TYPE_GFX,
375 static int pp_dpm_force_performance_level(void *handle,
376 enum amd_dpm_forced_level level)
378 struct pp_hwmgr *hwmgr;
379 struct pp_instance *pp_handle = (struct pp_instance *)handle;
382 ret = pp_check(pp_handle);
387 hwmgr = pp_handle->hwmgr;
389 if (level == hwmgr->dpm_level)
392 mutex_lock(&pp_handle->pp_lock);
393 pp_dpm_en_umd_pstate(hwmgr, &level);
394 hwmgr->request_dpm_level = level;
395 hwmgr_handle_task(pp_handle, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL);
396 mutex_unlock(&pp_handle->pp_lock);
401 static enum amd_dpm_forced_level pp_dpm_get_performance_level(
404 struct pp_hwmgr *hwmgr;
405 struct pp_instance *pp_handle = (struct pp_instance *)handle;
407 enum amd_dpm_forced_level level;
409 ret = pp_check(pp_handle);
414 hwmgr = pp_handle->hwmgr;
415 mutex_lock(&pp_handle->pp_lock);
416 level = hwmgr->dpm_level;
417 mutex_unlock(&pp_handle->pp_lock);
421 static uint32_t pp_dpm_get_sclk(void *handle, bool low)
423 struct pp_hwmgr *hwmgr;
424 struct pp_instance *pp_handle = (struct pp_instance *)handle;
428 ret = pp_check(pp_handle);
433 hwmgr = pp_handle->hwmgr;
435 if (hwmgr->hwmgr_func->get_sclk == NULL) {
436 pr_info("%s was not implemented.\n", __func__);
439 mutex_lock(&pp_handle->pp_lock);
440 clk = hwmgr->hwmgr_func->get_sclk(hwmgr, low);
441 mutex_unlock(&pp_handle->pp_lock);
445 static uint32_t pp_dpm_get_mclk(void *handle, bool low)
447 struct pp_hwmgr *hwmgr;
448 struct pp_instance *pp_handle = (struct pp_instance *)handle;
452 ret = pp_check(pp_handle);
457 hwmgr = pp_handle->hwmgr;
459 if (hwmgr->hwmgr_func->get_mclk == NULL) {
460 pr_info("%s was not implemented.\n", __func__);
463 mutex_lock(&pp_handle->pp_lock);
464 clk = hwmgr->hwmgr_func->get_mclk(hwmgr, low);
465 mutex_unlock(&pp_handle->pp_lock);
469 static void pp_dpm_powergate_vce(void *handle, bool gate)
471 struct pp_hwmgr *hwmgr;
472 struct pp_instance *pp_handle = (struct pp_instance *)handle;
475 ret = pp_check(pp_handle);
480 hwmgr = pp_handle->hwmgr;
482 if (hwmgr->hwmgr_func->powergate_vce == NULL) {
483 pr_info("%s was not implemented.\n", __func__);
486 mutex_lock(&pp_handle->pp_lock);
487 hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
488 mutex_unlock(&pp_handle->pp_lock);
491 static void pp_dpm_powergate_uvd(void *handle, bool gate)
493 struct pp_hwmgr *hwmgr;
494 struct pp_instance *pp_handle = (struct pp_instance *)handle;
497 ret = pp_check(pp_handle);
502 hwmgr = pp_handle->hwmgr;
504 if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
505 pr_info("%s was not implemented.\n", __func__);
508 mutex_lock(&pp_handle->pp_lock);
509 hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
510 mutex_unlock(&pp_handle->pp_lock);
513 static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
514 void *input, void *output)
517 struct pp_instance *pp_handle = (struct pp_instance *)handle;
519 ret = pp_check(pp_handle);
524 mutex_lock(&pp_handle->pp_lock);
525 ret = hwmgr_handle_task(pp_handle, task_id, input, output);
526 mutex_unlock(&pp_handle->pp_lock);
531 static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
533 struct pp_hwmgr *hwmgr;
534 struct pp_power_state *state;
535 struct pp_instance *pp_handle = (struct pp_instance *)handle;
537 enum amd_pm_state_type pm_type;
539 ret = pp_check(pp_handle);
544 hwmgr = pp_handle->hwmgr;
546 if (hwmgr->current_ps == NULL)
549 mutex_lock(&pp_handle->pp_lock);
551 state = hwmgr->current_ps;
553 switch (state->classification.ui_label) {
554 case PP_StateUILabel_Battery:
555 pm_type = POWER_STATE_TYPE_BATTERY;
557 case PP_StateUILabel_Balanced:
558 pm_type = POWER_STATE_TYPE_BALANCED;
560 case PP_StateUILabel_Performance:
561 pm_type = POWER_STATE_TYPE_PERFORMANCE;
564 if (state->classification.flags & PP_StateClassificationFlag_Boot)
565 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
567 pm_type = POWER_STATE_TYPE_DEFAULT;
570 mutex_unlock(&pp_handle->pp_lock);
575 static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
577 struct pp_hwmgr *hwmgr;
578 struct pp_instance *pp_handle = (struct pp_instance *)handle;
581 ret = pp_check(pp_handle);
586 hwmgr = pp_handle->hwmgr;
588 if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
589 pr_info("%s was not implemented.\n", __func__);
592 mutex_lock(&pp_handle->pp_lock);
593 hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
594 mutex_unlock(&pp_handle->pp_lock);
597 static uint32_t pp_dpm_get_fan_control_mode(void *handle)
599 struct pp_hwmgr *hwmgr;
600 struct pp_instance *pp_handle = (struct pp_instance *)handle;
604 ret = pp_check(pp_handle);
609 hwmgr = pp_handle->hwmgr;
611 if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
612 pr_info("%s was not implemented.\n", __func__);
615 mutex_lock(&pp_handle->pp_lock);
616 mode = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
617 mutex_unlock(&pp_handle->pp_lock);
621 static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
623 struct pp_hwmgr *hwmgr;
624 struct pp_instance *pp_handle = (struct pp_instance *)handle;
627 ret = pp_check(pp_handle);
632 hwmgr = pp_handle->hwmgr;
634 if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
635 pr_info("%s was not implemented.\n", __func__);
638 mutex_lock(&pp_handle->pp_lock);
639 ret = hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent);
640 mutex_unlock(&pp_handle->pp_lock);
644 static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
646 struct pp_hwmgr *hwmgr;
647 struct pp_instance *pp_handle = (struct pp_instance *)handle;
650 ret = pp_check(pp_handle);
655 hwmgr = pp_handle->hwmgr;
657 if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
658 pr_info("%s was not implemented.\n", __func__);
662 mutex_lock(&pp_handle->pp_lock);
663 ret = hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed);
664 mutex_unlock(&pp_handle->pp_lock);
668 static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm)
670 struct pp_hwmgr *hwmgr;
671 struct pp_instance *pp_handle = (struct pp_instance *)handle;
674 ret = pp_check(pp_handle);
679 hwmgr = pp_handle->hwmgr;
681 if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL)
684 mutex_lock(&pp_handle->pp_lock);
685 ret = hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm);
686 mutex_unlock(&pp_handle->pp_lock);
690 static int pp_dpm_get_temperature(void *handle)
692 struct pp_hwmgr *hwmgr;
693 struct pp_instance *pp_handle = (struct pp_instance *)handle;
696 ret = pp_check(pp_handle);
701 hwmgr = pp_handle->hwmgr;
703 if (hwmgr->hwmgr_func->get_temperature == NULL) {
704 pr_info("%s was not implemented.\n", __func__);
707 mutex_lock(&pp_handle->pp_lock);
708 ret = hwmgr->hwmgr_func->get_temperature(hwmgr);
709 mutex_unlock(&pp_handle->pp_lock);
713 static int pp_dpm_get_pp_num_states(void *handle,
714 struct pp_states_info *data)
716 struct pp_hwmgr *hwmgr;
718 struct pp_instance *pp_handle = (struct pp_instance *)handle;
721 memset(data, 0, sizeof(*data));
723 ret = pp_check(pp_handle);
728 hwmgr = pp_handle->hwmgr;
730 if (hwmgr->ps == NULL)
733 mutex_lock(&pp_handle->pp_lock);
735 data->nums = hwmgr->num_ps;
737 for (i = 0; i < hwmgr->num_ps; i++) {
738 struct pp_power_state *state = (struct pp_power_state *)
739 ((unsigned long)hwmgr->ps + i * hwmgr->ps_size);
740 switch (state->classification.ui_label) {
741 case PP_StateUILabel_Battery:
742 data->states[i] = POWER_STATE_TYPE_BATTERY;
744 case PP_StateUILabel_Balanced:
745 data->states[i] = POWER_STATE_TYPE_BALANCED;
747 case PP_StateUILabel_Performance:
748 data->states[i] = POWER_STATE_TYPE_PERFORMANCE;
751 if (state->classification.flags & PP_StateClassificationFlag_Boot)
752 data->states[i] = POWER_STATE_TYPE_INTERNAL_BOOT;
754 data->states[i] = POWER_STATE_TYPE_DEFAULT;
757 mutex_unlock(&pp_handle->pp_lock);
761 static int pp_dpm_get_pp_table(void *handle, char **table)
763 struct pp_hwmgr *hwmgr;
764 struct pp_instance *pp_handle = (struct pp_instance *)handle;
768 ret = pp_check(pp_handle);
773 hwmgr = pp_handle->hwmgr;
775 if (!hwmgr->soft_pp_table)
778 mutex_lock(&pp_handle->pp_lock);
779 *table = (char *)hwmgr->soft_pp_table;
780 size = hwmgr->soft_pp_table_size;
781 mutex_unlock(&pp_handle->pp_lock);
785 static int amd_powerplay_reset(void *handle)
787 struct pp_instance *instance = (struct pp_instance *)handle;
790 ret = pp_check(instance);
794 ret = pp_hw_fini(instance);
798 ret = hwmgr_hw_init(instance);
802 return hwmgr_handle_task(instance, AMD_PP_TASK_COMPLETE_INIT, NULL, NULL);
805 static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
807 struct pp_hwmgr *hwmgr;
808 struct pp_instance *pp_handle = (struct pp_instance *)handle;
811 ret = pp_check(pp_handle);
816 hwmgr = pp_handle->hwmgr;
817 mutex_lock(&pp_handle->pp_lock);
818 if (!hwmgr->hardcode_pp_table) {
819 hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table,
820 hwmgr->soft_pp_table_size,
822 if (!hwmgr->hardcode_pp_table) {
823 mutex_unlock(&pp_handle->pp_lock);
828 memcpy(hwmgr->hardcode_pp_table, buf, size);
830 hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;
831 mutex_unlock(&pp_handle->pp_lock);
833 ret = amd_powerplay_reset(handle);
837 if (hwmgr->hwmgr_func->avfs_control) {
838 ret = hwmgr->hwmgr_func->avfs_control(hwmgr, false);
846 static int pp_dpm_force_clock_level(void *handle,
847 enum pp_clock_type type, uint32_t mask)
849 struct pp_hwmgr *hwmgr;
850 struct pp_instance *pp_handle = (struct pp_instance *)handle;
853 ret = pp_check(pp_handle);
858 hwmgr = pp_handle->hwmgr;
860 if (hwmgr->hwmgr_func->force_clock_level == NULL) {
861 pr_info("%s was not implemented.\n", __func__);
864 mutex_lock(&pp_handle->pp_lock);
865 hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
866 mutex_unlock(&pp_handle->pp_lock);
870 static int pp_dpm_print_clock_levels(void *handle,
871 enum pp_clock_type type, char *buf)
873 struct pp_hwmgr *hwmgr;
874 struct pp_instance *pp_handle = (struct pp_instance *)handle;
877 ret = pp_check(pp_handle);
882 hwmgr = pp_handle->hwmgr;
884 if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
885 pr_info("%s was not implemented.\n", __func__);
888 mutex_lock(&pp_handle->pp_lock);
889 ret = hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
890 mutex_unlock(&pp_handle->pp_lock);
894 static int pp_dpm_get_sclk_od(void *handle)
896 struct pp_hwmgr *hwmgr;
897 struct pp_instance *pp_handle = (struct pp_instance *)handle;
900 ret = pp_check(pp_handle);
905 hwmgr = pp_handle->hwmgr;
907 if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
908 pr_info("%s was not implemented.\n", __func__);
911 mutex_lock(&pp_handle->pp_lock);
912 ret = hwmgr->hwmgr_func->get_sclk_od(hwmgr);
913 mutex_unlock(&pp_handle->pp_lock);
917 static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
919 struct pp_hwmgr *hwmgr;
920 struct pp_instance *pp_handle = (struct pp_instance *)handle;
923 ret = pp_check(pp_handle);
928 hwmgr = pp_handle->hwmgr;
930 if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
931 pr_info("%s was not implemented.\n", __func__);
935 mutex_lock(&pp_handle->pp_lock);
936 ret = hwmgr->hwmgr_func->set_sclk_od(hwmgr, value);
937 mutex_unlock(&pp_handle->pp_lock);
941 static int pp_dpm_get_mclk_od(void *handle)
943 struct pp_hwmgr *hwmgr;
944 struct pp_instance *pp_handle = (struct pp_instance *)handle;
947 ret = pp_check(pp_handle);
952 hwmgr = pp_handle->hwmgr;
954 if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
955 pr_info("%s was not implemented.\n", __func__);
958 mutex_lock(&pp_handle->pp_lock);
959 ret = hwmgr->hwmgr_func->get_mclk_od(hwmgr);
960 mutex_unlock(&pp_handle->pp_lock);
964 static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
966 struct pp_hwmgr *hwmgr;
967 struct pp_instance *pp_handle = (struct pp_instance *)handle;
970 ret = pp_check(pp_handle);
975 hwmgr = pp_handle->hwmgr;
977 if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
978 pr_info("%s was not implemented.\n", __func__);
981 mutex_lock(&pp_handle->pp_lock);
982 ret = hwmgr->hwmgr_func->set_mclk_od(hwmgr, value);
983 mutex_unlock(&pp_handle->pp_lock);
987 static int pp_dpm_read_sensor(void *handle, int idx,
988 void *value, int *size)
990 struct pp_hwmgr *hwmgr;
991 struct pp_instance *pp_handle = (struct pp_instance *)handle;
994 ret = pp_check(pp_handle);
999 hwmgr = pp_handle->hwmgr;
1001 if (hwmgr->hwmgr_func->read_sensor == NULL) {
1002 pr_info("%s was not implemented.\n", __func__);
1006 mutex_lock(&pp_handle->pp_lock);
1007 ret = hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size);
1008 mutex_unlock(&pp_handle->pp_lock);
1013 static struct amd_vce_state*
1014 pp_dpm_get_vce_clock_state(void *handle, unsigned idx)
1016 struct pp_hwmgr *hwmgr;
1017 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1020 ret = pp_check(pp_handle);
1025 hwmgr = pp_handle->hwmgr;
1027 if (hwmgr && idx < hwmgr->num_vce_state_tables)
1028 return &hwmgr->vce_states[idx];
1032 static int pp_dpm_reset_power_profile_state(void *handle,
1033 struct amd_pp_profile *request)
1035 struct pp_hwmgr *hwmgr;
1036 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1038 if (!request || pp_check(pp_handle))
1041 hwmgr = pp_handle->hwmgr;
1043 if (hwmgr->hwmgr_func->set_power_profile_state == NULL) {
1044 pr_info("%s was not implemented.\n", __func__);
1048 if (request->type == AMD_PP_GFX_PROFILE) {
1049 hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
1050 return hwmgr->hwmgr_func->set_power_profile_state(hwmgr,
1051 &hwmgr->gfx_power_profile);
1052 } else if (request->type == AMD_PP_COMPUTE_PROFILE) {
1053 hwmgr->compute_power_profile =
1054 hwmgr->default_compute_power_profile;
1055 return hwmgr->hwmgr_func->set_power_profile_state(hwmgr,
1056 &hwmgr->compute_power_profile);
1061 static int pp_dpm_get_power_profile_state(void *handle,
1062 struct amd_pp_profile *query)
1064 struct pp_hwmgr *hwmgr;
1065 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1067 if (!query || pp_check(pp_handle))
1070 hwmgr = pp_handle->hwmgr;
1072 if (query->type == AMD_PP_GFX_PROFILE)
1073 memcpy(query, &hwmgr->gfx_power_profile,
1074 sizeof(struct amd_pp_profile));
1075 else if (query->type == AMD_PP_COMPUTE_PROFILE)
1076 memcpy(query, &hwmgr->compute_power_profile,
1077 sizeof(struct amd_pp_profile));
1084 static int pp_dpm_set_power_profile_state(void *handle,
1085 struct amd_pp_profile *request)
1087 struct pp_hwmgr *hwmgr;
1088 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1091 if (!request || pp_check(pp_handle))
1094 hwmgr = pp_handle->hwmgr;
1096 if (hwmgr->hwmgr_func->set_power_profile_state == NULL) {
1097 pr_info("%s was not implemented.\n", __func__);
1101 if (request->min_sclk ||
1102 request->min_mclk ||
1103 request->activity_threshold ||
1105 request->down_hyst) {
1106 if (request->type == AMD_PP_GFX_PROFILE)
1107 memcpy(&hwmgr->gfx_power_profile, request,
1108 sizeof(struct amd_pp_profile));
1109 else if (request->type == AMD_PP_COMPUTE_PROFILE)
1110 memcpy(&hwmgr->compute_power_profile, request,
1111 sizeof(struct amd_pp_profile));
1115 if (request->type == hwmgr->current_power_profile)
1116 ret = hwmgr->hwmgr_func->set_power_profile_state(
1120 /* set power profile if it exists */
1121 switch (request->type) {
1122 case AMD_PP_GFX_PROFILE:
1123 ret = hwmgr->hwmgr_func->set_power_profile_state(
1125 &hwmgr->gfx_power_profile);
1127 case AMD_PP_COMPUTE_PROFILE:
1128 ret = hwmgr->hwmgr_func->set_power_profile_state(
1130 &hwmgr->compute_power_profile);
1138 hwmgr->current_power_profile = request->type;
1143 static int pp_dpm_switch_power_profile(void *handle,
1144 enum amd_pp_profile_type type)
1146 struct pp_hwmgr *hwmgr;
1147 struct amd_pp_profile request = {0};
1148 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1150 if (pp_check(pp_handle))
1153 hwmgr = pp_handle->hwmgr;
1155 if (hwmgr->current_power_profile != type) {
1156 request.type = type;
1157 pp_dpm_set_power_profile_state(handle, &request);
1163 static int pp_dpm_notify_smu_memory_info(void *handle,
1164 uint32_t virtual_addr_low,
1165 uint32_t virtual_addr_hi,
1166 uint32_t mc_addr_low,
1167 uint32_t mc_addr_hi,
1170 struct pp_hwmgr *hwmgr;
1171 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1174 ret = pp_check(pp_handle);
1179 hwmgr = pp_handle->hwmgr;
1181 if (hwmgr->hwmgr_func->notify_cac_buffer_info == NULL) {
1182 pr_info("%s was not implemented.\n", __func__);
1186 mutex_lock(&pp_handle->pp_lock);
1188 ret = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr, virtual_addr_low,
1189 virtual_addr_hi, mc_addr_low, mc_addr_hi,
1192 mutex_unlock(&pp_handle->pp_lock);
1197 static int pp_display_configuration_change(void *handle,
1198 const struct amd_pp_display_configuration *display_config)
1200 struct pp_hwmgr *hwmgr;
1201 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1204 ret = pp_check(pp_handle);
1209 hwmgr = pp_handle->hwmgr;
1210 mutex_lock(&pp_handle->pp_lock);
1211 phm_store_dal_configuration_data(hwmgr, display_config);
1212 mutex_unlock(&pp_handle->pp_lock);
1216 static int pp_get_display_power_level(void *handle,
1217 struct amd_pp_simple_clock_info *output)
1219 struct pp_hwmgr *hwmgr;
1220 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1223 ret = pp_check(pp_handle);
1228 hwmgr = pp_handle->hwmgr;
1233 mutex_lock(&pp_handle->pp_lock);
1234 ret = phm_get_dal_power_level(hwmgr, output);
1235 mutex_unlock(&pp_handle->pp_lock);
1239 static int pp_get_current_clocks(void *handle,
1240 struct amd_pp_clock_info *clocks)
1242 struct amd_pp_simple_clock_info simple_clocks;
1243 struct pp_clock_info hw_clocks;
1244 struct pp_hwmgr *hwmgr;
1245 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1248 ret = pp_check(pp_handle);
1253 hwmgr = pp_handle->hwmgr;
1255 mutex_lock(&pp_handle->pp_lock);
1257 phm_get_dal_power_level(hwmgr, &simple_clocks);
1259 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1260 PHM_PlatformCaps_PowerContainment))
1261 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware,
1262 &hw_clocks, PHM_PerformanceLevelDesignation_PowerContainment);
1264 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware,
1265 &hw_clocks, PHM_PerformanceLevelDesignation_Activity);
1268 pr_info("Error in phm_get_clock_info \n");
1269 mutex_unlock(&pp_handle->pp_lock);
1273 clocks->min_engine_clock = hw_clocks.min_eng_clk;
1274 clocks->max_engine_clock = hw_clocks.max_eng_clk;
1275 clocks->min_memory_clock = hw_clocks.min_mem_clk;
1276 clocks->max_memory_clock = hw_clocks.max_mem_clk;
1277 clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1278 clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1280 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1281 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1283 clocks->max_clocks_state = simple_clocks.level;
1285 if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) {
1286 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1287 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1289 mutex_unlock(&pp_handle->pp_lock);
1293 static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
1295 struct pp_hwmgr *hwmgr;
1296 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1299 ret = pp_check(pp_handle);
1304 hwmgr = pp_handle->hwmgr;
1309 mutex_lock(&pp_handle->pp_lock);
1310 ret = phm_get_clock_by_type(hwmgr, type, clocks);
1311 mutex_unlock(&pp_handle->pp_lock);
1315 static int pp_get_clock_by_type_with_latency(void *handle,
1316 enum amd_pp_clock_type type,
1317 struct pp_clock_levels_with_latency *clocks)
1319 struct pp_hwmgr *hwmgr;
1320 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1323 ret = pp_check(pp_handle);
1330 mutex_lock(&pp_handle->pp_lock);
1331 hwmgr = ((struct pp_instance *)handle)->hwmgr;
1332 ret = phm_get_clock_by_type_with_latency(hwmgr, type, clocks);
1333 mutex_unlock(&pp_handle->pp_lock);
1337 static int pp_get_clock_by_type_with_voltage(void *handle,
1338 enum amd_pp_clock_type type,
1339 struct pp_clock_levels_with_voltage *clocks)
1341 struct pp_hwmgr *hwmgr;
1342 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1345 ret = pp_check(pp_handle);
1352 hwmgr = ((struct pp_instance *)handle)->hwmgr;
1354 mutex_lock(&pp_handle->pp_lock);
1356 ret = phm_get_clock_by_type_with_voltage(hwmgr, type, clocks);
1358 mutex_unlock(&pp_handle->pp_lock);
1362 static int pp_set_watermarks_for_clocks_ranges(void *handle,
1363 struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
1365 struct pp_hwmgr *hwmgr;
1366 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1369 ret = pp_check(pp_handle);
1373 if (!wm_with_clock_ranges)
1376 hwmgr = ((struct pp_instance *)handle)->hwmgr;
1378 mutex_lock(&pp_handle->pp_lock);
1379 ret = phm_set_watermarks_for_clocks_ranges(hwmgr,
1380 wm_with_clock_ranges);
1381 mutex_unlock(&pp_handle->pp_lock);
1386 static int pp_display_clock_voltage_request(void *handle,
1387 struct pp_display_clock_request *clock)
1389 struct pp_hwmgr *hwmgr;
1390 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1393 ret = pp_check(pp_handle);
1400 hwmgr = ((struct pp_instance *)handle)->hwmgr;
1402 mutex_lock(&pp_handle->pp_lock);
1403 ret = phm_display_clock_voltage_request(hwmgr, clock);
1404 mutex_unlock(&pp_handle->pp_lock);
1409 static int pp_get_display_mode_validation_clocks(void *handle,
1410 struct amd_pp_simple_clock_info *clocks)
1412 struct pp_hwmgr *hwmgr;
1413 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1416 ret = pp_check(pp_handle);
1421 hwmgr = pp_handle->hwmgr;
1426 mutex_lock(&pp_handle->pp_lock);
1428 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
1429 ret = phm_get_max_high_clocks(hwmgr, clocks);
1431 mutex_unlock(&pp_handle->pp_lock);
1435 const struct amd_pm_funcs pp_dpm_funcs = {
1436 .get_temperature = pp_dpm_get_temperature,
1437 .load_firmware = pp_dpm_load_fw,
1438 .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
1439 .force_performance_level = pp_dpm_force_performance_level,
1440 .get_performance_level = pp_dpm_get_performance_level,
1441 .get_current_power_state = pp_dpm_get_current_power_state,
1442 .powergate_vce = pp_dpm_powergate_vce,
1443 .powergate_uvd = pp_dpm_powergate_uvd,
1444 .dispatch_tasks = pp_dpm_dispatch_tasks,
1445 .set_fan_control_mode = pp_dpm_set_fan_control_mode,
1446 .get_fan_control_mode = pp_dpm_get_fan_control_mode,
1447 .set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
1448 .get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
1449 .get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm,
1450 .get_pp_num_states = pp_dpm_get_pp_num_states,
1451 .get_pp_table = pp_dpm_get_pp_table,
1452 .set_pp_table = pp_dpm_set_pp_table,
1453 .force_clock_level = pp_dpm_force_clock_level,
1454 .print_clock_levels = pp_dpm_print_clock_levels,
1455 .get_sclk_od = pp_dpm_get_sclk_od,
1456 .set_sclk_od = pp_dpm_set_sclk_od,
1457 .get_mclk_od = pp_dpm_get_mclk_od,
1458 .set_mclk_od = pp_dpm_set_mclk_od,
1459 .read_sensor = pp_dpm_read_sensor,
1460 .get_vce_clock_state = pp_dpm_get_vce_clock_state,
1461 .reset_power_profile_state = pp_dpm_reset_power_profile_state,
1462 .get_power_profile_state = pp_dpm_get_power_profile_state,
1463 .set_power_profile_state = pp_dpm_set_power_profile_state,
1464 .switch_power_profile = pp_dpm_switch_power_profile,
1465 .set_clockgating_by_smu = pp_set_clockgating_by_smu,
1466 .notify_smu_memory_info = pp_dpm_notify_smu_memory_info,
1468 .get_sclk = pp_dpm_get_sclk,
1469 .get_mclk = pp_dpm_get_mclk,
1470 .display_configuration_change = pp_display_configuration_change,
1471 .get_display_power_level = pp_get_display_power_level,
1472 .get_current_clocks = pp_get_current_clocks,
1473 .get_clock_by_type = pp_get_clock_by_type,
1474 .get_clock_by_type_with_latency = pp_get_clock_by_type_with_latency,
1475 .get_clock_by_type_with_voltage = pp_get_clock_by_type_with_voltage,
1476 .set_watermarks_for_clocks_ranges = pp_set_watermarks_for_clocks_ranges,
1477 .display_clock_voltage_request = pp_display_clock_voltage_request,
1478 .get_display_mode_validation_clocks = pp_get_display_mode_validation_clocks,