2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "amd_shared.h"
32 * enum cgs_gpu_mem_type - GPU memory types
34 enum cgs_gpu_mem_type {
35 CGS_GPU_MEM_TYPE__VISIBLE_FB,
36 CGS_GPU_MEM_TYPE__INVISIBLE_FB,
37 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
38 CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB,
39 CGS_GPU_MEM_TYPE__GART_CACHEABLE,
40 CGS_GPU_MEM_TYPE__GART_WRITECOMBINE
44 * enum cgs_ind_reg - Indirect register spaces
54 CGS_IND_REG__AUDIO_ENDPT
58 * enum cgs_engine - Engines that can be statically power-gated
72 * enum cgs_ucode_id - Firmware types for different IPs
83 CGS_UCODE_ID_CP_MEC_JT1,
84 CGS_UCODE_ID_CP_MEC_JT2,
85 CGS_UCODE_ID_GMCON_RENG,
91 enum cgs_system_info_id {
92 CGS_SYSTEM_INFO_ADAPTER_BDF_ID = 1,
93 CGS_SYSTEM_INFO_PCIE_GEN_INFO,
94 CGS_SYSTEM_INFO_PCIE_MLW,
95 CGS_SYSTEM_INFO_PCIE_DEV,
96 CGS_SYSTEM_INFO_PCIE_REV,
97 CGS_SYSTEM_INFO_CG_FLAGS,
98 CGS_SYSTEM_INFO_PG_FLAGS,
99 CGS_SYSTEM_INFO_GFX_CU_INFO,
100 CGS_SYSTEM_INFO_GFX_SE_INFO,
101 CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID,
102 CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID,
103 CGS_SYSTEM_INFO_PCIE_BUS_DEVFN,
104 CGS_SYSTEM_INFO_ID_MAXIMUM,
107 struct cgs_system_info {
109 enum cgs_system_info_id info_id;
114 uint64_t padding[13];
118 * enum cgs_resource_type - GPU resource type
120 enum cgs_resource_type {
121 CGS_RESOURCE_TYPE_MMIO = 0,
122 CGS_RESOURCE_TYPE_FB,
123 CGS_RESOURCE_TYPE_IO,
124 CGS_RESOURCE_TYPE_DOORBELL,
125 CGS_RESOURCE_TYPE_ROM,
129 * struct cgs_firmware_info - Firmware information
131 struct cgs_firmware_info {
134 uint16_t feature_version;
138 /* only for smc firmware */
139 uint32_t ucode_start_address;
145 struct cgs_mode_info {
146 uint32_t refresh_rate;
148 uint32_t vblank_time_us;
151 struct cgs_display_info {
152 uint32_t display_count;
153 uint32_t active_display_mask;
154 struct cgs_mode_info *mode_info;
157 typedef unsigned long cgs_handle_t;
159 #define CGS_ACPI_METHOD_ATCS 0x53435441
160 #define CGS_ACPI_METHOD_ATIF 0x46495441
161 #define CGS_ACPI_METHOD_ATPX 0x58505441
162 #define CGS_ACPI_FIELD_METHOD_NAME 0x00000001
163 #define CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT 0x00000002
164 #define CGS_ACPI_MAX_BUFFER_SIZE 256
165 #define CGS_ACPI_TYPE_ANY 0x00
166 #define CGS_ACPI_TYPE_INTEGER 0x01
167 #define CGS_ACPI_TYPE_STRING 0x02
168 #define CGS_ACPI_TYPE_BUFFER 0x03
169 #define CGS_ACPI_TYPE_PACKAGE 0x04
171 struct cgs_acpi_method_argument {
173 uint32_t data_length;
180 struct cgs_acpi_method_info {
183 uint32_t input_count;
185 struct cgs_acpi_method_argument *pinput_argument;
186 uint32_t output_count;
187 struct cgs_acpi_method_argument *poutput_argument;
192 * cgs_alloc_gpu_mem() - Allocate GPU memory
193 * @cgs_device: opaque device handle
195 * @size: size in bytes
196 * @align: alignment in bytes
197 * @handle: memory handle (output)
199 * The memory types CGS_GPU_MEM_TYPE_*_CONTIG_FB force contiguous
200 * memory allocation. This guarantees that the MC address returned by
201 * cgs_gmap_gpu_mem is not mapped through the GART. The non-contiguous
202 * FB memory types may be GART mapped depending on memory
203 * fragmentation and memory allocator policies.
205 * If min/max_offset are non-0, the allocation will be forced to
206 * reside between these offsets in its respective memory heap. The
207 * base address that the offset relates to, depends on the memory
210 * - CGS_GPU_MEM_TYPE__*_CONTIG_FB: FB MC base address
211 * - CGS_GPU_MEM_TYPE__GART_*: GART aperture base address
212 * - others: undefined, don't use with max_offset
214 * Return: 0 on success, -errno otherwise
216 typedef int (*cgs_alloc_gpu_mem_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
217 uint64_t size, uint64_t align,
218 cgs_handle_t *handle);
221 * cgs_free_gpu_mem() - Free GPU memory
222 * @cgs_device: opaque device handle
223 * @handle: memory handle returned by alloc or import
225 * Return: 0 on success, -errno otherwise
227 typedef int (*cgs_free_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
230 * cgs_gmap_gpu_mem() - GPU-map GPU memory
231 * @cgs_device: opaque device handle
232 * @handle: memory handle returned by alloc or import
233 * @mcaddr: MC address (output)
235 * Ensures that a buffer is GPU accessible and returns its MC address.
237 * Return: 0 on success, -errno otherwise
239 typedef int (*cgs_gmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle,
243 * cgs_gunmap_gpu_mem() - GPU-unmap GPU memory
244 * @cgs_device: opaque device handle
245 * @handle: memory handle returned by alloc or import
247 * Allows the buffer to be migrated while it's not used by the GPU.
249 * Return: 0 on success, -errno otherwise
251 typedef int (*cgs_gunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
254 * cgs_kmap_gpu_mem() - Kernel-map GPU memory
256 * @cgs_device: opaque device handle
257 * @handle: memory handle returned by alloc or import
258 * @map: Kernel virtual address the memory was mapped to (output)
260 * Return: 0 on success, -errno otherwise
262 typedef int (*cgs_kmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle,
266 * cgs_kunmap_gpu_mem() - Kernel-unmap GPU memory
267 * @cgs_device: opaque device handle
268 * @handle: memory handle returned by alloc or import
270 * Return: 0 on success, -errno otherwise
272 typedef int (*cgs_kunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
275 * cgs_read_register() - Read an MMIO register
276 * @cgs_device: opaque device handle
277 * @offset: register offset
279 * Return: register value
281 typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset);
284 * cgs_write_register() - Write an MMIO register
285 * @cgs_device: opaque device handle
286 * @offset: register offset
287 * @value: register value
289 typedef void (*cgs_write_register_t)(struct cgs_device *cgs_device, unsigned offset,
293 * cgs_read_ind_register() - Read an indirect register
294 * @cgs_device: opaque device handle
295 * @offset: register offset
297 * Return: register value
299 typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
303 * cgs_write_ind_register() - Write an indirect register
304 * @cgs_device: opaque device handle
305 * @offset: register offset
306 * @value: register value
308 typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
309 unsigned index, uint32_t value);
311 #define CGS_REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
312 #define CGS_REG_FIELD_MASK(reg, field) reg##__##field##_MASK
314 #define CGS_REG_SET_FIELD(orig_val, reg, field, field_val) \
315 (((orig_val) & ~CGS_REG_FIELD_MASK(reg, field)) | \
316 (CGS_REG_FIELD_MASK(reg, field) & ((field_val) << CGS_REG_FIELD_SHIFT(reg, field))))
318 #define CGS_REG_GET_FIELD(value, reg, field) \
319 (((value) & CGS_REG_FIELD_MASK(reg, field)) >> CGS_REG_FIELD_SHIFT(reg, field))
321 #define CGS_WREG32_FIELD(device, reg, field, val) \
322 cgs_write_register(device, mm##reg, (cgs_read_register(device, mm##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))
324 #define CGS_WREG32_FIELD_IND(device, space, reg, field, val) \
325 cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))
328 * cgs_get_pci_resource() - provide access to a device resource (PCI BAR)
329 * @cgs_device: opaque device handle
330 * @resource_type: Type of Resource (MMIO, IO, ROM, FB, DOORBELL)
331 * @size: size of the region
332 * @offset: offset from the start of the region
333 * @resource_base: base address (not including offset) returned
335 * Return: 0 on success, -errno otherwise
337 typedef int (*cgs_get_pci_resource_t)(struct cgs_device *cgs_device,
338 enum cgs_resource_type resource_type,
341 uint64_t *resource_base);
344 * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table
345 * @cgs_device: opaque device handle
346 * @table: data table index
347 * @size: size of the table (output, may be NULL)
348 * @frev: table format revision (output, may be NULL)
349 * @crev: table content revision (output, may be NULL)
351 * Return: Pointer to start of the table, or NULL on failure
353 typedef const void *(*cgs_atom_get_data_table_t)(
354 struct cgs_device *cgs_device, unsigned table,
355 uint16_t *size, uint8_t *frev, uint8_t *crev);
358 * cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions
359 * @cgs_device: opaque device handle
360 * @table: data table index
361 * @frev: table format revision (output, may be NULL)
362 * @crev: table content revision (output, may be NULL)
364 * Return: 0 on success, -errno otherwise
366 typedef int (*cgs_atom_get_cmd_table_revs_t)(struct cgs_device *cgs_device, unsigned table,
367 uint8_t *frev, uint8_t *crev);
370 * cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table
371 * @cgs_device: opaque device handle
372 * @table: command table index
375 * Return: 0 on success, -errno otherwise
377 typedef int (*cgs_atom_exec_cmd_table_t)(struct cgs_device *cgs_device,
378 unsigned table, void *args);
381 * cgs_get_firmware_info - Get the firmware information from core driver
382 * @cgs_device: opaque device handle
383 * @type: the firmware type
384 * @info: returend firmware information
386 * Return: 0 on success, -errno otherwise
388 typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device,
389 enum cgs_ucode_id type,
390 struct cgs_firmware_info *info);
392 typedef int (*cgs_rel_firmware)(struct cgs_device *cgs_device,
393 enum cgs_ucode_id type);
395 typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device,
396 enum amd_ip_block_type block_type,
397 enum amd_powergating_state state);
399 typedef int(*cgs_set_clockgating_state)(struct cgs_device *cgs_device,
400 enum amd_ip_block_type block_type,
401 enum amd_clockgating_state state);
403 typedef int(*cgs_get_active_displays_info)(
404 struct cgs_device *cgs_device,
405 struct cgs_display_info *info);
407 typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled);
409 typedef int (*cgs_call_acpi_method)(struct cgs_device *cgs_device,
410 uint32_t acpi_method,
411 uint32_t acpi_function,
412 void *pinput, void *poutput,
413 uint32_t output_count,
415 uint32_t output_size);
417 typedef int (*cgs_query_system_info)(struct cgs_device *cgs_device,
418 struct cgs_system_info *sys_info);
420 typedef int (*cgs_is_virtualization_enabled_t)(void *cgs_device);
422 typedef int (*cgs_enter_safe_mode)(struct cgs_device *cgs_device, bool en);
424 typedef void (*cgs_lock_grbm_idx)(struct cgs_device *cgs_device, bool lock);
427 typedef void* (*cgs_register_pp_handle)(struct cgs_device *cgs_device,
428 int (*call_back_func)(struct amd_pp_init *, void **));
431 /* memory management calls (similar to KFD interface) */
432 cgs_alloc_gpu_mem_t alloc_gpu_mem;
433 cgs_free_gpu_mem_t free_gpu_mem;
434 cgs_gmap_gpu_mem_t gmap_gpu_mem;
435 cgs_gunmap_gpu_mem_t gunmap_gpu_mem;
436 cgs_kmap_gpu_mem_t kmap_gpu_mem;
437 cgs_kunmap_gpu_mem_t kunmap_gpu_mem;
439 cgs_read_register_t read_register;
440 cgs_write_register_t write_register;
441 cgs_read_ind_register_t read_ind_register;
442 cgs_write_ind_register_t write_ind_register;
444 cgs_get_pci_resource_t get_pci_resource;
446 cgs_atom_get_data_table_t atom_get_data_table;
447 cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs;
448 cgs_atom_exec_cmd_table_t atom_exec_cmd_table;
450 cgs_get_firmware_info get_firmware_info;
451 cgs_rel_firmware rel_firmware;
453 cgs_set_powergating_state set_powergating_state;
454 cgs_set_clockgating_state set_clockgating_state;
455 /* display manager */
456 cgs_get_active_displays_info get_active_displays_info;
457 /* notify dpm enabled */
458 cgs_notify_dpm_enabled notify_dpm_enabled;
460 cgs_call_acpi_method call_acpi_method;
461 /* get system info */
462 cgs_query_system_info query_system_info;
463 cgs_is_virtualization_enabled_t is_virtualization_enabled;
464 cgs_enter_safe_mode enter_safe_mode;
465 cgs_lock_grbm_idx lock_grbm_idx;
466 cgs_register_pp_handle register_pp_handle;
469 struct cgs_os_ops; /* To be define in OS-specific CGS header */
473 const struct cgs_ops *ops;
474 const struct cgs_os_ops *os_ops;
475 /* to be embedded at the start of driver private structure */
478 /* Convenience macros that make CGS indirect function calls look like
479 * normal function calls */
480 #define CGS_CALL(func,dev,...) \
481 (((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__))
482 #define CGS_OS_CALL(func,dev,...) \
483 (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__))
485 #define cgs_alloc_gpu_mem(dev,type,size,align,handle) \
486 CGS_CALL(alloc_gpu_mem,dev,type,size,align,handle)
487 #define cgs_free_gpu_mem(dev,handle) \
488 CGS_CALL(free_gpu_mem,dev,handle)
489 #define cgs_gmap_gpu_mem(dev,handle,mcaddr) \
490 CGS_CALL(gmap_gpu_mem,dev,handle,mcaddr)
491 #define cgs_gunmap_gpu_mem(dev,handle) \
492 CGS_CALL(gunmap_gpu_mem,dev,handle)
493 #define cgs_kmap_gpu_mem(dev,handle,map) \
494 CGS_CALL(kmap_gpu_mem,dev,handle,map)
495 #define cgs_kunmap_gpu_mem(dev,handle) \
496 CGS_CALL(kunmap_gpu_mem,dev,handle)
498 #define cgs_read_register(dev,offset) \
499 CGS_CALL(read_register,dev,offset)
500 #define cgs_write_register(dev,offset,value) \
501 CGS_CALL(write_register,dev,offset,value)
502 #define cgs_read_ind_register(dev,space,index) \
503 CGS_CALL(read_ind_register,dev,space,index)
504 #define cgs_write_ind_register(dev,space,index,value) \
505 CGS_CALL(write_ind_register,dev,space,index,value)
507 #define cgs_atom_get_data_table(dev,table,size,frev,crev) \
508 CGS_CALL(atom_get_data_table,dev,table,size,frev,crev)
509 #define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \
510 CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev)
511 #define cgs_atom_exec_cmd_table(dev,table,args) \
512 CGS_CALL(atom_exec_cmd_table,dev,table,args)
514 #define cgs_get_firmware_info(dev, type, info) \
515 CGS_CALL(get_firmware_info, dev, type, info)
516 #define cgs_rel_firmware(dev, type) \
517 CGS_CALL(rel_firmware, dev, type)
518 #define cgs_set_powergating_state(dev, block_type, state) \
519 CGS_CALL(set_powergating_state, dev, block_type, state)
520 #define cgs_set_clockgating_state(dev, block_type, state) \
521 CGS_CALL(set_clockgating_state, dev, block_type, state)
522 #define cgs_notify_dpm_enabled(dev, enabled) \
523 CGS_CALL(notify_dpm_enabled, dev, enabled)
525 #define cgs_get_active_displays_info(dev, info) \
526 CGS_CALL(get_active_displays_info, dev, info)
528 #define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) \
529 CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)
530 #define cgs_query_system_info(dev, sys_info) \
531 CGS_CALL(query_system_info, dev, sys_info)
532 #define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \
534 CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \
537 #define cgs_is_virtualization_enabled(cgs_device) \
538 CGS_CALL(is_virtualization_enabled, cgs_device)
540 #define cgs_enter_safe_mode(cgs_device, en) \
541 CGS_CALL(enter_safe_mode, cgs_device, en)
543 #define cgs_lock_grbm_idx(cgs_device, lock) \
544 CGS_CALL(lock_grbm_idx, cgs_device, lock)
545 #define cgs_register_pp_handle(cgs_device, call_back_func) \
546 CGS_CALL(register_pp_handle, cgs_device, call_back_func)
548 #endif /* _CGS_COMMON_H */