drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27
  28 #include "include/logger_interface.h"
  29
  30 #include "../dce110/irq_service_dce110.h"
  31
  32 #include "raven1/DCN/dcn_1_0_offset.h"
  33 #include "raven1/DCN/dcn_1_0_sh_mask.h"
  34 #include "vega10/soc15ip.h"
  35
  36 #include "irq_service_dcn10.h"
  37
  38 #include "ivsrcid/irqsrcs_dcn_1_0.h"
  39
  40 enum dc_irq_source to_dal_irq_source_dcn10(
  41                 struct irq_service *irq_service,
  42                 uint32_t src_id,
  43                 uint32_t ext_id)
  44 {
  45         switch (src_id) {
  46         case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
  47                 return DC_IRQ_SOURCE_VBLANK1;
  48         case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
  49                 return DC_IRQ_SOURCE_VBLANK2;
  50         case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
  51                 return DC_IRQ_SOURCE_VBLANK3;
  52         case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
  53                 return DC_IRQ_SOURCE_VBLANK4;
  54         case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
  55                 return DC_IRQ_SOURCE_VBLANK5;
  56         case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
  57                 return DC_IRQ_SOURCE_VBLANK6;
  58         case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
  59                 return DC_IRQ_SOURCE_PFLIP1;
  60         case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
  61                 return DC_IRQ_SOURCE_PFLIP2;
  62         case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
  63                 return DC_IRQ_SOURCE_PFLIP3;
  64         case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
  65                 return DC_IRQ_SOURCE_PFLIP4;
  66         case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
  67                 return DC_IRQ_SOURCE_PFLIP5;
  68         case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
  69                 return DC_IRQ_SOURCE_PFLIP6;
  70
  71         case DCN_1_0__SRCID__DC_HPD1_INT:
  72                 /* generic src_id for all HPD and HPDRX interrupts */
  73                 switch (ext_id) {
  74                 case DCN_1_0__CTXID__DC_HPD1_INT:
  75                         return DC_IRQ_SOURCE_HPD1;
  76                 case DCN_1_0__CTXID__DC_HPD2_INT:
  77                         return DC_IRQ_SOURCE_HPD2;
  78                 case DCN_1_0__CTXID__DC_HPD3_INT:
  79                         return DC_IRQ_SOURCE_HPD3;
  80                 case DCN_1_0__CTXID__DC_HPD4_INT:
  81                         return DC_IRQ_SOURCE_HPD4;
  82                 case DCN_1_0__CTXID__DC_HPD5_INT:
  83                         return DC_IRQ_SOURCE_HPD5;
  84                 case DCN_1_0__CTXID__DC_HPD6_INT:
  85                         return DC_IRQ_SOURCE_HPD6;
  86                 case DCN_1_0__CTXID__DC_HPD1_RX_INT:
  87                         return DC_IRQ_SOURCE_HPD1RX;
  88                 case DCN_1_0__CTXID__DC_HPD2_RX_INT:
  89                         return DC_IRQ_SOURCE_HPD2RX;
  90                 case DCN_1_0__CTXID__DC_HPD3_RX_INT:
  91                         return DC_IRQ_SOURCE_HPD3RX;
  92                 case DCN_1_0__CTXID__DC_HPD4_RX_INT:
  93                         return DC_IRQ_SOURCE_HPD4RX;
  94                 case DCN_1_0__CTXID__DC_HPD5_RX_INT:
  95                         return DC_IRQ_SOURCE_HPD5RX;
  96                 case DCN_1_0__CTXID__DC_HPD6_RX_INT:
  97                         return DC_IRQ_SOURCE_HPD6RX;
  98                 default:
  99                         return DC_IRQ_SOURCE_INVALID;
 100                 }
 101                 break;
 102
 103         default:
 104                 return DC_IRQ_SOURCE_INVALID;
 105         }
 106 }
 107
 108 static bool hpd_ack(
 109         struct irq_service *irq_service,
 110         const struct irq_source_info *info)
 111 {
 112         uint32_t addr = info->status_reg;
 113         uint32_t value = dm_read_reg(irq_service->ctx, addr);
 114         uint32_t current_status =
 115                 get_reg_field_value(
 116                         value,
 117                         HPD0_DC_HPD_INT_STATUS,
 118                         DC_HPD_SENSE_DELAYED);
 119
 120         dal_irq_service_ack_generic(irq_service, info);
 121
 122         value = dm_read_reg(irq_service->ctx, info->enable_reg);
 123
 124         set_reg_field_value(
 125                 value,
 126                 current_status ? 0 : 1,
 127                 HPD0_DC_HPD_INT_CONTROL,
 128                 DC_HPD_INT_POLARITY);
 129
 130         dm_write_reg(irq_service->ctx, info->enable_reg, value);
 131
 132         return true;
 133 }
 134
 135 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
 136         .set = NULL,
 137         .ack = hpd_ack
 138 };
 139
 140 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
 141         .set = NULL,
 142         .ack = NULL
 143 };
 144
 145 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
 146         .set = NULL,
 147         .ack = NULL
 148 };
 149
 150 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
 151         .set = NULL,
 152         .ack = NULL
 153 };
 154
 155 #define BASE_INNER(seg) \
 156         DCE_BASE__INST0_SEG ## seg
 157
 158 #define BASE(seg) \
 159         BASE_INNER(seg)
 160
 161 #define SRI(reg_name, block, id)\
 162         BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 163                         mm ## block ## id ## _ ## reg_name
 164
 165
 166 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
 167         .enable_reg = SRI(reg1, block, reg_num),\
 168         .enable_mask = \
 169                 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
 170         .enable_value = {\
 171                 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
 172                 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
 173         },\
 174         .ack_reg = SRI(reg2, block, reg_num),\
 175         .ack_mask = \
 176                 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
 177         .ack_value = \
 178                 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
 179
 180 #define hpd_int_entry(reg_num)\
 181         [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
 182                 IRQ_REG_ENTRY(HPD, reg_num,\
 183                         DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
 184                         DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
 185                 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
 186                 .funcs = &hpd_irq_info_funcs\
 187         }
 188
 189 #define hpd_rx_int_entry(reg_num)\
 190         [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
 191                 IRQ_REG_ENTRY(HPD, reg_num,\
 192                         DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
 193                         DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
 194                 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
 195                 .funcs = &hpd_rx_irq_info_funcs\
 196         }
 197 #define pflip_int_entry(reg_num)\
 198         [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
 199                 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
 200                         DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
 201                         DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
 202                 .funcs = &pflip_irq_info_funcs\
 203         }
 204
 205 #define vupdate_int_entry(reg_num)\
 206         [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
 207                 IRQ_REG_ENTRY(OTG, reg_num,\
 208                         OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\
 209                         OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\
 210                 .funcs = &vblank_irq_info_funcs\
 211         }
 212
 213 #define vblank_int_entry(reg_num)\
 214         [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
 215                 IRQ_REG_ENTRY(OTG, reg_num,\
 216                         OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
 217                         OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
 218                 .funcs = &vblank_irq_info_funcs\
 219         }
 220
 221 #define dummy_irq_entry() \
 222         {\
 223                 .funcs = &dummy_irq_info_funcs\
 224         }
 225
 226 #define i2c_int_entry(reg_num) \
 227         [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
 228
 229 #define dp_sink_int_entry(reg_num) \
 230         [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
 231
 232 #define gpio_pad_int_entry(reg_num) \
 233         [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
 234
 235 #define dc_underflow_int_entry(reg_num) \
 236         [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
 237
 238 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
 239         .set = dal_irq_service_dummy_set,
 240         .ack = dal_irq_service_dummy_ack
 241 };
 242
 243 static const struct irq_source_info
 244 irq_source_info_dcn10[DAL_IRQ_SOURCES_NUMBER] = {
 245         [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
 246         hpd_int_entry(0),
 247         hpd_int_entry(1),
 248         hpd_int_entry(2),
 249         hpd_int_entry(3),
 250         hpd_int_entry(4),
 251         hpd_int_entry(5),
 252         hpd_rx_int_entry(0),
 253         hpd_rx_int_entry(1),
 254         hpd_rx_int_entry(2),
 255         hpd_rx_int_entry(3),
 256         hpd_rx_int_entry(4),
 257         hpd_rx_int_entry(5),
 258         i2c_int_entry(1),
 259         i2c_int_entry(2),
 260         i2c_int_entry(3),
 261         i2c_int_entry(4),
 262         i2c_int_entry(5),
 263         i2c_int_entry(6),
 264         dp_sink_int_entry(1),
 265         dp_sink_int_entry(2),
 266         dp_sink_int_entry(3),
 267         dp_sink_int_entry(4),
 268         dp_sink_int_entry(5),
 269         dp_sink_int_entry(6),
 270         [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
 271         pflip_int_entry(0),
 272         pflip_int_entry(1),
 273         pflip_int_entry(2),
 274         pflip_int_entry(3),
 275         [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
 276         [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
 277         [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
 278         gpio_pad_int_entry(0),
 279         gpio_pad_int_entry(1),
 280         gpio_pad_int_entry(2),
 281         gpio_pad_int_entry(3),
 282         gpio_pad_int_entry(4),
 283         gpio_pad_int_entry(5),
 284         gpio_pad_int_entry(6),
 285         gpio_pad_int_entry(7),
 286         gpio_pad_int_entry(8),
 287         gpio_pad_int_entry(9),
 288         gpio_pad_int_entry(10),
 289         gpio_pad_int_entry(11),
 290         gpio_pad_int_entry(12),
 291         gpio_pad_int_entry(13),
 292         gpio_pad_int_entry(14),
 293         gpio_pad_int_entry(15),
 294         gpio_pad_int_entry(16),
 295         gpio_pad_int_entry(17),
 296         gpio_pad_int_entry(18),
 297         gpio_pad_int_entry(19),
 298         gpio_pad_int_entry(20),
 299         gpio_pad_int_entry(21),
 300         gpio_pad_int_entry(22),
 301         gpio_pad_int_entry(23),
 302         gpio_pad_int_entry(24),
 303         gpio_pad_int_entry(25),
 304         gpio_pad_int_entry(26),
 305         gpio_pad_int_entry(27),
 306         gpio_pad_int_entry(28),
 307         gpio_pad_int_entry(29),
 308         gpio_pad_int_entry(30),
 309         dc_underflow_int_entry(1),
 310         dc_underflow_int_entry(2),
 311         dc_underflow_int_entry(3),
 312         dc_underflow_int_entry(4),
 313         dc_underflow_int_entry(5),
 314         dc_underflow_int_entry(6),
 315         [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
 316         [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
 317         vupdate_int_entry(0),
 318         vupdate_int_entry(1),
 319         vupdate_int_entry(2),
 320         vupdate_int_entry(3),
 321         vupdate_int_entry(4),
 322         vupdate_int_entry(5),
 323         vblank_int_entry(0),
 324         vblank_int_entry(1),
 325         vblank_int_entry(2),
 326         vblank_int_entry(3),
 327         vblank_int_entry(4),
 328         vblank_int_entry(5),
 329 };
 330
 331 static const struct irq_service_funcs irq_service_funcs_dcn10 = {
 332                 .to_dal_irq_source = to_dal_irq_source_dcn10
 333 };
 334
 335 static void construct(
 336         struct irq_service *irq_service,
 337         struct irq_service_init_data *init_data)
 338 {
 339         dal_irq_service_construct(irq_service, init_data);
 340
 341         irq_service->info = irq_source_info_dcn10;
 342         irq_service->funcs = &irq_service_funcs_dcn10;
 343 }
 344
 345 struct irq_service *dal_irq_service_dcn10_create(
 346         struct irq_service_init_data *init_data)
 347 {
 348         struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
 349                                                   GFP_KERNEL);
 350
 351         if (!irq_service)
 352                 return NULL;
 353
 354         construct(irq_service, init_data);
 355         return irq_service;
 356 }