2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #ifndef __DC_HW_SEQUENCER_H__
27 #define __DC_HW_SEQUENCER_H__
29 #include "clock_source.h"
30 #include "inc/hw/timing_generator.h"
31 #include "inc/hw/opp.h"
32 #include "inc/hw/link_encoder.h"
33 #include "core_status.h"
35 enum pipe_gating_control {
36 PIPE_GATING_CONTROL_DISABLE = 0,
37 PIPE_GATING_CONTROL_ENABLE,
38 PIPE_GATING_CONTROL_INIT
42 bool blnd_crtc_trigger;
44 bool false_optc_underflow;
47 struct hwseq_wa_state {
48 bool DEGVIDCN10_253_applied;
52 struct dc_context *ctx;
53 const struct dce_hwseq_registers *regs;
54 const struct dce_hwseq_shift *shifts;
55 const struct dce_hwseq_mask *masks;
56 struct dce_hwseq_wa wa;
57 struct hwseq_wa_state wa_state;
62 struct dchub_init_data;
63 struct dc_static_screen_events;
65 struct resource_context;
67 struct hw_sequencer_funcs {
69 void (*init_hw)(struct dc *dc);
71 enum dc_status (*apply_ctx_to_hw)(
72 struct dc *dc, struct dc_state *context);
74 void (*reset_hw_ctx_wrap)(
75 struct dc *dc, struct dc_state *context);
77 void (*apply_ctx_for_surface)(
79 const struct dc_stream_state *stream,
81 struct dc_state *context);
83 void (*set_plane_config)(
85 struct pipe_ctx *pipe_ctx,
86 struct resource_context *res_ctx);
88 void (*program_gamut_remap)(
89 struct pipe_ctx *pipe_ctx);
91 void (*program_csc_matrix)(
92 struct pipe_ctx *pipe_ctx,
93 enum dc_color_space colorspace,
96 void (*update_plane_addr)(
98 struct pipe_ctx *pipe_ctx);
100 void (*update_dchub)(
101 struct dce_hwseq *hws,
102 struct dchub_init_data *dh_data);
104 void (*update_pending_status)(
105 struct pipe_ctx *pipe_ctx);
107 bool (*set_input_transfer_func)(
108 struct pipe_ctx *pipe_ctx,
109 const struct dc_plane_state *plane_state);
111 bool (*set_output_transfer_func)(
112 struct pipe_ctx *pipe_ctx,
113 const struct dc_stream_state *stream);
115 void (*power_down)(struct dc *dc);
117 void (*enable_accelerated_mode)(struct dc *dc, struct dc_state *context);
119 void (*enable_timing_synchronization)(
123 struct pipe_ctx *grouped_pipes[]);
125 void (*enable_per_frame_crtc_position_reset)(
128 struct pipe_ctx *grouped_pipes[]);
130 void (*enable_display_pipe_clock_gating)(
131 struct dc_context *ctx,
134 bool (*enable_display_power_gating)(
136 uint8_t controller_id,
138 enum pipe_gating_control power_gating);
140 void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx);
142 void (*update_info_frame)(struct pipe_ctx *pipe_ctx);
144 void (*enable_stream)(struct pipe_ctx *pipe_ctx);
146 void (*disable_stream)(struct pipe_ctx *pipe_ctx,
149 void (*unblank_stream)(struct pipe_ctx *pipe_ctx,
150 struct dc_link_settings *link_settings);
152 void (*blank_stream)(struct pipe_ctx *pipe_ctx);
153 void (*pipe_control_lock)(
155 struct pipe_ctx *pipe,
158 void (*set_bandwidth)(
160 struct dc_state *context,
161 bool decrease_allowed);
163 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
166 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
167 struct crtc_position *position);
169 void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,
170 int num_pipes, const struct dc_static_screen_events *events);
172 enum dc_status (*prog_pixclk_crtc_otg)(
173 struct pipe_ctx *pipe_ctx,
174 struct dc_state *context,
177 void (*setup_stereo)(
178 struct pipe_ctx *pipe_ctx,
181 void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable);
183 void (*log_hw_state)(struct dc *dc);
185 void (*wait_for_mpcc_disconnect)(struct dc *dc,
186 struct resource_pool *res_pool,
187 struct pipe_ctx *pipe_ctx);
189 void (*ready_shared_resources)(struct dc *dc, struct dc_state *context);
190 void (*optimize_shared_resources)(struct dc *dc);
191 void (*pplib_apply_display_requirements)(
193 struct dc_state *context);
194 void (*edp_power_control)(
195 struct dc_link *link,
197 void (*edp_backlight_control)(
198 struct dc_link *link,
200 void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up);
202 void (*set_cursor_position)(struct pipe_ctx *pipe);
203 void (*set_cursor_attribute)(struct pipe_ctx *pipe);
206 void color_space_to_black_color(
208 enum dc_color_space colorspace,
209 struct tg_color *black_color);
211 bool hwss_wait_for_blank_complete(
212 struct timing_generator *tg);
214 const uint16_t *find_color_matrix(
215 enum dc_color_space color_space,
216 uint32_t *array_size);
218 #endif /* __DC_HW_SEQUENCER_H__ */