2 * Copyright 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "display_mode_lib.h"
27 #include "display_mode_vba.h"
28 #include "display_rq_dlg_calc.h"
32 * This file is gcc-parseable HW gospel, coming straight from HW engineers.
34 * It doesn't adhere to Linux kernel style and sometimes will do things in odd
35 * ways. Unless there is something clearly wrong with it the code should
36 * remain as-is as it provides us with a guarantee from HW that it is correct.
39 static void calculate_ttu_cursor(struct display_mode_lib *mode_lib,
40 double *refcyc_per_req_delivery_pre_cur,
41 double *refcyc_per_req_delivery_cur,
42 double refclk_freq_in_mhz,
43 double ref_freq_to_pix_freq,
44 double hscale_pixel_rate_l,
48 unsigned int cur_width,
49 enum cursor_bpp cur_bpp);
51 #include "dml_inline_defs.h"
53 static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma)
55 unsigned int ret_val = 0;
57 if (source_format == dm_444_16) {
60 } else if (source_format == dm_444_32) {
63 } else if (source_format == dm_444_64) {
66 } else if (source_format == dm_420_8) {
71 } else if (source_format == dm_420_10) {
76 } else if (source_format == dm_444_8) {
82 static bool is_dual_plane(enum source_format_class source_format)
86 if ((source_format == dm_420_8) || (source_format == dm_420_10))
92 static double get_refcyc_per_delivery(struct display_mode_lib *mode_lib,
93 double refclk_freq_in_mhz,
94 double pclk_freq_in_mhz,
96 unsigned int recout_width,
99 double hscale_pixel_rate,
100 unsigned int delivery_width,
101 unsigned int req_per_swath_ub)
103 double refcyc_per_delivery = 0.0;
107 refcyc_per_delivery = (double) refclk_freq_in_mhz
108 * dml_min((double) recout_width, (double) hactive / 2.0)
109 / pclk_freq_in_mhz / (double) req_per_swath_ub;
111 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width
112 / pclk_freq_in_mhz / (double) req_per_swath_ub;
114 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width
115 / (double) hscale_pixel_rate / (double) req_per_swath_ub;
118 dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz);
119 dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz);
120 dml_print("DML_DLG: %s: recout_width = %d\n", __func__, recout_width);
121 dml_print("DML_DLG: %s: vratio = %3.2f\n", __func__, vratio);
122 dml_print("DML_DLG: %s: req_per_swath_ub = %d\n", __func__, req_per_swath_ub);
123 dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery);
125 return refcyc_per_delivery;
129 static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size)
131 if (tile_size == dm_256k_tile)
133 else if (tile_size == dm_64k_tile)
139 static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib,
140 display_data_rq_regs_st *rq_regs,
141 const display_data_rq_sizing_params_st rq_sizing)
143 dml_print("DML_DLG: %s: rq_sizing param\n", __func__);
144 print__data_rq_sizing_params_st(mode_lib, rq_sizing);
146 rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10;
148 if (rq_sizing.min_chunk_bytes == 0)
149 rq_regs->min_chunk_size = 0;
151 rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;
153 rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;
154 if (rq_sizing.min_meta_chunk_bytes == 0)
155 rq_regs->min_meta_chunk_size = 0;
157 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1;
159 rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6;
160 rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6;
163 static void extract_rq_regs(struct display_mode_lib *mode_lib,
164 display_rq_regs_st *rq_regs,
165 const display_rq_params_st rq_param)
167 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
168 unsigned int detile_buf_plane1_addr = 0;
170 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);
172 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height),
175 if (rq_param.yuv420) {
176 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c);
177 rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height),
181 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
182 rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height);
184 // FIXME: take the max between luma, chroma chunk size?
185 // okay for now, as we are setting chunk_bytes to 8kb anyways
186 if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb
187 rq_regs->drq_expansion_mode = 0;
189 rq_regs->drq_expansion_mode = 2;
191 rq_regs->prq_expansion_mode = 1;
192 rq_regs->mrq_expansion_mode = 1;
193 rq_regs->crq_expansion_mode = 1;
195 if (rq_param.yuv420) {
196 if ((double) rq_param.misc.rq_l.stored_swath_bytes
197 / (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) {
198 detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma
200 detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0),
202 0) / 64.0; // 2/3 to chroma
205 rq_regs->plane1_base_address = detile_buf_plane1_addr;
208 static void handle_det_buf_split(struct display_mode_lib *mode_lib,
209 display_rq_params_st *rq_param,
210 const display_pipe_source_params_st pipe_src_param)
212 unsigned int total_swath_bytes = 0;
213 unsigned int swath_bytes_l = 0;
214 unsigned int swath_bytes_c = 0;
215 unsigned int full_swath_bytes_packed_l = 0;
216 unsigned int full_swath_bytes_packed_c = 0;
219 bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
220 bool surf_vert = (pipe_src_param.source_scan == dm_vert);
221 unsigned int log2_swath_height_l = 0;
222 unsigned int log2_swath_height_c = 0;
223 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
225 full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes;
226 full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes;
228 if (rq_param->yuv420_10bpc) {
229 full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2 / 3,
232 full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2 / 3,
237 if (rq_param->yuv420) {
238 total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c;
240 if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request
243 swath_bytes_l = full_swath_bytes_packed_l;
244 swath_bytes_c = full_swath_bytes_packed_c;
245 } else { //128b request (for luma only for yuv420 8bpc)
248 swath_bytes_l = full_swath_bytes_packed_l / 2;
249 swath_bytes_c = full_swath_bytes_packed_c;
251 // Note: assumption, the config that pass in will fit into
252 // the detiled buffer.
254 total_swath_bytes = 2 * full_swath_bytes_packed_l;
256 if (total_swath_bytes <= detile_buf_size_in_bytes)
261 swath_bytes_l = total_swath_bytes;
264 rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l;
265 rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c;
268 log2_swath_height_l = 0;
269 log2_swath_height_c = 0;
270 } else if (!surf_vert) {
271 log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_height) - req128_l;
272 log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_height) - req128_c;
274 log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_width) - req128_l;
275 log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_width) - req128_c;
277 rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l;
278 rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c;
280 dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l);
281 dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c);
282 dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n",
284 full_swath_bytes_packed_l);
285 dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n",
287 full_swath_bytes_packed_c);
290 static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib,
291 display_data_rq_dlg_params_st *rq_dlg_param,
292 display_data_rq_misc_params_st *rq_misc_param,
293 display_data_rq_sizing_params_st *rq_sizing_param,
294 unsigned int vp_width,
295 unsigned int vp_height,
296 unsigned int data_pitch,
297 unsigned int meta_pitch,
298 unsigned int source_format,
300 unsigned int macro_tile_size,
301 unsigned int source_scan,
302 unsigned int is_chroma)
304 bool surf_linear = (tiling == dm_sw_linear);
305 bool surf_vert = (source_scan == dm_vert);
307 unsigned int bytes_per_element;
308 unsigned int bytes_per_element_y = get_bytes_per_element((enum source_format_class)(source_format),
310 unsigned int bytes_per_element_c = get_bytes_per_element((enum source_format_class)(source_format),
313 unsigned int blk256_width = 0;
314 unsigned int blk256_height = 0;
316 unsigned int blk256_width_y = 0;
317 unsigned int blk256_height_y = 0;
318 unsigned int blk256_width_c = 0;
319 unsigned int blk256_height_c = 0;
320 unsigned int log2_bytes_per_element;
321 unsigned int log2_blk256_width;
322 unsigned int log2_blk256_height;
323 unsigned int blk_bytes;
324 unsigned int log2_blk_bytes;
325 unsigned int log2_blk_height;
326 unsigned int log2_blk_width;
327 unsigned int log2_meta_req_bytes;
328 unsigned int log2_meta_req_height;
329 unsigned int log2_meta_req_width;
330 unsigned int meta_req_width;
331 unsigned int meta_req_height;
332 unsigned int log2_meta_row_height;
333 unsigned int meta_row_width_ub;
334 unsigned int log2_meta_chunk_bytes;
335 unsigned int log2_meta_chunk_height;
337 //full sized meta chunk width in unit of data elements
338 unsigned int log2_meta_chunk_width;
339 unsigned int log2_min_meta_chunk_bytes;
340 unsigned int min_meta_chunk_width;
341 unsigned int meta_chunk_width;
342 unsigned int meta_chunk_per_row_int;
343 unsigned int meta_row_remainder;
344 unsigned int meta_chunk_threshold;
345 unsigned int meta_blk_bytes;
346 unsigned int meta_blk_height;
347 unsigned int meta_blk_width;
348 unsigned int meta_surface_bytes;
349 unsigned int vmpg_bytes;
350 unsigned int meta_pte_req_per_frame_ub;
351 unsigned int meta_pte_bytes_per_frame_ub;
352 const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes);
353 const unsigned int dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs;
354 const unsigned int pde_proc_buffer_size_64k_reqs =
355 mode_lib->ip.pde_proc_buffer_size_64k_reqs;
357 unsigned int log2_vmpg_height = 0;
358 unsigned int log2_vmpg_width = 0;
359 unsigned int log2_dpte_req_height_ptes = 0;
360 unsigned int log2_dpte_req_height = 0;
361 unsigned int log2_dpte_req_width = 0;
362 unsigned int log2_dpte_row_height_linear = 0;
363 unsigned int log2_dpte_row_height = 0;
364 unsigned int log2_dpte_group_width = 0;
365 unsigned int dpte_row_width_ub = 0;
366 unsigned int dpte_req_height = 0;
367 unsigned int dpte_req_width = 0;
368 unsigned int dpte_group_width = 0;
369 unsigned int log2_dpte_group_bytes = 0;
370 unsigned int log2_dpte_group_length = 0;
371 unsigned int pde_buf_entries;
372 bool yuv420 = (source_format == dm_420_8 || source_format == dm_420_10);
374 Calculate256BBlockSizes((enum source_format_class)(source_format),
375 (enum dm_swizzle_mode)(tiling),
384 blk256_width = blk256_width_y;
385 blk256_height = blk256_height_y;
386 bytes_per_element = bytes_per_element_y;
388 blk256_width = blk256_width_c;
389 blk256_height = blk256_height_c;
390 bytes_per_element = bytes_per_element_c;
393 log2_bytes_per_element = dml_log2(bytes_per_element);
395 dml_print("DML_DLG: %s: surf_linear = %d\n", __func__, surf_linear);
396 dml_print("DML_DLG: %s: surf_vert = %d\n", __func__, surf_vert);
397 dml_print("DML_DLG: %s: blk256_width = %d\n", __func__, blk256_width);
398 dml_print("DML_DLG: %s: blk256_height = %d\n", __func__, blk256_height);
400 log2_blk256_width = dml_log2((double) blk256_width);
401 log2_blk256_height = dml_log2((double) blk256_height);
402 blk_bytes = surf_linear ?
403 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size);
404 log2_blk_bytes = dml_log2((double) blk_bytes);
409 // "+" in log is multiply
410 // "-" in log is divide
411 // "/2" is like square root
412 // blk is vertical biased
413 if (tiling != dm_sw_linear)
414 log2_blk_height = log2_blk256_height
415 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
417 log2_blk_height = 0; // blk height of 1
419 log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height;
422 rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1)
424 rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width;
426 rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_height - 1, blk256_height, 1)
428 rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height;
432 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height
435 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width
438 rq_misc_param->blk256_height = blk256_height;
439 rq_misc_param->blk256_width = blk256_width;
444 log2_meta_req_bytes = 6; // meta request is 64b and is 8x8byte meta element
446 // each 64b meta request for dcn is 8x8 meta elements and
447 // a meta element covers one 256b block of the the data surface.
448 log2_meta_req_height = log2_blk256_height + 3; // meta req is 8x8 byte, each byte represent 1 blk256
449 log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element
450 - log2_meta_req_height;
451 meta_req_width = 1 << log2_meta_req_width;
452 meta_req_height = 1 << log2_meta_req_height;
453 log2_meta_row_height = 0;
454 meta_row_width_ub = 0;
456 // the dimensions of a meta row are meta_row_width x meta_row_height in elements.
457 // calculate upper bound of the meta_row_width
459 log2_meta_row_height = log2_meta_req_height;
460 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1)
462 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width;
464 log2_meta_row_height = log2_meta_req_width;
465 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1)
467 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height;
469 rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64;
471 rq_dlg_param->meta_row_height = 1 << log2_meta_row_height;
473 log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes);
474 log2_meta_chunk_height = log2_meta_row_height;
476 //full sized meta chunk width in unit of data elements
477 log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element
478 - log2_meta_chunk_height;
479 log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes);
480 min_meta_chunk_width = 1
481 << (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element
482 - log2_meta_chunk_height);
483 meta_chunk_width = 1 << log2_meta_chunk_width;
484 meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width);
485 meta_row_remainder = meta_row_width_ub % meta_chunk_width;
486 meta_chunk_threshold = 0;
487 meta_blk_bytes = 4096;
488 meta_blk_height = blk256_height * 64;
489 meta_blk_width = meta_blk_bytes * 256 / bytes_per_element / meta_blk_height;
490 meta_surface_bytes = meta_pitch
491 * (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1) + meta_blk_height)
492 * bytes_per_element / 256;
493 vmpg_bytes = mode_lib->soc.vmm_page_size_bytes;
494 meta_pte_req_per_frame_ub = (dml_round_to_multiple(meta_surface_bytes - vmpg_bytes,
496 1) + 8 * vmpg_bytes) / (8 * vmpg_bytes);
497 meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; //64B mpte request
498 rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub;
500 dml_print("DML_DLG: %s: meta_blk_height = %d\n", __func__, meta_blk_height);
501 dml_print("DML_DLG: %s: meta_blk_width = %d\n", __func__, meta_blk_width);
502 dml_print("DML_DLG: %s: meta_surface_bytes = %d\n", __func__, meta_surface_bytes);
503 dml_print("DML_DLG: %s: meta_pte_req_per_frame_ub = %d\n",
505 meta_pte_req_per_frame_ub);
506 dml_print("DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n",
508 meta_pte_bytes_per_frame_ub);
511 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
513 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height;
515 if (meta_row_remainder <= meta_chunk_threshold)
516 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1;
518 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2;
524 log2_vmpg_height = 0; // one line high
526 log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height;
528 log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height;
530 // only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4.
531 if (surf_linear) { //one 64B PTE request returns 8 PTEs
532 log2_dpte_req_height_ptes = 0;
533 log2_dpte_req_width = log2_vmpg_width + 3;
534 log2_dpte_req_height = 0;
535 } else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size
536 //one 64B req gives 8x1 PTEs for 4KB tile
537 log2_dpte_req_height_ptes = 0;
538 log2_dpte_req_width = log2_blk_width + 3;
539 log2_dpte_req_height = log2_blk_height + 0;
540 } else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB
541 //two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB
542 log2_dpte_req_height_ptes = 4;
543 log2_dpte_req_width = log2_blk256_width + 4; // log2_64KB_width
544 log2_dpte_req_height = log2_blk256_height + 4; // log2_64KB_height
545 } else { //64KB page size and must 64KB tile block
546 //one 64B req gives 8x1 PTEs for 64KB tile
547 log2_dpte_req_height_ptes = 0;
548 log2_dpte_req_width = log2_blk_width + 3;
549 log2_dpte_req_height = log2_blk_height + 0;
552 // The dpte request dimensions in data elements is dpte_req_width x dpte_req_height
553 // log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent
554 // That depends on the pte shape (i.e. 8x1, 4x2, 2x4)
555 //log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes;
556 //log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes;
557 dpte_req_height = 1 << log2_dpte_req_height;
558 dpte_req_width = 1 << log2_dpte_req_width;
560 // calculate pitch dpte row buffer can hold
561 // round the result down to a power of two.
562 pde_buf_entries = yuv420 ? (pde_proc_buffer_size_64k_reqs >> 1) : pde_proc_buffer_size_64k_reqs;
564 unsigned int dpte_row_height;
566 log2_dpte_row_height_linear = dml_floor(dml_log2(dml_min(64 * 1024 * pde_buf_entries
573 ASSERT(log2_dpte_row_height_linear >= 3);
575 if (log2_dpte_row_height_linear > 7)
576 log2_dpte_row_height_linear = 7;
578 log2_dpte_row_height = log2_dpte_row_height_linear;
579 // For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary.
580 // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
581 dpte_row_height = 1 << log2_dpte_row_height;
582 dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1,
585 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
587 // the upper bound of the dpte_row_width without dependency on viewport position follows.
588 // for tiled mode, row height is the same as req height and row store up to vp size upper bound
590 log2_dpte_row_height = log2_dpte_req_height;
591 dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
593 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
595 log2_dpte_row_height =
596 (log2_blk_width < log2_dpte_req_width) ?
597 log2_blk_width : log2_dpte_req_width;
598 dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1)
600 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height;
603 if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB
604 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request
606 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request
608 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
610 // the dpte_group_bytes is reduced for the specific case of vertical
611 // access of a tile surface that has dpte request of 8x1 ptes.
612 if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group
613 rq_sizing_param->dpte_group_bytes = 512;
616 rq_sizing_param->dpte_group_bytes = 2048;
618 //since pte request size is 64byte, the number of data pte requests per full sized group is as follows.
619 log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes);
620 log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests
622 // full sized data pte group width in elements
624 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width;
626 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height;
628 //But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B
629 if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB
630 log2_dpte_group_width = log2_dpte_group_width - 1;
632 dpte_group_width = 1 << log2_dpte_group_width;
634 // since dpte groups are only aligned to dpte_req_width and not dpte_group_width,
635 // the upper bound for the dpte groups per row is as follows.
636 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width,
640 static void get_surf_rq_param(struct display_mode_lib *mode_lib,
641 display_data_rq_sizing_params_st *rq_sizing_param,
642 display_data_rq_dlg_params_st *rq_dlg_param,
643 display_data_rq_misc_params_st *rq_misc_param,
644 const display_pipe_source_params_st pipe_src_param,
648 unsigned int vp_width = 0;
649 unsigned int vp_height = 0;
650 unsigned int data_pitch = 0;
651 unsigned int meta_pitch = 0;
652 unsigned int ppe = mode_422 ? 2 : 1;
654 // FIXME check if ppe apply for both luma and chroma in 422 case
656 vp_width = pipe_src_param.viewport_width_c / ppe;
657 vp_height = pipe_src_param.viewport_height_c;
658 data_pitch = pipe_src_param.data_pitch_c;
659 meta_pitch = pipe_src_param.meta_pitch_c;
661 vp_width = pipe_src_param.viewport_width / ppe;
662 vp_height = pipe_src_param.viewport_height;
663 data_pitch = pipe_src_param.data_pitch;
664 meta_pitch = pipe_src_param.meta_pitch;
667 rq_sizing_param->chunk_bytes = 8192;
669 if (rq_sizing_param->chunk_bytes == 64 * 1024)
670 rq_sizing_param->min_chunk_bytes = 0;
672 rq_sizing_param->min_chunk_bytes = 1024;
674 rq_sizing_param->meta_chunk_bytes = 2048;
675 rq_sizing_param->min_meta_chunk_bytes = 256;
677 rq_sizing_param->mpte_group_bytes = 2048;
679 get_meta_and_pte_attr(mode_lib,
687 pipe_src_param.source_format,
688 pipe_src_param.sw_mode,
689 pipe_src_param.macro_tile_size,
690 pipe_src_param.source_scan,
694 void dml_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib,
695 display_rq_params_st *rq_param,
696 const display_pipe_source_params_st pipe_src_param)
698 // get param for luma surface
699 rq_param->yuv420 = pipe_src_param.source_format == dm_420_8
700 || pipe_src_param.source_format == dm_420_10;
701 rq_param->yuv420_10bpc = pipe_src_param.source_format == dm_420_10;
703 get_surf_rq_param(mode_lib,
704 &(rq_param->sizing.rq_l),
705 &(rq_param->dlg.rq_l),
706 &(rq_param->misc.rq_l),
710 if (is_dual_plane((enum source_format_class)(pipe_src_param.source_format))) {
711 // get param for chroma surface
712 get_surf_rq_param(mode_lib,
713 &(rq_param->sizing.rq_c),
714 &(rq_param->dlg.rq_c),
715 &(rq_param->misc.rq_c),
720 // calculate how to split the det buffer space between luma and chroma
721 handle_det_buf_split(mode_lib, rq_param, pipe_src_param);
722 print__rq_params_st(mode_lib, *rq_param);
725 void dml_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib,
726 display_rq_regs_st *rq_regs,
727 const display_pipe_source_params_st pipe_src_param)
729 display_rq_params_st rq_param = {0};
731 memset(rq_regs, 0, sizeof(*rq_regs));
732 dml_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_src_param);
733 extract_rq_regs(mode_lib, rq_regs, rq_param);
735 print__rq_regs_st(mode_lib, *rq_regs);
738 // Note: currently taken in as is.
739 // Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma.
740 void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,
741 const display_e2e_pipe_params_st *e2e_pipe_param,
742 const unsigned int num_pipes,
743 const unsigned int pipe_idx,
744 display_dlg_regs_st *disp_dlg_regs,
745 display_ttu_regs_st *disp_ttu_regs,
746 const display_rq_dlg_params_st rq_dlg_param,
747 const display_dlg_sys_params_st dlg_sys_param,
748 const bool cstate_en,
749 const bool pstate_en,
751 const bool ignore_viewport_pos,
752 const bool immediate_flip_support)
754 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
755 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
756 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout;
757 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;
758 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth;
759 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps;
761 // -------------------------
762 // Section 1.15.2.1: OTG dependent Params
763 // -------------------------
765 unsigned int htotal = dst->htotal;
766 // unsigned int hblank_start = dst.hblank_start; // TODO: Remove
767 unsigned int hblank_end = dst->hblank_end;
768 unsigned int vblank_start = dst->vblank_start;
769 unsigned int vblank_end = dst->vblank_end;
770 unsigned int min_vblank = mode_lib->ip.min_vblank_lines;
772 double dppclk_freq_in_mhz = clks->dppclk_mhz;
773 double dispclk_freq_in_mhz = clks->dispclk_mhz;
774 double refclk_freq_in_mhz = clks->refclk_mhz;
775 double pclk_freq_in_mhz = dst->pixel_rate_mhz;
776 bool interlaced = dst->interlaced;
778 double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz;
780 double min_dcfclk_mhz;
782 double min_ttu_vblank;
784 double min_dst_y_ttu_vblank;
785 unsigned int dlg_vblank_start;
788 unsigned int access_dir;
789 unsigned int vp_height_l;
790 unsigned int vp_width_l;
791 unsigned int vp_height_c;
792 unsigned int vp_width_c;
795 unsigned int htaps_l;
796 unsigned int htaps_c;
803 double line_time_in_us;
806 // double vinit_bot_l;
807 // double vinit_bot_c;
809 // unsigned int swath_height_l;
810 unsigned int swath_width_ub_l;
811 // unsigned int dpte_bytes_per_row_ub_l;
812 unsigned int dpte_groups_per_row_ub_l;
813 // unsigned int meta_pte_bytes_per_frame_ub_l;
814 // unsigned int meta_bytes_per_row_ub_l;
816 // unsigned int swath_height_c;
817 unsigned int swath_width_ub_c;
818 // unsigned int dpte_bytes_per_row_ub_c;
819 unsigned int dpte_groups_per_row_ub_c;
821 unsigned int meta_chunks_per_row_ub_l;
822 unsigned int meta_chunks_per_row_ub_c;
823 unsigned int vupdate_offset;
824 unsigned int vupdate_width;
825 unsigned int vready_offset;
827 unsigned int dppclk_delay_subtotal;
828 unsigned int dispclk_delay_subtotal;
829 unsigned int pixel_rate_delay_subtotal;
831 unsigned int vstartup_start;
832 unsigned int dst_x_after_scaler;
833 unsigned int dst_y_after_scaler;
835 double dst_y_prefetch;
836 double dst_y_per_vm_vblank;
837 double dst_y_per_row_vblank;
838 double dst_y_per_vm_flip;
839 double dst_y_per_row_flip;
840 double min_dst_y_per_vm_vblank;
841 double min_dst_y_per_row_vblank;
845 unsigned int req_per_swath_ub_l;
846 unsigned int req_per_swath_ub_c;
847 unsigned int meta_row_height_l;
848 unsigned int meta_row_height_c;
849 unsigned int swath_width_pixels_ub_l;
850 unsigned int swath_width_pixels_ub_c;
851 unsigned int scaler_rec_in_width_l;
852 unsigned int scaler_rec_in_width_c;
853 unsigned int dpte_row_height_l;
854 unsigned int dpte_row_height_c;
855 double hscale_pixel_rate_l;
856 double hscale_pixel_rate_c;
857 double min_hratio_fact_l;
858 double min_hratio_fact_c;
859 double refcyc_per_line_delivery_pre_l;
860 double refcyc_per_line_delivery_pre_c;
861 double refcyc_per_line_delivery_l;
862 double refcyc_per_line_delivery_c;
864 double refcyc_per_req_delivery_pre_l;
865 double refcyc_per_req_delivery_pre_c;
866 double refcyc_per_req_delivery_l;
867 double refcyc_per_req_delivery_c;
869 unsigned int full_recout_width;
870 double xfc_transfer_delay;
871 double xfc_precharge_delay;
872 double xfc_remote_surface_flip_latency;
873 double xfc_dst_y_delta_drq_limit;
874 double xfc_prefetch_margin;
875 double refcyc_per_req_delivery_pre_cur0;
876 double refcyc_per_req_delivery_cur0;
877 double refcyc_per_req_delivery_pre_cur1;
878 double refcyc_per_req_delivery_cur1;
880 memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs));
881 memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs));
883 dml_print("DML_DLG: %s: cstate_en = %d\n", __func__, cstate_en);
884 dml_print("DML_DLG: %s: pstate_en = %d\n", __func__, pstate_en);
885 dml_print("DML_DLG: %s: vm_en = %d\n", __func__, vm_en);
886 dml_print("DML_DLG: %s: ignore_viewport_pos = %d\n", __func__, ignore_viewport_pos);
887 dml_print("DML_DLG: %s: immediate_flip_support = %d\n", __func__, immediate_flip_support);
889 dml_print("DML_DLG: %s: dppclk_freq_in_mhz = %3.2f\n", __func__, dppclk_freq_in_mhz);
890 dml_print("DML_DLG: %s: dispclk_freq_in_mhz = %3.2f\n", __func__, dispclk_freq_in_mhz);
891 dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz);
892 dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz);
893 dml_print("DML_DLG: %s: interlaced = %d\n", __func__, interlaced);
894 ASSERT(ref_freq_to_pix_freq < 4.0);
896 disp_dlg_regs->ref_freq_to_pix_freq =
897 (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));
898 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal
900 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits
901 disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end
902 * (double) ref_freq_to_pix_freq);
903 ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13));
905 min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz;
906 set_prefetch_mode(mode_lib, cstate_en, pstate_en, ignore_viewport_pos, immediate_flip_support);
907 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes);
908 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
910 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal;
911 dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start;
913 disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start
914 + min_dst_y_ttu_vblank) * dml_pow(2, 2));
915 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));
917 dml_print("DML_DLG: %s: min_dcfclk_mhz = %3.2f\n",
920 dml_print("DML_DLG: %s: min_ttu_vblank = %3.2f\n",
923 dml_print("DML_DLG: %s: min_dst_y_ttu_vblank = %3.2f\n",
925 min_dst_y_ttu_vblank);
926 dml_print("DML_DLG: %s: t_calc_us = %3.2f\n",
929 dml_print("DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x\n",
931 disp_dlg_regs->min_dst_y_next_start);
932 dml_print("DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n",
934 ref_freq_to_pix_freq);
936 // -------------------------
937 // Section 1.15.2.2: Prefetch, Active and TTU
938 // -------------------------
942 dual_plane = is_dual_plane((enum source_format_class)(src->source_format));
943 mode_422 = 0; // FIXME
944 access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
945 // bytes_per_element_l = get_bytes_per_element(source_format_class(src.source_format), 0);
946 // bytes_per_element_c = get_bytes_per_element(source_format_class(src.source_format), 1);
947 vp_height_l = src->viewport_height;
948 vp_width_l = src->viewport_width;
949 vp_height_c = src->viewport_height_c;
950 vp_width_c = src->viewport_width_c;
953 htaps_l = taps->htaps;
954 htaps_c = taps->htaps_c;
955 hratio_l = scl->hscl_ratio;
956 hratio_c = scl->hscl_ratio_c;
957 vratio_l = scl->vscl_ratio;
958 vratio_c = scl->vscl_ratio_c;
959 scl_enable = scl->scl_enable;
961 line_time_in_us = (htotal / pclk_freq_in_mhz);
962 // vinit_l = scl.vinit;
963 // vinit_c = scl.vinit_c;
964 // vinit_bot_l = scl.vinit_bot;
965 // vinit_bot_c = scl.vinit_bot_c;
967 // unsigned int swath_height_l = rq_dlg_param.rq_l.swath_height;
968 swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub;
969 // unsigned int dpte_bytes_per_row_ub_l = rq_dlg_param.rq_l.dpte_bytes_per_row_ub;
970 dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub;
971 // unsigned int meta_pte_bytes_per_frame_ub_l = rq_dlg_param.rq_l.meta_pte_bytes_per_frame_ub;
972 // unsigned int meta_bytes_per_row_ub_l = rq_dlg_param.rq_l.meta_bytes_per_row_ub;
974 // unsigned int swath_height_c = rq_dlg_param.rq_c.swath_height;
975 swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub;
976 // dpte_bytes_per_row_ub_c = rq_dlg_param.rq_c.dpte_bytes_per_row_ub;
977 dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub;
979 meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub;
980 meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub;
981 vupdate_offset = dst->vupdate_offset;
982 vupdate_width = dst->vupdate_width;
983 vready_offset = dst->vready_offset;
985 dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal;
986 dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal;
989 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl;
991 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl_lb_only;
993 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_cnvc_formatter
994 + src->num_cursors * mode_lib->ip.dppclk_delay_cnvc_cursor;
996 if (dout->dsc_enable) {
997 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
999 dispclk_delay_subtotal += dsc_delay;
1002 pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz
1003 + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz;
1005 vstartup_start = dst->vstartup_start;
1007 if (vstartup_start / 2.0
1008 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
1009 <= vblank_end / 2.0)
1010 disp_dlg_regs->vready_after_vcount0 = 1;
1012 disp_dlg_regs->vready_after_vcount0 = 0;
1015 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
1017 disp_dlg_regs->vready_after_vcount0 = 1;
1019 disp_dlg_regs->vready_after_vcount0 = 0;
1022 // TODO: Where is this coming from?
1024 vstartup_start = vstartup_start / 2;
1026 // TODO: What if this min_vblank doesn't match the value in the dml_config_settings.cpp?
1027 if (vstartup_start >= min_vblank) {
1028 dml_print("WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d\n",
1032 dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n",
1036 min_vblank = vstartup_start + 1;
1037 dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n",
1043 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1044 dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1046 dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal);
1047 dml_print("DML_DLG: %s: pixel_rate_delay_subtotal = %d\n",
1049 pixel_rate_delay_subtotal);
1050 dml_print("DML_DLG: %s: dst_x_after_scaler = %d\n",
1052 dst_x_after_scaler);
1053 dml_print("DML_DLG: %s: dst_y_after_scaler = %d\n",
1055 dst_y_after_scaler);
1058 line_wait = mode_lib->soc.urgent_latency_us;
1060 line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait);
1062 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us
1063 + mode_lib->soc.urgent_latency_us,
1065 line_wait = line_wait / line_time_in_us;
1067 dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1068 dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch);
1070 dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib,
1074 dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib,
1078 dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1079 dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1081 min_dst_y_per_vm_vblank = 8.0;
1082 min_dst_y_per_row_vblank = 16.0;
1087 min_dst_y_per_vm_vblank = 100.0;
1088 min_dst_y_per_row_vblank = 100.0;
1091 dml_print("DML_DLG: %s: dst_y_per_vm_vblank = %3.2f\n", __func__, dst_y_per_vm_vblank);
1092 dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank);
1094 ASSERT(dst_y_per_vm_vblank < min_dst_y_per_vm_vblank);
1095 ASSERT(dst_y_per_row_vblank < min_dst_y_per_row_vblank);
1097 ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
1098 lsw = dst_y_prefetch - (dst_y_per_vm_vblank + dst_y_per_row_vblank);
1100 dml_print("DML_DLG: %s: lsw = %3.2f\n", __func__, lsw);
1102 vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1103 vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1105 dml_print("DML_DLG: %s: vratio_pre_l=%3.2f\n", __func__, vratio_pre_l);
1106 dml_print("DML_DLG: %s: vratio_pre_c=%3.2f\n", __func__, vratio_pre_c);
1109 req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub;
1110 req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub;
1111 meta_row_height_l = rq_dlg_param.rq_l.meta_row_height;
1112 meta_row_height_c = rq_dlg_param.rq_c.meta_row_height;
1113 swath_width_pixels_ub_l = 0;
1114 swath_width_pixels_ub_c = 0;
1115 scaler_rec_in_width_l = 0;
1116 scaler_rec_in_width_c = 0;
1117 dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height;
1118 dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height;
1121 swath_width_pixels_ub_l = swath_width_ub_l * 2; // *2 for 2 pixel per element
1122 swath_width_pixels_ub_c = swath_width_ub_c * 2;
1124 swath_width_pixels_ub_l = swath_width_ub_l * 1;
1125 swath_width_pixels_ub_c = swath_width_ub_c * 1;
1128 hscale_pixel_rate_l = 0.;
1129 hscale_pixel_rate_c = 0.;
1130 min_hratio_fact_l = 1.0;
1131 min_hratio_fact_c = 1.0;
1134 min_hratio_fact_l = 2.0;
1135 else if (htaps_l <= 6) {
1136 if ((hratio_l * 2.0) > 4.0)
1137 min_hratio_fact_l = 4.0;
1139 min_hratio_fact_l = hratio_l * 2.0;
1142 min_hratio_fact_l = 4.0;
1144 min_hratio_fact_l = hratio_l;
1147 hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz;
1150 min_hratio_fact_c = 2.0;
1151 else if (htaps_c <= 6) {
1152 if ((hratio_c * 2.0) > 4.0)
1153 min_hratio_fact_c = 4.0;
1155 min_hratio_fact_c = hratio_c * 2.0;
1158 min_hratio_fact_c = 4.0;
1160 min_hratio_fact_c = hratio_c;
1163 hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz;
1165 refcyc_per_line_delivery_pre_l = 0.;
1166 refcyc_per_line_delivery_pre_c = 0.;
1167 refcyc_per_line_delivery_l = 0.;
1168 refcyc_per_line_delivery_c = 0.;
1170 refcyc_per_req_delivery_pre_l = 0.;
1171 refcyc_per_req_delivery_pre_c = 0.;
1172 refcyc_per_req_delivery_l = 0.;
1173 refcyc_per_req_delivery_c = 0.;
1175 full_recout_width = 0;
1177 if (src->is_hsplit) {
1178 // This "hack" is only allowed (and valid) for MPC combine. In ODM
1179 // combine, you MUST specify the full_recout_width...according to Oswin
1180 if (dst->full_recout_width == 0 && !dst->odm_combine) {
1181 dml_print("DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n",
1183 full_recout_width = dst->recout_width * 2; // assume half split for dcn1
1185 full_recout_width = dst->full_recout_width;
1187 full_recout_width = dst->recout_width;
1189 // mpc_combine and odm_combine are mutually exclusive
1190 refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(mode_lib,
1197 hscale_pixel_rate_l,
1198 swath_width_pixels_ub_l,
1201 refcyc_per_line_delivery_l = get_refcyc_per_delivery(mode_lib,
1208 hscale_pixel_rate_l,
1209 swath_width_pixels_ub_l,
1212 dml_print("DML_DLG: %s: full_recout_width = %d\n",
1215 dml_print("DML_DLG: %s: hscale_pixel_rate_l = %3.2f\n",
1217 hscale_pixel_rate_l);
1218 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n",
1220 refcyc_per_line_delivery_pre_l);
1221 dml_print("DML_DLG: %s: refcyc_per_line_delivery_l = %3.2f\n",
1223 refcyc_per_line_delivery_l);
1226 refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery(mode_lib,
1233 hscale_pixel_rate_c,
1234 swath_width_pixels_ub_c,
1237 refcyc_per_line_delivery_c = get_refcyc_per_delivery(mode_lib,
1244 hscale_pixel_rate_c,
1245 swath_width_pixels_ub_c,
1248 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n",
1250 refcyc_per_line_delivery_pre_c);
1251 dml_print("DML_DLG: %s: refcyc_per_line_delivery_c = %3.2f\n",
1253 refcyc_per_line_delivery_c);
1256 // TTU - Luma / Chroma
1257 if (access_dir) { // vertical access
1258 scaler_rec_in_width_l = vp_height_l;
1259 scaler_rec_in_width_c = vp_height_c;
1261 scaler_rec_in_width_l = vp_width_l;
1262 scaler_rec_in_width_c = vp_width_c;
1265 refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery(mode_lib,
1272 hscale_pixel_rate_l,
1273 scaler_rec_in_width_l,
1274 req_per_swath_ub_l); // per req
1275 refcyc_per_req_delivery_l = get_refcyc_per_delivery(mode_lib,
1282 hscale_pixel_rate_l,
1283 scaler_rec_in_width_l,
1284 req_per_swath_ub_l); // per req
1286 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n",
1288 refcyc_per_req_delivery_pre_l);
1289 dml_print("DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f\n",
1291 refcyc_per_req_delivery_l);
1293 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));
1294 ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
1297 refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery(mode_lib,
1304 hscale_pixel_rate_c,
1305 scaler_rec_in_width_c,
1306 req_per_swath_ub_c); // per req
1307 refcyc_per_req_delivery_c = get_refcyc_per_delivery(mode_lib,
1314 hscale_pixel_rate_c,
1315 scaler_rec_in_width_c,
1316 req_per_swath_ub_c); // per req
1318 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n",
1320 refcyc_per_req_delivery_pre_c);
1321 dml_print("DML_DLG: %s: refcyc_per_req_delivery_c = %3.2f\n",
1323 refcyc_per_req_delivery_c);
1325 ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));
1326 ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
1330 xfc_transfer_delay = get_xfc_transfer_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1331 xfc_precharge_delay = get_xfc_precharge_delay(mode_lib,
1335 xfc_remote_surface_flip_latency = get_xfc_remote_surface_flip_latency(mode_lib,
1339 xfc_dst_y_delta_drq_limit = xfc_remote_surface_flip_latency;
1340 xfc_prefetch_margin = get_xfc_prefetch_margin(mode_lib,
1346 refcyc_per_req_delivery_pre_cur0 = 0.0;
1347 refcyc_per_req_delivery_cur0 = 0.0;
1348 if (src->num_cursors > 0) {
1349 calculate_ttu_cursor(mode_lib,
1350 &refcyc_per_req_delivery_pre_cur0,
1351 &refcyc_per_req_delivery_cur0,
1353 ref_freq_to_pix_freq,
1354 hscale_pixel_rate_l,
1358 src->cur0_src_width,
1359 (enum cursor_bpp)(src->cur0_bpp));
1362 refcyc_per_req_delivery_pre_cur1 = 0.0;
1363 refcyc_per_req_delivery_cur1 = 0.0;
1364 if (src->num_cursors > 1) {
1365 calculate_ttu_cursor(mode_lib,
1366 &refcyc_per_req_delivery_pre_cur1,
1367 &refcyc_per_req_delivery_cur1,
1369 ref_freq_to_pix_freq,
1370 hscale_pixel_rate_l,
1374 src->cur1_src_width,
1375 (enum cursor_bpp)(src->cur1_bpp));
1381 // Assignment to register structures
1382 disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line
1383 disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk
1384 ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13));
1385 disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));
1386 disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));
1387 disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));
1388 disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2));
1389 disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));
1391 disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));
1392 disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));
1394 disp_dlg_regs->refcyc_per_pte_group_vblank_l =
1395 (unsigned int) (dst_y_per_row_vblank * (double) htotal
1396 * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l);
1397 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13));
1400 disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank
1401 * (double) htotal * ref_freq_to_pix_freq
1402 / (double) dpte_groups_per_row_ub_c);
1403 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c
1404 < (unsigned int) dml_pow(2, 13));
1407 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l =
1408 (unsigned int) (dst_y_per_row_vblank * (double) htotal
1409 * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l);
1410 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13));
1412 disp_dlg_regs->refcyc_per_meta_chunk_vblank_c =
1413 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now
1415 disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal
1416 * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l;
1417 disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal
1418 * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l;
1421 disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip
1422 * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c;
1423 disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip
1424 * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c;
1427 disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l
1428 / (double) vratio_l * dml_pow(2, 2));
1429 ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17));
1432 disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c
1433 / (double) vratio_c * dml_pow(2, 2));
1434 if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {
1435 dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n",
1437 disp_dlg_regs->dst_y_per_pte_row_nom_c,
1438 (unsigned int) dml_pow(2, 17) - 1);
1442 disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l
1443 / (double) vratio_l * dml_pow(2, 2));
1444 ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17));
1446 disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now
1448 disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l
1449 / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
1450 / (double) dpte_groups_per_row_ub_l);
1451 if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))
1452 disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;
1453 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l
1454 / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
1455 / (double) meta_chunks_per_row_ub_l);
1456 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))
1457 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;
1460 disp_dlg_regs->refcyc_per_pte_group_nom_c =
1461 (unsigned int) ((double) dpte_row_height_c / (double) vratio_c
1462 * (double) htotal * ref_freq_to_pix_freq
1463 / (double) dpte_groups_per_row_ub_c);
1464 if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))
1465 disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;
1467 // TODO: Is this the right calculation? Does htotal need to be halved?
1468 disp_dlg_regs->refcyc_per_meta_chunk_nom_c =
1469 (unsigned int) ((double) meta_row_height_c / (double) vratio_c
1470 * (double) htotal * ref_freq_to_pix_freq
1471 / (double) meta_chunks_per_row_ub_c);
1472 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))
1473 disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1;
1476 disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l,
1478 disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l,
1480 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13));
1481 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13));
1483 disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c,
1485 disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(refcyc_per_line_delivery_c,
1487 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13));
1488 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13));
1490 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3;
1491 disp_dlg_regs->dst_y_offset_cur0 = 0;
1492 disp_dlg_regs->chunk_hdl_adjust_cur1 = 3;
1493 disp_dlg_regs->dst_y_offset_cur1 = 0;
1495 disp_dlg_regs->xfc_reg_transfer_delay = xfc_transfer_delay;
1496 disp_dlg_regs->xfc_reg_precharge_delay = xfc_precharge_delay;
1497 disp_dlg_regs->xfc_reg_remote_surface_flip_latency = xfc_remote_surface_flip_latency;
1498 disp_dlg_regs->xfc_reg_prefetch_margin = dml_ceil(xfc_prefetch_margin * refclk_freq_in_mhz,
1501 // slave has to have this value also set to off
1502 if (src->xfc_enable && !src->xfc_slave)
1503 disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1);
1505 disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off
1507 disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l
1509 disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l
1511 disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c
1513 disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c
1515 disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 =
1516 (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));
1517 disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0
1519 disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 =
1520 (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10));
1521 disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1
1523 disp_ttu_regs->qos_level_low_wm = 0;
1524 ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
1525 disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal
1526 * ref_freq_to_pix_freq);
1527 ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
1529 disp_ttu_regs->qos_level_flip = 14;
1530 disp_ttu_regs->qos_level_fixed_l = 8;
1531 disp_ttu_regs->qos_level_fixed_c = 8;
1532 disp_ttu_regs->qos_level_fixed_cur0 = 8;
1533 disp_ttu_regs->qos_ramp_disable_l = 0;
1534 disp_ttu_regs->qos_ramp_disable_c = 0;
1535 disp_ttu_regs->qos_ramp_disable_cur0 = 0;
1537 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;
1538 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
1540 print__ttu_regs_st(mode_lib, *disp_ttu_regs);
1541 print__dlg_regs_st(mode_lib, *disp_dlg_regs);
1544 void dml_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
1545 display_dlg_regs_st *dlg_regs,
1546 display_ttu_regs_st *ttu_regs,
1547 display_e2e_pipe_params_st *e2e_pipe_param,
1548 const unsigned int num_pipes,
1549 const unsigned int pipe_idx,
1550 const bool cstate_en,
1551 const bool pstate_en,
1553 const bool ignore_viewport_pos,
1554 const bool immediate_flip_support)
1556 display_rq_params_st rq_param = {0};
1557 display_dlg_sys_params_st dlg_sys_param = {0};
1559 // Get watermark and Tex.
1560 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes);
1561 dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib,
1564 dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes);
1565 dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes);
1566 dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes);
1567 dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes);
1568 dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib,
1571 dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib,
1574 dlg_sys_param.t_srx_delay_us = mode_lib->ip.dcfclk_cstate_latency
1575 / dlg_sys_param.deepsleep_dcfclk_mhz; // TODO: Deprecated
1577 print__dlg_sys_params_st(mode_lib, dlg_sys_param);
1579 // system parameter calculation done
1581 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx);
1582 dml_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe.src);
1583 dml_rq_dlg_get_dlg_params(mode_lib,
1594 ignore_viewport_pos,
1595 immediate_flip_support);
1596 dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);
1599 void dml_rq_dlg_get_arb_params(struct display_mode_lib *mode_lib, display_arb_params_st *arb_param)
1601 memset(arb_param, 0, sizeof(*arb_param));
1602 arb_param->max_req_outstanding = 256;
1603 arb_param->min_req_outstanding = 68;
1604 arb_param->sat_level_us = 60;
1607 void calculate_ttu_cursor(struct display_mode_lib *mode_lib,
1608 double *refcyc_per_req_delivery_pre_cur,
1609 double *refcyc_per_req_delivery_cur,
1610 double refclk_freq_in_mhz,
1611 double ref_freq_to_pix_freq,
1612 double hscale_pixel_rate_l,
1614 double vratio_pre_l,
1616 unsigned int cur_width,
1617 enum cursor_bpp cur_bpp)
1619 unsigned int cur_src_width = cur_width;
1620 unsigned int cur_req_size = 0;
1621 unsigned int cur_req_width = 0;
1622 double cur_width_ub = 0.0;
1623 double cur_req_per_width = 0.0;
1624 double hactive_cur = 0.0;
1626 ASSERT(cur_src_width <= 256);
1628 *refcyc_per_req_delivery_pre_cur = 0.0;
1629 *refcyc_per_req_delivery_cur = 0.0;
1630 if (cur_src_width > 0) {
1631 unsigned int cur_bit_per_pixel = 0;
1633 if (cur_bpp == dm_cur_2bit) {
1634 cur_req_size = 64; // byte
1635 cur_bit_per_pixel = 2;
1637 cur_bit_per_pixel = 32;
1638 if (cur_src_width >= 1 && cur_src_width <= 16)
1640 else if (cur_src_width >= 17 && cur_src_width <= 31)
1646 cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0);
1647 cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1)
1648 * (double) cur_req_width;
1649 cur_req_per_width = cur_width_ub / (double) cur_req_width;
1650 hactive_cur = (double) cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor
1652 if (vratio_pre_l <= 1.0) {
1653 *refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq
1654 / (double) cur_req_per_width;
1656 *refcyc_per_req_delivery_pre_cur = (double) refclk_freq_in_mhz
1657 * (double) cur_src_width / hscale_pixel_rate_l
1658 / (double) cur_req_per_width;
1661 ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));
1663 if (vratio_l <= 1.0) {
1664 *refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq
1665 / (double) cur_req_per_width;
1667 *refcyc_per_req_delivery_cur = (double) refclk_freq_in_mhz
1668 * (double) cur_src_width / hscale_pixel_rate_l
1669 / (double) cur_req_per_width;
1672 dml_print("DML_DLG: %s: cur_req_width = %d\n",
1675 dml_print("DML_DLG: %s: cur_width_ub = %3.2f\n",
1678 dml_print("DML_DLG: %s: cur_req_per_width = %3.2f\n",
1681 dml_print("DML_DLG: %s: hactive_cur = %3.2f\n",
1684 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur = %3.2f\n",
1686 *refcyc_per_req_delivery_pre_cur);
1687 dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur = %3.2f\n",
1689 *refcyc_per_req_delivery_cur);
1691 ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));
1695 unsigned int dml_rq_dlg_get_calculated_vstartup(struct display_mode_lib *mode_lib,
1696 display_e2e_pipe_params_st *e2e_pipe_param,
1697 const unsigned int num_pipes,
1698 const unsigned int pipe_idx)
1700 unsigned int vstartup_pipe[DC__NUM_PIPES__MAX];
1701 bool visited[DC__NUM_PIPES__MAX];
1702 unsigned int pipe_inst = 0;
1703 unsigned int i, j, k;
1705 for (k = 0; k < num_pipes; ++k)
1708 for (i = 0; i < num_pipes; i++) {
1709 if (e2e_pipe_param[i].pipe.src.is_hsplit && !visited[i]) {
1710 unsigned int grp = e2e_pipe_param[i].pipe.src.hsplit_grp;
1712 for (j = i; j < num_pipes; j++) {
1713 if (e2e_pipe_param[j].pipe.src.hsplit_grp == grp
1714 && e2e_pipe_param[j].pipe.src.is_hsplit
1716 vstartup_pipe[j] = get_vstartup_calculated(mode_lib,
1728 vstartup_pipe[i] = get_vstartup_calculated(mode_lib,
1737 return vstartup_pipe[pipe_idx];
1741 void dml_rq_dlg_get_row_heights(struct display_mode_lib *mode_lib,
1742 unsigned int *o_dpte_row_height,
1743 unsigned int *o_meta_row_height,
1744 unsigned int vp_width,
1745 unsigned int data_pitch,
1748 int macro_tile_size,
1752 display_data_rq_dlg_params_st rq_dlg_param;
1753 display_data_rq_misc_params_st rq_misc_param;
1754 display_data_rq_sizing_params_st rq_sizing_param;
1756 get_meta_and_pte_attr(mode_lib,
1770 *o_dpte_row_height = rq_dlg_param.dpte_row_height;
1771 *o_meta_row_height = rq_dlg_param.meta_row_height;