2 * Copyright 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
31 #define TO_DCN10_IPP(ipp)\
32 container_of(ipp, struct dcn10_ipp, base)
34 #define IPP_REG_LIST_DCN(id) \
35 SRI(FORMAT_CONTROL, CNVC_CFG, id), \
36 SRI(DPP_CONTROL, DPP_TOP, id), \
37 SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
38 SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
39 SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
40 SRI(CURSOR0_COLOR1, CNVC_CUR, id)
42 #define IPP_REG_LIST_DCN10(id) \
43 IPP_REG_LIST_DCN(id), \
44 SRI(CURSOR_SETTINS, HUBPREQ, id), \
45 SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \
46 SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \
47 SRI(CURSOR_SIZE, CURSOR, id), \
48 SRI(CURSOR_CONTROL, CURSOR, id), \
49 SRI(CURSOR_POSITION, CURSOR, id), \
50 SRI(CURSOR_HOT_SPOT, CURSOR, id), \
51 SRI(CURSOR_DST_OFFSET, CURSOR, id)
53 #define CURSOR0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4
54 #define CURSOR0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L
55 #define CURSOR1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4
56 #define CURSOR1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L
57 #define CURSOR2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4
58 #define CURSOR2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L
59 #define CURSOR3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4
60 #define CURSOR3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L
62 #define IPP_SF(reg_name, field_name, post_fix)\
63 .field_name = reg_name ## __ ## field_name ## post_fix
65 #define IPP_MASK_SH_LIST_DCN(mask_sh) \
66 IPP_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
67 IPP_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \
68 IPP_SF(CNVC_CFG0_FORMAT_CONTROL, ALPHA_EN, mask_sh), \
69 IPP_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
70 IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \
71 IPP_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \
72 IPP_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \
73 IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \
74 IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh)
76 #define IPP_MASK_SH_LIST_DCN10(mask_sh) \
77 IPP_MASK_SH_LIST_DCN(mask_sh),\
78 IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \
79 IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
80 IPP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
81 IPP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
82 IPP_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
83 IPP_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
84 IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
85 IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
86 IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
87 IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
88 IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
89 IPP_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
90 IPP_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
91 IPP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
92 IPP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
93 IPP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
94 IPP_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh)
96 #define IPP_DCN10_REG_FIELD_LIST(type) \
97 type CNVC_SURFACE_PIXEL_FORMAT; \
100 type FORMAT_EXPANSION_MODE; \
101 type CURSOR0_DST_Y_OFFSET; \
102 type CURSOR0_CHUNK_HDL_ADJUST; \
106 type CUR0_EXPANSION_MODE; \
107 type CURSOR_SURFACE_ADDRESS_HIGH; \
108 type CURSOR_SURFACE_ADDRESS; \
110 type CURSOR_HEIGHT; \
112 type CURSOR_2X_MAGNIFY; \
114 type CURSOR_LINES_PER_CHUNK; \
115 type CURSOR_ENABLE; \
117 type CURSOR_X_POSITION; \
118 type CURSOR_Y_POSITION; \
119 type CURSOR_HOT_SPOT_X; \
120 type CURSOR_HOT_SPOT_Y; \
121 type CURSOR_DST_X_OFFSET; \
124 struct dcn10_ipp_shift {
125 IPP_DCN10_REG_FIELD_LIST(uint8_t);
128 struct dcn10_ipp_mask {
129 IPP_DCN10_REG_FIELD_LIST(uint32_t);
132 struct dcn10_ipp_registers {
133 uint32_t DPP_CONTROL;
134 uint32_t CURSOR_SETTINS;
135 uint32_t CURSOR_SETTINGS;
136 uint32_t CNVC_SURFACE_PIXEL_FORMAT;
137 uint32_t CURSOR0_CONTROL;
138 uint32_t CURSOR0_COLOR0;
139 uint32_t CURSOR0_COLOR1;
140 uint32_t FORMAT_CONTROL;
141 uint32_t CURSOR_SURFACE_ADDRESS_HIGH;
142 uint32_t CURSOR_SURFACE_ADDRESS;
143 uint32_t CURSOR_SIZE;
144 uint32_t CURSOR_CONTROL;
145 uint32_t CURSOR_POSITION;
146 uint32_t CURSOR_HOT_SPOT;
147 uint32_t CURSOR_DST_OFFSET;
151 struct input_pixel_processor base;
153 const struct dcn10_ipp_registers *regs;
154 const struct dcn10_ipp_shift *ipp_shift;
155 const struct dcn10_ipp_mask *ipp_mask;
157 struct dc_cursor_attributes curs_attr;
160 void dcn10_ipp_construct(struct dcn10_ipp *ippn10,
161 struct dc_context *ctx,
163 const struct dcn10_ipp_registers *regs,
164 const struct dcn10_ipp_shift *ipp_shift,
165 const struct dcn10_ipp_mask *ipp_mask);
167 #endif /* _DCN10_IPP_H_ */