drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27
  28 #include "core_types.h"
  29
  30 #include "reg_helper.h"
  31 #include "dcn10_dpp.h"
  32 #include "basics/conversion.h"
  33 #include "dcn10_cm_common.h"
  34
  35 #define NUM_PHASES    64
  36 #define HORZ_MAX_TAPS 8
  37 #define VERT_MAX_TAPS 8
  38
  39 #define BLACK_OFFSET_RGB_Y 0x0
  40 #define BLACK_OFFSET_CBCR  0x8000
  41
  42 #define REG(reg)\
  43         dpp->tf_regs->reg
  44
  45 #define CTX \
  46         dpp->base.ctx
  47
  48 #undef FN
  49 #define FN(reg_name, field_name) \
  50         dpp->tf_shift->field_name, dpp->tf_mask->field_name
  51
  52 struct dcn10_input_csc_matrix {
  53         enum dc_color_space color_space;
  54         uint16_t regval[12];
  55 };
  56
  57 enum dcn10_coef_filter_type_sel {
  58         SCL_COEF_LUMA_VERT_FILTER = 0,
  59         SCL_COEF_LUMA_HORZ_FILTER = 1,
  60         SCL_COEF_CHROMA_VERT_FILTER = 2,
  61         SCL_COEF_CHROMA_HORZ_FILTER = 3,
  62         SCL_COEF_ALPHA_VERT_FILTER = 4,
  63         SCL_COEF_ALPHA_HORZ_FILTER = 5
  64 };
  65
  66 enum dscl_autocal_mode {
  67         AUTOCAL_MODE_OFF = 0,
  68
  69         /* Autocal calculate the scaling ratio and initial phase and the
  70          * DSCL_MODE_SEL must be set to 1
  71          */
  72         AUTOCAL_MODE_AUTOSCALE = 1,
  73         /* Autocal perform auto centering without replication and the
  74          * DSCL_MODE_SEL must be set to 0
  75          */
  76         AUTOCAL_MODE_AUTOCENTER = 2,
  77         /* Autocal perform auto centering and auto replication and the
  78          * DSCL_MODE_SEL must be set to 0
  79          */
  80         AUTOCAL_MODE_AUTOREPLICATE = 3
  81 };
  82
  83 enum dscl_mode_sel {
  84         DSCL_MODE_SCALING_444_BYPASS = 0,
  85         DSCL_MODE_SCALING_444_RGB_ENABLE = 1,
  86         DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2,
  87         DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3,
  88         DSCL_MODE_SCALING_420_LUMA_BYPASS = 4,
  89         DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5,
  90         DSCL_MODE_DSCL_BYPASS = 6
  91 };
  92
  93 enum gamut_remap_select {
  94         GAMUT_REMAP_BYPASS = 0,
  95         GAMUT_REMAP_COEFF,
  96         GAMUT_REMAP_COMA_COEFF,
  97         GAMUT_REMAP_COMB_COEFF
  98 };
  99
 100 static const struct dcn10_input_csc_matrix dcn10_input_csc_matrix[] = {
 101         {COLOR_SPACE_SRGB,
 102                 {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
 103         {COLOR_SPACE_SRGB_LIMITED,
 104                 {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
 105         {COLOR_SPACE_YCBCR601,
 106                 {0x2cdd, 0x2000, 0, 0xe991, 0xe926, 0x2000, 0xf4fd, 0x10ef,
 107                                                 0, 0x2000, 0x38b4, 0xe3a6} },
 108         {COLOR_SPACE_YCBCR601_LIMITED,
 109                 {0x3353, 0x2568, 0, 0xe400, 0xe5dc, 0x2568, 0xf367, 0x1108,
 110                                                 0, 0x2568, 0x40de, 0xdd3a} },
 111         {COLOR_SPACE_YCBCR709,
 112                 {0x3265, 0x2000, 0, 0xe6ce, 0xf105, 0x2000, 0xfa01, 0xa7d, 0,
 113                                                 0x2000, 0x3b61, 0xe24f} },
 114
 115         {COLOR_SPACE_YCBCR709_LIMITED,
 116                 {0x39a6, 0x2568, 0, 0xe0d6, 0xeedd, 0x2568, 0xf925, 0x9a8, 0,
 117                                                 0x2568, 0x43ee, 0xdbb2} }
 118 };
 119
 120
 121
 122 static void program_gamut_remap(
 123                 struct dcn10_dpp *dpp,
 124                 const uint16_t *regval,
 125                 enum gamut_remap_select select)
 126 {
 127         uint16_t selection = 0;
 128         struct color_matrices_reg gam_regs;
 129
 130         if (regval == NULL || select == GAMUT_REMAP_BYPASS) {
 131                 REG_SET(CM_GAMUT_REMAP_CONTROL, 0,
 132                                 CM_GAMUT_REMAP_MODE, 0);
 133                 return;
 134         }
 135         switch (select) {
 136         case GAMUT_REMAP_COEFF:
 137                 selection = 1;
 138                 break;
 139         case GAMUT_REMAP_COMA_COEFF:
 140                 selection = 2;
 141                 break;
 142         case GAMUT_REMAP_COMB_COEFF:
 143                 selection = 3;
 144                 break;
 145         default:
 146                 break;
 147         }
 148
 149         gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;
 150         gam_regs.masks.csc_c11  = dpp->tf_mask->CM_GAMUT_REMAP_C11;
 151         gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;
 152         gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;
 153
 154
 155         if (select == GAMUT_REMAP_COEFF) {
 156                 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);
 157                 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);
 158
 159                 cm_helper_program_color_matrices(
 160                                 dpp->base.ctx,
 161                                 regval,
 162                                 &gam_regs);
 163
 164         } else  if (select == GAMUT_REMAP_COMA_COEFF) {
 165
 166                 gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12);
 167                 gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34);
 168
 169                 cm_helper_program_color_matrices(
 170                                 dpp->base.ctx,
 171                                 regval,
 172                                 &gam_regs);
 173
 174         } else {
 175
 176                 gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12);
 177                 gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34);
 178
 179                 cm_helper_program_color_matrices(
 180                                 dpp->base.ctx,
 181                                 regval,
 182                                 &gam_regs);
 183         }
 184
 185         REG_SET(
 186                         CM_GAMUT_REMAP_CONTROL, 0,
 187                         CM_GAMUT_REMAP_MODE, selection);
 188
 189 }
 190
 191 void dpp1_cm_set_gamut_remap(
 192         struct dpp *dpp_base,
 193         const struct dpp_grph_csc_adjustment *adjust)
 194 {
 195         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 196
 197         if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW)
 198                 /* Bypass if type is bypass or hw */
 199                 program_gamut_remap(dpp, NULL, GAMUT_REMAP_BYPASS);
 200         else {
 201                 struct fixed31_32 arr_matrix[12];
 202                 uint16_t arr_reg_val[12];
 203
 204                 arr_matrix[0] = adjust->temperature_matrix[0];
 205                 arr_matrix[1] = adjust->temperature_matrix[1];
 206                 arr_matrix[2] = adjust->temperature_matrix[2];
 207                 arr_matrix[3] = dal_fixed31_32_zero;
 208
 209                 arr_matrix[4] = adjust->temperature_matrix[3];
 210                 arr_matrix[5] = adjust->temperature_matrix[4];
 211                 arr_matrix[6] = adjust->temperature_matrix[5];
 212                 arr_matrix[7] = dal_fixed31_32_zero;
 213
 214                 arr_matrix[8] = adjust->temperature_matrix[6];
 215                 arr_matrix[9] = adjust->temperature_matrix[7];
 216                 arr_matrix[10] = adjust->temperature_matrix[8];
 217                 arr_matrix[11] = dal_fixed31_32_zero;
 218
 219                 convert_float_matrix(
 220                         arr_reg_val, arr_matrix, 12);
 221
 222                 program_gamut_remap(dpp, arr_reg_val, GAMUT_REMAP_COEFF);
 223         }
 224 }
 225
 226 void dpp1_cm_set_output_csc_default(
 227                 struct dpp *dpp_base,
 228                 enum dc_color_space colorspace)
 229 {
 230
 231         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 232         uint32_t ocsc_mode = 0;
 233
 234         switch (colorspace) {
 235                 case COLOR_SPACE_SRGB:
 236                 case COLOR_SPACE_2020_RGB_FULLRANGE:
 237                         ocsc_mode = 0;
 238                         break;
 239                 case COLOR_SPACE_SRGB_LIMITED:
 240                 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
 241                         ocsc_mode = 1;
 242                         break;
 243                 case COLOR_SPACE_YCBCR601:
 244                 case COLOR_SPACE_YCBCR601_LIMITED:
 245                         ocsc_mode = 2;
 246                         break;
 247                 case COLOR_SPACE_YCBCR709:
 248                 case COLOR_SPACE_YCBCR709_LIMITED:
 249                 case COLOR_SPACE_2020_YCBCR:
 250                         ocsc_mode = 3;
 251                         break;
 252                 case COLOR_SPACE_UNKNOWN:
 253                 default:
 254                         break;
 255         }
 256
 257         REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
 258
 259 }
 260
 261 static void dpp1_cm_get_reg_field(
 262                 struct dcn10_dpp *dpp,
 263                 struct xfer_func_reg *reg)
 264 {
 265         reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
 266         reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
 267         reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
 268         reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
 269         reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
 270         reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
 271         reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
 272         reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
 273
 274         reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B;
 275         reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B;
 276         reg->shifts.field_region_end_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;
 277         reg->masks.field_region_end_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;
 278         reg->shifts.field_region_end_base = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;
 279         reg->masks.field_region_end_base = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;
 280         reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;
 281         reg->masks.field_region_linear_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;
 282         reg->shifts.exp_region_start = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_B;
 283         reg->masks.exp_region_start = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_B;
 284         reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;
 285         reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;
 286 }
 287
 288 static void dpp1_cm_program_color_matrix(
 289                 struct dcn10_dpp *dpp,
 290                 const struct out_csc_color_matrix *tbl_entry)
 291 {
 292         uint32_t mode;
 293         struct color_matrices_reg gam_regs;
 294
 295         REG_GET(CM_OCSC_CONTROL, CM_OCSC_MODE, &mode);
 296
 297         if (tbl_entry == NULL) {
 298                 BREAK_TO_DEBUGGER();
 299                 return;
 300         }
 301
 302         gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11;
 303         gam_regs.masks.csc_c11  = dpp->tf_mask->CM_OCSC_C11;
 304         gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12;
 305         gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12;
 306
 307         if (mode == 4) {
 308
 309                 gam_regs.csc_c11_c12 = REG(CM_OCSC_C11_C12);
 310                 gam_regs.csc_c33_c34 = REG(CM_OCSC_C33_C34);
 311
 312                 cm_helper_program_color_matrices(
 313                                 dpp->base.ctx,
 314                                 tbl_entry->regval,
 315                                 &gam_regs);
 316
 317         } else {
 318
 319                 gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12);
 320                 gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34);
 321
 322                 cm_helper_program_color_matrices(
 323                                 dpp->base.ctx,
 324                                 tbl_entry->regval,
 325                                 &gam_regs);
 326         }
 327 }
 328
 329 void dpp1_cm_set_output_csc_adjustment(
 330                 struct dpp *dpp_base,
 331                 const struct out_csc_color_matrix *tbl_entry)
 332 {
 333         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 334         //enum csc_color_mode config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
 335         uint32_t ocsc_mode = 4;
 336
 337         /**
 338         *if (tbl_entry != NULL) {
 339         *       switch (tbl_entry->color_space) {
 340         *       case COLOR_SPACE_SRGB:
 341         *       case COLOR_SPACE_2020_RGB_FULLRANGE:
 342         *               ocsc_mode = 0;
 343         *               break;
 344         *       case COLOR_SPACE_SRGB_LIMITED:
 345         *       case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
 346         *               ocsc_mode = 1;
 347         *               break;
 348         *       case COLOR_SPACE_YCBCR601:
 349         *       case COLOR_SPACE_YCBCR601_LIMITED:
 350         *               ocsc_mode = 2;
 351         *               break;
 352         *       case COLOR_SPACE_YCBCR709:
 353         *       case COLOR_SPACE_YCBCR709_LIMITED:
 354         *       case COLOR_SPACE_2020_YCBCR:
 355         *               ocsc_mode = 3;
 356         *               break;
 357         *       case COLOR_SPACE_UNKNOWN:
 358         *       default:
 359         *               break;
 360         *       }
 361         *}
 362         */
 363
 364         REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
 365         dpp1_cm_program_color_matrix(dpp, tbl_entry);
 366 }
 367
 368 void dpp1_cm_power_on_regamma_lut(
 369         struct dpp *dpp_base,
 370         bool power_on)
 371 {
 372         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 373         REG_SET(CM_MEM_PWR_CTRL, 0,
 374                         RGAM_MEM_PWR_FORCE, power_on == true ? 0:1);
 375
 376 }
 377
 378 void dpp1_cm_program_regamma_lut(
 379                 struct dpp *dpp_base,
 380                 const struct pwl_result_data *rgb,
 381                 uint32_t num)
 382 {
 383         uint32_t i;
 384         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 385         for (i = 0 ; i < num; i++) {
 386                 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg);
 387                 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg);
 388                 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg);
 389
 390                 REG_SET(CM_RGAM_LUT_DATA, 0,
 391                                 CM_RGAM_LUT_DATA, rgb[i].delta_red_reg);
 392                 REG_SET(CM_RGAM_LUT_DATA, 0,
 393                                 CM_RGAM_LUT_DATA, rgb[i].delta_green_reg);
 394                 REG_SET(CM_RGAM_LUT_DATA, 0,
 395                                 CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg);
 396
 397         }
 398
 399 }
 400
 401 void dpp1_cm_configure_regamma_lut(
 402                 struct dpp *dpp_base,
 403                 bool is_ram_a)
 404 {
 405         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 406
 407         REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK,
 408                         CM_RGAM_LUT_WRITE_EN_MASK, 7);
 409         REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK,
 410                         CM_RGAM_LUT_WRITE_SEL, is_ram_a == true ? 0:1);
 411         REG_SET(CM_RGAM_LUT_INDEX, 0, CM_RGAM_LUT_INDEX, 0);
 412 }
 413
 414 /*program re gamma RAM A*/
 415 void dpp1_cm_program_regamma_luta_settings(
 416                 struct dpp *dpp_base,
 417                 const struct pwl_params *params)
 418 {
 419         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 420         struct xfer_func_reg gam_regs;
 421
 422         dpp1_cm_get_reg_field(dpp, &gam_regs);
 423
 424         gam_regs.start_cntl_b = REG(CM_RGAM_RAMA_START_CNTL_B);
 425         gam_regs.start_cntl_g = REG(CM_RGAM_RAMA_START_CNTL_G);
 426         gam_regs.start_cntl_r = REG(CM_RGAM_RAMA_START_CNTL_R);
 427         gam_regs.start_slope_cntl_b = REG(CM_RGAM_RAMA_SLOPE_CNTL_B);
 428         gam_regs.start_slope_cntl_g = REG(CM_RGAM_RAMA_SLOPE_CNTL_G);
 429         gam_regs.start_slope_cntl_r = REG(CM_RGAM_RAMA_SLOPE_CNTL_R);
 430         gam_regs.start_end_cntl1_b = REG(CM_RGAM_RAMA_END_CNTL1_B);
 431         gam_regs.start_end_cntl2_b = REG(CM_RGAM_RAMA_END_CNTL2_B);
 432         gam_regs.start_end_cntl1_g = REG(CM_RGAM_RAMA_END_CNTL1_G);
 433         gam_regs.start_end_cntl2_g = REG(CM_RGAM_RAMA_END_CNTL2_G);
 434         gam_regs.start_end_cntl1_r = REG(CM_RGAM_RAMA_END_CNTL1_R);
 435         gam_regs.start_end_cntl2_r = REG(CM_RGAM_RAMA_END_CNTL2_R);
 436         gam_regs.region_start = REG(CM_RGAM_RAMA_REGION_0_1);
 437         gam_regs.region_end = REG(CM_RGAM_RAMA_REGION_32_33);
 438
 439         cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);
 440
 441 }
 442
 443 /*program re gamma RAM B*/
 444 void dpp1_cm_program_regamma_lutb_settings(
 445                 struct dpp *dpp_base,
 446                 const struct pwl_params *params)
 447 {
 448         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 449         struct xfer_func_reg gam_regs;
 450
 451         dpp1_cm_get_reg_field(dpp, &gam_regs);
 452
 453         gam_regs.start_cntl_b = REG(CM_RGAM_RAMB_START_CNTL_B);
 454         gam_regs.start_cntl_g = REG(CM_RGAM_RAMB_START_CNTL_G);
 455         gam_regs.start_cntl_r = REG(CM_RGAM_RAMB_START_CNTL_R);
 456         gam_regs.start_slope_cntl_b = REG(CM_RGAM_RAMB_SLOPE_CNTL_B);
 457         gam_regs.start_slope_cntl_g = REG(CM_RGAM_RAMB_SLOPE_CNTL_G);
 458         gam_regs.start_slope_cntl_r = REG(CM_RGAM_RAMB_SLOPE_CNTL_R);
 459         gam_regs.start_end_cntl1_b = REG(CM_RGAM_RAMB_END_CNTL1_B);
 460         gam_regs.start_end_cntl2_b = REG(CM_RGAM_RAMB_END_CNTL2_B);
 461         gam_regs.start_end_cntl1_g = REG(CM_RGAM_RAMB_END_CNTL1_G);
 462         gam_regs.start_end_cntl2_g = REG(CM_RGAM_RAMB_END_CNTL2_G);
 463         gam_regs.start_end_cntl1_r = REG(CM_RGAM_RAMB_END_CNTL1_R);
 464         gam_regs.start_end_cntl2_r = REG(CM_RGAM_RAMB_END_CNTL2_R);
 465         gam_regs.region_start = REG(CM_RGAM_RAMB_REGION_0_1);
 466         gam_regs.region_end = REG(CM_RGAM_RAMB_REGION_32_33);
 467
 468         cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);
 469 }
 470
 471 void dpp1_program_input_csc(
 472                 struct dpp *dpp_base,
 473                 enum dc_color_space color_space,
 474                 enum dcn10_input_csc_select select)
 475 {
 476         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 477         int i;
 478         int arr_size = sizeof(dcn10_input_csc_matrix)/sizeof(struct dcn10_input_csc_matrix);
 479         const uint16_t *regval = NULL;
 480         uint32_t selection = 1;
 481         struct color_matrices_reg gam_regs;
 482
 483         if (select == INPUT_CSC_SELECT_BYPASS) {
 484                 REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0);
 485                 return;
 486         }
 487
 488         for (i = 0; i < arr_size; i++)
 489                 if (dcn10_input_csc_matrix[i].color_space == color_space) {
 490                         regval = dcn10_input_csc_matrix[i].regval;
 491                         break;
 492                 }
 493
 494         if (regval == NULL) {
 495                 BREAK_TO_DEBUGGER();
 496                 return;
 497         }
 498
 499         if (select == INPUT_CSC_SELECT_COMA)
 500                 selection = 2;
 501         REG_SET(CM_ICSC_CONTROL, 0,
 502                         CM_ICSC_MODE, selection);
 503
 504         gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11;
 505         gam_regs.masks.csc_c11  = dpp->tf_mask->CM_ICSC_C11;
 506         gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12;
 507         gam_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12;
 508
 509
 510         if (select == INPUT_CSC_SELECT_ICSC) {
 511
 512                 gam_regs.csc_c11_c12 = REG(CM_ICSC_C11_C12);
 513                 gam_regs.csc_c33_c34 = REG(CM_ICSC_C33_C34);
 514
 515                 cm_helper_program_color_matrices(
 516                                 dpp->base.ctx,
 517                                 regval,
 518                                 &gam_regs);
 519         } else {
 520
 521                 gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12);
 522                 gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34);
 523
 524                 cm_helper_program_color_matrices(
 525                                 dpp->base.ctx,
 526                                 regval,
 527                                 &gam_regs);
 528         }
 529 }
 530
 531 /*program de gamma RAM B*/
 532 void dpp1_program_degamma_lutb_settings(
 533                 struct dpp *dpp_base,
 534                 const struct pwl_params *params)
 535 {
 536         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 537         struct xfer_func_reg gam_regs;
 538
 539         dpp1_cm_get_reg_field(dpp, &gam_regs);
 540
 541         gam_regs.start_cntl_b = REG(CM_DGAM_RAMB_START_CNTL_B);
 542         gam_regs.start_cntl_g = REG(CM_DGAM_RAMB_START_CNTL_G);
 543         gam_regs.start_cntl_r = REG(CM_DGAM_RAMB_START_CNTL_R);
 544         gam_regs.start_slope_cntl_b = REG(CM_DGAM_RAMB_SLOPE_CNTL_B);
 545         gam_regs.start_slope_cntl_g = REG(CM_DGAM_RAMB_SLOPE_CNTL_G);
 546         gam_regs.start_slope_cntl_r = REG(CM_DGAM_RAMB_SLOPE_CNTL_R);
 547         gam_regs.start_end_cntl1_b = REG(CM_DGAM_RAMB_END_CNTL1_B);
 548         gam_regs.start_end_cntl2_b = REG(CM_DGAM_RAMB_END_CNTL2_B);
 549         gam_regs.start_end_cntl1_g = REG(CM_DGAM_RAMB_END_CNTL1_G);
 550         gam_regs.start_end_cntl2_g = REG(CM_DGAM_RAMB_END_CNTL2_G);
 551         gam_regs.start_end_cntl1_r = REG(CM_DGAM_RAMB_END_CNTL1_R);
 552         gam_regs.start_end_cntl2_r = REG(CM_DGAM_RAMB_END_CNTL2_R);
 553         gam_regs.region_start = REG(CM_DGAM_RAMB_REGION_0_1);
 554         gam_regs.region_end = REG(CM_DGAM_RAMB_REGION_14_15);
 555
 556
 557         cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);
 558 }
 559
 560 /*program de gamma RAM A*/
 561 void dpp1_program_degamma_luta_settings(
 562                 struct dpp *dpp_base,
 563                 const struct pwl_params *params)
 564 {
 565         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 566         struct xfer_func_reg gam_regs;
 567
 568         dpp1_cm_get_reg_field(dpp, &gam_regs);
 569
 570         gam_regs.start_cntl_b = REG(CM_DGAM_RAMA_START_CNTL_B);
 571         gam_regs.start_cntl_g = REG(CM_DGAM_RAMA_START_CNTL_G);
 572         gam_regs.start_cntl_r = REG(CM_DGAM_RAMA_START_CNTL_R);
 573         gam_regs.start_slope_cntl_b = REG(CM_DGAM_RAMA_SLOPE_CNTL_B);
 574         gam_regs.start_slope_cntl_g = REG(CM_DGAM_RAMA_SLOPE_CNTL_G);
 575         gam_regs.start_slope_cntl_r = REG(CM_DGAM_RAMA_SLOPE_CNTL_R);
 576         gam_regs.start_end_cntl1_b = REG(CM_DGAM_RAMA_END_CNTL1_B);
 577         gam_regs.start_end_cntl2_b = REG(CM_DGAM_RAMA_END_CNTL2_B);
 578         gam_regs.start_end_cntl1_g = REG(CM_DGAM_RAMA_END_CNTL1_G);
 579         gam_regs.start_end_cntl2_g = REG(CM_DGAM_RAMA_END_CNTL2_G);
 580         gam_regs.start_end_cntl1_r = REG(CM_DGAM_RAMA_END_CNTL1_R);
 581         gam_regs.start_end_cntl2_r = REG(CM_DGAM_RAMA_END_CNTL2_R);
 582         gam_regs.region_start = REG(CM_DGAM_RAMA_REGION_0_1);
 583         gam_regs.region_end = REG(CM_DGAM_RAMA_REGION_14_15);
 584
 585         cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);
 586 }
 587
 588 void dpp1_power_on_degamma_lut(
 589                 struct dpp *dpp_base,
 590         bool power_on)
 591 {
 592         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 593
 594         REG_SET(CM_MEM_PWR_CTRL, 0,
 595                         SHARED_MEM_PWR_DIS, power_on == true ? 0:1);
 596
 597 }
 598
 599 static void dpp1_enable_cm_block(
 600                 struct dpp *dpp_base)
 601 {
 602         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 603
 604         REG_UPDATE(CM_CMOUT_CONTROL, CM_CMOUT_ROUND_TRUNC_MODE, 8);
 605         REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0);
 606 }
 607
 608 void dpp1_set_degamma(
 609                 struct dpp *dpp_base,
 610                 enum ipp_degamma_mode mode)
 611 {
 612         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 613         dpp1_enable_cm_block(dpp_base);
 614
 615         switch (mode) {
 616         case IPP_DEGAMMA_MODE_BYPASS:
 617                 /* Setting de gamma bypass for now */
 618                 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 0);
 619                 break;
 620         case IPP_DEGAMMA_MODE_HW_sRGB:
 621                 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 1);
 622                 break;
 623         case IPP_DEGAMMA_MODE_HW_xvYCC:
 624                 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2);
 625                         break;
 626         default:
 627                 BREAK_TO_DEBUGGER();
 628                 break;
 629         }
 630 }
 631
 632 void dpp1_degamma_ram_select(
 633                 struct dpp *dpp_base,
 634                                                         bool use_ram_a)
 635 {
 636         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 637
 638         if (use_ram_a)
 639                 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 3);
 640         else
 641                 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 4);
 642
 643 }
 644
 645 static bool dpp1_degamma_ram_inuse(
 646                 struct dpp *dpp_base,
 647                                                         bool *ram_a_inuse)
 648 {
 649         bool ret = false;
 650         uint32_t status_reg = 0;
 651         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 652
 653         REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS,
 654                         &status_reg);
 655
 656         if (status_reg == 9) {
 657                 *ram_a_inuse = true;
 658                 ret = true;
 659         } else if (status_reg == 10) {
 660                 *ram_a_inuse = false;
 661                 ret = true;
 662         }
 663         return ret;
 664 }
 665
 666 void dpp1_program_degamma_lut(
 667                 struct dpp *dpp_base,
 668                 const struct pwl_result_data *rgb,
 669                 uint32_t num,
 670                 bool is_ram_a)
 671 {
 672         uint32_t i;
 673
 674         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 675         REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, 0);
 676         REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK,
 677                                    CM_DGAM_LUT_WRITE_EN_MASK, 7);
 678         REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL,
 679                                         is_ram_a == true ? 0:1);
 680
 681         REG_SET(CM_DGAM_LUT_INDEX, 0, CM_DGAM_LUT_INDEX, 0);
 682         for (i = 0 ; i < num; i++) {
 683                 REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].red_reg);
 684                 REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].green_reg);
 685                 REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].blue_reg);
 686
 687                 REG_SET(CM_DGAM_LUT_DATA, 0,
 688                                 CM_DGAM_LUT_DATA, rgb[i].delta_red_reg);
 689                 REG_SET(CM_DGAM_LUT_DATA, 0,
 690                                 CM_DGAM_LUT_DATA, rgb[i].delta_green_reg);
 691                 REG_SET(CM_DGAM_LUT_DATA, 0,
 692                                 CM_DGAM_LUT_DATA, rgb[i].delta_blue_reg);
 693         }
 694 }
 695
 696 void dpp1_set_degamma_pwl(struct dpp *dpp_base,
 697                                                                  const struct pwl_params *params)
 698 {
 699         bool is_ram_a = true;
 700
 701         dpp1_power_on_degamma_lut(dpp_base, true);
 702         dpp1_enable_cm_block(dpp_base);
 703         dpp1_degamma_ram_inuse(dpp_base, &is_ram_a);
 704         if (is_ram_a == true)
 705                 dpp1_program_degamma_lutb_settings(dpp_base, params);
 706         else
 707                 dpp1_program_degamma_luta_settings(dpp_base, params);
 708
 709         dpp1_program_degamma_lut(dpp_base, params->rgb_resulted,
 710                                                         params->hw_points_num, !is_ram_a);
 711         dpp1_degamma_ram_select(dpp_base, !is_ram_a);
 712 }
 713
 714 void dpp1_full_bypass(struct dpp *dpp_base)
 715 {
 716         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 717
 718         /* Input pixel format: ARGB8888 */
 719         REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
 720                         CNVC_SURFACE_PIXEL_FORMAT, 0x8);
 721
 722         /* Zero expansion */
 723         REG_SET_3(FORMAT_CONTROL, 0,
 724                         CNVC_BYPASS, 0,
 725                         FORMAT_CONTROL__ALPHA_EN, 0,
 726                         FORMAT_EXPANSION_MODE, 0);
 727
 728         /* COLOR_KEYER_CONTROL.COLOR_KEYER_EN = 0 this should be default */
 729         if (dpp->tf_mask->CM_BYPASS_EN)
 730                 REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1);
 731
 732         /* Setting degamma bypass for now */
 733         REG_SET(CM_DGAM_CONTROL, 0, CM_DGAM_LUT_MODE, 0);
 734 }
 735
 736 static bool dpp1_ingamma_ram_inuse(struct dpp *dpp_base,
 737                                                         bool *ram_a_inuse)
 738 {
 739         bool in_use = false;
 740         uint32_t status_reg = 0;
 741         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 742
 743         REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS,
 744                                 &status_reg);
 745
 746         // 1 => IGAM_RAMA, 3 => IGAM_RAMA & DGAM_ROMA, 4 => IGAM_RAMA & DGAM_ROMB
 747         if (status_reg == 1 || status_reg == 3 || status_reg == 4) {
 748                 *ram_a_inuse = true;
 749                 in_use = true;
 750         // 2 => IGAM_RAMB, 5 => IGAM_RAMB & DGAM_ROMA, 6 => IGAM_RAMB & DGAM_ROMB
 751         } else if (status_reg == 2 || status_reg == 5 || status_reg == 6) {
 752                 *ram_a_inuse = false;
 753                 in_use = true;
 754         }
 755         return in_use;
 756 }
 757
 758 /*
 759  * Input gamma LUT currently supports 256 values only. This means input color
 760  * can have a maximum of 8 bits per channel (= 256 possible values) in order to
 761  * have a one-to-one mapping with the LUT. Truncation will occur with color
 762  * values greater than 8 bits.
 763  *
 764  * In the future, this function should support additional input gamma methods,
 765  * such as piecewise linear mapping, and input gamma bypass.
 766  */
 767 void dpp1_program_input_lut(
 768                 struct dpp *dpp_base,
 769                 const struct dc_gamma *gamma)
 770 {
 771         int i;
 772         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 773         bool rama_occupied = false;
 774         uint32_t ram_num;
 775         // Power on LUT memory.
 776         REG_SET(CM_MEM_PWR_CTRL, 0, SHARED_MEM_PWR_DIS, 1);
 777         dpp1_enable_cm_block(dpp_base);
 778         // Determine whether to use RAM A or RAM B
 779         dpp1_ingamma_ram_inuse(dpp_base, &rama_occupied);
 780         if (!rama_occupied)
 781                 REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, 0);
 782         else
 783                 REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, 1);
 784         // RW mode is 256-entry LUT
 785         REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, 0);
 786         // IGAM Input format should be 8 bits per channel.
 787         REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 0);
 788         // Do not mask any R,G,B values
 789         REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, 7);
 790         // LUT-256, unsigned, integer, new u0.12 format
 791         REG_UPDATE_3(
 792                 CM_IGAM_CONTROL,
 793                 CM_IGAM_LUT_FORMAT_R, 3,
 794                 CM_IGAM_LUT_FORMAT_G, 3,
 795                 CM_IGAM_LUT_FORMAT_B, 3);
 796         // Start at index 0 of IGAM LUT
 797         REG_UPDATE(CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, 0);
 798         for (i = 0; i < gamma->num_entries; i++) {
 799                 REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR,
 800                                 dal_fixed31_32_round(
 801                                         gamma->entries.red[i]));
 802                 REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR,
 803                                 dal_fixed31_32_round(
 804                                         gamma->entries.green[i]));
 805                 REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR,
 806                                 dal_fixed31_32_round(
 807                                         gamma->entries.blue[i]));
 808         }
 809         // Power off LUT memory
 810         REG_SET(CM_MEM_PWR_CTRL, 0, SHARED_MEM_PWR_DIS, 0);
 811         // Enable IGAM LUT on ram we just wrote to. 2 => RAMA, 3 => RAMB
 812         REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, rama_occupied ? 3 : 2);
 813         REG_GET(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, &ram_num);
 814 }