1 /* Copyright 2016 Advanced Micro Devices, Inc.
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
10 * The above copyright notice and this permission notice shall be included in
11 * all copies or substantial portions of the Software.
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
19 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __DAL_DPP_DCN10_H__
26 #define __DAL_DPP_DCN10_H__
30 #define TO_DCN10_DPP(dpp)\
31 container_of(dpp, struct dcn10_dpp, base)
33 /* TODO: Use correct number of taps. Using polaris values for now */
34 #define LB_TOTAL_NUMBER_OF_ENTRIES 5124
35 #define LB_BITS_PER_ENTRY 144
37 #define TF_SF(reg_name, field_name, post_fix)\
38 .field_name = reg_name ## __ ## field_name ## post_fix
40 //Used to resolve corner case
41 #define TF2_SF(reg_name, field_name, post_fix)\
42 .field_name = reg_name ## _ ## field_name ## post_fix
44 #define TF_REG_LIST_DCN(id) \
45 SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\
46 SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\
47 SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\
48 SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \
49 SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \
50 SRI(OTG_H_BLANK, DSCL, id), \
51 SRI(OTG_V_BLANK, DSCL, id), \
52 SRI(SCL_MODE, DSCL, id), \
53 SRI(LB_DATA_FORMAT, DSCL, id), \
54 SRI(LB_MEMORY_CTRL, DSCL, id), \
55 SRI(DSCL_AUTOCAL, DSCL, id), \
56 SRI(SCL_BLACK_OFFSET, DSCL, id), \
57 SRI(DSCL_CONTROL, DSCL, id), \
58 SRI(SCL_TAP_CONTROL, DSCL, id), \
59 SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \
60 SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \
61 SRI(DSCL_2TAP_CONTROL, DSCL, id), \
62 SRI(MPC_SIZE, DSCL, id), \
63 SRI(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \
64 SRI(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \
65 SRI(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \
66 SRI(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \
67 SRI(SCL_HORZ_FILTER_INIT, DSCL, id), \
68 SRI(SCL_HORZ_FILTER_INIT_C, DSCL, id), \
69 SRI(SCL_VERT_FILTER_INIT, DSCL, id), \
70 SRI(SCL_VERT_FILTER_INIT_BOT, DSCL, id), \
71 SRI(SCL_VERT_FILTER_INIT_C, DSCL, id), \
72 SRI(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id), \
73 SRI(RECOUT_START, DSCL, id), \
74 SRI(RECOUT_SIZE, DSCL, id), \
75 SRI(OBUF_CONTROL, DSCL, id), \
76 SRI(CM_ICSC_CONTROL, CM, id), \
77 SRI(CM_ICSC_C11_C12, CM, id), \
78 SRI(CM_ICSC_C33_C34, CM, id), \
79 SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \
80 SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \
81 SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \
82 SRI(CM_DGAM_RAMB_SLOPE_CNTL_B, CM, id), \
83 SRI(CM_DGAM_RAMB_SLOPE_CNTL_G, CM, id), \
84 SRI(CM_DGAM_RAMB_SLOPE_CNTL_R, CM, id), \
85 SRI(CM_DGAM_RAMB_END_CNTL1_B, CM, id), \
86 SRI(CM_DGAM_RAMB_END_CNTL2_B, CM, id), \
87 SRI(CM_DGAM_RAMB_END_CNTL1_G, CM, id), \
88 SRI(CM_DGAM_RAMB_END_CNTL2_G, CM, id), \
89 SRI(CM_DGAM_RAMB_END_CNTL1_R, CM, id), \
90 SRI(CM_DGAM_RAMB_END_CNTL2_R, CM, id), \
91 SRI(CM_DGAM_RAMB_REGION_0_1, CM, id), \
92 SRI(CM_DGAM_RAMB_REGION_14_15, CM, id), \
93 SRI(CM_DGAM_RAMA_START_CNTL_B, CM, id), \
94 SRI(CM_DGAM_RAMA_START_CNTL_G, CM, id), \
95 SRI(CM_DGAM_RAMA_START_CNTL_R, CM, id), \
96 SRI(CM_DGAM_RAMA_SLOPE_CNTL_B, CM, id), \
97 SRI(CM_DGAM_RAMA_SLOPE_CNTL_G, CM, id), \
98 SRI(CM_DGAM_RAMA_SLOPE_CNTL_R, CM, id), \
99 SRI(CM_DGAM_RAMA_END_CNTL1_B, CM, id), \
100 SRI(CM_DGAM_RAMA_END_CNTL2_B, CM, id), \
101 SRI(CM_DGAM_RAMA_END_CNTL1_G, CM, id), \
102 SRI(CM_DGAM_RAMA_END_CNTL2_G, CM, id), \
103 SRI(CM_DGAM_RAMA_END_CNTL1_R, CM, id), \
104 SRI(CM_DGAM_RAMA_END_CNTL2_R, CM, id), \
105 SRI(CM_DGAM_RAMA_REGION_0_1, CM, id), \
106 SRI(CM_DGAM_RAMA_REGION_14_15, CM, id), \
107 SRI(CM_MEM_PWR_CTRL, CM, id), \
108 SRI(CM_DGAM_LUT_WRITE_EN_MASK, CM, id), \
109 SRI(CM_DGAM_LUT_INDEX, CM, id), \
110 SRI(CM_DGAM_LUT_DATA, CM, id), \
111 SRI(CM_CONTROL, CM, id), \
112 SRI(CM_DGAM_CONTROL, CM, id), \
113 SRI(FORMAT_CONTROL, CNVC_CFG, id), \
114 SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
115 SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
116 SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
117 SRI(CURSOR0_COLOR1, CNVC_CUR, id)
121 #define TF_REG_LIST_DCN10(id) \
122 TF_REG_LIST_DCN(id), \
123 SRI(CM_COMA_C11_C12, CM, id),\
124 SRI(CM_COMA_C33_C34, CM, id),\
125 SRI(CM_COMB_C11_C12, CM, id),\
126 SRI(CM_COMB_C33_C34, CM, id),\
127 SRI(CM_OCSC_CONTROL, CM, id), \
128 SRI(CM_OCSC_C11_C12, CM, id), \
129 SRI(CM_OCSC_C33_C34, CM, id), \
130 SRI(CM_MEM_PWR_CTRL, CM, id), \
131 SRI(CM_RGAM_LUT_DATA, CM, id), \
132 SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id),\
133 SRI(CM_RGAM_LUT_INDEX, CM, id), \
134 SRI(CM_RGAM_RAMB_START_CNTL_B, CM, id), \
135 SRI(CM_RGAM_RAMB_START_CNTL_G, CM, id), \
136 SRI(CM_RGAM_RAMB_START_CNTL_R, CM, id), \
137 SRI(CM_RGAM_RAMB_SLOPE_CNTL_B, CM, id), \
138 SRI(CM_RGAM_RAMB_SLOPE_CNTL_G, CM, id), \
139 SRI(CM_RGAM_RAMB_SLOPE_CNTL_R, CM, id), \
140 SRI(CM_RGAM_RAMB_END_CNTL1_B, CM, id), \
141 SRI(CM_RGAM_RAMB_END_CNTL2_B, CM, id), \
142 SRI(CM_RGAM_RAMB_END_CNTL1_G, CM, id), \
143 SRI(CM_RGAM_RAMB_END_CNTL2_G, CM, id), \
144 SRI(CM_RGAM_RAMB_END_CNTL1_R, CM, id), \
145 SRI(CM_RGAM_RAMB_END_CNTL2_R, CM, id), \
146 SRI(CM_RGAM_RAMB_REGION_0_1, CM, id), \
147 SRI(CM_RGAM_RAMB_REGION_32_33, CM, id), \
148 SRI(CM_RGAM_RAMA_START_CNTL_B, CM, id), \
149 SRI(CM_RGAM_RAMA_START_CNTL_G, CM, id), \
150 SRI(CM_RGAM_RAMA_START_CNTL_R, CM, id), \
151 SRI(CM_RGAM_RAMA_SLOPE_CNTL_B, CM, id), \
152 SRI(CM_RGAM_RAMA_SLOPE_CNTL_G, CM, id), \
153 SRI(CM_RGAM_RAMA_SLOPE_CNTL_R, CM, id), \
154 SRI(CM_RGAM_RAMA_END_CNTL1_B, CM, id), \
155 SRI(CM_RGAM_RAMA_END_CNTL2_B, CM, id), \
156 SRI(CM_RGAM_RAMA_END_CNTL1_G, CM, id), \
157 SRI(CM_RGAM_RAMA_END_CNTL2_G, CM, id), \
158 SRI(CM_RGAM_RAMA_END_CNTL1_R, CM, id), \
159 SRI(CM_RGAM_RAMA_END_CNTL2_R, CM, id), \
160 SRI(CM_RGAM_RAMA_REGION_0_1, CM, id), \
161 SRI(CM_RGAM_RAMA_REGION_32_33, CM, id), \
162 SRI(CM_RGAM_CONTROL, CM, id), \
163 SRI(CM_IGAM_CONTROL, CM, id), \
164 SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \
165 SRI(CM_IGAM_LUT_RW_INDEX, CM, id), \
166 SRI(CM_IGAM_LUT_SEQ_COLOR, CM, id), \
167 SRI(CURSOR_CONTROL, CURSOR, id), \
168 SRI(CM_CMOUT_CONTROL, CM, id)
171 #define TF_REG_LIST_SH_MASK_DCN(mask_sh)\
172 TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\
173 TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C11, mask_sh),\
174 TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C12, mask_sh),\
175 TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C33, mask_sh),\
176 TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C34, mask_sh),\
177 TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\
178 TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh),\
179 TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh),\
180 TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh),\
181 TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_START, mask_sh),\
182 TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_END, mask_sh),\
183 TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_START, mask_sh),\
184 TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_END, mask_sh),\
185 TF_SF(DSCL0_LB_DATA_FORMAT, INTERLEAVE_EN, mask_sh),\
186 TF2_SF(DSCL0, LB_DATA_FORMAT__ALPHA_EN, mask_sh),\
187 TF_SF(DSCL0_LB_MEMORY_CTRL, MEMORY_CONFIG, mask_sh),\
188 TF_SF(DSCL0_LB_MEMORY_CTRL, LB_MAX_PARTITIONS, mask_sh),\
189 TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_MODE, mask_sh),\
190 TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_NUM_PIPE, mask_sh),\
191 TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\
192 TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_RGB_Y, mask_sh),\
193 TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_CBCR, mask_sh),\
194 TF_SF(DSCL0_DSCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh),\
195 TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\
196 TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS, mask_sh),\
197 TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS_C, mask_sh),\
198 TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS_C, mask_sh),\
199 TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\
200 TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_PHASE, mask_sh),\
201 TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_FILTER_TYPE, mask_sh),\
202 TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\
203 TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\
204 TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\
205 TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\
206 TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh),\
207 TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_EN, mask_sh),\
208 TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_FACTOR, mask_sh),\
209 TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh),\
210 TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_EN, mask_sh),\
211 TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_FACTOR, mask_sh),\
212 TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\
213 TF_SF(DSCL0_SCL_MODE, DSCL_MODE, mask_sh),\
214 TF_SF(DSCL0_RECOUT_START, RECOUT_START_X, mask_sh),\
215 TF_SF(DSCL0_RECOUT_START, RECOUT_START_Y, mask_sh),\
216 TF_SF(DSCL0_RECOUT_SIZE, RECOUT_WIDTH, mask_sh),\
217 TF_SF(DSCL0_RECOUT_SIZE, RECOUT_HEIGHT, mask_sh),\
218 TF_SF(DSCL0_MPC_SIZE, MPC_WIDTH, mask_sh),\
219 TF_SF(DSCL0_MPC_SIZE, MPC_HEIGHT, mask_sh),\
220 TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh),\
221 TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh),\
222 TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C, SCL_H_SCALE_RATIO_C, mask_sh),\
223 TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C, SCL_V_SCALE_RATIO_C, mask_sh),\
224 TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh),\
225 TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh),\
226 TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_FRAC_C, mask_sh),\
227 TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_INT_C, mask_sh),\
228 TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh),\
229 TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh),\
230 TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_FRAC_BOT, mask_sh),\
231 TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_INT_BOT, mask_sh),\
232 TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_FRAC_C, mask_sh),\
233 TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_INT_C, mask_sh),\
234 TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_FRAC_BOT_C, mask_sh),\
235 TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh),\
236 TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\
237 TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \
238 TF_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh), \
239 TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \
240 TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \
241 TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \
242 TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \
243 TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \
244 TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_B, mask_sh), \
245 TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
246 TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_G, mask_sh), \
247 TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \
248 TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_R, mask_sh), \
249 TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \
250 TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_B, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
251 TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_G, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
252 TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_R, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
253 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_B, CM_DGAM_RAMB_EXP_REGION_END_B, mask_sh), \
254 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \
255 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \
256 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_G, CM_DGAM_RAMB_EXP_REGION_END_G, mask_sh), \
257 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \
258 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \
259 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_R, CM_DGAM_RAMB_EXP_REGION_END_R, mask_sh), \
260 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \
261 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \
262 TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \
263 TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
264 TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \
265 TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
266 TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \
267 TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
268 TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \
269 TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
270 TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_B, mask_sh), \
271 TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \
272 TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_G, mask_sh), \
273 TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \
274 TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_R, mask_sh), \
275 TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \
276 TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_B, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
277 TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_G, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
278 TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_R, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
279 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_B, CM_DGAM_RAMA_EXP_REGION_END_B, mask_sh), \
280 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \
281 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
282 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_G, CM_DGAM_RAMA_EXP_REGION_END_G, mask_sh), \
283 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \
284 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
285 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_R, CM_DGAM_RAMA_EXP_REGION_END_R, mask_sh), \
286 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \
287 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
288 TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \
289 TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
290 TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \
291 TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
292 TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \
293 TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
294 TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \
295 TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
296 TF_SF(CM0_CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, mask_sh), \
297 TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_EN_MASK, mask_sh), \
298 TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, mask_sh), \
299 TF_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \
300 TF_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \
301 TF_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \
302 TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \
303 TF2_SF(CNVC_CFG0, FORMAT_CONTROL__ALPHA_EN, mask_sh), \
304 TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
305 TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
306 TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \
307 TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \
308 TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \
309 TF_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \
310 TF_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh)
312 #define TF_REG_LIST_SH_MASK_DCN10(mask_sh)\
313 TF_REG_LIST_SH_MASK_DCN(mask_sh),\
314 TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh),\
315 TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh),\
316 TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_REDUCE_MODE, mask_sh),\
317 TF_SF(DSCL0_LB_DATA_FORMAT, DYNAMIC_PIXEL_DEPTH, mask_sh),\
318 TF_SF(DSCL0_LB_DATA_FORMAT, DITHER_EN, mask_sh),\
319 TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C11, mask_sh),\
320 TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C12, mask_sh),\
321 TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C33, mask_sh),\
322 TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C34, mask_sh),\
323 TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C11, mask_sh),\
324 TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C12, mask_sh),\
325 TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C33, mask_sh),\
326 TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C34, mask_sh),\
327 TF_SF(CM0_CM_OCSC_CONTROL, CM_OCSC_MODE, mask_sh), \
328 TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C11, mask_sh), \
329 TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \
330 TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \
331 TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \
332 TF_SF(CM0_CM_MEM_PWR_CTRL, RGAM_MEM_PWR_FORCE, mask_sh), \
333 TF_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh), \
334 TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_EN_MASK, mask_sh), \
335 TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_SEL, mask_sh), \
336 TF_SF(CM0_CM_RGAM_LUT_INDEX, CM_RGAM_LUT_INDEX, mask_sh), \
337 TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_B, mask_sh), \
338 TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
339 TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_G, mask_sh), \
340 TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \
341 TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_R, mask_sh), \
342 TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \
343 TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_B, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
344 TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_G, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
345 TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_R, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
346 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_B, CM_RGAM_RAMB_EXP_REGION_END_B, mask_sh), \
347 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \
348 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \
349 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_G, CM_RGAM_RAMB_EXP_REGION_END_G, mask_sh), \
350 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \
351 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \
352 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_R, CM_RGAM_RAMB_EXP_REGION_END_R, mask_sh), \
353 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \
354 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \
355 TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \
356 TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
357 TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \
358 TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
359 TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \
360 TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \
361 TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \
362 TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
363 TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_B, mask_sh), \
364 TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \
365 TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_G, mask_sh), \
366 TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \
367 TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_R, mask_sh), \
368 TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \
369 TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_B, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
370 TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_G, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
371 TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_R, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
372 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_B, CM_RGAM_RAMA_EXP_REGION_END_B, mask_sh), \
373 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \
374 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
375 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_G, CM_RGAM_RAMA_EXP_REGION_END_G, mask_sh), \
376 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \
377 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
378 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_R, CM_RGAM_RAMA_EXP_REGION_END_R, mask_sh), \
379 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \
380 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
381 TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \
382 TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
383 TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \
384 TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
385 TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \
386 TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \
387 TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \
388 TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
389 TF_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \
390 TF_SF(DSCL0_OBUF_CONTROL, OBUF_H_2X_UPSCALE_EN, mask_sh), \
391 TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, mask_sh), \
392 TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_R, mask_sh), \
393 TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_G, mask_sh), \
394 TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_B, mask_sh), \
395 TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, mask_sh), \
396 TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, mask_sh), \
397 TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, mask_sh), \
398 TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, mask_sh), \
399 TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, mask_sh), \
400 TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, mask_sh), \
401 TF_SF(CM0_CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, mask_sh), \
402 TF_SF(CM0_CM_CONTROL, CM_BYPASS_EN, mask_sh), \
403 TF_SF(CM0_CM_IGAM_LUT_SEQ_COLOR, CM_IGAM_LUT_SEQ_COLOR, mask_sh), \
404 TF_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh), \
405 TF_SF(CM0_CM_CMOUT_CONTROL, CM_CMOUT_ROUND_TRUNC_MODE, mask_sh), \
406 TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
407 TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
408 TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
409 TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh)
411 #define TF_REG_FIELD_LIST(type) \
412 type EXT_OVERSCAN_LEFT; \
413 type EXT_OVERSCAN_RIGHT; \
414 type EXT_OVERSCAN_BOTTOM; \
415 type EXT_OVERSCAN_TOP; \
416 type OTG_H_BLANK_START; \
417 type OTG_H_BLANK_END; \
418 type OTG_V_BLANK_START; \
419 type OTG_V_BLANK_END; \
421 type PIXEL_EXPAN_MODE; \
422 type PIXEL_REDUCE_MODE; \
423 type DYNAMIC_PIXEL_DEPTH; \
425 type INTERLEAVE_EN; \
426 type LB_DATA_FORMAT__ALPHA_EN; \
427 type MEMORY_CONFIG; \
428 type LB_MAX_PARTITIONS; \
430 type AUTOCAL_NUM_PIPE; \
431 type AUTOCAL_PIPE_ID; \
432 type SCL_BLACK_OFFSET_RGB_Y; \
433 type SCL_BLACK_OFFSET_CBCR; \
434 type SCL_BOUNDARY_MODE; \
435 type SCL_V_NUM_TAPS; \
436 type SCL_H_NUM_TAPS; \
437 type SCL_V_NUM_TAPS_C; \
438 type SCL_H_NUM_TAPS_C; \
439 type SCL_COEF_RAM_TAP_PAIR_IDX; \
440 type SCL_COEF_RAM_PHASE; \
441 type SCL_COEF_RAM_FILTER_TYPE; \
442 type SCL_COEF_RAM_EVEN_TAP_COEF; \
443 type SCL_COEF_RAM_EVEN_TAP_COEF_EN; \
444 type SCL_COEF_RAM_ODD_TAP_COEF; \
445 type SCL_COEF_RAM_ODD_TAP_COEF_EN; \
446 type SCL_H_2TAP_HARDCODE_COEF_EN; \
447 type SCL_H_2TAP_SHARP_EN; \
448 type SCL_H_2TAP_SHARP_FACTOR; \
449 type SCL_V_2TAP_HARDCODE_COEF_EN; \
450 type SCL_V_2TAP_SHARP_EN; \
451 type SCL_V_2TAP_SHARP_FACTOR; \
452 type SCL_COEF_RAM_SELECT; \
454 type RECOUT_START_X; \
455 type RECOUT_START_Y; \
457 type RECOUT_HEIGHT; \
460 type SCL_H_SCALE_RATIO; \
461 type SCL_V_SCALE_RATIO; \
462 type SCL_H_SCALE_RATIO_C; \
463 type SCL_V_SCALE_RATIO_C; \
464 type SCL_H_INIT_FRAC; \
465 type SCL_H_INIT_INT; \
466 type SCL_H_INIT_FRAC_C; \
467 type SCL_H_INIT_INT_C; \
468 type SCL_V_INIT_FRAC; \
469 type SCL_V_INIT_INT; \
470 type SCL_V_INIT_FRAC_BOT; \
471 type SCL_V_INIT_INT_BOT; \
472 type SCL_V_INIT_FRAC_C; \
473 type SCL_V_INIT_INT_C; \
474 type SCL_V_INIT_FRAC_BOT_C; \
475 type SCL_V_INIT_INT_BOT_C; \
476 type SCL_CHROMA_COEF_MODE; \
477 type SCL_COEF_RAM_SELECT_CURRENT; \
478 type CM_GAMUT_REMAP_MODE; \
479 type CM_GAMUT_REMAP_C11; \
480 type CM_GAMUT_REMAP_C12; \
481 type CM_GAMUT_REMAP_C33; \
482 type CM_GAMUT_REMAP_C34; \
496 type RGAM_MEM_PWR_FORCE; \
497 type CM_RGAM_LUT_DATA; \
498 type CM_RGAM_LUT_WRITE_EN_MASK; \
499 type CM_RGAM_LUT_WRITE_SEL; \
500 type CM_RGAM_LUT_INDEX; \
501 type CM_RGAM_RAMB_EXP_REGION_START_B; \
502 type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; \
503 type CM_RGAM_RAMB_EXP_REGION_START_G; \
504 type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G; \
505 type CM_RGAM_RAMB_EXP_REGION_START_R; \
506 type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R; \
507 type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \
508 type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \
509 type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \
510 type CM_RGAM_RAMB_EXP_REGION_END_B; \
511 type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; \
512 type CM_RGAM_RAMB_EXP_REGION_END_BASE_B; \
513 type CM_RGAM_RAMB_EXP_REGION_END_G; \
514 type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G; \
515 type CM_RGAM_RAMB_EXP_REGION_END_BASE_G; \
516 type CM_RGAM_RAMB_EXP_REGION_END_R; \
517 type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R; \
518 type CM_RGAM_RAMB_EXP_REGION_END_BASE_R; \
519 type CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET; \
520 type CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \
521 type CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET; \
522 type CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \
523 type CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET; \
524 type CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS; \
525 type CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET; \
526 type CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS; \
527 type CM_RGAM_RAMA_EXP_REGION_START_B; \
528 type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B; \
529 type CM_RGAM_RAMA_EXP_REGION_START_G; \
530 type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G; \
531 type CM_RGAM_RAMA_EXP_REGION_START_R; \
532 type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R; \
533 type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \
534 type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \
535 type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \
536 type CM_RGAM_RAMA_EXP_REGION_END_B; \
537 type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B; \
538 type CM_RGAM_RAMA_EXP_REGION_END_BASE_B; \
539 type CM_RGAM_RAMA_EXP_REGION_END_G; \
540 type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G; \
541 type CM_RGAM_RAMA_EXP_REGION_END_BASE_G; \
542 type CM_RGAM_RAMA_EXP_REGION_END_R; \
543 type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R; \
544 type CM_RGAM_RAMA_EXP_REGION_END_BASE_R; \
545 type CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; \
546 type CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \
547 type CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; \
548 type CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \
549 type CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET; \
550 type CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS; \
551 type CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET; \
552 type CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \
553 type CM_RGAM_LUT_MODE; \
554 type CM_CMOUT_ROUND_TRUNC_MODE; \
556 type OBUF_H_2X_UPSCALE_EN; \
557 type CM_BLNDGAM_LUT_MODE; \
558 type CM_BLNDGAM_RAMB_EXP_REGION_START_B; \
559 type CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B; \
560 type CM_BLNDGAM_RAMB_EXP_REGION_START_G; \
561 type CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G; \
562 type CM_BLNDGAM_RAMB_EXP_REGION_START_R; \
563 type CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R; \
564 type CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \
565 type CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \
566 type CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \
567 type CM_BLNDGAM_RAMB_EXP_REGION_END_B; \
568 type CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B; \
569 type CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B; \
570 type CM_BLNDGAM_RAMB_EXP_REGION_END_G; \
571 type CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G; \
572 type CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G; \
573 type CM_BLNDGAM_RAMB_EXP_REGION_END_R; \
574 type CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R; \
575 type CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R; \
576 type CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET; \
577 type CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \
578 type CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET; \
579 type CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \
580 type CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET; \
581 type CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS; \
582 type CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET; \
583 type CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS; \
584 type CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET; \
585 type CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS; \
586 type CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET; \
587 type CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS; \
588 type CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET; \
589 type CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS; \
590 type CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET; \
591 type CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS; \
592 type CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET; \
593 type CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS; \
594 type CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET; \
595 type CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS; \
596 type CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET; \
597 type CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS; \
598 type CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET; \
599 type CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS; \
600 type CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET; \
601 type CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS; \
602 type CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET; \
603 type CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS; \
604 type CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET; \
605 type CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS; \
606 type CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET; \
607 type CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS; \
608 type CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET; \
609 type CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS; \
610 type CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET; \
611 type CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS; \
612 type CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET; \
613 type CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS; \
614 type CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET; \
615 type CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS; \
616 type CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET; \
617 type CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS; \
618 type CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET; \
619 type CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS; \
620 type CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET; \
621 type CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS; \
622 type CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET; \
623 type CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS; \
624 type CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET; \
625 type CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS; \
626 type CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET; \
627 type CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS; \
628 type CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET; \
629 type CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS; \
630 type CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET; \
631 type CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS; \
632 type CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET; \
633 type CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS; \
634 type CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET; \
635 type CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS; \
636 type CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET; \
637 type CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS; \
638 type CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET; \
639 type CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS; \
640 type CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET; \
641 type CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS; \
642 type CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET; \
643 type CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS; \
644 type CM_BLNDGAM_RAMA_EXP_REGION_START_B; \
645 type CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; \
646 type CM_BLNDGAM_RAMA_EXP_REGION_START_G; \
647 type CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G; \
648 type CM_BLNDGAM_RAMA_EXP_REGION_START_R; \
649 type CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R; \
650 type CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \
651 type CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \
652 type CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \
653 type CM_BLNDGAM_RAMA_EXP_REGION_END_B; \
654 type CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; \
655 type CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; \
656 type CM_BLNDGAM_RAMA_EXP_REGION_END_G; \
657 type CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G; \
658 type CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G; \
659 type CM_BLNDGAM_RAMA_EXP_REGION_END_R; \
660 type CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R; \
661 type CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R; \
662 type CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; \
663 type CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \
664 type CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; \
665 type CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \
666 type CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET; \
667 type CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS; \
668 type CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET; \
669 type CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS; \
670 type CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET; \
671 type CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS; \
672 type CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET; \
673 type CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS; \
674 type CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET; \
675 type CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS; \
676 type CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET; \
677 type CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS; \
678 type CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET; \
679 type CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS; \
680 type CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET; \
681 type CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS; \
682 type CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET; \
683 type CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS; \
684 type CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET; \
685 type CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS; \
686 type CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET; \
687 type CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS; \
688 type CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET; \
689 type CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS; \
690 type CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET; \
691 type CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \
692 type CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET; \
693 type CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \
694 type CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET; \
695 type CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS; \
696 type CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET; \
697 type CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS; \
698 type CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET; \
699 type CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS; \
700 type CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET; \
701 type CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS; \
702 type CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET; \
703 type CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS; \
704 type CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET; \
705 type CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS; \
706 type CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET; \
707 type CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS; \
708 type CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET; \
709 type CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS; \
710 type CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET; \
711 type CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS; \
712 type CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET; \
713 type CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS; \
714 type CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET; \
715 type CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS; \
716 type CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET; \
717 type CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS; \
718 type CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET; \
719 type CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS; \
720 type CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET; \
721 type CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS; \
722 type CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET; \
723 type CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS; \
724 type CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET; \
725 type CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS; \
726 type CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET; \
727 type CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS; \
728 type CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET; \
729 type CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \
730 type CM_BLNDGAM_LUT_WRITE_EN_MASK; \
731 type CM_BLNDGAM_LUT_WRITE_SEL; \
732 type CM_BLNDGAM_LUT_INDEX; \
733 type CM_BLNDGAM_LUT_DATA; \
734 type CM_3DLUT_MODE; \
735 type CM_3DLUT_SIZE; \
736 type CM_3DLUT_INDEX; \
737 type CM_3DLUT_DATA0; \
738 type CM_3DLUT_DATA1; \
739 type CM_3DLUT_DATA_30BIT; \
740 type CM_3DLUT_WRITE_EN_MASK; \
741 type CM_3DLUT_RAM_SEL; \
742 type CM_3DLUT_30BIT_EN; \
743 type CM_3DLUT_CONFIG_STATUS; \
744 type CM_3DLUT_READ_SEL; \
745 type CM_SHAPER_LUT_MODE; \
746 type CM_SHAPER_RAMB_EXP_REGION_START_B; \
747 type CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B; \
748 type CM_SHAPER_RAMB_EXP_REGION_START_G; \
749 type CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G; \
750 type CM_SHAPER_RAMB_EXP_REGION_START_R; \
751 type CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R; \
752 type CM_SHAPER_RAMB_EXP_REGION_END_B; \
753 type CM_SHAPER_RAMB_EXP_REGION_END_BASE_B; \
754 type CM_SHAPER_RAMB_EXP_REGION_END_G; \
755 type CM_SHAPER_RAMB_EXP_REGION_END_BASE_G; \
756 type CM_SHAPER_RAMB_EXP_REGION_END_R; \
757 type CM_SHAPER_RAMB_EXP_REGION_END_BASE_R; \
758 type CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET; \
759 type CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS; \
760 type CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET; \
761 type CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS; \
762 type CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET; \
763 type CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS; \
764 type CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET; \
765 type CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS; \
766 type CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET; \
767 type CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS; \
768 type CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET; \
769 type CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS; \
770 type CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET; \
771 type CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS; \
772 type CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET; \
773 type CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS; \
774 type CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET; \
775 type CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS; \
776 type CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET; \
777 type CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS; \
778 type CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET; \
779 type CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS; \
780 type CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET; \
781 type CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS; \
782 type CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET; \
783 type CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS; \
784 type CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET; \
785 type CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS; \
786 type CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET; \
787 type CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS; \
788 type CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET; \
789 type CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS; \
790 type CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET; \
791 type CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS; \
792 type CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET; \
793 type CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS; \
794 type CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET; \
795 type CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS; \
796 type CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET; \
797 type CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS; \
798 type CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET; \
799 type CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS; \
800 type CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET; \
801 type CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS; \
802 type CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET; \
803 type CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS; \
804 type CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET; \
805 type CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS; \
806 type CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET; \
807 type CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS; \
808 type CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET; \
809 type CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS; \
810 type CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET; \
811 type CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS; \
812 type CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET; \
813 type CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS; \
814 type CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET; \
815 type CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS; \
816 type CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET; \
817 type CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS; \
818 type CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET; \
819 type CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS; \
820 type CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET; \
821 type CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS; \
822 type CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET; \
823 type CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS; \
824 type CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET; \
825 type CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS; \
826 type CM_SHAPER_RAMA_EXP_REGION_START_B; \
827 type CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B; \
828 type CM_SHAPER_RAMA_EXP_REGION_START_G; \
829 type CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G; \
830 type CM_SHAPER_RAMA_EXP_REGION_START_R; \
831 type CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R; \
832 type CM_SHAPER_RAMA_EXP_REGION_END_B; \
833 type CM_SHAPER_RAMA_EXP_REGION_END_BASE_B; \
834 type CM_SHAPER_RAMA_EXP_REGION_END_G; \
835 type CM_SHAPER_RAMA_EXP_REGION_END_BASE_G; \
836 type CM_SHAPER_RAMA_EXP_REGION_END_R; \
837 type CM_SHAPER_RAMA_EXP_REGION_END_BASE_R; \
838 type CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET; \
839 type CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS; \
840 type CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET; \
841 type CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS; \
842 type CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET; \
843 type CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS; \
844 type CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET; \
845 type CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS; \
846 type CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET; \
847 type CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS; \
848 type CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET; \
849 type CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS; \
850 type CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET; \
851 type CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS; \
852 type CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET; \
853 type CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS; \
854 type CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET; \
855 type CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS; \
856 type CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET; \
857 type CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS; \
858 type CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET; \
859 type CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS; \
860 type CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET; \
861 type CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS; \
862 type CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET; \
863 type CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS; \
864 type CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET; \
865 type CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS; \
866 type CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET; \
867 type CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS; \
868 type CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET; \
869 type CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS; \
870 type CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET; \
871 type CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS; \
872 type CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET; \
873 type CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS; \
874 type CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET; \
875 type CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS; \
876 type CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET; \
877 type CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS; \
878 type CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET; \
879 type CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS; \
880 type CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET; \
881 type CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS; \
882 type CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET; \
883 type CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS; \
884 type CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET; \
885 type CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS; \
886 type CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET; \
887 type CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS; \
888 type CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET; \
889 type CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS; \
890 type CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET; \
891 type CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS; \
892 type CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET; \
893 type CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS; \
894 type CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET; \
895 type CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS; \
896 type CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET; \
897 type CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS; \
898 type CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET; \
899 type CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS; \
900 type CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET; \
901 type CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS; \
902 type CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET; \
903 type CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS; \
904 type CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET; \
905 type CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS; \
906 type CM_SHAPER_LUT_WRITE_EN_MASK; \
907 type CM_SHAPER_LUT_WRITE_SEL; \
908 type CM_SHAPER_LUT_INDEX; \
909 type CM_SHAPER_LUT_DATA; \
910 type CM_DGAM_CONFIG_STATUS; \
916 type CM_DGAM_RAMB_EXP_REGION_START_B; \
917 type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B; \
918 type CM_DGAM_RAMB_EXP_REGION_START_G; \
919 type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G; \
920 type CM_DGAM_RAMB_EXP_REGION_START_R; \
921 type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R; \
922 type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \
923 type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \
924 type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \
925 type CM_DGAM_RAMB_EXP_REGION_END_B; \
926 type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B; \
927 type CM_DGAM_RAMB_EXP_REGION_END_BASE_B; \
928 type CM_DGAM_RAMB_EXP_REGION_END_G; \
929 type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G; \
930 type CM_DGAM_RAMB_EXP_REGION_END_BASE_G; \
931 type CM_DGAM_RAMB_EXP_REGION_END_R; \
932 type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R; \
933 type CM_DGAM_RAMB_EXP_REGION_END_BASE_R; \
934 type CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET; \
935 type CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \
936 type CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET; \
937 type CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \
938 type CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET; \
939 type CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS; \
940 type CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET; \
941 type CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS; \
942 type CM_DGAM_RAMA_EXP_REGION_START_B; \
943 type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B; \
944 type CM_DGAM_RAMA_EXP_REGION_START_G; \
945 type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G; \
946 type CM_DGAM_RAMA_EXP_REGION_START_R; \
947 type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R; \
948 type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \
949 type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \
950 type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \
951 type CM_DGAM_RAMA_EXP_REGION_END_B; \
952 type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B; \
953 type CM_DGAM_RAMA_EXP_REGION_END_BASE_B; \
954 type CM_DGAM_RAMA_EXP_REGION_END_G; \
955 type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G; \
956 type CM_DGAM_RAMA_EXP_REGION_END_BASE_G; \
957 type CM_DGAM_RAMA_EXP_REGION_END_R; \
958 type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R; \
959 type CM_DGAM_RAMA_EXP_REGION_END_BASE_R; \
960 type CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET; \
961 type CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \
962 type CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET; \
963 type CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \
964 type CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET; \
965 type CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \
966 type CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET; \
967 type CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \
968 type SHARED_MEM_PWR_DIS; \
969 type CM_IGAM_LUT_FORMAT_R; \
970 type CM_IGAM_LUT_FORMAT_G; \
971 type CM_IGAM_LUT_FORMAT_B; \
972 type CM_IGAM_LUT_HOST_EN; \
973 type CM_IGAM_LUT_RW_MODE; \
974 type CM_IGAM_LUT_WRITE_EN_MASK; \
975 type CM_IGAM_LUT_SEL; \
976 type CM_IGAM_LUT_SEQ_COLOR; \
977 type CM_IGAM_DGAM_CONFIG_STATUS; \
978 type CM_DGAM_LUT_WRITE_EN_MASK; \
979 type CM_DGAM_LUT_WRITE_SEL; \
980 type CM_DGAM_LUT_INDEX; \
981 type CM_DGAM_LUT_DATA; \
982 type CM_DGAM_LUT_MODE; \
983 type CM_IGAM_LUT_MODE; \
984 type CM_IGAM_INPUT_FORMAT; \
985 type CM_IGAM_LUT_RW_INDEX; \
987 type FORMAT_EXPANSION_MODE; \
990 type CNVC_SURFACE_PIXEL_FORMAT; \
993 type CURSOR_LINES_PER_CHUNK; \
994 type CURSOR_ENABLE; \
996 type CUR0_EXPANSION_MODE; \
999 type FORMAT_CONTROL__ALPHA_EN; \
1005 struct dcn_dpp_shift {
1006 TF_REG_FIELD_LIST(uint8_t);
1009 struct dcn_dpp_mask {
1010 TF_REG_FIELD_LIST(uint32_t);
1016 struct dcn_dpp_registers {
1017 uint32_t DSCL_EXT_OVERSCAN_LEFT_RIGHT;
1018 uint32_t DSCL_EXT_OVERSCAN_TOP_BOTTOM;
1019 uint32_t OTG_H_BLANK;
1020 uint32_t OTG_V_BLANK;
1022 uint32_t LB_DATA_FORMAT;
1023 uint32_t LB_MEMORY_CTRL;
1024 uint32_t DSCL_AUTOCAL;
1025 uint32_t SCL_BLACK_OFFSET;
1026 uint32_t DSCL_CONTROL;
1027 uint32_t SCL_TAP_CONTROL;
1028 uint32_t SCL_COEF_RAM_TAP_SELECT;
1029 uint32_t SCL_COEF_RAM_TAP_DATA;
1030 uint32_t DSCL_2TAP_CONTROL;
1032 uint32_t SCL_HORZ_FILTER_SCALE_RATIO;
1033 uint32_t SCL_VERT_FILTER_SCALE_RATIO;
1034 uint32_t SCL_HORZ_FILTER_SCALE_RATIO_C;
1035 uint32_t SCL_VERT_FILTER_SCALE_RATIO_C;
1036 uint32_t SCL_HORZ_FILTER_INIT;
1037 uint32_t SCL_HORZ_FILTER_INIT_C;
1038 uint32_t SCL_VERT_FILTER_INIT;
1039 uint32_t SCL_VERT_FILTER_INIT_BOT;
1040 uint32_t SCL_VERT_FILTER_INIT_C;
1041 uint32_t SCL_VERT_FILTER_INIT_BOT_C;
1042 uint32_t RECOUT_START;
1043 uint32_t RECOUT_SIZE;
1044 uint32_t CM_GAMUT_REMAP_CONTROL;
1045 uint32_t CM_GAMUT_REMAP_C11_C12;
1046 uint32_t CM_GAMUT_REMAP_C33_C34;
1047 uint32_t CM_COMA_C11_C12;
1048 uint32_t CM_COMA_C33_C34;
1049 uint32_t CM_COMB_C11_C12;
1050 uint32_t CM_COMB_C33_C34;
1051 uint32_t CM_OCSC_CONTROL;
1052 uint32_t CM_OCSC_C11_C12;
1053 uint32_t CM_OCSC_C33_C34;
1054 uint32_t CM_MEM_PWR_CTRL;
1055 uint32_t CM_RGAM_LUT_DATA;
1056 uint32_t CM_RGAM_LUT_WRITE_EN_MASK;
1057 uint32_t CM_RGAM_LUT_INDEX;
1058 uint32_t CM_RGAM_RAMB_START_CNTL_B;
1059 uint32_t CM_RGAM_RAMB_START_CNTL_G;
1060 uint32_t CM_RGAM_RAMB_START_CNTL_R;
1061 uint32_t CM_RGAM_RAMB_SLOPE_CNTL_B;
1062 uint32_t CM_RGAM_RAMB_SLOPE_CNTL_G;
1063 uint32_t CM_RGAM_RAMB_SLOPE_CNTL_R;
1064 uint32_t CM_RGAM_RAMB_END_CNTL1_B;
1065 uint32_t CM_RGAM_RAMB_END_CNTL2_B;
1066 uint32_t CM_RGAM_RAMB_END_CNTL1_G;
1067 uint32_t CM_RGAM_RAMB_END_CNTL2_G;
1068 uint32_t CM_RGAM_RAMB_END_CNTL1_R;
1069 uint32_t CM_RGAM_RAMB_END_CNTL2_R;
1070 uint32_t CM_RGAM_RAMB_REGION_0_1;
1071 uint32_t CM_RGAM_RAMB_REGION_32_33;
1072 uint32_t CM_RGAM_RAMA_START_CNTL_B;
1073 uint32_t CM_RGAM_RAMA_START_CNTL_G;
1074 uint32_t CM_RGAM_RAMA_START_CNTL_R;
1075 uint32_t CM_RGAM_RAMA_SLOPE_CNTL_B;
1076 uint32_t CM_RGAM_RAMA_SLOPE_CNTL_G;
1077 uint32_t CM_RGAM_RAMA_SLOPE_CNTL_R;
1078 uint32_t CM_RGAM_RAMA_END_CNTL1_B;
1079 uint32_t CM_RGAM_RAMA_END_CNTL2_B;
1080 uint32_t CM_RGAM_RAMA_END_CNTL1_G;
1081 uint32_t CM_RGAM_RAMA_END_CNTL2_G;
1082 uint32_t CM_RGAM_RAMA_END_CNTL1_R;
1083 uint32_t CM_RGAM_RAMA_END_CNTL2_R;
1084 uint32_t CM_RGAM_RAMA_REGION_0_1;
1085 uint32_t CM_RGAM_RAMA_REGION_32_33;
1086 uint32_t CM_RGAM_CONTROL;
1087 uint32_t CM_CMOUT_CONTROL;
1088 uint32_t OBUF_CONTROL;
1089 uint32_t CM_BLNDGAM_LUT_WRITE_EN_MASK;
1090 uint32_t CM_BLNDGAM_CONTROL;
1091 uint32_t CM_BLNDGAM_RAMB_START_CNTL_B;
1092 uint32_t CM_BLNDGAM_RAMB_START_CNTL_G;
1093 uint32_t CM_BLNDGAM_RAMB_START_CNTL_R;
1094 uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_B;
1095 uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_G;
1096 uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_R;
1097 uint32_t CM_BLNDGAM_RAMB_END_CNTL1_B;
1098 uint32_t CM_BLNDGAM_RAMB_END_CNTL2_B;
1099 uint32_t CM_BLNDGAM_RAMB_END_CNTL1_G;
1100 uint32_t CM_BLNDGAM_RAMB_END_CNTL2_G;
1101 uint32_t CM_BLNDGAM_RAMB_END_CNTL1_R;
1102 uint32_t CM_BLNDGAM_RAMB_END_CNTL2_R;
1103 uint32_t CM_BLNDGAM_RAMB_REGION_0_1;
1104 uint32_t CM_BLNDGAM_RAMB_REGION_2_3;
1105 uint32_t CM_BLNDGAM_RAMB_REGION_4_5;
1106 uint32_t CM_BLNDGAM_RAMB_REGION_6_7;
1107 uint32_t CM_BLNDGAM_RAMB_REGION_8_9;
1108 uint32_t CM_BLNDGAM_RAMB_REGION_10_11;
1109 uint32_t CM_BLNDGAM_RAMB_REGION_12_13;
1110 uint32_t CM_BLNDGAM_RAMB_REGION_14_15;
1111 uint32_t CM_BLNDGAM_RAMB_REGION_16_17;
1112 uint32_t CM_BLNDGAM_RAMB_REGION_18_19;
1113 uint32_t CM_BLNDGAM_RAMB_REGION_20_21;
1114 uint32_t CM_BLNDGAM_RAMB_REGION_22_23;
1115 uint32_t CM_BLNDGAM_RAMB_REGION_24_25;
1116 uint32_t CM_BLNDGAM_RAMB_REGION_26_27;
1117 uint32_t CM_BLNDGAM_RAMB_REGION_28_29;
1118 uint32_t CM_BLNDGAM_RAMB_REGION_30_31;
1119 uint32_t CM_BLNDGAM_RAMB_REGION_32_33;
1120 uint32_t CM_BLNDGAM_RAMA_START_CNTL_B;
1121 uint32_t CM_BLNDGAM_RAMA_START_CNTL_G;
1122 uint32_t CM_BLNDGAM_RAMA_START_CNTL_R;
1123 uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_B;
1124 uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_G;
1125 uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_R;
1126 uint32_t CM_BLNDGAM_RAMA_END_CNTL1_B;
1127 uint32_t CM_BLNDGAM_RAMA_END_CNTL2_B;
1128 uint32_t CM_BLNDGAM_RAMA_END_CNTL1_G;
1129 uint32_t CM_BLNDGAM_RAMA_END_CNTL2_G;
1130 uint32_t CM_BLNDGAM_RAMA_END_CNTL1_R;
1131 uint32_t CM_BLNDGAM_RAMA_END_CNTL2_R;
1132 uint32_t CM_BLNDGAM_RAMA_REGION_0_1;
1133 uint32_t CM_BLNDGAM_RAMA_REGION_2_3;
1134 uint32_t CM_BLNDGAM_RAMA_REGION_4_5;
1135 uint32_t CM_BLNDGAM_RAMA_REGION_6_7;
1136 uint32_t CM_BLNDGAM_RAMA_REGION_8_9;
1137 uint32_t CM_BLNDGAM_RAMA_REGION_10_11;
1138 uint32_t CM_BLNDGAM_RAMA_REGION_12_13;
1139 uint32_t CM_BLNDGAM_RAMA_REGION_14_15;
1140 uint32_t CM_BLNDGAM_RAMA_REGION_16_17;
1141 uint32_t CM_BLNDGAM_RAMA_REGION_18_19;
1142 uint32_t CM_BLNDGAM_RAMA_REGION_20_21;
1143 uint32_t CM_BLNDGAM_RAMA_REGION_22_23;
1144 uint32_t CM_BLNDGAM_RAMA_REGION_24_25;
1145 uint32_t CM_BLNDGAM_RAMA_REGION_26_27;
1146 uint32_t CM_BLNDGAM_RAMA_REGION_28_29;
1147 uint32_t CM_BLNDGAM_RAMA_REGION_30_31;
1148 uint32_t CM_BLNDGAM_RAMA_REGION_32_33;
1149 uint32_t CM_BLNDGAM_LUT_INDEX;
1150 uint32_t CM_BLNDGAM_LUT_DATA;
1151 uint32_t CM_3DLUT_MODE;
1152 uint32_t CM_3DLUT_INDEX;
1153 uint32_t CM_3DLUT_DATA;
1154 uint32_t CM_3DLUT_DATA_30BIT;
1155 uint32_t CM_3DLUT_READ_WRITE_CONTROL;
1156 uint32_t CM_SHAPER_LUT_WRITE_EN_MASK;
1157 uint32_t CM_SHAPER_CONTROL;
1158 uint32_t CM_SHAPER_RAMB_START_CNTL_B;
1159 uint32_t CM_SHAPER_RAMB_START_CNTL_G;
1160 uint32_t CM_SHAPER_RAMB_START_CNTL_R;
1161 uint32_t CM_SHAPER_RAMB_END_CNTL_B;
1162 uint32_t CM_SHAPER_RAMB_END_CNTL_G;
1163 uint32_t CM_SHAPER_RAMB_END_CNTL_R;
1164 uint32_t CM_SHAPER_RAMB_REGION_0_1;
1165 uint32_t CM_SHAPER_RAMB_REGION_2_3;
1166 uint32_t CM_SHAPER_RAMB_REGION_4_5;
1167 uint32_t CM_SHAPER_RAMB_REGION_6_7;
1168 uint32_t CM_SHAPER_RAMB_REGION_8_9;
1169 uint32_t CM_SHAPER_RAMB_REGION_10_11;
1170 uint32_t CM_SHAPER_RAMB_REGION_12_13;
1171 uint32_t CM_SHAPER_RAMB_REGION_14_15;
1172 uint32_t CM_SHAPER_RAMB_REGION_16_17;
1173 uint32_t CM_SHAPER_RAMB_REGION_18_19;
1174 uint32_t CM_SHAPER_RAMB_REGION_20_21;
1175 uint32_t CM_SHAPER_RAMB_REGION_22_23;
1176 uint32_t CM_SHAPER_RAMB_REGION_24_25;
1177 uint32_t CM_SHAPER_RAMB_REGION_26_27;
1178 uint32_t CM_SHAPER_RAMB_REGION_28_29;
1179 uint32_t CM_SHAPER_RAMB_REGION_30_31;
1180 uint32_t CM_SHAPER_RAMB_REGION_32_33;
1181 uint32_t CM_SHAPER_RAMA_START_CNTL_B;
1182 uint32_t CM_SHAPER_RAMA_START_CNTL_G;
1183 uint32_t CM_SHAPER_RAMA_START_CNTL_R;
1184 uint32_t CM_SHAPER_RAMA_END_CNTL_B;
1185 uint32_t CM_SHAPER_RAMA_END_CNTL_G;
1186 uint32_t CM_SHAPER_RAMA_END_CNTL_R;
1187 uint32_t CM_SHAPER_RAMA_REGION_0_1;
1188 uint32_t CM_SHAPER_RAMA_REGION_2_3;
1189 uint32_t CM_SHAPER_RAMA_REGION_4_5;
1190 uint32_t CM_SHAPER_RAMA_REGION_6_7;
1191 uint32_t CM_SHAPER_RAMA_REGION_8_9;
1192 uint32_t CM_SHAPER_RAMA_REGION_10_11;
1193 uint32_t CM_SHAPER_RAMA_REGION_12_13;
1194 uint32_t CM_SHAPER_RAMA_REGION_14_15;
1195 uint32_t CM_SHAPER_RAMA_REGION_16_17;
1196 uint32_t CM_SHAPER_RAMA_REGION_18_19;
1197 uint32_t CM_SHAPER_RAMA_REGION_20_21;
1198 uint32_t CM_SHAPER_RAMA_REGION_22_23;
1199 uint32_t CM_SHAPER_RAMA_REGION_24_25;
1200 uint32_t CM_SHAPER_RAMA_REGION_26_27;
1201 uint32_t CM_SHAPER_RAMA_REGION_28_29;
1202 uint32_t CM_SHAPER_RAMA_REGION_30_31;
1203 uint32_t CM_SHAPER_RAMA_REGION_32_33;
1204 uint32_t CM_SHAPER_LUT_INDEX;
1205 uint32_t CM_SHAPER_LUT_DATA;
1206 uint32_t CM_ICSC_CONTROL;
1207 uint32_t CM_ICSC_C11_C12;
1208 uint32_t CM_ICSC_C33_C34;
1209 uint32_t CM_DGAM_RAMB_START_CNTL_B;
1210 uint32_t CM_DGAM_RAMB_START_CNTL_G;
1211 uint32_t CM_DGAM_RAMB_START_CNTL_R;
1212 uint32_t CM_DGAM_RAMB_SLOPE_CNTL_B;
1213 uint32_t CM_DGAM_RAMB_SLOPE_CNTL_G;
1214 uint32_t CM_DGAM_RAMB_SLOPE_CNTL_R;
1215 uint32_t CM_DGAM_RAMB_END_CNTL1_B;
1216 uint32_t CM_DGAM_RAMB_END_CNTL2_B;
1217 uint32_t CM_DGAM_RAMB_END_CNTL1_G;
1218 uint32_t CM_DGAM_RAMB_END_CNTL2_G;
1219 uint32_t CM_DGAM_RAMB_END_CNTL1_R;
1220 uint32_t CM_DGAM_RAMB_END_CNTL2_R;
1221 uint32_t CM_DGAM_RAMB_REGION_0_1;
1222 uint32_t CM_DGAM_RAMB_REGION_14_15;
1223 uint32_t CM_DGAM_RAMA_START_CNTL_B;
1224 uint32_t CM_DGAM_RAMA_START_CNTL_G;
1225 uint32_t CM_DGAM_RAMA_START_CNTL_R;
1226 uint32_t CM_DGAM_RAMA_SLOPE_CNTL_B;
1227 uint32_t CM_DGAM_RAMA_SLOPE_CNTL_G;
1228 uint32_t CM_DGAM_RAMA_SLOPE_CNTL_R;
1229 uint32_t CM_DGAM_RAMA_END_CNTL1_B;
1230 uint32_t CM_DGAM_RAMA_END_CNTL2_B;
1231 uint32_t CM_DGAM_RAMA_END_CNTL1_G;
1232 uint32_t CM_DGAM_RAMA_END_CNTL2_G;
1233 uint32_t CM_DGAM_RAMA_END_CNTL1_R;
1234 uint32_t CM_DGAM_RAMA_END_CNTL2_R;
1235 uint32_t CM_DGAM_RAMA_REGION_0_1;
1236 uint32_t CM_DGAM_RAMA_REGION_14_15;
1237 uint32_t CM_DGAM_LUT_WRITE_EN_MASK;
1238 uint32_t CM_DGAM_LUT_INDEX;
1239 uint32_t CM_DGAM_LUT_DATA;
1240 uint32_t CM_CONTROL;
1241 uint32_t CM_DGAM_CONTROL;
1242 uint32_t CM_IGAM_CONTROL;
1243 uint32_t CM_IGAM_LUT_RW_CONTROL;
1244 uint32_t CM_IGAM_LUT_RW_INDEX;
1245 uint32_t CM_IGAM_LUT_SEQ_COLOR;
1246 uint32_t FORMAT_CONTROL;
1247 uint32_t CNVC_SURFACE_PIXEL_FORMAT;
1248 uint32_t CURSOR_CONTROL;
1249 uint32_t CURSOR0_CONTROL;
1250 uint32_t CURSOR0_COLOR0;
1251 uint32_t CURSOR0_COLOR1;
1257 const struct dcn_dpp_registers *tf_regs;
1258 const struct dcn_dpp_shift *tf_shift;
1259 const struct dcn_dpp_mask *tf_mask;
1261 const uint16_t *filter_v;
1262 const uint16_t *filter_h;
1263 const uint16_t *filter_v_c;
1264 const uint16_t *filter_h_c;
1265 int lb_pixel_depth_supported;
1267 int lb_bits_per_entry;
1268 bool is_write_to_ram_a_safe;
1271 enum dcn10_input_csc_select {
1272 INPUT_CSC_SELECT_BYPASS = 0,
1273 INPUT_CSC_SELECT_ICSC,
1274 INPUT_CSC_SELECT_COMA
1277 bool dpp1_dscl_is_lb_conf_valid(
1282 void dpp1_dscl_calc_lb_num_partitions(
1283 const struct scaler_data *scl_data,
1284 enum lb_memory_config lb_config,
1288 void dpp1_degamma_ram_select(
1289 struct dpp *dpp_base,
1292 void dpp1_program_degamma_luta_settings(
1293 struct dpp *dpp_base,
1294 const struct pwl_params *params);
1296 void dpp1_program_degamma_lutb_settings(
1297 struct dpp *dpp_base,
1298 const struct pwl_params *params);
1300 void dpp1_program_degamma_lut(
1301 struct dpp *dpp_base,
1302 const struct pwl_result_data *rgb,
1306 void dpp1_power_on_degamma_lut(
1307 struct dpp *dpp_base,
1310 void dpp1_program_input_csc(
1311 struct dpp *dpp_base,
1312 enum dc_color_space color_space,
1313 enum dcn10_input_csc_select select);
1315 void dpp1_program_input_lut(
1316 struct dpp *dpp_base,
1317 const struct dc_gamma *gamma);
1319 void dpp1_full_bypass(struct dpp *dpp_base);
1321 void dpp1_set_degamma(
1322 struct dpp *dpp_base,
1323 enum ipp_degamma_mode mode);
1325 void dpp1_set_degamma_pwl(struct dpp *dpp_base,
1326 const struct pwl_params *params);
1328 bool dpp_get_optimal_number_of_taps(
1330 struct scaler_data *scl_data,
1331 const struct scaling_taps *in_taps);
1333 void dpp_reset(struct dpp *dpp_base);
1335 void dpp1_cm_program_regamma_lut(
1336 struct dpp *dpp_base,
1337 const struct pwl_result_data *rgb,
1340 void dpp1_cm_power_on_regamma_lut(
1341 struct dpp *dpp_base,
1344 void dpp1_cm_configure_regamma_lut(
1345 struct dpp *dpp_base,
1348 /*program re gamma RAM A*/
1349 void dpp1_cm_program_regamma_luta_settings(
1350 struct dpp *dpp_base,
1351 const struct pwl_params *params);
1353 /*program re gamma RAM B*/
1354 void dpp1_cm_program_regamma_lutb_settings(
1355 struct dpp *dpp_base,
1356 const struct pwl_params *params);
1357 void dpp1_cm_set_output_csc_adjustment(
1358 struct dpp *dpp_base,
1359 const struct out_csc_color_matrix *tbl_entry);
1361 void dpp1_cm_set_output_csc_default(
1362 struct dpp *dpp_base,
1363 enum dc_color_space colorspace);
1365 void dpp1_cm_set_gamut_remap(
1367 const struct dpp_grph_csc_adjustment *adjust);
1369 void dpp1_dscl_set_scaler_manual_scale(
1370 struct dpp *dpp_base,
1371 const struct scaler_data *scl_data);
1373 void dpp1_cnv_setup (
1374 struct dpp *dpp_base,
1375 enum surface_pixel_format input_format,
1376 enum expansion_mode mode);
1378 void dpp1_full_bypass(struct dpp *dpp_base);
1380 void dpp1_construct(struct dcn10_dpp *dpp1,
1381 struct dc_context *ctx,
1383 const struct dcn_dpp_registers *tf_regs,
1384 const struct dcn_dpp_shift *tf_shift,
1385 const struct dcn_dpp_mask *tf_mask);
git.samba.org / sfrench / cifs-2.6.git / blob