drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dce/dce_8_0_d.h"
  27 #include "dce/dce_8_0_sh_mask.h"
  28
  29 #include "dm_services.h"
  30
  31 #include "link_encoder.h"
  32 #include "stream_encoder.h"
  33
  34 #include "resource.h"
  35 #include "include/irq_service_interface.h"
  36 #include "irq/dce80/irq_service_dce80.h"
  37 #include "dce110/dce110_timing_generator.h"
  38 #include "dce110/dce110_resource.h"
  39 #include "dce80/dce80_timing_generator.h"
  40 #include "dce/dce_clk_mgr.h"
  41 #include "dce/dce_mem_input.h"
  42 #include "dce/dce_link_encoder.h"
  43 #include "dce/dce_stream_encoder.h"
  44 #include "dce/dce_ipp.h"
  45 #include "dce/dce_transform.h"
  46 #include "dce/dce_opp.h"
  47 #include "dce/dce_clock_source.h"
  48 #include "dce/dce_audio.h"
  49 #include "dce/dce_hwseq.h"
  50 #include "dce80/dce80_hw_sequencer.h"
  51 #include "dce100/dce100_resource.h"
  52
  53 #include "reg_helper.h"
  54
  55 #include "dce/dce_dmcu.h"
  56 #include "dce/dce_aux.h"
  57 #include "dce/dce_abm.h"
  58 #include "dce/dce_i2c.h"
  59 /* TODO remove this include */
  60
  61 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
  62 #include "gmc/gmc_7_1_d.h"
  63 #include "gmc/gmc_7_1_sh_mask.h"
  64 #endif
  65
  66 #ifndef mmDP_DPHY_INTERNAL_CTRL
  67 #define mmDP_DPHY_INTERNAL_CTRL                         0x1CDE
  68 #define mmDP0_DP_DPHY_INTERNAL_CTRL                     0x1CDE
  69 #define mmDP1_DP_DPHY_INTERNAL_CTRL                     0x1FDE
  70 #define mmDP2_DP_DPHY_INTERNAL_CTRL                     0x42DE
  71 #define mmDP3_DP_DPHY_INTERNAL_CTRL                     0x45DE
  72 #define mmDP4_DP_DPHY_INTERNAL_CTRL                     0x48DE
  73 #define mmDP5_DP_DPHY_INTERNAL_CTRL                     0x4BDE
  74 #define mmDP6_DP_DPHY_INTERNAL_CTRL                     0x4EDE
  75 #endif
  76
  77
  78 #ifndef mmBIOS_SCRATCH_2
  79         #define mmBIOS_SCRATCH_2 0x05CB
  80         #define mmBIOS_SCRATCH_3 0x05CC
  81         #define mmBIOS_SCRATCH_6 0x05CF
  82 #endif
  83
  84 #ifndef mmDP_DPHY_FAST_TRAINING
  85         #define mmDP_DPHY_FAST_TRAINING                         0x1CCE
  86         #define mmDP0_DP_DPHY_FAST_TRAINING                     0x1CCE
  87         #define mmDP1_DP_DPHY_FAST_TRAINING                     0x1FCE
  88         #define mmDP2_DP_DPHY_FAST_TRAINING                     0x42CE
  89         #define mmDP3_DP_DPHY_FAST_TRAINING                     0x45CE
  90         #define mmDP4_DP_DPHY_FAST_TRAINING                     0x48CE
  91         #define mmDP5_DP_DPHY_FAST_TRAINING                     0x4BCE
  92         #define mmDP6_DP_DPHY_FAST_TRAINING                     0x4ECE
  93 #endif
  94
  95
  96 #ifndef mmHPD_DC_HPD_CONTROL
  97         #define mmHPD_DC_HPD_CONTROL                            0x189A
  98         #define mmHPD0_DC_HPD_CONTROL                           0x189A
  99         #define mmHPD1_DC_HPD_CONTROL                           0x18A2
 100         #define mmHPD2_DC_HPD_CONTROL                           0x18AA
 101         #define mmHPD3_DC_HPD_CONTROL                           0x18B2
 102         #define mmHPD4_DC_HPD_CONTROL                           0x18BA
 103         #define mmHPD5_DC_HPD_CONTROL                           0x18C2
 104 #endif
 105
 106 #define DCE11_DIG_FE_CNTL 0x4a00
 107 #define DCE11_DIG_BE_CNTL 0x4a47
 108 #define DCE11_DP_SEC 0x4ac3
 109
 110 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = {
 111                 {
 112                         .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
 113                         .dcp =  (mmGRPH_CONTROL - mmGRPH_CONTROL),
 114                         .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
 115                                         - mmDPG_WATERMARK_MASK_CONTROL),
 116                 },
 117                 {
 118                         .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
 119                         .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
 120                         .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
 121                                         - mmDPG_WATERMARK_MASK_CONTROL),
 122                 },
 123                 {
 124                         .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
 125                         .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
 126                         .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
 127                                         - mmDPG_WATERMARK_MASK_CONTROL),
 128                 },
 129                 {
 130                         .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
 131                         .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
 132                         .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
 133                                         - mmDPG_WATERMARK_MASK_CONTROL),
 134                 },
 135                 {
 136                         .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
 137                         .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
 138                         .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
 139                                         - mmDPG_WATERMARK_MASK_CONTROL),
 140                 },
 141                 {
 142                         .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
 143                         .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
 144                         .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
 145                                         - mmDPG_WATERMARK_MASK_CONTROL),
 146                 }
 147 };
 148
 149 /* set register offset */
 150 #define SR(reg_name)\
 151         .reg_name = mm ## reg_name
 152
 153 /* set register offset with instance */
 154 #define SRI(reg_name, block, id)\
 155         .reg_name = mm ## block ## id ## _ ## reg_name
 156
 157
 158 static const struct clk_mgr_registers disp_clk_regs = {
 159                 CLK_COMMON_REG_LIST_DCE_BASE()
 160 };
 161
 162 static const struct clk_mgr_shift disp_clk_shift = {
 163                 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 164 };
 165
 166 static const struct clk_mgr_mask disp_clk_mask = {
 167                 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 168 };
 169
 170 #define ipp_regs(id)\
 171 [id] = {\
 172                 IPP_COMMON_REG_LIST_DCE_BASE(id)\
 173 }
 174
 175 static const struct dce_ipp_registers ipp_regs[] = {
 176                 ipp_regs(0),
 177                 ipp_regs(1),
 178                 ipp_regs(2),
 179                 ipp_regs(3),
 180                 ipp_regs(4),
 181                 ipp_regs(5)
 182 };
 183
 184 static const struct dce_ipp_shift ipp_shift = {
 185                 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 186 };
 187
 188 static const struct dce_ipp_mask ipp_mask = {
 189                 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 190 };
 191
 192 #define transform_regs(id)\
 193 [id] = {\
 194                 XFM_COMMON_REG_LIST_DCE80(id)\
 195 }
 196
 197 static const struct dce_transform_registers xfm_regs[] = {
 198                 transform_regs(0),
 199                 transform_regs(1),
 200                 transform_regs(2),
 201                 transform_regs(3),
 202                 transform_regs(4),
 203                 transform_regs(5)
 204 };
 205
 206 static const struct dce_transform_shift xfm_shift = {
 207                 XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT)
 208 };
 209
 210 static const struct dce_transform_mask xfm_mask = {
 211                 XFM_COMMON_MASK_SH_LIST_DCE80(_MASK)
 212 };
 213
 214 #define aux_regs(id)\
 215 [id] = {\
 216         AUX_REG_LIST(id)\
 217 }
 218
 219 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
 220         aux_regs(0),
 221         aux_regs(1),
 222         aux_regs(2),
 223         aux_regs(3),
 224         aux_regs(4),
 225         aux_regs(5)
 226 };
 227
 228 #define hpd_regs(id)\
 229 [id] = {\
 230         HPD_REG_LIST(id)\
 231 }
 232
 233 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
 234                 hpd_regs(0),
 235                 hpd_regs(1),
 236                 hpd_regs(2),
 237                 hpd_regs(3),
 238                 hpd_regs(4),
 239                 hpd_regs(5)
 240 };
 241
 242 #define link_regs(id)\
 243 [id] = {\
 244         LE_DCE80_REG_LIST(id)\
 245 }
 246
 247 static const struct dce110_link_enc_registers link_enc_regs[] = {
 248         link_regs(0),
 249         link_regs(1),
 250         link_regs(2),
 251         link_regs(3),
 252         link_regs(4),
 253         link_regs(5),
 254         link_regs(6),
 255 };
 256
 257 #define stream_enc_regs(id)\
 258 [id] = {\
 259         SE_COMMON_REG_LIST_DCE_BASE(id),\
 260         .AFMT_CNTL = 0,\
 261 }
 262
 263 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
 264         stream_enc_regs(0),
 265         stream_enc_regs(1),
 266         stream_enc_regs(2),
 267         stream_enc_regs(3),
 268         stream_enc_regs(4),
 269         stream_enc_regs(5),
 270         stream_enc_regs(6)
 271 };
 272
 273 static const struct dce_stream_encoder_shift se_shift = {
 274                 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
 275 };
 276
 277 static const struct dce_stream_encoder_mask se_mask = {
 278                 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
 279 };
 280
 281 #define opp_regs(id)\
 282 [id] = {\
 283         OPP_DCE_80_REG_LIST(id),\
 284 }
 285
 286 static const struct dce_opp_registers opp_regs[] = {
 287         opp_regs(0),
 288         opp_regs(1),
 289         opp_regs(2),
 290         opp_regs(3),
 291         opp_regs(4),
 292         opp_regs(5)
 293 };
 294
 295 static const struct dce_opp_shift opp_shift = {
 296         OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT)
 297 };
 298
 299 static const struct dce_opp_mask opp_mask = {
 300         OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK)
 301 };
 302
 303 #define aux_engine_regs(id)\
 304 [id] = {\
 305         AUX_COMMON_REG_LIST(id), \
 306         .AUX_RESET_MASK = 0 \
 307 }
 308
 309 static const struct dce110_aux_registers aux_engine_regs[] = {
 310                 aux_engine_regs(0),
 311                 aux_engine_regs(1),
 312                 aux_engine_regs(2),
 313                 aux_engine_regs(3),
 314                 aux_engine_regs(4),
 315                 aux_engine_regs(5)
 316 };
 317
 318 #define audio_regs(id)\
 319 [id] = {\
 320         AUD_COMMON_REG_LIST(id)\
 321 }
 322
 323 static const struct dce_audio_registers audio_regs[] = {
 324         audio_regs(0),
 325         audio_regs(1),
 326         audio_regs(2),
 327         audio_regs(3),
 328         audio_regs(4),
 329         audio_regs(5),
 330         audio_regs(6),
 331 };
 332
 333 static const struct dce_audio_shift audio_shift = {
 334                 AUD_COMMON_MASK_SH_LIST(__SHIFT)
 335 };
 336
 337 static const struct dce_aduio_mask audio_mask = {
 338                 AUD_COMMON_MASK_SH_LIST(_MASK)
 339 };
 340
 341 #define clk_src_regs(id)\
 342 [id] = {\
 343         CS_COMMON_REG_LIST_DCE_80(id),\
 344 }
 345
 346
 347 static const struct dce110_clk_src_regs clk_src_regs[] = {
 348         clk_src_regs(0),
 349         clk_src_regs(1),
 350         clk_src_regs(2)
 351 };
 352
 353 static const struct dce110_clk_src_shift cs_shift = {
 354                 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 355 };
 356
 357 static const struct dce110_clk_src_mask cs_mask = {
 358                 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 359 };
 360
 361 static const struct bios_registers bios_regs = {
 362         .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
 363         .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
 364 };
 365
 366 static const struct resource_caps res_cap = {
 367                 .num_timing_generator = 6,
 368                 .num_audio = 6,
 369                 .num_stream_encoder = 6,
 370                 .num_pll = 3,
 371                 .num_ddc = 6,
 372 };
 373
 374 static const struct resource_caps res_cap_81 = {
 375                 .num_timing_generator = 4,
 376                 .num_audio = 7,
 377                 .num_stream_encoder = 7,
 378                 .num_pll = 3,
 379                 .num_ddc = 6,
 380 };
 381
 382 static const struct resource_caps res_cap_83 = {
 383                 .num_timing_generator = 2,
 384                 .num_audio = 6,
 385                 .num_stream_encoder = 6,
 386                 .num_pll = 2,
 387                 .num_ddc = 2,
 388 };
 389
 390 static const struct dce_dmcu_registers dmcu_regs = {
 391                 DMCU_DCE80_REG_LIST()
 392 };
 393
 394 static const struct dce_dmcu_shift dmcu_shift = {
 395                 DMCU_MASK_SH_LIST_DCE80(__SHIFT)
 396 };
 397
 398 static const struct dce_dmcu_mask dmcu_mask = {
 399                 DMCU_MASK_SH_LIST_DCE80(_MASK)
 400 };
 401 static const struct dce_abm_registers abm_regs = {
 402                 ABM_DCE110_COMMON_REG_LIST()
 403 };
 404
 405 static const struct dce_abm_shift abm_shift = {
 406                 ABM_MASK_SH_LIST_DCE110(__SHIFT)
 407 };
 408
 409 static const struct dce_abm_mask abm_mask = {
 410                 ABM_MASK_SH_LIST_DCE110(_MASK)
 411 };
 412
 413 #define CTX  ctx
 414 #define REG(reg) mm ## reg
 415
 416 #ifndef mmCC_DC_HDMI_STRAPS
 417 #define mmCC_DC_HDMI_STRAPS 0x1918
 418 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
 419 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
 420 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
 421 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
 422 #endif
 423
 424 static void read_dce_straps(
 425         struct dc_context *ctx,
 426         struct resource_straps *straps)
 427 {
 428         REG_GET_2(CC_DC_HDMI_STRAPS,
 429                         HDMI_DISABLE, &straps->hdmi_disable,
 430                         AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
 431
 432         REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
 433 }
 434
 435 static struct audio *create_audio(
 436                 struct dc_context *ctx, unsigned int inst)
 437 {
 438         return dce_audio_create(ctx, inst,
 439                         &audio_regs[inst], &audio_shift, &audio_mask);
 440 }
 441
 442 static struct timing_generator *dce80_timing_generator_create(
 443                 struct dc_context *ctx,
 444                 uint32_t instance,
 445                 const struct dce110_timing_generator_offsets *offsets)
 446 {
 447         struct dce110_timing_generator *tg110 =
 448                 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
 449
 450         if (!tg110)
 451                 return NULL;
 452
 453         dce80_timing_generator_construct(tg110, ctx, instance, offsets);
 454         return &tg110->base;
 455 }
 456
 457 static struct output_pixel_processor *dce80_opp_create(
 458         struct dc_context *ctx,
 459         uint32_t inst)
 460 {
 461         struct dce110_opp *opp =
 462                 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
 463
 464         if (!opp)
 465                 return NULL;
 466
 467         dce110_opp_construct(opp,
 468                              ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
 469         return &opp->base;
 470 }
 471
 472 struct dce_aux *dce80_aux_engine_create(
 473         struct dc_context *ctx,
 474         uint32_t inst)
 475 {
 476         struct aux_engine_dce110 *aux_engine =
 477                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 478
 479         if (!aux_engine)
 480                 return NULL;
 481
 482         dce110_aux_engine_construct(aux_engine, ctx, inst,
 483                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 484                                     &aux_engine_regs[inst]);
 485
 486         return &aux_engine->base;
 487 }
 488 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 489
 490 static const struct dce_i2c_registers i2c_hw_regs[] = {
 491                 i2c_inst_regs(1),
 492                 i2c_inst_regs(2),
 493                 i2c_inst_regs(3),
 494                 i2c_inst_regs(4),
 495                 i2c_inst_regs(5),
 496                 i2c_inst_regs(6),
 497 };
 498
 499 static const struct dce_i2c_shift i2c_shifts = {
 500                 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 501 };
 502
 503 static const struct dce_i2c_mask i2c_masks = {
 504                 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 505 };
 506
 507 struct dce_i2c_hw *dce80_i2c_hw_create(
 508         struct dc_context *ctx,
 509         uint32_t inst)
 510 {
 511         struct dce_i2c_hw *dce_i2c_hw =
 512                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 513
 514         if (!dce_i2c_hw)
 515                 return NULL;
 516
 517         dce_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 518                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 519
 520         return dce_i2c_hw;
 521 }
 522
 523 struct dce_i2c_sw *dce80_i2c_sw_create(
 524         struct dc_context *ctx)
 525 {
 526         struct dce_i2c_sw *dce_i2c_sw =
 527                 kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL);
 528
 529         if (!dce_i2c_sw)
 530                 return NULL;
 531
 532         dce_i2c_sw_construct(dce_i2c_sw, ctx);
 533
 534         return dce_i2c_sw;
 535 }
 536 static struct stream_encoder *dce80_stream_encoder_create(
 537         enum engine_id eng_id,
 538         struct dc_context *ctx)
 539 {
 540         struct dce110_stream_encoder *enc110 =
 541                 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
 542
 543         if (!enc110)
 544                 return NULL;
 545
 546         dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
 547                                         &stream_enc_regs[eng_id],
 548                                         &se_shift, &se_mask);
 549         return &enc110->base;
 550 }
 551
 552 #define SRII(reg_name, block, id)\
 553         .reg_name[id] = mm ## block ## id ## _ ## reg_name
 554
 555 static const struct dce_hwseq_registers hwseq_reg = {
 556                 HWSEQ_DCE8_REG_LIST()
 557 };
 558
 559 static const struct dce_hwseq_shift hwseq_shift = {
 560                 HWSEQ_DCE8_MASK_SH_LIST(__SHIFT)
 561 };
 562
 563 static const struct dce_hwseq_mask hwseq_mask = {
 564                 HWSEQ_DCE8_MASK_SH_LIST(_MASK)
 565 };
 566
 567 static struct dce_hwseq *dce80_hwseq_create(
 568         struct dc_context *ctx)
 569 {
 570         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
 571
 572         if (hws) {
 573                 hws->ctx = ctx;
 574                 hws->regs = &hwseq_reg;
 575                 hws->shifts = &hwseq_shift;
 576                 hws->masks = &hwseq_mask;
 577         }
 578         return hws;
 579 }
 580
 581 static const struct resource_create_funcs res_create_funcs = {
 582         .read_dce_straps = read_dce_straps,
 583         .create_audio = create_audio,
 584         .create_stream_encoder = dce80_stream_encoder_create,
 585         .create_hwseq = dce80_hwseq_create,
 586 };
 587
 588 #define mi_inst_regs(id) { \
 589         MI_DCE8_REG_LIST(id), \
 590         .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
 591 }
 592 static const struct dce_mem_input_registers mi_regs[] = {
 593                 mi_inst_regs(0),
 594                 mi_inst_regs(1),
 595                 mi_inst_regs(2),
 596                 mi_inst_regs(3),
 597                 mi_inst_regs(4),
 598                 mi_inst_regs(5),
 599 };
 600
 601 static const struct dce_mem_input_shift mi_shifts = {
 602                 MI_DCE8_MASK_SH_LIST(__SHIFT),
 603                 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
 604 };
 605
 606 static const struct dce_mem_input_mask mi_masks = {
 607                 MI_DCE8_MASK_SH_LIST(_MASK),
 608                 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
 609 };
 610
 611 static struct mem_input *dce80_mem_input_create(
 612         struct dc_context *ctx,
 613         uint32_t inst)
 614 {
 615         struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
 616                                                GFP_KERNEL);
 617
 618         if (!dce_mi) {
 619                 BREAK_TO_DEBUGGER();
 620                 return NULL;
 621         }
 622
 623         dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
 624         dce_mi->wa.single_head_rdreq_dmif_limit = 2;
 625         return &dce_mi->base;
 626 }
 627
 628 static void dce80_transform_destroy(struct transform **xfm)
 629 {
 630         kfree(TO_DCE_TRANSFORM(*xfm));
 631         *xfm = NULL;
 632 }
 633
 634 static struct transform *dce80_transform_create(
 635         struct dc_context *ctx,
 636         uint32_t inst)
 637 {
 638         struct dce_transform *transform =
 639                 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
 640
 641         if (!transform)
 642                 return NULL;
 643
 644         dce_transform_construct(transform, ctx, inst,
 645                                 &xfm_regs[inst], &xfm_shift, &xfm_mask);
 646         transform->prescaler_on = false;
 647         return &transform->base;
 648 }
 649
 650 static const struct encoder_feature_support link_enc_feature = {
 651                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
 652                 .max_hdmi_pixel_clock = 297000,
 653                 .flags.bits.IS_HBR2_CAPABLE = true,
 654                 .flags.bits.IS_TPS3_CAPABLE = true
 655 };
 656
 657 struct link_encoder *dce80_link_encoder_create(
 658         const struct encoder_init_data *enc_init_data)
 659 {
 660         struct dce110_link_encoder *enc110 =
 661                 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
 662
 663         if (!enc110)
 664                 return NULL;
 665
 666         dce110_link_encoder_construct(enc110,
 667                                       enc_init_data,
 668                                       &link_enc_feature,
 669                                       &link_enc_regs[enc_init_data->transmitter],
 670                                       &link_enc_aux_regs[enc_init_data->channel - 1],
 671                                       &link_enc_hpd_regs[enc_init_data->hpd_source]);
 672         return &enc110->base;
 673 }
 674
 675 struct clock_source *dce80_clock_source_create(
 676         struct dc_context *ctx,
 677         struct dc_bios *bios,
 678         enum clock_source_id id,
 679         const struct dce110_clk_src_regs *regs,
 680         bool dp_clk_src)
 681 {
 682         struct dce110_clk_src *clk_src =
 683                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 684
 685         if (!clk_src)
 686                 return NULL;
 687
 688         if (dce110_clk_src_construct(clk_src, ctx, bios, id,
 689                         regs, &cs_shift, &cs_mask)) {
 690                 clk_src->base.dp_clk_src = dp_clk_src;
 691                 return &clk_src->base;
 692         }
 693
 694         BREAK_TO_DEBUGGER();
 695         return NULL;
 696 }
 697
 698 void dce80_clock_source_destroy(struct clock_source **clk_src)
 699 {
 700         kfree(TO_DCE110_CLK_SRC(*clk_src));
 701         *clk_src = NULL;
 702 }
 703
 704 static struct input_pixel_processor *dce80_ipp_create(
 705         struct dc_context *ctx, uint32_t inst)
 706 {
 707         struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
 708
 709         if (!ipp) {
 710                 BREAK_TO_DEBUGGER();
 711                 return NULL;
 712         }
 713
 714         dce_ipp_construct(ipp, ctx, inst,
 715                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 716         return &ipp->base;
 717 }
 718
 719 static void destruct(struct dce110_resource_pool *pool)
 720 {
 721         unsigned int i;
 722
 723         for (i = 0; i < pool->base.pipe_count; i++) {
 724                 if (pool->base.opps[i] != NULL)
 725                         dce110_opp_destroy(&pool->base.opps[i]);
 726
 727                 if (pool->base.transforms[i] != NULL)
 728                         dce80_transform_destroy(&pool->base.transforms[i]);
 729
 730                 if (pool->base.ipps[i] != NULL)
 731                         dce_ipp_destroy(&pool->base.ipps[i]);
 732
 733                 if (pool->base.mis[i] != NULL) {
 734                         kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
 735                         pool->base.mis[i] = NULL;
 736                 }
 737
 738                 if (pool->base.timing_generators[i] != NULL)    {
 739                         kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
 740                         pool->base.timing_generators[i] = NULL;
 741                 }
 742         }
 743
 744         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
 745                 if (pool->base.engines[i] != NULL)
 746                         dce110_engine_destroy(&pool->base.engines[i]);
 747                 if (pool->base.hw_i2cs[i] != NULL) {
 748                         kfree(pool->base.hw_i2cs[i]);
 749                         pool->base.hw_i2cs[i] = NULL;
 750                 }
 751                 if (pool->base.sw_i2cs[i] != NULL) {
 752                         kfree(pool->base.sw_i2cs[i]);
 753                         pool->base.sw_i2cs[i] = NULL;
 754                 }
 755         }
 756
 757         for (i = 0; i < pool->base.stream_enc_count; i++) {
 758                 if (pool->base.stream_enc[i] != NULL)
 759                         kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 760         }
 761
 762         for (i = 0; i < pool->base.clk_src_count; i++) {
 763                 if (pool->base.clock_sources[i] != NULL) {
 764                         dce80_clock_source_destroy(&pool->base.clock_sources[i]);
 765                 }
 766         }
 767
 768         if (pool->base.abm != NULL)
 769                         dce_abm_destroy(&pool->base.abm);
 770
 771         if (pool->base.dmcu != NULL)
 772                         dce_dmcu_destroy(&pool->base.dmcu);
 773
 774         if (pool->base.dp_clock_source != NULL)
 775                 dce80_clock_source_destroy(&pool->base.dp_clock_source);
 776
 777         for (i = 0; i < pool->base.audio_count; i++)    {
 778                 if (pool->base.audios[i] != NULL) {
 779                         dce_aud_destroy(&pool->base.audios[i]);
 780                 }
 781         }
 782
 783         if (pool->base.clk_mgr != NULL)
 784                 dce_clk_mgr_destroy(&pool->base.clk_mgr);
 785
 786         if (pool->base.irqs != NULL) {
 787                 dal_irq_service_destroy(&pool->base.irqs);
 788         }
 789 }
 790
 791 bool dce80_validate_bandwidth(
 792         struct dc *dc,
 793         struct dc_state *context)
 794 {
 795         int i;
 796         bool at_least_one_pipe = false;
 797
 798         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 799                 if (context->res_ctx.pipe_ctx[i].stream)
 800                         at_least_one_pipe = true;
 801         }
 802
 803         if (at_least_one_pipe) {
 804                 /* TODO implement when needed but for now hardcode max value*/
 805                 context->bw.dce.dispclk_khz = 681000;
 806                 context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
 807         } else {
 808                 context->bw.dce.dispclk_khz = 0;
 809                 context->bw.dce.yclk_khz = 0;
 810         }
 811
 812         return true;
 813 }
 814
 815 static bool dce80_validate_surface_sets(
 816                 struct dc_state *context)
 817 {
 818         int i;
 819
 820         for (i = 0; i < context->stream_count; i++) {
 821                 if (context->stream_status[i].plane_count == 0)
 822                         continue;
 823
 824                 if (context->stream_status[i].plane_count > 1)
 825                         return false;
 826
 827                 if (context->stream_status[i].plane_states[0]->format
 828                                 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
 829                         return false;
 830         }
 831
 832         return true;
 833 }
 834
 835 enum dc_status dce80_validate_global(
 836                 struct dc *dc,
 837                 struct dc_state *context)
 838 {
 839         if (!dce80_validate_surface_sets(context))
 840                 return DC_FAIL_SURFACE_VALIDATE;
 841
 842         return DC_OK;
 843 }
 844
 845 static void dce80_destroy_resource_pool(struct resource_pool **pool)
 846 {
 847         struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
 848
 849         destruct(dce110_pool);
 850         kfree(dce110_pool);
 851         *pool = NULL;
 852 }
 853
 854 static const struct resource_funcs dce80_res_pool_funcs = {
 855         .destroy = dce80_destroy_resource_pool,
 856         .link_enc_create = dce80_link_encoder_create,
 857         .validate_bandwidth = dce80_validate_bandwidth,
 858         .validate_plane = dce100_validate_plane,
 859         .add_stream_to_ctx = dce100_add_stream_to_ctx,
 860         .validate_global = dce80_validate_global
 861 };
 862
 863 static bool dce80_construct(
 864         uint8_t num_virtual_links,
 865         struct dc *dc,
 866         struct dce110_resource_pool *pool)
 867 {
 868         unsigned int i;
 869         struct dc_context *ctx = dc->ctx;
 870         struct dc_firmware_info info;
 871         struct dc_bios *bp;
 872
 873         ctx->dc_bios->regs = &bios_regs;
 874
 875         pool->base.res_cap = &res_cap;
 876         pool->base.funcs = &dce80_res_pool_funcs;
 877
 878
 879         /*************************************************
 880          *  Resource + asic cap harcoding                *
 881          *************************************************/
 882         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
 883         pool->base.pipe_count = res_cap.num_timing_generator;
 884         pool->base.timing_generator_count = res_cap.num_timing_generator;
 885         dc->caps.max_downscale_ratio = 200;
 886         dc->caps.i2c_speed_in_khz = 40;
 887         dc->caps.max_cursor_size = 128;
 888         dc->caps.dual_link_dvi = true;
 889
 890         /*************************************************
 891          *  Create resources                             *
 892          *************************************************/
 893
 894         bp = ctx->dc_bios;
 895
 896         if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
 897                 info.external_clock_source_frequency_for_dp != 0) {
 898                 pool->base.dp_clock_source =
 899                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
 900
 901                 pool->base.clock_sources[0] =
 902                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
 903                 pool->base.clock_sources[1] =
 904                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
 905                 pool->base.clock_sources[2] =
 906                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
 907                 pool->base.clk_src_count = 3;
 908
 909         } else {
 910                 pool->base.dp_clock_source =
 911                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
 912
 913                 pool->base.clock_sources[0] =
 914                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
 915                 pool->base.clock_sources[1] =
 916                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
 917                 pool->base.clk_src_count = 2;
 918         }
 919
 920         if (pool->base.dp_clock_source == NULL) {
 921                 dm_error("DC: failed to create dp clock source!\n");
 922                 BREAK_TO_DEBUGGER();
 923                 goto res_create_fail;
 924         }
 925
 926         for (i = 0; i < pool->base.clk_src_count; i++) {
 927                 if (pool->base.clock_sources[i] == NULL) {
 928                         dm_error("DC: failed to create clock sources!\n");
 929                         BREAK_TO_DEBUGGER();
 930                         goto res_create_fail;
 931                 }
 932         }
 933
 934         pool->base.clk_mgr = dce_clk_mgr_create(ctx,
 935                         &disp_clk_regs,
 936                         &disp_clk_shift,
 937                         &disp_clk_mask);
 938         if (pool->base.clk_mgr == NULL) {
 939                 dm_error("DC: failed to create display clock!\n");
 940                 BREAK_TO_DEBUGGER();
 941                 goto res_create_fail;
 942         }
 943
 944         pool->base.dmcu = dce_dmcu_create(ctx,
 945                         &dmcu_regs,
 946                         &dmcu_shift,
 947                         &dmcu_mask);
 948         if (pool->base.dmcu == NULL) {
 949                 dm_error("DC: failed to create dmcu!\n");
 950                 BREAK_TO_DEBUGGER();
 951                 goto res_create_fail;
 952         }
 953
 954         pool->base.abm = dce_abm_create(ctx,
 955                         &abm_regs,
 956                         &abm_shift,
 957                         &abm_mask);
 958         if (pool->base.abm == NULL) {
 959                 dm_error("DC: failed to create abm!\n");
 960                 BREAK_TO_DEBUGGER();
 961                 goto res_create_fail;
 962         }
 963
 964         {
 965                 struct irq_service_init_data init_data;
 966                 init_data.ctx = dc->ctx;
 967                 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
 968                 if (!pool->base.irqs)
 969                         goto res_create_fail;
 970         }
 971
 972         for (i = 0; i < pool->base.pipe_count; i++) {
 973                 pool->base.timing_generators[i] = dce80_timing_generator_create(
 974                                 ctx, i, &dce80_tg_offsets[i]);
 975                 if (pool->base.timing_generators[i] == NULL) {
 976                         BREAK_TO_DEBUGGER();
 977                         dm_error("DC: failed to create tg!\n");
 978                         goto res_create_fail;
 979                 }
 980
 981                 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
 982                 if (pool->base.mis[i] == NULL) {
 983                         BREAK_TO_DEBUGGER();
 984                         dm_error("DC: failed to create memory input!\n");
 985                         goto res_create_fail;
 986                 }
 987
 988                 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
 989                 if (pool->base.ipps[i] == NULL) {
 990                         BREAK_TO_DEBUGGER();
 991                         dm_error("DC: failed to create input pixel processor!\n");
 992                         goto res_create_fail;
 993                 }
 994
 995                 pool->base.transforms[i] = dce80_transform_create(ctx, i);
 996                 if (pool->base.transforms[i] == NULL) {
 997                         BREAK_TO_DEBUGGER();
 998                         dm_error("DC: failed to create transform!\n");
 999                         goto res_create_fail;
1000                 }
1001
1002                 pool->base.opps[i] = dce80_opp_create(ctx, i);
1003                 if (pool->base.opps[i] == NULL) {
1004                         BREAK_TO_DEBUGGER();
1005                         dm_error("DC: failed to create output pixel processor!\n");
1006                         goto res_create_fail;
1007                 }
1008         }
1009
1010         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1011                 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1012                 if (pool->base.engines[i] == NULL) {
1013                         BREAK_TO_DEBUGGER();
1014                         dm_error(
1015                                 "DC:failed to create aux engine!!\n");
1016                         goto res_create_fail;
1017                 }
1018                 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1019                 if (pool->base.hw_i2cs[i] == NULL) {
1020                         BREAK_TO_DEBUGGER();
1021                         dm_error(
1022                                 "DC:failed to create i2c engine!!\n");
1023                         goto res_create_fail;
1024                 }
1025                 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1026                 if (pool->base.sw_i2cs[i] == NULL) {
1027                         BREAK_TO_DEBUGGER();
1028                         dm_error(
1029                                 "DC:failed to create sw i2c!!\n");
1030                         goto res_create_fail;
1031                 }
1032         }
1033
1034         dc->caps.max_planes =  pool->base.pipe_count;
1035         dc->caps.disable_dp_clk_share = true;
1036
1037         if (!resource_construct(num_virtual_links, dc, &pool->base,
1038                         &res_create_funcs))
1039                 goto res_create_fail;
1040
1041         /* Create hardware sequencer */
1042         dce80_hw_sequencer_construct(dc);
1043
1044         return true;
1045
1046 res_create_fail:
1047         destruct(pool);
1048         return false;
1049 }
1050
1051 struct resource_pool *dce80_create_resource_pool(
1052         uint8_t num_virtual_links,
1053         struct dc *dc)
1054 {
1055         struct dce110_resource_pool *pool =
1056                 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1057
1058         if (!pool)
1059                 return NULL;
1060
1061         if (dce80_construct(num_virtual_links, dc, pool))
1062                 return &pool->base;
1063
1064         BREAK_TO_DEBUGGER();
1065         return NULL;
1066 }
1067
1068 static bool dce81_construct(
1069         uint8_t num_virtual_links,
1070         struct dc *dc,
1071         struct dce110_resource_pool *pool)
1072 {
1073         unsigned int i;
1074         struct dc_context *ctx = dc->ctx;
1075         struct dc_firmware_info info;
1076         struct dc_bios *bp;
1077
1078         ctx->dc_bios->regs = &bios_regs;
1079
1080         pool->base.res_cap = &res_cap_81;
1081         pool->base.funcs = &dce80_res_pool_funcs;
1082
1083
1084         /*************************************************
1085          *  Resource + asic cap harcoding                *
1086          *************************************************/
1087         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1088         pool->base.pipe_count = res_cap_81.num_timing_generator;
1089         pool->base.timing_generator_count = res_cap_81.num_timing_generator;
1090         dc->caps.max_downscale_ratio = 200;
1091         dc->caps.i2c_speed_in_khz = 40;
1092         dc->caps.max_cursor_size = 128;
1093         dc->caps.is_apu = true;
1094
1095         /*************************************************
1096          *  Create resources                             *
1097          *************************************************/
1098
1099         bp = ctx->dc_bios;
1100
1101         if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
1102                 info.external_clock_source_frequency_for_dp != 0) {
1103                 pool->base.dp_clock_source =
1104                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1105
1106                 pool->base.clock_sources[0] =
1107                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
1108                 pool->base.clock_sources[1] =
1109                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1110                 pool->base.clock_sources[2] =
1111                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1112                 pool->base.clk_src_count = 3;
1113
1114         } else {
1115                 pool->base.dp_clock_source =
1116                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
1117
1118                 pool->base.clock_sources[0] =
1119                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1120                 pool->base.clock_sources[1] =
1121                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1122                 pool->base.clk_src_count = 2;
1123         }
1124
1125         if (pool->base.dp_clock_source == NULL) {
1126                 dm_error("DC: failed to create dp clock source!\n");
1127                 BREAK_TO_DEBUGGER();
1128                 goto res_create_fail;
1129         }
1130
1131         for (i = 0; i < pool->base.clk_src_count; i++) {
1132                 if (pool->base.clock_sources[i] == NULL) {
1133                         dm_error("DC: failed to create clock sources!\n");
1134                         BREAK_TO_DEBUGGER();
1135                         goto res_create_fail;
1136                 }
1137         }
1138
1139         pool->base.clk_mgr = dce_clk_mgr_create(ctx,
1140                         &disp_clk_regs,
1141                         &disp_clk_shift,
1142                         &disp_clk_mask);
1143         if (pool->base.clk_mgr == NULL) {
1144                 dm_error("DC: failed to create display clock!\n");
1145                 BREAK_TO_DEBUGGER();
1146                 goto res_create_fail;
1147         }
1148
1149         pool->base.dmcu = dce_dmcu_create(ctx,
1150                         &dmcu_regs,
1151                         &dmcu_shift,
1152                         &dmcu_mask);
1153         if (pool->base.dmcu == NULL) {
1154                 dm_error("DC: failed to create dmcu!\n");
1155                 BREAK_TO_DEBUGGER();
1156                 goto res_create_fail;
1157         }
1158
1159         pool->base.abm = dce_abm_create(ctx,
1160                         &abm_regs,
1161                         &abm_shift,
1162                         &abm_mask);
1163         if (pool->base.abm == NULL) {
1164                 dm_error("DC: failed to create abm!\n");
1165                 BREAK_TO_DEBUGGER();
1166                 goto res_create_fail;
1167         }
1168
1169         {
1170                 struct irq_service_init_data init_data;
1171                 init_data.ctx = dc->ctx;
1172                 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1173                 if (!pool->base.irqs)
1174                         goto res_create_fail;
1175         }
1176
1177         for (i = 0; i < pool->base.pipe_count; i++) {
1178                 pool->base.timing_generators[i] = dce80_timing_generator_create(
1179                                 ctx, i, &dce80_tg_offsets[i]);
1180                 if (pool->base.timing_generators[i] == NULL) {
1181                         BREAK_TO_DEBUGGER();
1182                         dm_error("DC: failed to create tg!\n");
1183                         goto res_create_fail;
1184                 }
1185
1186                 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1187                 if (pool->base.mis[i] == NULL) {
1188                         BREAK_TO_DEBUGGER();
1189                         dm_error("DC: failed to create memory input!\n");
1190                         goto res_create_fail;
1191                 }
1192
1193                 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1194                 if (pool->base.ipps[i] == NULL) {
1195                         BREAK_TO_DEBUGGER();
1196                         dm_error("DC: failed to create input pixel processor!\n");
1197                         goto res_create_fail;
1198                 }
1199
1200                 pool->base.transforms[i] = dce80_transform_create(ctx, i);
1201                 if (pool->base.transforms[i] == NULL) {
1202                         BREAK_TO_DEBUGGER();
1203                         dm_error("DC: failed to create transform!\n");
1204                         goto res_create_fail;
1205                 }
1206
1207                 pool->base.opps[i] = dce80_opp_create(ctx, i);
1208                 if (pool->base.opps[i] == NULL) {
1209                         BREAK_TO_DEBUGGER();
1210                         dm_error("DC: failed to create output pixel processor!\n");
1211                         goto res_create_fail;
1212                 }
1213         }
1214
1215         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1216                 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1217                 if (pool->base.engines[i] == NULL) {
1218                         BREAK_TO_DEBUGGER();
1219                         dm_error(
1220                                 "DC:failed to create aux engine!!\n");
1221                         goto res_create_fail;
1222                 }
1223                 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1224                 if (pool->base.hw_i2cs[i] == NULL) {
1225                         BREAK_TO_DEBUGGER();
1226                         dm_error(
1227                                 "DC:failed to create i2c engine!!\n");
1228                         goto res_create_fail;
1229                 }
1230                 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1231                 if (pool->base.sw_i2cs[i] == NULL) {
1232                         BREAK_TO_DEBUGGER();
1233                         dm_error(
1234                                 "DC:failed to create sw i2c!!\n");
1235                         goto res_create_fail;
1236                 }
1237         }
1238
1239         dc->caps.max_planes =  pool->base.pipe_count;
1240         dc->caps.disable_dp_clk_share = true;
1241
1242         if (!resource_construct(num_virtual_links, dc, &pool->base,
1243                         &res_create_funcs))
1244                 goto res_create_fail;
1245
1246         /* Create hardware sequencer */
1247         dce80_hw_sequencer_construct(dc);
1248
1249         return true;
1250
1251 res_create_fail:
1252         destruct(pool);
1253         return false;
1254 }
1255
1256 struct resource_pool *dce81_create_resource_pool(
1257         uint8_t num_virtual_links,
1258         struct dc *dc)
1259 {
1260         struct dce110_resource_pool *pool =
1261                 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1262
1263         if (!pool)
1264                 return NULL;
1265
1266         if (dce81_construct(num_virtual_links, dc, pool))
1267                 return &pool->base;
1268
1269         BREAK_TO_DEBUGGER();
1270         return NULL;
1271 }
1272
1273 static bool dce83_construct(
1274         uint8_t num_virtual_links,
1275         struct dc *dc,
1276         struct dce110_resource_pool *pool)
1277 {
1278         unsigned int i;
1279         struct dc_context *ctx = dc->ctx;
1280         struct dc_firmware_info info;
1281         struct dc_bios *bp;
1282
1283         ctx->dc_bios->regs = &bios_regs;
1284
1285         pool->base.res_cap = &res_cap_83;
1286         pool->base.funcs = &dce80_res_pool_funcs;
1287
1288
1289         /*************************************************
1290          *  Resource + asic cap harcoding                *
1291          *************************************************/
1292         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1293         pool->base.pipe_count = res_cap_83.num_timing_generator;
1294         pool->base.timing_generator_count = res_cap_83.num_timing_generator;
1295         dc->caps.max_downscale_ratio = 200;
1296         dc->caps.i2c_speed_in_khz = 40;
1297         dc->caps.max_cursor_size = 128;
1298         dc->caps.is_apu = true;
1299
1300         /*************************************************
1301          *  Create resources                             *
1302          *************************************************/
1303
1304         bp = ctx->dc_bios;
1305
1306         if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
1307                 info.external_clock_source_frequency_for_dp != 0) {
1308                 pool->base.dp_clock_source =
1309                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1310
1311                 pool->base.clock_sources[0] =
1312                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
1313                 pool->base.clock_sources[1] =
1314                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1315                 pool->base.clk_src_count = 2;
1316
1317         } else {
1318                 pool->base.dp_clock_source =
1319                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);
1320
1321                 pool->base.clock_sources[0] =
1322                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1323                 pool->base.clk_src_count = 1;
1324         }
1325
1326         if (pool->base.dp_clock_source == NULL) {
1327                 dm_error("DC: failed to create dp clock source!\n");
1328                 BREAK_TO_DEBUGGER();
1329                 goto res_create_fail;
1330         }
1331
1332         for (i = 0; i < pool->base.clk_src_count; i++) {
1333                 if (pool->base.clock_sources[i] == NULL) {
1334                         dm_error("DC: failed to create clock sources!\n");
1335                         BREAK_TO_DEBUGGER();
1336                         goto res_create_fail;
1337                 }
1338         }
1339
1340         pool->base.clk_mgr = dce_clk_mgr_create(ctx,
1341                         &disp_clk_regs,
1342                         &disp_clk_shift,
1343                         &disp_clk_mask);
1344         if (pool->base.clk_mgr == NULL) {
1345                 dm_error("DC: failed to create display clock!\n");
1346                 BREAK_TO_DEBUGGER();
1347                 goto res_create_fail;
1348         }
1349
1350         pool->base.dmcu = dce_dmcu_create(ctx,
1351                         &dmcu_regs,
1352                         &dmcu_shift,
1353                         &dmcu_mask);
1354         if (pool->base.dmcu == NULL) {
1355                 dm_error("DC: failed to create dmcu!\n");
1356                 BREAK_TO_DEBUGGER();
1357                 goto res_create_fail;
1358         }
1359
1360         pool->base.abm = dce_abm_create(ctx,
1361                         &abm_regs,
1362                         &abm_shift,
1363                         &abm_mask);
1364         if (pool->base.abm == NULL) {
1365                 dm_error("DC: failed to create abm!\n");
1366                 BREAK_TO_DEBUGGER();
1367                 goto res_create_fail;
1368         }
1369
1370         {
1371                 struct irq_service_init_data init_data;
1372                 init_data.ctx = dc->ctx;
1373                 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1374                 if (!pool->base.irqs)
1375                         goto res_create_fail;
1376         }
1377
1378         for (i = 0; i < pool->base.pipe_count; i++) {
1379                 pool->base.timing_generators[i] = dce80_timing_generator_create(
1380                                 ctx, i, &dce80_tg_offsets[i]);
1381                 if (pool->base.timing_generators[i] == NULL) {
1382                         BREAK_TO_DEBUGGER();
1383                         dm_error("DC: failed to create tg!\n");
1384                         goto res_create_fail;
1385                 }
1386
1387                 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1388                 if (pool->base.mis[i] == NULL) {
1389                         BREAK_TO_DEBUGGER();
1390                         dm_error("DC: failed to create memory input!\n");
1391                         goto res_create_fail;
1392                 }
1393
1394                 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1395                 if (pool->base.ipps[i] == NULL) {
1396                         BREAK_TO_DEBUGGER();
1397                         dm_error("DC: failed to create input pixel processor!\n");
1398                         goto res_create_fail;
1399                 }
1400
1401                 pool->base.transforms[i] = dce80_transform_create(ctx, i);
1402                 if (pool->base.transforms[i] == NULL) {
1403                         BREAK_TO_DEBUGGER();
1404                         dm_error("DC: failed to create transform!\n");
1405                         goto res_create_fail;
1406                 }
1407
1408                 pool->base.opps[i] = dce80_opp_create(ctx, i);
1409                 if (pool->base.opps[i] == NULL) {
1410                         BREAK_TO_DEBUGGER();
1411                         dm_error("DC: failed to create output pixel processor!\n");
1412                         goto res_create_fail;
1413                 }
1414         }
1415
1416         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1417                 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1418                 if (pool->base.engines[i] == NULL) {
1419                         BREAK_TO_DEBUGGER();
1420                         dm_error(
1421                                 "DC:failed to create aux engine!!\n");
1422                         goto res_create_fail;
1423                 }
1424                 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1425                 if (pool->base.hw_i2cs[i] == NULL) {
1426                         BREAK_TO_DEBUGGER();
1427                         dm_error(
1428                                 "DC:failed to create i2c engine!!\n");
1429                         goto res_create_fail;
1430                 }
1431                 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1432                 if (pool->base.sw_i2cs[i] == NULL) {
1433                         BREAK_TO_DEBUGGER();
1434                         dm_error(
1435                                 "DC:failed to create sw i2c!!\n");
1436                         goto res_create_fail;
1437                 }
1438         }
1439
1440         dc->caps.max_planes =  pool->base.pipe_count;
1441         dc->caps.disable_dp_clk_share = true;
1442
1443         if (!resource_construct(num_virtual_links, dc, &pool->base,
1444                         &res_create_funcs))
1445                 goto res_create_fail;
1446
1447         /* Create hardware sequencer */
1448         dce80_hw_sequencer_construct(dc);
1449
1450         return true;
1451
1452 res_create_fail:
1453         destruct(pool);
1454         return false;
1455 }
1456
1457 struct resource_pool *dce83_create_resource_pool(
1458         uint8_t num_virtual_links,
1459         struct dc *dc)
1460 {
1461         struct dce110_resource_pool *pool =
1462                 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1463
1464         if (!pool)
1465                 return NULL;
1466
1467         if (dce83_construct(num_virtual_links, dc, pool))
1468                 return &pool->base;
1469
1470         BREAK_TO_DEBUGGER();
1471         return NULL;
1472 }