drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dce/dce_8_0_d.h"
  27 #include "dce/dce_8_0_sh_mask.h"
  28
  29 #include "dm_services.h"
  30
  31 #include "link_encoder.h"
  32 #include "stream_encoder.h"
  33
  34 #include "resource.h"
  35 #include "include/irq_service_interface.h"
  36 #include "irq/dce80/irq_service_dce80.h"
  37 #include "dce110/dce110_timing_generator.h"
  38 #include "dce110/dce110_resource.h"
  39 #include "dce80/dce80_timing_generator.h"
  40 #include "dce/dce_mem_input.h"
  41 #include "dce/dce_link_encoder.h"
  42 #include "dce/dce_stream_encoder.h"
  43 #include "dce/dce_mem_input.h"
  44 #include "dce/dce_ipp.h"
  45 #include "dce/dce_transform.h"
  46 #include "dce/dce_opp.h"
  47 #include "dce/dce_clocks.h"
  48 #include "dce/dce_clock_source.h"
  49 #include "dce/dce_audio.h"
  50 #include "dce/dce_hwseq.h"
  51 #include "dce80/dce80_hw_sequencer.h"
  52 #include "dce100/dce100_resource.h"
  53
  54 #include "reg_helper.h"
  55
  56 /* TODO remove this include */
  57
  58 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
  59 #include "gmc/gmc_7_1_d.h"
  60 #include "gmc/gmc_7_1_sh_mask.h"
  61 #endif
  62
  63 #ifndef mmDP_DPHY_INTERNAL_CTRL
  64 #define mmDP_DPHY_INTERNAL_CTRL                         0x1CDE
  65 #define mmDP0_DP_DPHY_INTERNAL_CTRL                     0x1CDE
  66 #define mmDP1_DP_DPHY_INTERNAL_CTRL                     0x1FDE
  67 #define mmDP2_DP_DPHY_INTERNAL_CTRL                     0x42DE
  68 #define mmDP3_DP_DPHY_INTERNAL_CTRL                     0x45DE
  69 #define mmDP4_DP_DPHY_INTERNAL_CTRL                     0x48DE
  70 #define mmDP5_DP_DPHY_INTERNAL_CTRL                     0x4BDE
  71 #define mmDP6_DP_DPHY_INTERNAL_CTRL                     0x4EDE
  72 #endif
  73
  74
  75 #ifndef mmBIOS_SCRATCH_2
  76         #define mmBIOS_SCRATCH_2 0x05CB
  77         #define mmBIOS_SCRATCH_6 0x05CF
  78 #endif
  79
  80 #ifndef mmDP_DPHY_FAST_TRAINING
  81         #define mmDP_DPHY_FAST_TRAINING                         0x1CCE
  82         #define mmDP0_DP_DPHY_FAST_TRAINING                     0x1CCE
  83         #define mmDP1_DP_DPHY_FAST_TRAINING                     0x1FCE
  84         #define mmDP2_DP_DPHY_FAST_TRAINING                     0x42CE
  85         #define mmDP3_DP_DPHY_FAST_TRAINING                     0x45CE
  86         #define mmDP4_DP_DPHY_FAST_TRAINING                     0x48CE
  87         #define mmDP5_DP_DPHY_FAST_TRAINING                     0x4BCE
  88         #define mmDP6_DP_DPHY_FAST_TRAINING                     0x4ECE
  89 #endif
  90
  91
  92 #ifndef mmHPD_DC_HPD_CONTROL
  93         #define mmHPD_DC_HPD_CONTROL                            0x189A
  94         #define mmHPD0_DC_HPD_CONTROL                           0x189A
  95         #define mmHPD1_DC_HPD_CONTROL                           0x18A2
  96         #define mmHPD2_DC_HPD_CONTROL                           0x18AA
  97         #define mmHPD3_DC_HPD_CONTROL                           0x18B2
  98         #define mmHPD4_DC_HPD_CONTROL                           0x18BA
  99         #define mmHPD5_DC_HPD_CONTROL                           0x18C2
 100 #endif
 101
 102 #define DCE11_DIG_FE_CNTL 0x4a00
 103 #define DCE11_DIG_BE_CNTL 0x4a47
 104 #define DCE11_DP_SEC 0x4ac3
 105
 106 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = {
 107                 {
 108                         .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
 109                         .dcp =  (mmGRPH_CONTROL - mmGRPH_CONTROL),
 110                         .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
 111                                         - mmDPG_WATERMARK_MASK_CONTROL),
 112                 },
 113                 {
 114                         .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
 115                         .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
 116                         .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
 117                                         - mmDPG_WATERMARK_MASK_CONTROL),
 118                 },
 119                 {
 120                         .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
 121                         .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
 122                         .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
 123                                         - mmDPG_WATERMARK_MASK_CONTROL),
 124                 },
 125                 {
 126                         .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
 127                         .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
 128                         .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
 129                                         - mmDPG_WATERMARK_MASK_CONTROL),
 130                 },
 131                 {
 132                         .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
 133                         .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
 134                         .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
 135                                         - mmDPG_WATERMARK_MASK_CONTROL),
 136                 },
 137                 {
 138                         .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
 139                         .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
 140                         .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
 141                                         - mmDPG_WATERMARK_MASK_CONTROL),
 142                 }
 143 };
 144
 145 /* set register offset */
 146 #define SR(reg_name)\
 147         .reg_name = mm ## reg_name
 148
 149 /* set register offset with instance */
 150 #define SRI(reg_name, block, id)\
 151         .reg_name = mm ## block ## id ## _ ## reg_name
 152
 153
 154 static const struct dce_disp_clk_registers disp_clk_regs = {
 155                 CLK_COMMON_REG_LIST_DCE_BASE()
 156 };
 157
 158 static const struct dce_disp_clk_shift disp_clk_shift = {
 159                 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 160 };
 161
 162 static const struct dce_disp_clk_mask disp_clk_mask = {
 163                 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 164 };
 165
 166 #define ipp_regs(id)\
 167 [id] = {\
 168                 IPP_COMMON_REG_LIST_DCE_BASE(id)\
 169 }
 170
 171 static const struct dce_ipp_registers ipp_regs[] = {
 172                 ipp_regs(0),
 173                 ipp_regs(1),
 174                 ipp_regs(2),
 175                 ipp_regs(3),
 176                 ipp_regs(4),
 177                 ipp_regs(5)
 178 };
 179
 180 static const struct dce_ipp_shift ipp_shift = {
 181                 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 182 };
 183
 184 static const struct dce_ipp_mask ipp_mask = {
 185                 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 186 };
 187
 188 #define transform_regs(id)\
 189 [id] = {\
 190                 XFM_COMMON_REG_LIST_DCE80(id)\
 191 }
 192
 193 static const struct dce_transform_registers xfm_regs[] = {
 194                 transform_regs(0),
 195                 transform_regs(1),
 196                 transform_regs(2),
 197                 transform_regs(3),
 198                 transform_regs(4),
 199                 transform_regs(5)
 200 };
 201
 202 static const struct dce_transform_shift xfm_shift = {
 203                 XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT)
 204 };
 205
 206 static const struct dce_transform_mask xfm_mask = {
 207                 XFM_COMMON_MASK_SH_LIST_DCE80(_MASK)
 208 };
 209
 210 #define aux_regs(id)\
 211 [id] = {\
 212         AUX_REG_LIST(id)\
 213 }
 214
 215 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
 216         aux_regs(0),
 217         aux_regs(1),
 218         aux_regs(2),
 219         aux_regs(3),
 220         aux_regs(4),
 221         aux_regs(5)
 222 };
 223
 224 #define hpd_regs(id)\
 225 [id] = {\
 226         HPD_REG_LIST(id)\
 227 }
 228
 229 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
 230                 hpd_regs(0),
 231                 hpd_regs(1),
 232                 hpd_regs(2),
 233                 hpd_regs(3),
 234                 hpd_regs(4),
 235                 hpd_regs(5)
 236 };
 237
 238 #define link_regs(id)\
 239 [id] = {\
 240         LE_DCE80_REG_LIST(id)\
 241 }
 242
 243 static const struct dce110_link_enc_registers link_enc_regs[] = {
 244         link_regs(0),
 245         link_regs(1),
 246         link_regs(2),
 247         link_regs(3),
 248         link_regs(4),
 249         link_regs(5),
 250         link_regs(6),
 251 };
 252
 253 #define stream_enc_regs(id)\
 254 [id] = {\
 255         SE_COMMON_REG_LIST_DCE_BASE(id),\
 256         .AFMT_CNTL = 0,\
 257 }
 258
 259 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
 260         stream_enc_regs(0),
 261         stream_enc_regs(1),
 262         stream_enc_regs(2),
 263         stream_enc_regs(3),
 264         stream_enc_regs(4),
 265         stream_enc_regs(5),
 266         stream_enc_regs(6)
 267 };
 268
 269 static const struct dce_stream_encoder_shift se_shift = {
 270                 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
 271 };
 272
 273 static const struct dce_stream_encoder_mask se_mask = {
 274                 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
 275 };
 276
 277 #define opp_regs(id)\
 278 [id] = {\
 279         OPP_DCE_80_REG_LIST(id),\
 280 }
 281
 282 static const struct dce_opp_registers opp_regs[] = {
 283         opp_regs(0),
 284         opp_regs(1),
 285         opp_regs(2),
 286         opp_regs(3),
 287         opp_regs(4),
 288         opp_regs(5)
 289 };
 290
 291 static const struct dce_opp_shift opp_shift = {
 292         OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT)
 293 };
 294
 295 static const struct dce_opp_mask opp_mask = {
 296         OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK)
 297 };
 298
 299 #define audio_regs(id)\
 300 [id] = {\
 301         AUD_COMMON_REG_LIST(id)\
 302 }
 303
 304 static const struct dce_audio_registers audio_regs[] = {
 305         audio_regs(0),
 306         audio_regs(1),
 307         audio_regs(2),
 308         audio_regs(3),
 309         audio_regs(4),
 310         audio_regs(5),
 311         audio_regs(6),
 312 };
 313
 314 static const struct dce_audio_shift audio_shift = {
 315                 AUD_COMMON_MASK_SH_LIST(__SHIFT)
 316 };
 317
 318 static const struct dce_aduio_mask audio_mask = {
 319                 AUD_COMMON_MASK_SH_LIST(_MASK)
 320 };
 321
 322 #define clk_src_regs(id)\
 323 [id] = {\
 324         CS_COMMON_REG_LIST_DCE_80(id),\
 325 }
 326
 327
 328 static const struct dce110_clk_src_regs clk_src_regs[] = {
 329         clk_src_regs(0),
 330         clk_src_regs(1),
 331         clk_src_regs(2)
 332 };
 333
 334 static const struct dce110_clk_src_shift cs_shift = {
 335                 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 336 };
 337
 338 static const struct dce110_clk_src_mask cs_mask = {
 339                 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 340 };
 341
 342 static const struct bios_registers bios_regs = {
 343         .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
 344 };
 345
 346 static const struct resource_caps res_cap = {
 347                 .num_timing_generator = 6,
 348                 .num_audio = 6,
 349                 .num_stream_encoder = 6,
 350                 .num_pll = 3,
 351 };
 352
 353 static const struct resource_caps res_cap_81 = {
 354                 .num_timing_generator = 4,
 355                 .num_audio = 7,
 356                 .num_stream_encoder = 7,
 357                 .num_pll = 3,
 358 };
 359
 360 static const struct resource_caps res_cap_83 = {
 361                 .num_timing_generator = 2,
 362                 .num_audio = 6,
 363                 .num_stream_encoder = 6,
 364                 .num_pll = 2,
 365 };
 366
 367 #define CTX  ctx
 368 #define REG(reg) mm ## reg
 369
 370 #ifndef mmCC_DC_HDMI_STRAPS
 371 #define mmCC_DC_HDMI_STRAPS 0x1918
 372 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
 373 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
 374 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
 375 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
 376 #endif
 377
 378 static void read_dce_straps(
 379         struct dc_context *ctx,
 380         struct resource_straps *straps)
 381 {
 382         REG_GET_2(CC_DC_HDMI_STRAPS,
 383                         HDMI_DISABLE, &straps->hdmi_disable,
 384                         AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
 385
 386         REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
 387 }
 388
 389 static struct audio *create_audio(
 390                 struct dc_context *ctx, unsigned int inst)
 391 {
 392         return dce_audio_create(ctx, inst,
 393                         &audio_regs[inst], &audio_shift, &audio_mask);
 394 }
 395
 396 static struct timing_generator *dce80_timing_generator_create(
 397                 struct dc_context *ctx,
 398                 uint32_t instance,
 399                 const struct dce110_timing_generator_offsets *offsets)
 400 {
 401         struct dce110_timing_generator *tg110 =
 402                 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
 403
 404         if (!tg110)
 405                 return NULL;
 406
 407         dce80_timing_generator_construct(tg110, ctx, instance, offsets);
 408         return &tg110->base;
 409 }
 410
 411 static struct output_pixel_processor *dce80_opp_create(
 412         struct dc_context *ctx,
 413         uint32_t inst)
 414 {
 415         struct dce110_opp *opp =
 416                 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
 417
 418         if (!opp)
 419                 return NULL;
 420
 421         dce110_opp_construct(opp,
 422                              ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
 423         return &opp->base;
 424 }
 425
 426 static struct stream_encoder *dce80_stream_encoder_create(
 427         enum engine_id eng_id,
 428         struct dc_context *ctx)
 429 {
 430         struct dce110_stream_encoder *enc110 =
 431                 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
 432
 433         if (!enc110)
 434                 return NULL;
 435
 436         dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
 437                                         &stream_enc_regs[eng_id],
 438                                         &se_shift, &se_mask);
 439         return &enc110->base;
 440 }
 441
 442 #define SRII(reg_name, block, id)\
 443         .reg_name[id] = mm ## block ## id ## _ ## reg_name
 444
 445 static const struct dce_hwseq_registers hwseq_reg = {
 446                 HWSEQ_DCE8_REG_LIST()
 447 };
 448
 449 static const struct dce_hwseq_shift hwseq_shift = {
 450                 HWSEQ_DCE8_MASK_SH_LIST(__SHIFT)
 451 };
 452
 453 static const struct dce_hwseq_mask hwseq_mask = {
 454                 HWSEQ_DCE8_MASK_SH_LIST(_MASK)
 455 };
 456
 457 static struct dce_hwseq *dce80_hwseq_create(
 458         struct dc_context *ctx)
 459 {
 460         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
 461
 462         if (hws) {
 463                 hws->ctx = ctx;
 464                 hws->regs = &hwseq_reg;
 465                 hws->shifts = &hwseq_shift;
 466                 hws->masks = &hwseq_mask;
 467         }
 468         return hws;
 469 }
 470
 471 static const struct resource_create_funcs res_create_funcs = {
 472         .read_dce_straps = read_dce_straps,
 473         .create_audio = create_audio,
 474         .create_stream_encoder = dce80_stream_encoder_create,
 475         .create_hwseq = dce80_hwseq_create,
 476 };
 477
 478 #define mi_inst_regs(id) { \
 479         MI_DCE8_REG_LIST(id), \
 480         .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
 481 }
 482 static const struct dce_mem_input_registers mi_regs[] = {
 483                 mi_inst_regs(0),
 484                 mi_inst_regs(1),
 485                 mi_inst_regs(2),
 486                 mi_inst_regs(3),
 487                 mi_inst_regs(4),
 488                 mi_inst_regs(5),
 489 };
 490
 491 static const struct dce_mem_input_shift mi_shifts = {
 492                 MI_DCE8_MASK_SH_LIST(__SHIFT),
 493                 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
 494 };
 495
 496 static const struct dce_mem_input_mask mi_masks = {
 497                 MI_DCE8_MASK_SH_LIST(_MASK),
 498                 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
 499 };
 500
 501 static struct mem_input *dce80_mem_input_create(
 502         struct dc_context *ctx,
 503         uint32_t inst)
 504 {
 505         struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
 506                                                GFP_KERNEL);
 507
 508         if (!dce_mi) {
 509                 BREAK_TO_DEBUGGER();
 510                 return NULL;
 511         }
 512
 513         dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
 514         dce_mi->wa.single_head_rdreq_dmif_limit = 2;
 515         return &dce_mi->base;
 516 }
 517
 518 static void dce80_transform_destroy(struct transform **xfm)
 519 {
 520         kfree(TO_DCE_TRANSFORM(*xfm));
 521         *xfm = NULL;
 522 }
 523
 524 static struct transform *dce80_transform_create(
 525         struct dc_context *ctx,
 526         uint32_t inst)
 527 {
 528         struct dce_transform *transform =
 529                 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
 530
 531         if (!transform)
 532                 return NULL;
 533
 534         dce_transform_construct(transform, ctx, inst,
 535                                 &xfm_regs[inst], &xfm_shift, &xfm_mask);
 536         transform->prescaler_on = false;
 537         return &transform->base;
 538 }
 539
 540 static const struct encoder_feature_support link_enc_feature = {
 541                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
 542                 .max_hdmi_pixel_clock = 297000,
 543                 .flags.bits.IS_HBR2_CAPABLE = true,
 544                 .flags.bits.IS_TPS3_CAPABLE = true,
 545                 .flags.bits.IS_YCBCR_CAPABLE = true
 546 };
 547
 548 struct link_encoder *dce80_link_encoder_create(
 549         const struct encoder_init_data *enc_init_data)
 550 {
 551         struct dce110_link_encoder *enc110 =
 552                 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
 553
 554         if (!enc110)
 555                 return NULL;
 556
 557         dce110_link_encoder_construct(enc110,
 558                                       enc_init_data,
 559                                       &link_enc_feature,
 560                                       &link_enc_regs[enc_init_data->transmitter],
 561                                       &link_enc_aux_regs[enc_init_data->channel - 1],
 562                                       &link_enc_hpd_regs[enc_init_data->hpd_source]);
 563         return &enc110->base;
 564 }
 565
 566 struct clock_source *dce80_clock_source_create(
 567         struct dc_context *ctx,
 568         struct dc_bios *bios,
 569         enum clock_source_id id,
 570         const struct dce110_clk_src_regs *regs,
 571         bool dp_clk_src)
 572 {
 573         struct dce110_clk_src *clk_src =
 574                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 575
 576         if (!clk_src)
 577                 return NULL;
 578
 579         if (dce110_clk_src_construct(clk_src, ctx, bios, id,
 580                         regs, &cs_shift, &cs_mask)) {
 581                 clk_src->base.dp_clk_src = dp_clk_src;
 582                 return &clk_src->base;
 583         }
 584
 585         BREAK_TO_DEBUGGER();
 586         return NULL;
 587 }
 588
 589 void dce80_clock_source_destroy(struct clock_source **clk_src)
 590 {
 591         kfree(TO_DCE110_CLK_SRC(*clk_src));
 592         *clk_src = NULL;
 593 }
 594
 595 static struct input_pixel_processor *dce80_ipp_create(
 596         struct dc_context *ctx, uint32_t inst)
 597 {
 598         struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
 599
 600         if (!ipp) {
 601                 BREAK_TO_DEBUGGER();
 602                 return NULL;
 603         }
 604
 605         dce_ipp_construct(ipp, ctx, inst,
 606                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 607         return &ipp->base;
 608 }
 609
 610 static void destruct(struct dce110_resource_pool *pool)
 611 {
 612         unsigned int i;
 613
 614         for (i = 0; i < pool->base.pipe_count; i++) {
 615                 if (pool->base.opps[i] != NULL)
 616                         dce110_opp_destroy(&pool->base.opps[i]);
 617
 618                 if (pool->base.transforms[i] != NULL)
 619                         dce80_transform_destroy(&pool->base.transforms[i]);
 620
 621                 if (pool->base.ipps[i] != NULL)
 622                         dce_ipp_destroy(&pool->base.ipps[i]);
 623
 624                 if (pool->base.mis[i] != NULL) {
 625                         kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
 626                         pool->base.mis[i] = NULL;
 627                 }
 628
 629                 if (pool->base.timing_generators[i] != NULL)    {
 630                         kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
 631                         pool->base.timing_generators[i] = NULL;
 632                 }
 633         }
 634
 635         for (i = 0; i < pool->base.stream_enc_count; i++) {
 636                 if (pool->base.stream_enc[i] != NULL)
 637                         kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 638         }
 639
 640         for (i = 0; i < pool->base.clk_src_count; i++) {
 641                 if (pool->base.clock_sources[i] != NULL) {
 642                         dce80_clock_source_destroy(&pool->base.clock_sources[i]);
 643                 }
 644         }
 645
 646         if (pool->base.dp_clock_source != NULL)
 647                 dce80_clock_source_destroy(&pool->base.dp_clock_source);
 648
 649         for (i = 0; i < pool->base.audio_count; i++)    {
 650                 if (pool->base.audios[i] != NULL) {
 651                         dce_aud_destroy(&pool->base.audios[i]);
 652                 }
 653         }
 654
 655         if (pool->base.display_clock != NULL)
 656                 dce_disp_clk_destroy(&pool->base.display_clock);
 657
 658         if (pool->base.irqs != NULL) {
 659                 dal_irq_service_destroy(&pool->base.irqs);
 660         }
 661 }
 662
 663 static enum dc_status build_mapped_resource(
 664                 const struct dc *dc,
 665                 struct dc_state *context,
 666                 struct dc_stream_state *stream)
 667 {
 668         struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
 669
 670         if (!pipe_ctx)
 671                 return DC_ERROR_UNEXPECTED;
 672
 673         dce110_resource_build_pipe_hw_param(pipe_ctx);
 674
 675         resource_build_info_frame(pipe_ctx);
 676
 677         return DC_OK;
 678 }
 679
 680 bool dce80_validate_bandwidth(
 681         struct dc *dc,
 682         struct dc_state *context)
 683 {
 684         /* TODO implement when needed but for now hardcode max value*/
 685         context->bw.dce.dispclk_khz = 681000;
 686         context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER;
 687
 688         return true;
 689 }
 690
 691 static bool dce80_validate_surface_sets(
 692                 struct dc_state *context)
 693 {
 694         int i;
 695
 696         for (i = 0; i < context->stream_count; i++) {
 697                 if (context->stream_status[i].plane_count == 0)
 698                         continue;
 699
 700                 if (context->stream_status[i].plane_count > 1)
 701                         return false;
 702
 703                 if (context->stream_status[i].plane_states[0]->format
 704                                 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
 705                         return false;
 706         }
 707
 708         return true;
 709 }
 710
 711 enum dc_status dce80_validate_global(
 712                 struct dc *dc,
 713                 struct dc_state *context)
 714 {
 715         if (!dce80_validate_surface_sets(context))
 716                 return DC_FAIL_SURFACE_VALIDATE;
 717
 718         return DC_OK;
 719 }
 720
 721 enum dc_status dce80_validate_guaranteed(
 722                 struct dc *dc,
 723                 struct dc_stream_state *dc_stream,
 724                 struct dc_state *context)
 725 {
 726         enum dc_status result = DC_ERROR_UNEXPECTED;
 727
 728         context->streams[0] = dc_stream;
 729         dc_stream_retain(context->streams[0]);
 730         context->stream_count++;
 731
 732         result = resource_map_pool_resources(dc, context, dc_stream);
 733
 734         if (result == DC_OK)
 735                 result = resource_map_clock_resources(dc, context, dc_stream);
 736
 737         if (result == DC_OK)
 738                 result = build_mapped_resource(dc, context, dc_stream);
 739
 740         if (result == DC_OK) {
 741                 validate_guaranteed_copy_streams(
 742                                 context, dc->caps.max_streams);
 743                 result = resource_build_scaling_params_for_context(dc, context);
 744         }
 745
 746         if (result == DC_OK)
 747                 result = dce80_validate_bandwidth(dc, context);
 748
 749         return result;
 750 }
 751
 752 static void dce80_destroy_resource_pool(struct resource_pool **pool)
 753 {
 754         struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
 755
 756         destruct(dce110_pool);
 757         kfree(dce110_pool);
 758         *pool = NULL;
 759 }
 760
 761 static const struct resource_funcs dce80_res_pool_funcs = {
 762         .destroy = dce80_destroy_resource_pool,
 763         .link_enc_create = dce80_link_encoder_create,
 764         .validate_guaranteed = dce80_validate_guaranteed,
 765         .validate_bandwidth = dce80_validate_bandwidth,
 766         .validate_plane = dce100_validate_plane,
 767         .add_stream_to_ctx = dce100_add_stream_to_ctx,
 768         .validate_global = dce80_validate_global
 769 };
 770
 771 static bool dce80_construct(
 772         uint8_t num_virtual_links,
 773         struct dc *dc,
 774         struct dce110_resource_pool *pool)
 775 {
 776         unsigned int i;
 777         struct dc_context *ctx = dc->ctx;
 778         struct dc_firmware_info info;
 779         struct dc_bios *bp;
 780         struct dm_pp_static_clock_info static_clk_info = {0};
 781
 782         ctx->dc_bios->regs = &bios_regs;
 783
 784         pool->base.res_cap = &res_cap;
 785         pool->base.funcs = &dce80_res_pool_funcs;
 786
 787
 788         /*************************************************
 789          *  Resource + asic cap harcoding                *
 790          *************************************************/
 791         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
 792         pool->base.pipe_count = res_cap.num_timing_generator;
 793         dc->caps.max_downscale_ratio = 200;
 794         dc->caps.i2c_speed_in_khz = 40;
 795         dc->caps.max_cursor_size = 128;
 796         dc->caps.dual_link_dvi = true;
 797
 798         /*************************************************
 799          *  Create resources                             *
 800          *************************************************/
 801
 802         bp = ctx->dc_bios;
 803
 804         if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
 805                 info.external_clock_source_frequency_for_dp != 0) {
 806                 pool->base.dp_clock_source =
 807                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
 808
 809                 pool->base.clock_sources[0] =
 810                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
 811                 pool->base.clock_sources[1] =
 812                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
 813                 pool->base.clock_sources[2] =
 814                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
 815                 pool->base.clk_src_count = 3;
 816
 817         } else {
 818                 pool->base.dp_clock_source =
 819                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
 820
 821                 pool->base.clock_sources[0] =
 822                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
 823                 pool->base.clock_sources[1] =
 824                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
 825                 pool->base.clk_src_count = 2;
 826         }
 827
 828         if (pool->base.dp_clock_source == NULL) {
 829                 dm_error("DC: failed to create dp clock source!\n");
 830                 BREAK_TO_DEBUGGER();
 831                 goto res_create_fail;
 832         }
 833
 834         for (i = 0; i < pool->base.clk_src_count; i++) {
 835                 if (pool->base.clock_sources[i] == NULL) {
 836                         dm_error("DC: failed to create clock sources!\n");
 837                         BREAK_TO_DEBUGGER();
 838                         goto res_create_fail;
 839                 }
 840         }
 841
 842         pool->base.display_clock = dce_disp_clk_create(ctx,
 843                         &disp_clk_regs,
 844                         &disp_clk_shift,
 845                         &disp_clk_mask);
 846         if (pool->base.display_clock == NULL) {
 847                 dm_error("DC: failed to create display clock!\n");
 848                 BREAK_TO_DEBUGGER();
 849                 goto res_create_fail;
 850         }
 851
 852
 853         if (dm_pp_get_static_clocks(ctx, &static_clk_info))
 854                 pool->base.display_clock->max_clks_state =
 855                                         static_clk_info.max_clocks_state;
 856
 857         {
 858                 struct irq_service_init_data init_data;
 859                 init_data.ctx = dc->ctx;
 860                 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
 861                 if (!pool->base.irqs)
 862                         goto res_create_fail;
 863         }
 864
 865         for (i = 0; i < pool->base.pipe_count; i++) {
 866                 pool->base.timing_generators[i] = dce80_timing_generator_create(
 867                                 ctx, i, &dce80_tg_offsets[i]);
 868                 if (pool->base.timing_generators[i] == NULL) {
 869                         BREAK_TO_DEBUGGER();
 870                         dm_error("DC: failed to create tg!\n");
 871                         goto res_create_fail;
 872                 }
 873
 874                 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
 875                 if (pool->base.mis[i] == NULL) {
 876                         BREAK_TO_DEBUGGER();
 877                         dm_error("DC: failed to create memory input!\n");
 878                         goto res_create_fail;
 879                 }
 880
 881                 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
 882                 if (pool->base.ipps[i] == NULL) {
 883                         BREAK_TO_DEBUGGER();
 884                         dm_error("DC: failed to create input pixel processor!\n");
 885                         goto res_create_fail;
 886                 }
 887
 888                 pool->base.transforms[i] = dce80_transform_create(ctx, i);
 889                 if (pool->base.transforms[i] == NULL) {
 890                         BREAK_TO_DEBUGGER();
 891                         dm_error("DC: failed to create transform!\n");
 892                         goto res_create_fail;
 893                 }
 894
 895                 pool->base.opps[i] = dce80_opp_create(ctx, i);
 896                 if (pool->base.opps[i] == NULL) {
 897                         BREAK_TO_DEBUGGER();
 898                         dm_error("DC: failed to create output pixel processor!\n");
 899                         goto res_create_fail;
 900                 }
 901         }
 902
 903         dc->caps.max_planes =  pool->base.pipe_count;
 904
 905         if (!resource_construct(num_virtual_links, dc, &pool->base,
 906                         &res_create_funcs))
 907                 goto res_create_fail;
 908
 909         /* Create hardware sequencer */
 910         dce80_hw_sequencer_construct(dc);
 911
 912         return true;
 913
 914 res_create_fail:
 915         destruct(pool);
 916         return false;
 917 }
 918
 919 struct resource_pool *dce80_create_resource_pool(
 920         uint8_t num_virtual_links,
 921         struct dc *dc)
 922 {
 923         struct dce110_resource_pool *pool =
 924                 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
 925
 926         if (!pool)
 927                 return NULL;
 928
 929         if (dce80_construct(num_virtual_links, dc, pool))
 930                 return &pool->base;
 931
 932         BREAK_TO_DEBUGGER();
 933         return NULL;
 934 }
 935
 936 static bool dce81_construct(
 937         uint8_t num_virtual_links,
 938         struct dc *dc,
 939         struct dce110_resource_pool *pool)
 940 {
 941         unsigned int i;
 942         struct dc_context *ctx = dc->ctx;
 943         struct dc_firmware_info info;
 944         struct dc_bios *bp;
 945         struct dm_pp_static_clock_info static_clk_info = {0};
 946
 947         ctx->dc_bios->regs = &bios_regs;
 948
 949         pool->base.res_cap = &res_cap_81;
 950         pool->base.funcs = &dce80_res_pool_funcs;
 951
 952
 953         /*************************************************
 954          *  Resource + asic cap harcoding                *
 955          *************************************************/
 956         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
 957         pool->base.pipe_count = res_cap_81.num_timing_generator;
 958         dc->caps.max_downscale_ratio = 200;
 959         dc->caps.i2c_speed_in_khz = 40;
 960         dc->caps.max_cursor_size = 128;
 961         dc->caps.is_apu = true;
 962
 963         /*************************************************
 964          *  Create resources                             *
 965          *************************************************/
 966
 967         bp = ctx->dc_bios;
 968
 969         if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
 970                 info.external_clock_source_frequency_for_dp != 0) {
 971                 pool->base.dp_clock_source =
 972                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
 973
 974                 pool->base.clock_sources[0] =
 975                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
 976                 pool->base.clock_sources[1] =
 977                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
 978                 pool->base.clock_sources[2] =
 979                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
 980                 pool->base.clk_src_count = 3;
 981
 982         } else {
 983                 pool->base.dp_clock_source =
 984                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
 985
 986                 pool->base.clock_sources[0] =
 987                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
 988                 pool->base.clock_sources[1] =
 989                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
 990                 pool->base.clk_src_count = 2;
 991         }
 992
 993         if (pool->base.dp_clock_source == NULL) {
 994                 dm_error("DC: failed to create dp clock source!\n");
 995                 BREAK_TO_DEBUGGER();
 996                 goto res_create_fail;
 997         }
 998
 999         for (i = 0; i < pool->base.clk_src_count; i++) {
1000                 if (pool->base.clock_sources[i] == NULL) {
1001                         dm_error("DC: failed to create clock sources!\n");
1002                         BREAK_TO_DEBUGGER();
1003                         goto res_create_fail;
1004                 }
1005         }
1006
1007         pool->base.display_clock = dce_disp_clk_create(ctx,
1008                         &disp_clk_regs,
1009                         &disp_clk_shift,
1010                         &disp_clk_mask);
1011         if (pool->base.display_clock == NULL) {
1012                 dm_error("DC: failed to create display clock!\n");
1013                 BREAK_TO_DEBUGGER();
1014                 goto res_create_fail;
1015         }
1016
1017
1018         if (dm_pp_get_static_clocks(ctx, &static_clk_info))
1019                 pool->base.display_clock->max_clks_state =
1020                                         static_clk_info.max_clocks_state;
1021
1022         {
1023                 struct irq_service_init_data init_data;
1024                 init_data.ctx = dc->ctx;
1025                 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1026                 if (!pool->base.irqs)
1027                         goto res_create_fail;
1028         }
1029
1030         for (i = 0; i < pool->base.pipe_count; i++) {
1031                 pool->base.timing_generators[i] = dce80_timing_generator_create(
1032                                 ctx, i, &dce80_tg_offsets[i]);
1033                 if (pool->base.timing_generators[i] == NULL) {
1034                         BREAK_TO_DEBUGGER();
1035                         dm_error("DC: failed to create tg!\n");
1036                         goto res_create_fail;
1037                 }
1038
1039                 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1040                 if (pool->base.mis[i] == NULL) {
1041                         BREAK_TO_DEBUGGER();
1042                         dm_error("DC: failed to create memory input!\n");
1043                         goto res_create_fail;
1044                 }
1045
1046                 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1047                 if (pool->base.ipps[i] == NULL) {
1048                         BREAK_TO_DEBUGGER();
1049                         dm_error("DC: failed to create input pixel processor!\n");
1050                         goto res_create_fail;
1051                 }
1052
1053                 pool->base.transforms[i] = dce80_transform_create(ctx, i);
1054                 if (pool->base.transforms[i] == NULL) {
1055                         BREAK_TO_DEBUGGER();
1056                         dm_error("DC: failed to create transform!\n");
1057                         goto res_create_fail;
1058                 }
1059
1060                 pool->base.opps[i] = dce80_opp_create(ctx, i);
1061                 if (pool->base.opps[i] == NULL) {
1062                         BREAK_TO_DEBUGGER();
1063                         dm_error("DC: failed to create output pixel processor!\n");
1064                         goto res_create_fail;
1065                 }
1066         }
1067
1068         dc->caps.max_planes =  pool->base.pipe_count;
1069
1070         if (!resource_construct(num_virtual_links, dc, &pool->base,
1071                         &res_create_funcs))
1072                 goto res_create_fail;
1073
1074         /* Create hardware sequencer */
1075         dce80_hw_sequencer_construct(dc);
1076
1077         return true;
1078
1079 res_create_fail:
1080         destruct(pool);
1081         return false;
1082 }
1083
1084 struct resource_pool *dce81_create_resource_pool(
1085         uint8_t num_virtual_links,
1086         struct dc *dc)
1087 {
1088         struct dce110_resource_pool *pool =
1089                 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1090
1091         if (!pool)
1092                 return NULL;
1093
1094         if (dce81_construct(num_virtual_links, dc, pool))
1095                 return &pool->base;
1096
1097         BREAK_TO_DEBUGGER();
1098         return NULL;
1099 }
1100
1101 static bool dce83_construct(
1102         uint8_t num_virtual_links,
1103         struct dc *dc,
1104         struct dce110_resource_pool *pool)
1105 {
1106         unsigned int i;
1107         struct dc_context *ctx = dc->ctx;
1108         struct dc_firmware_info info;
1109         struct dc_bios *bp;
1110         struct dm_pp_static_clock_info static_clk_info = {0};
1111
1112         ctx->dc_bios->regs = &bios_regs;
1113
1114         pool->base.res_cap = &res_cap_83;
1115         pool->base.funcs = &dce80_res_pool_funcs;
1116
1117
1118         /*************************************************
1119          *  Resource + asic cap harcoding                *
1120          *************************************************/
1121         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1122         pool->base.pipe_count = res_cap_83.num_timing_generator;
1123         dc->caps.max_downscale_ratio = 200;
1124         dc->caps.i2c_speed_in_khz = 40;
1125         dc->caps.max_cursor_size = 128;
1126         dc->caps.is_apu = true;
1127
1128         /*************************************************
1129          *  Create resources                             *
1130          *************************************************/
1131
1132         bp = ctx->dc_bios;
1133
1134         if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
1135                 info.external_clock_source_frequency_for_dp != 0) {
1136                 pool->base.dp_clock_source =
1137                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1138
1139                 pool->base.clock_sources[0] =
1140                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
1141                 pool->base.clock_sources[1] =
1142                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1143                 pool->base.clk_src_count = 2;
1144
1145         } else {
1146                 pool->base.dp_clock_source =
1147                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);
1148
1149                 pool->base.clock_sources[0] =
1150                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1151                 pool->base.clk_src_count = 1;
1152         }
1153
1154         if (pool->base.dp_clock_source == NULL) {
1155                 dm_error("DC: failed to create dp clock source!\n");
1156                 BREAK_TO_DEBUGGER();
1157                 goto res_create_fail;
1158         }
1159
1160         for (i = 0; i < pool->base.clk_src_count; i++) {
1161                 if (pool->base.clock_sources[i] == NULL) {
1162                         dm_error("DC: failed to create clock sources!\n");
1163                         BREAK_TO_DEBUGGER();
1164                         goto res_create_fail;
1165                 }
1166         }
1167
1168         pool->base.display_clock = dce_disp_clk_create(ctx,
1169                         &disp_clk_regs,
1170                         &disp_clk_shift,
1171                         &disp_clk_mask);
1172         if (pool->base.display_clock == NULL) {
1173                 dm_error("DC: failed to create display clock!\n");
1174                 BREAK_TO_DEBUGGER();
1175                 goto res_create_fail;
1176         }
1177
1178
1179         if (dm_pp_get_static_clocks(ctx, &static_clk_info))
1180                 pool->base.display_clock->max_clks_state =
1181                                         static_clk_info.max_clocks_state;
1182
1183         {
1184                 struct irq_service_init_data init_data;
1185                 init_data.ctx = dc->ctx;
1186                 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1187                 if (!pool->base.irqs)
1188                         goto res_create_fail;
1189         }
1190
1191         for (i = 0; i < pool->base.pipe_count; i++) {
1192                 pool->base.timing_generators[i] = dce80_timing_generator_create(
1193                                 ctx, i, &dce80_tg_offsets[i]);
1194                 if (pool->base.timing_generators[i] == NULL) {
1195                         BREAK_TO_DEBUGGER();
1196                         dm_error("DC: failed to create tg!\n");
1197                         goto res_create_fail;
1198                 }
1199
1200                 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1201                 if (pool->base.mis[i] == NULL) {
1202                         BREAK_TO_DEBUGGER();
1203                         dm_error("DC: failed to create memory input!\n");
1204                         goto res_create_fail;
1205                 }
1206
1207                 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1208                 if (pool->base.ipps[i] == NULL) {
1209                         BREAK_TO_DEBUGGER();
1210                         dm_error("DC: failed to create input pixel processor!\n");
1211                         goto res_create_fail;
1212                 }
1213
1214                 pool->base.transforms[i] = dce80_transform_create(ctx, i);
1215                 if (pool->base.transforms[i] == NULL) {
1216                         BREAK_TO_DEBUGGER();
1217                         dm_error("DC: failed to create transform!\n");
1218                         goto res_create_fail;
1219                 }
1220
1221                 pool->base.opps[i] = dce80_opp_create(ctx, i);
1222                 if (pool->base.opps[i] == NULL) {
1223                         BREAK_TO_DEBUGGER();
1224                         dm_error("DC: failed to create output pixel processor!\n");
1225                         goto res_create_fail;
1226                 }
1227         }
1228
1229         dc->caps.max_planes =  pool->base.pipe_count;
1230
1231         if (!resource_construct(num_virtual_links, dc, &pool->base,
1232                         &res_create_funcs))
1233                 goto res_create_fail;
1234
1235         /* Create hardware sequencer */
1236         dce80_hw_sequencer_construct(dc);
1237
1238         return true;
1239
1240 res_create_fail:
1241         destruct(pool);
1242         return false;
1243 }
1244
1245 struct resource_pool *dce83_create_resource_pool(
1246         uint8_t num_virtual_links,
1247         struct dc *dc)
1248 {
1249         struct dce110_resource_pool *pool =
1250                 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1251
1252         if (!pool)
1253                 return NULL;
1254
1255         if (dce83_construct(num_virtual_links, dc, pool))
1256                 return &pool->base;
1257
1258         BREAK_TO_DEBUGGER();
1259         return NULL;
1260 }