2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "dm_services.h"
28 #include "core_types.h"
29 #include "dce80_hw_sequencer.h"
31 #include "dce/dce_hwseq.h"
32 #include "dce110/dce110_hw_sequencer.h"
33 #include "dce100/dce100_hw_sequencer.h"
35 /* include DCE8 register header files */
36 #include "dce/dce_8_0_d.h"
37 #include "dce/dce_8_0_sh_mask.h"
39 struct dce80_hw_seq_reg_offsets {
43 static const struct dce80_hw_seq_reg_offsets reg_offsets[] = {
45 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
48 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
51 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
54 .crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
57 .crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
60 .crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
64 #define HW_REG_CRTC(reg, id)\
65 (reg + reg_offsets[id].crtc)
67 /*******************************************************************************
69 ******************************************************************************/
71 /***************************PIPE_CONTROL***********************************/
73 static bool dce80_enable_display_power_gating(
75 uint8_t controller_id,
77 enum pipe_gating_control power_gating)
79 enum bp_result bp_result = BP_RESULT_OK;
80 enum bp_pipe_control_action cntl;
81 struct dc_context *ctx = dc->ctx;
83 if (power_gating == PIPE_GATING_CONTROL_INIT)
84 cntl = ASIC_PIPE_INIT;
85 else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
86 cntl = ASIC_PIPE_ENABLE;
88 cntl = ASIC_PIPE_DISABLE;
90 if (!(power_gating == PIPE_GATING_CONTROL_INIT && controller_id != 0)){
92 bp_result = dcb->funcs->enable_disp_power_gating(
93 dcb, controller_id + 1, cntl);
95 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
96 * by default when command table is called
99 HW_REG_CRTC(mmMASTER_UPDATE_MODE, controller_id),
103 if (bp_result == BP_RESULT_OK)
109 void dce80_hw_sequencer_construct(struct dc *dc)
111 dce110_hw_sequencer_construct(dc);
113 dc->hwss.enable_display_power_gating = dce80_enable_display_power_gating;
114 dc->hwss.pipe_control_lock = dce_pipe_control_lock;
115 dc->hwss.set_bandwidth = dce100_set_bandwidth;