drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27
  28 #include "link_encoder.h"
  29 #include "stream_encoder.h"
  30
  31 #include "resource.h"
  32 #include "dce110/dce110_resource.h"
  33
  34 #include "include/irq_service_interface.h"
  35 #include "dce/dce_audio.h"
  36 #include "dce110/dce110_timing_generator.h"
  37 #include "irq/dce110/irq_service_dce110.h"
  38 #include "dce110/dce110_timing_generator_v.h"
  39 #include "dce/dce_link_encoder.h"
  40 #include "dce/dce_stream_encoder.h"
  41 #include "dce/dce_mem_input.h"
  42 #include "dce110/dce110_mem_input_v.h"
  43 #include "dce/dce_ipp.h"
  44 #include "dce/dce_transform.h"
  45 #include "dce110/dce110_transform_v.h"
  46 #include "dce/dce_opp.h"
  47 #include "dce110/dce110_opp_v.h"
  48 #include "dce/dce_clocks.h"
  49 #include "dce/dce_clock_source.h"
  50 #include "dce/dce_hwseq.h"
  51 #include "dce110/dce110_hw_sequencer.h"
  52 #include "dce/dce_abm.h"
  53 #include "dce/dce_dmcu.h"
  54
  55 #if defined(CONFIG_DRM_AMD_DC_FBC)
  56 #include "dce110/dce110_compressor.h"
  57 #endif
  58
  59 #include "reg_helper.h"
  60
  61 #include "dce/dce_11_0_d.h"
  62 #include "dce/dce_11_0_sh_mask.h"
  63
  64 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
  65 #include "gmc/gmc_8_2_d.h"
  66 #include "gmc/gmc_8_2_sh_mask.h"
  67 #endif
  68
  69 #ifndef mmDP_DPHY_INTERNAL_CTRL
  70         #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
  71         #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
  72         #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
  73         #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
  74         #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
  75         #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
  76         #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
  77         #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
  78         #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
  79         #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
  80 #endif
  81
  82 #ifndef mmBIOS_SCRATCH_2
  83         #define mmBIOS_SCRATCH_2 0x05CB
  84         #define mmBIOS_SCRATCH_6 0x05CF
  85 #endif
  86
  87 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
  88         #define mmDP_DPHY_BS_SR_SWAP_CNTL                       0x4ADC
  89         #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                   0x4ADC
  90         #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                   0x4BDC
  91         #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                   0x4CDC
  92         #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                   0x4DDC
  93         #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                   0x4EDC
  94         #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL                   0x4FDC
  95         #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL                   0x54DC
  96 #endif
  97
  98 #ifndef mmDP_DPHY_FAST_TRAINING
  99         #define mmDP_DPHY_FAST_TRAINING                         0x4ABC
 100         #define mmDP0_DP_DPHY_FAST_TRAINING                     0x4ABC
 101         #define mmDP1_DP_DPHY_FAST_TRAINING                     0x4BBC
 102         #define mmDP2_DP_DPHY_FAST_TRAINING                     0x4CBC
 103         #define mmDP3_DP_DPHY_FAST_TRAINING                     0x4DBC
 104         #define mmDP4_DP_DPHY_FAST_TRAINING                     0x4EBC
 105         #define mmDP5_DP_DPHY_FAST_TRAINING                     0x4FBC
 106         #define mmDP6_DP_DPHY_FAST_TRAINING                     0x54BC
 107 #endif
 108
 109 #ifndef DPHY_RX_FAST_TRAINING_CAPABLE
 110         #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1
 111 #endif
 112
 113 static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = {
 114         {
 115                 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
 116                 .dcp =  (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
 117         },
 118         {
 119                 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
 120                 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
 121         },
 122         {
 123                 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
 124                 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
 125         },
 126         {
 127                 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
 128                 .dcp =  (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
 129         },
 130         {
 131                 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
 132                 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
 133         },
 134         {
 135                 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
 136                 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
 137         }
 138 };
 139
 140 /* set register offset */
 141 #define SR(reg_name)\
 142         .reg_name = mm ## reg_name
 143
 144 /* set register offset with instance */
 145 #define SRI(reg_name, block, id)\
 146         .reg_name = mm ## block ## id ## _ ## reg_name
 147
 148 static const struct dce_disp_clk_registers disp_clk_regs = {
 149                 CLK_COMMON_REG_LIST_DCE_BASE()
 150 };
 151
 152 static const struct dce_disp_clk_shift disp_clk_shift = {
 153                 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 154 };
 155
 156 static const struct dce_disp_clk_mask disp_clk_mask = {
 157                 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 158 };
 159
 160 static const struct dce_dmcu_registers dmcu_regs = {
 161                 DMCU_DCE110_COMMON_REG_LIST()
 162 };
 163
 164 static const struct dce_dmcu_shift dmcu_shift = {
 165                 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
 166 };
 167
 168 static const struct dce_dmcu_mask dmcu_mask = {
 169                 DMCU_MASK_SH_LIST_DCE110(_MASK)
 170 };
 171
 172 static const struct dce_abm_registers abm_regs = {
 173                 ABM_DCE110_COMMON_REG_LIST()
 174 };
 175
 176 static const struct dce_abm_shift abm_shift = {
 177                 ABM_MASK_SH_LIST_DCE110(__SHIFT)
 178 };
 179
 180 static const struct dce_abm_mask abm_mask = {
 181                 ABM_MASK_SH_LIST_DCE110(_MASK)
 182 };
 183
 184 #define ipp_regs(id)\
 185 [id] = {\
 186                 IPP_DCE110_REG_LIST_DCE_BASE(id)\
 187 }
 188
 189 static const struct dce_ipp_registers ipp_regs[] = {
 190                 ipp_regs(0),
 191                 ipp_regs(1),
 192                 ipp_regs(2)
 193 };
 194
 195 static const struct dce_ipp_shift ipp_shift = {
 196                 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 197 };
 198
 199 static const struct dce_ipp_mask ipp_mask = {
 200                 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 201 };
 202
 203 #define transform_regs(id)\
 204 [id] = {\
 205                 XFM_COMMON_REG_LIST_DCE110(id)\
 206 }
 207
 208 static const struct dce_transform_registers xfm_regs[] = {
 209                 transform_regs(0),
 210                 transform_regs(1),
 211                 transform_regs(2)
 212 };
 213
 214 static const struct dce_transform_shift xfm_shift = {
 215                 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
 216 };
 217
 218 static const struct dce_transform_mask xfm_mask = {
 219                 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
 220 };
 221
 222 #define aux_regs(id)\
 223 [id] = {\
 224         AUX_REG_LIST(id)\
 225 }
 226
 227 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
 228                 aux_regs(0),
 229                 aux_regs(1),
 230                 aux_regs(2),
 231                 aux_regs(3),
 232                 aux_regs(4),
 233                 aux_regs(5)
 234 };
 235
 236 #define hpd_regs(id)\
 237 [id] = {\
 238         HPD_REG_LIST(id)\
 239 }
 240
 241 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
 242                 hpd_regs(0),
 243                 hpd_regs(1),
 244                 hpd_regs(2),
 245                 hpd_regs(3),
 246                 hpd_regs(4),
 247                 hpd_regs(5)
 248 };
 249
 250
 251 #define link_regs(id)\
 252 [id] = {\
 253         LE_DCE110_REG_LIST(id)\
 254 }
 255
 256 static const struct dce110_link_enc_registers link_enc_regs[] = {
 257         link_regs(0),
 258         link_regs(1),
 259         link_regs(2),
 260         link_regs(3),
 261         link_regs(4),
 262         link_regs(5),
 263         link_regs(6),
 264 };
 265
 266 #define stream_enc_regs(id)\
 267 [id] = {\
 268         SE_COMMON_REG_LIST(id),\
 269         .TMDS_CNTL = 0,\
 270 }
 271
 272 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
 273         stream_enc_regs(0),
 274         stream_enc_regs(1),
 275         stream_enc_regs(2)
 276 };
 277
 278 static const struct dce_stream_encoder_shift se_shift = {
 279                 SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
 280 };
 281
 282 static const struct dce_stream_encoder_mask se_mask = {
 283                 SE_COMMON_MASK_SH_LIST_DCE110(_MASK)
 284 };
 285
 286 #define opp_regs(id)\
 287 [id] = {\
 288         OPP_DCE_110_REG_LIST(id),\
 289 }
 290
 291 static const struct dce_opp_registers opp_regs[] = {
 292         opp_regs(0),
 293         opp_regs(1),
 294         opp_regs(2),
 295         opp_regs(3),
 296         opp_regs(4),
 297         opp_regs(5)
 298 };
 299
 300 static const struct dce_opp_shift opp_shift = {
 301         OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT)
 302 };
 303
 304 static const struct dce_opp_mask opp_mask = {
 305         OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK)
 306 };
 307
 308 #define audio_regs(id)\
 309 [id] = {\
 310         AUD_COMMON_REG_LIST(id)\
 311 }
 312
 313 static const struct dce_audio_registers audio_regs[] = {
 314         audio_regs(0),
 315         audio_regs(1),
 316         audio_regs(2),
 317         audio_regs(3),
 318         audio_regs(4),
 319         audio_regs(5),
 320         audio_regs(6),
 321 };
 322
 323 static const struct dce_audio_shift audio_shift = {
 324                 AUD_COMMON_MASK_SH_LIST(__SHIFT)
 325 };
 326
 327 static const struct dce_aduio_mask audio_mask = {
 328                 AUD_COMMON_MASK_SH_LIST(_MASK)
 329 };
 330
 331 /* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */
 332
 333
 334 #define clk_src_regs(id)\
 335 [id] = {\
 336         CS_COMMON_REG_LIST_DCE_100_110(id),\
 337 }
 338
 339 static const struct dce110_clk_src_regs clk_src_regs[] = {
 340         clk_src_regs(0),
 341         clk_src_regs(1),
 342         clk_src_regs(2)
 343 };
 344
 345 static const struct dce110_clk_src_shift cs_shift = {
 346                 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 347 };
 348
 349 static const struct dce110_clk_src_mask cs_mask = {
 350                 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 351 };
 352
 353 static const struct bios_registers bios_regs = {
 354         .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
 355 };
 356
 357 static const struct resource_caps carrizo_resource_cap = {
 358                 .num_timing_generator = 3,
 359                 .num_video_plane = 1,
 360                 .num_audio = 3,
 361                 .num_stream_encoder = 3,
 362                 .num_pll = 2,
 363 };
 364
 365 static const struct resource_caps stoney_resource_cap = {
 366                 .num_timing_generator = 2,
 367                 .num_video_plane = 1,
 368                 .num_audio = 3,
 369                 .num_stream_encoder = 3,
 370                 .num_pll = 2,
 371 };
 372
 373 #define CTX  ctx
 374 #define REG(reg) mm ## reg
 375
 376 #ifndef mmCC_DC_HDMI_STRAPS
 377 #define mmCC_DC_HDMI_STRAPS 0x4819
 378 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
 379 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
 380 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
 381 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
 382 #endif
 383
 384 static void read_dce_straps(
 385         struct dc_context *ctx,
 386         struct resource_straps *straps)
 387 {
 388         REG_GET_2(CC_DC_HDMI_STRAPS,
 389                         HDMI_DISABLE, &straps->hdmi_disable,
 390                         AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
 391
 392         REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
 393 }
 394
 395 static struct audio *create_audio(
 396                 struct dc_context *ctx, unsigned int inst)
 397 {
 398         return dce_audio_create(ctx, inst,
 399                         &audio_regs[inst], &audio_shift, &audio_mask);
 400 }
 401
 402 static struct timing_generator *dce110_timing_generator_create(
 403                 struct dc_context *ctx,
 404                 uint32_t instance,
 405                 const struct dce110_timing_generator_offsets *offsets)
 406 {
 407         struct dce110_timing_generator *tg110 =
 408                 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
 409
 410         if (!tg110)
 411                 return NULL;
 412
 413         dce110_timing_generator_construct(tg110, ctx, instance, offsets);
 414         return &tg110->base;
 415 }
 416
 417 static struct stream_encoder *dce110_stream_encoder_create(
 418         enum engine_id eng_id,
 419         struct dc_context *ctx)
 420 {
 421         struct dce110_stream_encoder *enc110 =
 422                 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
 423
 424         if (!enc110)
 425                 return NULL;
 426
 427         dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
 428                                         &stream_enc_regs[eng_id],
 429                                         &se_shift, &se_mask);
 430         return &enc110->base;
 431 }
 432
 433 #define SRII(reg_name, block, id)\
 434         .reg_name[id] = mm ## block ## id ## _ ## reg_name
 435
 436 static const struct dce_hwseq_registers hwseq_stoney_reg = {
 437                 HWSEQ_ST_REG_LIST()
 438 };
 439
 440 static const struct dce_hwseq_registers hwseq_cz_reg = {
 441                 HWSEQ_CZ_REG_LIST()
 442 };
 443
 444 static const struct dce_hwseq_shift hwseq_shift = {
 445                 HWSEQ_DCE11_MASK_SH_LIST(__SHIFT),
 446 };
 447
 448 static const struct dce_hwseq_mask hwseq_mask = {
 449                 HWSEQ_DCE11_MASK_SH_LIST(_MASK),
 450 };
 451
 452 static struct dce_hwseq *dce110_hwseq_create(
 453         struct dc_context *ctx)
 454 {
 455         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
 456
 457         if (hws) {
 458                 hws->ctx = ctx;
 459                 hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ?
 460                                 &hwseq_stoney_reg : &hwseq_cz_reg;
 461                 hws->shifts = &hwseq_shift;
 462                 hws->masks = &hwseq_mask;
 463                 hws->wa.blnd_crtc_trigger = true;
 464         }
 465         return hws;
 466 }
 467
 468 static const struct resource_create_funcs res_create_funcs = {
 469         .read_dce_straps = read_dce_straps,
 470         .create_audio = create_audio,
 471         .create_stream_encoder = dce110_stream_encoder_create,
 472         .create_hwseq = dce110_hwseq_create,
 473 };
 474
 475 #define mi_inst_regs(id) { \
 476         MI_DCE11_REG_LIST(id), \
 477         .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
 478 }
 479 static const struct dce_mem_input_registers mi_regs[] = {
 480                 mi_inst_regs(0),
 481                 mi_inst_regs(1),
 482                 mi_inst_regs(2),
 483 };
 484
 485 static const struct dce_mem_input_shift mi_shifts = {
 486                 MI_DCE11_MASK_SH_LIST(__SHIFT),
 487                 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
 488 };
 489
 490 static const struct dce_mem_input_mask mi_masks = {
 491                 MI_DCE11_MASK_SH_LIST(_MASK),
 492                 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
 493 };
 494
 495
 496 static struct mem_input *dce110_mem_input_create(
 497         struct dc_context *ctx,
 498         uint32_t inst)
 499 {
 500         struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
 501                                                GFP_KERNEL);
 502
 503         if (!dce_mi) {
 504                 BREAK_TO_DEBUGGER();
 505                 return NULL;
 506         }
 507
 508         dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
 509         dce_mi->wa.single_head_rdreq_dmif_limit = 3;
 510         return &dce_mi->base;
 511 }
 512
 513 static void dce110_transform_destroy(struct transform **xfm)
 514 {
 515         kfree(TO_DCE_TRANSFORM(*xfm));
 516         *xfm = NULL;
 517 }
 518
 519 static struct transform *dce110_transform_create(
 520         struct dc_context *ctx,
 521         uint32_t inst)
 522 {
 523         struct dce_transform *transform =
 524                 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
 525
 526         if (!transform)
 527                 return NULL;
 528
 529         dce_transform_construct(transform, ctx, inst,
 530                                 &xfm_regs[inst], &xfm_shift, &xfm_mask);
 531         return &transform->base;
 532 }
 533
 534 static struct input_pixel_processor *dce110_ipp_create(
 535         struct dc_context *ctx, uint32_t inst)
 536 {
 537         struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
 538
 539         if (!ipp) {
 540                 BREAK_TO_DEBUGGER();
 541                 return NULL;
 542         }
 543
 544         dce_ipp_construct(ipp, ctx, inst,
 545                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 546         return &ipp->base;
 547 }
 548
 549 static const struct encoder_feature_support link_enc_feature = {
 550                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
 551                 .max_hdmi_pixel_clock = 594000,
 552                 .flags.bits.IS_HBR2_CAPABLE = true,
 553                 .flags.bits.IS_TPS3_CAPABLE = true,
 554                 .flags.bits.IS_YCBCR_CAPABLE = true
 555 };
 556
 557 static struct link_encoder *dce110_link_encoder_create(
 558         const struct encoder_init_data *enc_init_data)
 559 {
 560         struct dce110_link_encoder *enc110 =
 561                 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
 562
 563         if (!enc110)
 564                 return NULL;
 565
 566         dce110_link_encoder_construct(enc110,
 567                                       enc_init_data,
 568                                       &link_enc_feature,
 569                                       &link_enc_regs[enc_init_data->transmitter],
 570                                       &link_enc_aux_regs[enc_init_data->channel - 1],
 571                                       &link_enc_hpd_regs[enc_init_data->hpd_source]);
 572         return &enc110->base;
 573 }
 574
 575 static struct output_pixel_processor *dce110_opp_create(
 576         struct dc_context *ctx,
 577         uint32_t inst)
 578 {
 579         struct dce110_opp *opp =
 580                 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
 581
 582         if (!opp)
 583                 return NULL;
 584
 585         dce110_opp_construct(opp,
 586                              ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
 587         return &opp->base;
 588 }
 589
 590 struct clock_source *dce110_clock_source_create(
 591         struct dc_context *ctx,
 592         struct dc_bios *bios,
 593         enum clock_source_id id,
 594         const struct dce110_clk_src_regs *regs,
 595         bool dp_clk_src)
 596 {
 597         struct dce110_clk_src *clk_src =
 598                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 599
 600         if (!clk_src)
 601                 return NULL;
 602
 603         if (dce110_clk_src_construct(clk_src, ctx, bios, id,
 604                         regs, &cs_shift, &cs_mask)) {
 605                 clk_src->base.dp_clk_src = dp_clk_src;
 606                 return &clk_src->base;
 607         }
 608
 609         BREAK_TO_DEBUGGER();
 610         return NULL;
 611 }
 612
 613 void dce110_clock_source_destroy(struct clock_source **clk_src)
 614 {
 615         struct dce110_clk_src *dce110_clk_src;
 616
 617         if (!clk_src)
 618                 return;
 619
 620         dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src);
 621
 622         kfree(dce110_clk_src->dp_ss_params);
 623         kfree(dce110_clk_src->hdmi_ss_params);
 624         kfree(dce110_clk_src->dvi_ss_params);
 625
 626         kfree(dce110_clk_src);
 627         *clk_src = NULL;
 628 }
 629
 630 static void destruct(struct dce110_resource_pool *pool)
 631 {
 632         unsigned int i;
 633
 634         for (i = 0; i < pool->base.pipe_count; i++) {
 635                 if (pool->base.opps[i] != NULL)
 636                         dce110_opp_destroy(&pool->base.opps[i]);
 637
 638                 if (pool->base.transforms[i] != NULL)
 639                         dce110_transform_destroy(&pool->base.transforms[i]);
 640
 641                 if (pool->base.ipps[i] != NULL)
 642                         dce_ipp_destroy(&pool->base.ipps[i]);
 643
 644                 if (pool->base.mis[i] != NULL) {
 645                         kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
 646                         pool->base.mis[i] = NULL;
 647                 }
 648
 649                 if (pool->base.timing_generators[i] != NULL)    {
 650                         kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
 651                         pool->base.timing_generators[i] = NULL;
 652                 }
 653         }
 654
 655         for (i = 0; i < pool->base.stream_enc_count; i++) {
 656                 if (pool->base.stream_enc[i] != NULL)
 657                         kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 658         }
 659
 660         for (i = 0; i < pool->base.clk_src_count; i++) {
 661                 if (pool->base.clock_sources[i] != NULL) {
 662                         dce110_clock_source_destroy(&pool->base.clock_sources[i]);
 663                 }
 664         }
 665
 666         if (pool->base.dp_clock_source != NULL)
 667                 dce110_clock_source_destroy(&pool->base.dp_clock_source);
 668
 669         for (i = 0; i < pool->base.audio_count; i++)    {
 670                 if (pool->base.audios[i] != NULL) {
 671                         dce_aud_destroy(&pool->base.audios[i]);
 672                 }
 673         }
 674
 675         if (pool->base.abm != NULL)
 676                 dce_abm_destroy(&pool->base.abm);
 677
 678         if (pool->base.dmcu != NULL)
 679                 dce_dmcu_destroy(&pool->base.dmcu);
 680
 681         if (pool->base.display_clock != NULL)
 682                 dce_disp_clk_destroy(&pool->base.display_clock);
 683
 684         if (pool->base.irqs != NULL) {
 685                 dal_irq_service_destroy(&pool->base.irqs);
 686         }
 687 }
 688
 689
 690 static void get_pixel_clock_parameters(
 691         const struct pipe_ctx *pipe_ctx,
 692         struct pixel_clk_params *pixel_clk_params)
 693 {
 694         const struct dc_stream_state *stream = pipe_ctx->stream;
 695
 696         /*TODO: is this halved for YCbCr 420? in that case we might want to move
 697          * the pixel clock normalization for hdmi up to here instead of doing it
 698          * in pll_adjust_pix_clk
 699          */
 700         pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz;
 701         pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
 702         pixel_clk_params->signal_type = pipe_ctx->stream->signal;
 703         pixel_clk_params->controller_id = pipe_ctx->pipe_idx + 1;
 704         /* TODO: un-hardcode*/
 705         pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
 706                                                 LINK_RATE_REF_FREQ_IN_KHZ;
 707         pixel_clk_params->flags.ENABLE_SS = 0;
 708         pixel_clk_params->color_depth =
 709                 stream->timing.display_color_depth;
 710         pixel_clk_params->flags.DISPLAY_BLANKED = 1;
 711         pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding ==
 712                         PIXEL_ENCODING_YCBCR420);
 713         pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
 714         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) {
 715                 pixel_clk_params->color_depth = COLOR_DEPTH_888;
 716         }
 717         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
 718                 pixel_clk_params->requested_pix_clk  = pixel_clk_params->requested_pix_clk / 2;
 719         }
 720 }
 721
 722 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
 723 {
 724         get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
 725         pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
 726                 pipe_ctx->clock_source,
 727                 &pipe_ctx->stream_res.pix_clk_params,
 728                 &pipe_ctx->pll_settings);
 729         resource_build_bit_depth_reduction_params(pipe_ctx->stream,
 730                         &pipe_ctx->stream->bit_depth_params);
 731         pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
 732 }
 733
 734 static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx)
 735 {
 736         if (pipe_ctx->pipe_idx != underlay_idx)
 737                 return true;
 738         if (!pipe_ctx->plane_state)
 739                 return false;
 740         if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
 741                 return false;
 742         return true;
 743 }
 744
 745 static enum dc_status build_mapped_resource(
 746                 const struct dc *dc,
 747                 struct dc_state *context,
 748                 struct dc_stream_state *stream)
 749 {
 750         struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
 751
 752         if (!pipe_ctx)
 753                 return DC_ERROR_UNEXPECTED;
 754
 755         if (!is_surface_pixel_format_supported(pipe_ctx,
 756                         dc->res_pool->underlay_pipe_index))
 757                 return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED;
 758
 759         dce110_resource_build_pipe_hw_param(pipe_ctx);
 760
 761         /* TODO: validate audio ASIC caps, encoder */
 762
 763         resource_build_info_frame(pipe_ctx);
 764
 765         return DC_OK;
 766 }
 767
 768 static bool dce110_validate_bandwidth(
 769         struct dc *dc,
 770         struct dc_state *context)
 771 {
 772         bool result = false;
 773
 774         dm_logger_write(
 775                 dc->ctx->logger, LOG_BANDWIDTH_CALCS,
 776                 "%s: start",
 777                 __func__);
 778
 779         if (bw_calcs(
 780                         dc->ctx,
 781                         dc->bw_dceip,
 782                         dc->bw_vbios,
 783                         context->res_ctx.pipe_ctx,
 784                         dc->res_pool->pipe_count,
 785                         &context->bw.dce))
 786                 result =  true;
 787
 788         if (!result)
 789                 dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION,
 790                         "%s: %dx%d@%d Bandwidth validation failed!\n",
 791                         __func__,
 792                         context->streams[0]->timing.h_addressable,
 793                         context->streams[0]->timing.v_addressable,
 794                         context->streams[0]->timing.pix_clk_khz);
 795
 796         if (memcmp(&dc->current_state->bw.dce,
 797                         &context->bw.dce, sizeof(context->bw.dce))) {
 798                 struct log_entry log_entry;
 799                 dm_logger_open(
 800                         dc->ctx->logger,
 801                         &log_entry,
 802                         LOG_BANDWIDTH_CALCS);
 803                 dm_logger_append(&log_entry, "%s: finish,\n"
 804                         "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
 805                         "stutMark_b: %d stutMark_a: %d\n",
 806                         __func__,
 807                         context->bw.dce.nbp_state_change_wm_ns[0].b_mark,
 808                         context->bw.dce.nbp_state_change_wm_ns[0].a_mark,
 809                         context->bw.dce.urgent_wm_ns[0].b_mark,
 810                         context->bw.dce.urgent_wm_ns[0].a_mark,
 811                         context->bw.dce.stutter_exit_wm_ns[0].b_mark,
 812                         context->bw.dce.stutter_exit_wm_ns[0].a_mark);
 813                 dm_logger_append(&log_entry,
 814                         "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
 815                         "stutMark_b: %d stutMark_a: %d\n",
 816                         context->bw.dce.nbp_state_change_wm_ns[1].b_mark,
 817                         context->bw.dce.nbp_state_change_wm_ns[1].a_mark,
 818                         context->bw.dce.urgent_wm_ns[1].b_mark,
 819                         context->bw.dce.urgent_wm_ns[1].a_mark,
 820                         context->bw.dce.stutter_exit_wm_ns[1].b_mark,
 821                         context->bw.dce.stutter_exit_wm_ns[1].a_mark);
 822                 dm_logger_append(&log_entry,
 823                         "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
 824                         "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n",
 825                         context->bw.dce.nbp_state_change_wm_ns[2].b_mark,
 826                         context->bw.dce.nbp_state_change_wm_ns[2].a_mark,
 827                         context->bw.dce.urgent_wm_ns[2].b_mark,
 828                         context->bw.dce.urgent_wm_ns[2].a_mark,
 829                         context->bw.dce.stutter_exit_wm_ns[2].b_mark,
 830                         context->bw.dce.stutter_exit_wm_ns[2].a_mark,
 831                         context->bw.dce.stutter_mode_enable);
 832                 dm_logger_append(&log_entry,
 833                         "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
 834                         "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n",
 835                         context->bw.dce.cpuc_state_change_enable,
 836                         context->bw.dce.cpup_state_change_enable,
 837                         context->bw.dce.nbp_state_change_enable,
 838                         context->bw.dce.all_displays_in_sync,
 839                         context->bw.dce.dispclk_khz,
 840                         context->bw.dce.sclk_khz,
 841                         context->bw.dce.sclk_deep_sleep_khz,
 842                         context->bw.dce.yclk_khz,
 843                         context->bw.dce.blackout_recovery_time_us);
 844                 dm_logger_close(&log_entry);
 845         }
 846         return result;
 847 }
 848
 849 static bool dce110_validate_surface_sets(
 850                 struct dc_state *context)
 851 {
 852         int i, j;
 853
 854         for (i = 0; i < context->stream_count; i++) {
 855                 if (context->stream_status[i].plane_count == 0)
 856                         continue;
 857
 858                 if (context->stream_status[i].plane_count > 2)
 859                         return false;
 860
 861                 for (j = 0; j < context->stream_status[i].plane_count; j++) {
 862                         struct dc_plane_state *plane =
 863                                 context->stream_status[i].plane_states[j];
 864
 865                         /* underlay validation */
 866                         if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
 867
 868                                 if ((plane->src_rect.width > 1920 ||
 869                                         plane->src_rect.height > 1080))
 870                                         return false;
 871
 872                                 /* irrespective of plane format,
 873                                  * stream should be RGB encoded
 874                                  */
 875                                 if (context->streams[i]->timing.pixel_encoding
 876                                                 != PIXEL_ENCODING_RGB)
 877                                         return false;
 878
 879                         }
 880
 881                 }
 882         }
 883
 884         return true;
 885 }
 886
 887 enum dc_status dce110_validate_global(
 888                 struct dc *dc,
 889                 struct dc_state *context)
 890 {
 891         if (!dce110_validate_surface_sets(context))
 892                 return DC_FAIL_SURFACE_VALIDATE;
 893
 894         return DC_OK;
 895 }
 896
 897 static enum dc_status dce110_add_stream_to_ctx(
 898                 struct dc *dc,
 899                 struct dc_state *new_ctx,
 900                 struct dc_stream_state *dc_stream)
 901 {
 902         enum dc_status result = DC_ERROR_UNEXPECTED;
 903
 904         result = resource_map_pool_resources(dc, new_ctx, dc_stream);
 905
 906         if (result == DC_OK)
 907                 result = resource_map_clock_resources(dc, new_ctx, dc_stream);
 908
 909
 910         if (result == DC_OK)
 911                 result = build_mapped_resource(dc, new_ctx, dc_stream);
 912
 913         return result;
 914 }
 915
 916 static enum dc_status dce110_validate_guaranteed(
 917                 struct dc *dc,
 918                 struct dc_stream_state *dc_stream,
 919                 struct dc_state *context)
 920 {
 921         enum dc_status result = DC_ERROR_UNEXPECTED;
 922
 923         context->streams[0] = dc_stream;
 924         dc_stream_retain(context->streams[0]);
 925         context->stream_count++;
 926
 927         result = resource_map_pool_resources(dc, context, dc_stream);
 928
 929         if (result == DC_OK)
 930                 result = resource_map_clock_resources(dc, context, dc_stream);
 931
 932         if (result == DC_OK)
 933                 result = build_mapped_resource(dc, context, dc_stream);
 934
 935         if (result == DC_OK) {
 936                 validate_guaranteed_copy_streams(
 937                                 context, dc->caps.max_streams);
 938                 result = resource_build_scaling_params_for_context(dc, context);
 939         }
 940
 941         if (result == DC_OK)
 942                 if (!dce110_validate_bandwidth(dc, context))
 943                         result = DC_FAIL_BANDWIDTH_VALIDATE;
 944
 945         return result;
 946 }
 947
 948 static struct pipe_ctx *dce110_acquire_underlay(
 949                 struct dc_state *context,
 950                 const struct resource_pool *pool,
 951                 struct dc_stream_state *stream)
 952 {
 953         struct dc *dc = stream->ctx->dc;
 954         struct resource_context *res_ctx = &context->res_ctx;
 955         unsigned int underlay_idx = pool->underlay_pipe_index;
 956         struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx];
 957
 958         if (res_ctx->pipe_ctx[underlay_idx].stream)
 959                 return NULL;
 960
 961         pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx];
 962         pipe_ctx->plane_res.mi = pool->mis[underlay_idx];
 963         /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/
 964         pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx];
 965         pipe_ctx->stream_res.opp = pool->opps[underlay_idx];
 966         pipe_ctx->pipe_idx = underlay_idx;
 967
 968         pipe_ctx->stream = stream;
 969
 970         if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) {
 971                 struct tg_color black_color = {0};
 972                 struct dc_bios *dcb = dc->ctx->dc_bios;
 973
 974                 dc->hwss.enable_display_power_gating(
 975                                 dc,
 976                                 pipe_ctx->pipe_idx,
 977                                 dcb, PIPE_GATING_CONTROL_DISABLE);
 978
 979                 /*
 980                  * This is for powering on underlay, so crtc does not
 981                  * need to be enabled
 982                  */
 983
 984                 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg,
 985                                 &stream->timing,
 986                                 false);
 987
 988                 pipe_ctx->stream_res.tg->funcs->enable_advanced_request(
 989                                 pipe_ctx->stream_res.tg,
 990                                 true,
 991                                 &stream->timing);
 992
 993                 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi,
 994                                 stream->timing.h_total,
 995                                 stream->timing.v_total,
 996                                 stream->timing.pix_clk_khz,
 997                                 context->stream_count);
 998
 999                 color_space_to_black_color(dc,
1000                                 COLOR_SPACE_YCBCR601, &black_color);
1001                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1002                                 pipe_ctx->stream_res.tg,
1003                                 &black_color);
1004         }
1005
1006         return pipe_ctx;
1007 }
1008
1009 static void dce110_destroy_resource_pool(struct resource_pool **pool)
1010 {
1011         struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
1012
1013         destruct(dce110_pool);
1014         kfree(dce110_pool);
1015         *pool = NULL;
1016 }
1017
1018
1019 static const struct resource_funcs dce110_res_pool_funcs = {
1020         .destroy = dce110_destroy_resource_pool,
1021         .link_enc_create = dce110_link_encoder_create,
1022         .validate_guaranteed = dce110_validate_guaranteed,
1023         .validate_bandwidth = dce110_validate_bandwidth,
1024         .acquire_idle_pipe_for_layer = dce110_acquire_underlay,
1025         .add_stream_to_ctx = dce110_add_stream_to_ctx,
1026         .validate_global = dce110_validate_global
1027 };
1028
1029 static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool)
1030 {
1031         struct dce110_timing_generator *dce110_tgv = kzalloc(sizeof(*dce110_tgv),
1032                                                              GFP_KERNEL);
1033         struct dce_transform *dce110_xfmv = kzalloc(sizeof(*dce110_xfmv),
1034                                                     GFP_KERNEL);
1035         struct dce_mem_input *dce110_miv = kzalloc(sizeof(*dce110_miv),
1036                                                    GFP_KERNEL);
1037         struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv),
1038                                                  GFP_KERNEL);
1039
1040         if (!dce110_tgv || !dce110_xfmv || !dce110_miv || !dce110_oppv) {
1041                 kfree(dce110_tgv);
1042                 kfree(dce110_xfmv);
1043                 kfree(dce110_miv);
1044                 kfree(dce110_oppv);
1045                 return false;
1046         }
1047
1048         dce110_opp_v_construct(dce110_oppv, ctx);
1049
1050         dce110_timing_generator_v_construct(dce110_tgv, ctx);
1051         dce110_mem_input_v_construct(dce110_miv, ctx);
1052         dce110_transform_v_construct(dce110_xfmv, ctx);
1053
1054         pool->opps[pool->pipe_count] = &dce110_oppv->base;
1055         pool->timing_generators[pool->pipe_count] = &dce110_tgv->base;
1056         pool->mis[pool->pipe_count] = &dce110_miv->base;
1057         pool->transforms[pool->pipe_count] = &dce110_xfmv->base;
1058         pool->pipe_count++;
1059
1060         /* update the public caps to indicate an underlay is available */
1061         ctx->dc->caps.max_slave_planes = 1;
1062         ctx->dc->caps.max_slave_planes = 1;
1063
1064         return true;
1065 }
1066
1067 static void bw_calcs_data_update_from_pplib(struct dc *dc)
1068 {
1069         struct dm_pp_clock_levels clks = {0};
1070
1071         /*do system clock*/
1072         dm_pp_get_clock_levels_by_type(
1073                         dc->ctx,
1074                         DM_PP_CLOCK_TYPE_ENGINE_CLK,
1075                         &clks);
1076         /* convert all the clock fro kHz to fix point mHz */
1077         dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1078                         clks.clocks_in_khz[clks.num_levels-1], 1000);
1079         dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
1080                         clks.clocks_in_khz[clks.num_levels/8], 1000);
1081         dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
1082                         clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1083         dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
1084                         clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1085         dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
1086                         clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1087         dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
1088                         clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1089         dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
1090                         clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1091         dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
1092                         clks.clocks_in_khz[0], 1000);
1093         dc->sclk_lvls = clks;
1094
1095         /*do display clock*/
1096         dm_pp_get_clock_levels_by_type(
1097                         dc->ctx,
1098                         DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1099                         &clks);
1100         dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed(
1101                         clks.clocks_in_khz[clks.num_levels-1], 1000);
1102         dc->bw_vbios->mid_voltage_max_dispclk  = bw_frc_to_fixed(
1103                         clks.clocks_in_khz[clks.num_levels>>1], 1000);
1104         dc->bw_vbios->low_voltage_max_dispclk  = bw_frc_to_fixed(
1105                         clks.clocks_in_khz[0], 1000);
1106
1107         /*do memory clock*/
1108         dm_pp_get_clock_levels_by_type(
1109                         dc->ctx,
1110                         DM_PP_CLOCK_TYPE_MEMORY_CLK,
1111                         &clks);
1112
1113         dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1114                 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000);
1115         dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1116                 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER,
1117                 1000);
1118         dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1119                 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER,
1120                 1000);
1121 }
1122
1123 const struct resource_caps *dce110_resource_cap(
1124         struct hw_asic_id *asic_id)
1125 {
1126         if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev))
1127                 return &stoney_resource_cap;
1128         else
1129                 return &carrizo_resource_cap;
1130 }
1131
1132 static bool construct(
1133         uint8_t num_virtual_links,
1134         struct dc *dc,
1135         struct dce110_resource_pool *pool,
1136         struct hw_asic_id asic_id)
1137 {
1138         unsigned int i;
1139         struct dc_context *ctx = dc->ctx;
1140         struct dc_firmware_info info;
1141         struct dc_bios *bp;
1142         struct dm_pp_static_clock_info static_clk_info = {0};
1143
1144         ctx->dc_bios->regs = &bios_regs;
1145
1146         pool->base.res_cap = dce110_resource_cap(&ctx->asic_id);
1147         pool->base.funcs = &dce110_res_pool_funcs;
1148
1149         /*************************************************
1150          *  Resource + asic cap harcoding                *
1151          *************************************************/
1152
1153         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1154         pool->base.underlay_pipe_index = pool->base.pipe_count;
1155
1156         dc->caps.max_downscale_ratio = 150;
1157         dc->caps.i2c_speed_in_khz = 100;
1158         dc->caps.max_cursor_size = 128;
1159
1160         /*************************************************
1161          *  Create resources                             *
1162          *************************************************/
1163
1164         bp = ctx->dc_bios;
1165
1166         if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
1167                 info.external_clock_source_frequency_for_dp != 0) {
1168                 pool->base.dp_clock_source =
1169                                 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1170
1171                 pool->base.clock_sources[0] =
1172                                 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0,
1173                                                 &clk_src_regs[0], false);
1174                 pool->base.clock_sources[1] =
1175                                 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1,
1176                                                 &clk_src_regs[1], false);
1177
1178                 pool->base.clk_src_count = 2;
1179
1180                 /* TODO: find out if CZ support 3 PLLs */
1181         }
1182
1183         if (pool->base.dp_clock_source == NULL) {
1184                 dm_error("DC: failed to create dp clock source!\n");
1185                 BREAK_TO_DEBUGGER();
1186                 goto res_create_fail;
1187         }
1188
1189         for (i = 0; i < pool->base.clk_src_count; i++) {
1190                 if (pool->base.clock_sources[i] == NULL) {
1191                         dm_error("DC: failed to create clock sources!\n");
1192                         BREAK_TO_DEBUGGER();
1193                         goto res_create_fail;
1194                 }
1195         }
1196
1197         pool->base.display_clock = dce110_disp_clk_create(ctx,
1198                         &disp_clk_regs,
1199                         &disp_clk_shift,
1200                         &disp_clk_mask);
1201         if (pool->base.display_clock == NULL) {
1202                 dm_error("DC: failed to create display clock!\n");
1203                 BREAK_TO_DEBUGGER();
1204                 goto res_create_fail;
1205         }
1206
1207         pool->base.dmcu = dce_dmcu_create(ctx,
1208                         &dmcu_regs,
1209                         &dmcu_shift,
1210                         &dmcu_mask);
1211         if (pool->base.dmcu == NULL) {
1212                 dm_error("DC: failed to create dmcu!\n");
1213                 BREAK_TO_DEBUGGER();
1214                 goto res_create_fail;
1215         }
1216
1217         pool->base.abm = dce_abm_create(ctx,
1218                         &abm_regs,
1219                         &abm_shift,
1220                         &abm_mask);
1221         if (pool->base.abm == NULL) {
1222                 dm_error("DC: failed to create abm!\n");
1223                 BREAK_TO_DEBUGGER();
1224                 goto res_create_fail;
1225         }
1226
1227         /* get static clock information for PPLIB or firmware, save
1228          * max_clock_state
1229          */
1230         if (dm_pp_get_static_clocks(ctx, &static_clk_info))
1231                 pool->base.display_clock->max_clks_state =
1232                                 static_clk_info.max_clocks_state;
1233
1234         {
1235                 struct irq_service_init_data init_data;
1236                 init_data.ctx = dc->ctx;
1237                 pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1238                 if (!pool->base.irqs)
1239                         goto res_create_fail;
1240         }
1241
1242         for (i = 0; i < pool->base.pipe_count; i++) {
1243                 pool->base.timing_generators[i] = dce110_timing_generator_create(
1244                                 ctx, i, &dce110_tg_offsets[i]);
1245                 if (pool->base.timing_generators[i] == NULL) {
1246                         BREAK_TO_DEBUGGER();
1247                         dm_error("DC: failed to create tg!\n");
1248                         goto res_create_fail;
1249                 }
1250
1251                 pool->base.mis[i] = dce110_mem_input_create(ctx, i);
1252                 if (pool->base.mis[i] == NULL) {
1253                         BREAK_TO_DEBUGGER();
1254                         dm_error(
1255                                 "DC: failed to create memory input!\n");
1256                         goto res_create_fail;
1257                 }
1258
1259                 pool->base.ipps[i] = dce110_ipp_create(ctx, i);
1260                 if (pool->base.ipps[i] == NULL) {
1261                         BREAK_TO_DEBUGGER();
1262                         dm_error(
1263                                 "DC: failed to create input pixel processor!\n");
1264                         goto res_create_fail;
1265                 }
1266
1267                 pool->base.transforms[i] = dce110_transform_create(ctx, i);
1268                 if (pool->base.transforms[i] == NULL) {
1269                         BREAK_TO_DEBUGGER();
1270                         dm_error(
1271                                 "DC: failed to create transform!\n");
1272                         goto res_create_fail;
1273                 }
1274
1275                 pool->base.opps[i] = dce110_opp_create(ctx, i);
1276                 if (pool->base.opps[i] == NULL) {
1277                         BREAK_TO_DEBUGGER();
1278                         dm_error(
1279                                 "DC: failed to create output pixel processor!\n");
1280                         goto res_create_fail;
1281                 }
1282         }
1283
1284 #if defined(CONFIG_DRM_AMD_DC_FBC)
1285         dc->fbc_compressor = dce110_compressor_create(ctx);
1286
1287
1288
1289 #endif
1290         if (!underlay_create(ctx, &pool->base))
1291                 goto res_create_fail;
1292
1293         if (!resource_construct(num_virtual_links, dc, &pool->base,
1294                         &res_create_funcs))
1295                 goto res_create_fail;
1296
1297         /* Create hardware sequencer */
1298         dce110_hw_sequencer_construct(dc);
1299
1300         dc->caps.max_planes =  pool->base.pipe_count;
1301
1302         bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1303
1304         bw_calcs_data_update_from_pplib(dc);
1305
1306         return true;
1307
1308 res_create_fail:
1309         destruct(pool);
1310         return false;
1311 }
1312
1313 struct resource_pool *dce110_create_resource_pool(
1314         uint8_t num_virtual_links,
1315         struct dc *dc,
1316         struct hw_asic_id asic_id)
1317 {
1318         struct dce110_resource_pool *pool =
1319                 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1320
1321         if (!pool)
1322                 return NULL;
1323
1324         if (construct(num_virtual_links, dc, pool, asic_id))
1325                 return &pool->base;
1326
1327         BREAK_TO_DEBUGGER();
1328         return NULL;
1329 }