drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include "dm_services.h"
  26 #include "dc.h"
  27 #include "dc_bios_types.h"
  28 #include "core_types.h"
  29 #include "core_status.h"
  30 #include "resource.h"
  31 #include "dm_helpers.h"
  32 #include "dce110_hw_sequencer.h"
  33 #include "dce110_timing_generator.h"
  34 #include "dce/dce_hwseq.h"
  35 #include "gpio_service_interface.h"
  36
  37 #if defined(CONFIG_DRM_AMD_DC_FBC)
  38 #include "dce110_compressor.h"
  39 #endif
  40
  41 #include "bios/bios_parser_helper.h"
  42 #include "timing_generator.h"
  43 #include "mem_input.h"
  44 #include "opp.h"
  45 #include "ipp.h"
  46 #include "transform.h"
  47 #include "stream_encoder.h"
  48 #include "link_encoder.h"
  49 #include "link_hwss.h"
  50 #include "clock_source.h"
  51 #include "abm.h"
  52 #include "audio.h"
  53 #include "reg_helper.h"
  54
  55 /* include DCE11 register header files */
  56 #include "dce/dce_11_0_d.h"
  57 #include "dce/dce_11_0_sh_mask.h"
  58 #include "custom_float.h"
  59
  60 /*
  61  * All values are in milliseconds;
  62  * For eDP, after power-up/power/down,
  63  * 300/500 msec max. delay from LCDVCC to black video generation
  64  */
  65 #define PANEL_POWER_UP_TIMEOUT 300
  66 #define PANEL_POWER_DOWN_TIMEOUT 500
  67 #define HPD_CHECK_INTERVAL 10
  68
  69 #define CTX \
  70         hws->ctx
  71 #define REG(reg)\
  72         hws->regs->reg
  73
  74 #undef FN
  75 #define FN(reg_name, field_name) \
  76         hws->shifts->field_name, hws->masks->field_name
  77
  78 struct dce110_hw_seq_reg_offsets {
  79         uint32_t crtc;
  80 };
  81
  82 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
  83 {
  84         .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  85 },
  86 {
  87         .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  88 },
  89 {
  90         .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  91 },
  92 {
  93         .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  94 }
  95 };
  96
  97 #define HW_REG_BLND(reg, id)\
  98         (reg + reg_offsets[id].blnd)
  99
 100 #define HW_REG_CRTC(reg, id)\
 101         (reg + reg_offsets[id].crtc)
 102
 103 #define MAX_WATERMARK 0xFFFF
 104 #define SAFE_NBP_MARK 0x7FFF
 105
 106 /*******************************************************************************
 107  * Private definitions
 108  ******************************************************************************/
 109 /***************************PIPE_CONTROL***********************************/
 110 static void dce110_init_pte(struct dc_context *ctx)
 111 {
 112         uint32_t addr;
 113         uint32_t value = 0;
 114         uint32_t chunk_int = 0;
 115         uint32_t chunk_mul = 0;
 116
 117         addr = mmUNP_DVMM_PTE_CONTROL;
 118         value = dm_read_reg(ctx, addr);
 119
 120         set_reg_field_value(
 121                 value,
 122                 0,
 123                 DVMM_PTE_CONTROL,
 124                 DVMM_USE_SINGLE_PTE);
 125
 126         set_reg_field_value(
 127                 value,
 128                 1,
 129                 DVMM_PTE_CONTROL,
 130                 DVMM_PTE_BUFFER_MODE0);
 131
 132         set_reg_field_value(
 133                 value,
 134                 1,
 135                 DVMM_PTE_CONTROL,
 136                 DVMM_PTE_BUFFER_MODE1);
 137
 138         dm_write_reg(ctx, addr, value);
 139
 140         addr = mmDVMM_PTE_REQ;
 141         value = dm_read_reg(ctx, addr);
 142
 143         chunk_int = get_reg_field_value(
 144                 value,
 145                 DVMM_PTE_REQ,
 146                 HFLIP_PTEREQ_PER_CHUNK_INT);
 147
 148         chunk_mul = get_reg_field_value(
 149                 value,
 150                 DVMM_PTE_REQ,
 151                 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 152
 153         if (chunk_int != 0x4 || chunk_mul != 0x4) {
 154
 155                 set_reg_field_value(
 156                         value,
 157                         255,
 158                         DVMM_PTE_REQ,
 159                         MAX_PTEREQ_TO_ISSUE);
 160
 161                 set_reg_field_value(
 162                         value,
 163                         4,
 164                         DVMM_PTE_REQ,
 165                         HFLIP_PTEREQ_PER_CHUNK_INT);
 166
 167                 set_reg_field_value(
 168                         value,
 169                         4,
 170                         DVMM_PTE_REQ,
 171                         HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 172
 173                 dm_write_reg(ctx, addr, value);
 174         }
 175 }
 176 /**************************************************************************/
 177
 178 static void enable_display_pipe_clock_gating(
 179         struct dc_context *ctx,
 180         bool clock_gating)
 181 {
 182         /*TODO*/
 183 }
 184
 185 static bool dce110_enable_display_power_gating(
 186         struct dc *dc,
 187         uint8_t controller_id,
 188         struct dc_bios *dcb,
 189         enum pipe_gating_control power_gating)
 190 {
 191         enum bp_result bp_result = BP_RESULT_OK;
 192         enum bp_pipe_control_action cntl;
 193         struct dc_context *ctx = dc->ctx;
 194         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
 195
 196         if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
 197                 return true;
 198
 199         if (power_gating == PIPE_GATING_CONTROL_INIT)
 200                 cntl = ASIC_PIPE_INIT;
 201         else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
 202                 cntl = ASIC_PIPE_ENABLE;
 203         else
 204                 cntl = ASIC_PIPE_DISABLE;
 205
 206         if (controller_id == underlay_idx)
 207                 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
 208
 209         if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
 210
 211                 bp_result = dcb->funcs->enable_disp_power_gating(
 212                                                 dcb, controller_id + 1, cntl);
 213
 214                 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
 215                  * by default when command table is called
 216                  *
 217                  * Bios parser accepts controller_id = 6 as indicative of
 218                  * underlay pipe in dce110. But we do not support more
 219                  * than 3.
 220                  */
 221                 if (controller_id < CONTROLLER_ID_MAX - 1)
 222                         dm_write_reg(ctx,
 223                                 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
 224                                 0);
 225         }
 226
 227         if (power_gating != PIPE_GATING_CONTROL_ENABLE)
 228                 dce110_init_pte(ctx);
 229
 230         if (bp_result == BP_RESULT_OK)
 231                 return true;
 232         else
 233                 return false;
 234 }
 235
 236 static void build_prescale_params(struct ipp_prescale_params *prescale_params,
 237                 const struct dc_plane_state *plane_state)
 238 {
 239         prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
 240
 241         switch (plane_state->format) {
 242         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 243         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 244                 prescale_params->scale = 0x2020;
 245                 break;
 246         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 247         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 248                 prescale_params->scale = 0x2008;
 249                 break;
 250         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 251         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 252                 prescale_params->scale = 0x2000;
 253                 break;
 254         default:
 255                 ASSERT(false);
 256                 break;
 257         }
 258 }
 259
 260 static bool dce110_set_input_transfer_func(
 261         struct pipe_ctx *pipe_ctx,
 262         const struct dc_plane_state *plane_state)
 263 {
 264         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
 265         const struct dc_transfer_func *tf = NULL;
 266         struct ipp_prescale_params prescale_params = { 0 };
 267         bool result = true;
 268
 269         if (ipp == NULL)
 270                 return false;
 271
 272         if (plane_state->in_transfer_func)
 273                 tf = plane_state->in_transfer_func;
 274
 275         build_prescale_params(&prescale_params, plane_state);
 276         ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
 277
 278         if (plane_state->gamma_correction && dce_use_lut(plane_state))
 279                 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
 280
 281         if (tf == NULL) {
 282                 /* Default case if no input transfer function specified */
 283                 ipp->funcs->ipp_set_degamma(ipp,
 284                                 IPP_DEGAMMA_MODE_HW_sRGB);
 285         } else if (tf->type == TF_TYPE_PREDEFINED) {
 286                 switch (tf->tf) {
 287                 case TRANSFER_FUNCTION_SRGB:
 288                         ipp->funcs->ipp_set_degamma(ipp,
 289                                         IPP_DEGAMMA_MODE_HW_sRGB);
 290                         break;
 291                 case TRANSFER_FUNCTION_BT709:
 292                         ipp->funcs->ipp_set_degamma(ipp,
 293                                         IPP_DEGAMMA_MODE_HW_xvYCC);
 294                         break;
 295                 case TRANSFER_FUNCTION_LINEAR:
 296                         ipp->funcs->ipp_set_degamma(ipp,
 297                                         IPP_DEGAMMA_MODE_BYPASS);
 298                         break;
 299                 case TRANSFER_FUNCTION_PQ:
 300                         result = false;
 301                         break;
 302                 default:
 303                         result = false;
 304                         break;
 305                 }
 306         } else if (tf->type == TF_TYPE_BYPASS) {
 307                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 308         } else {
 309                 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
 310                 result = false;
 311         }
 312
 313         return result;
 314 }
 315
 316 static bool convert_to_custom_float(
 317                 struct pwl_result_data *rgb_resulted,
 318                 struct curve_points *arr_points,
 319                 uint32_t hw_points_num)
 320 {
 321         struct custom_float_format fmt;
 322
 323         struct pwl_result_data *rgb = rgb_resulted;
 324
 325         uint32_t i = 0;
 326
 327         fmt.exponenta_bits = 6;
 328         fmt.mantissa_bits = 12;
 329         fmt.sign = true;
 330
 331         if (!convert_to_custom_float_format(
 332                 arr_points[0].x,
 333                 &fmt,
 334                 &arr_points[0].custom_float_x)) {
 335                 BREAK_TO_DEBUGGER();
 336                 return false;
 337         }
 338
 339         if (!convert_to_custom_float_format(
 340                 arr_points[0].offset,
 341                 &fmt,
 342                 &arr_points[0].custom_float_offset)) {
 343                 BREAK_TO_DEBUGGER();
 344                 return false;
 345         }
 346
 347         if (!convert_to_custom_float_format(
 348                 arr_points[0].slope,
 349                 &fmt,
 350                 &arr_points[0].custom_float_slope)) {
 351                 BREAK_TO_DEBUGGER();
 352                 return false;
 353         }
 354
 355         fmt.mantissa_bits = 10;
 356         fmt.sign = false;
 357
 358         if (!convert_to_custom_float_format(
 359                 arr_points[1].x,
 360                 &fmt,
 361                 &arr_points[1].custom_float_x)) {
 362                 BREAK_TO_DEBUGGER();
 363                 return false;
 364         }
 365
 366         if (!convert_to_custom_float_format(
 367                 arr_points[1].y,
 368                 &fmt,
 369                 &arr_points[1].custom_float_y)) {
 370                 BREAK_TO_DEBUGGER();
 371                 return false;
 372         }
 373
 374         if (!convert_to_custom_float_format(
 375                 arr_points[2].slope,
 376                 &fmt,
 377                 &arr_points[2].custom_float_slope)) {
 378                 BREAK_TO_DEBUGGER();
 379                 return false;
 380         }
 381
 382         fmt.mantissa_bits = 12;
 383         fmt.sign = true;
 384
 385         while (i != hw_points_num) {
 386                 if (!convert_to_custom_float_format(
 387                         rgb->red,
 388                         &fmt,
 389                         &rgb->red_reg)) {
 390                         BREAK_TO_DEBUGGER();
 391                         return false;
 392                 }
 393
 394                 if (!convert_to_custom_float_format(
 395                         rgb->green,
 396                         &fmt,
 397                         &rgb->green_reg)) {
 398                         BREAK_TO_DEBUGGER();
 399                         return false;
 400                 }
 401
 402                 if (!convert_to_custom_float_format(
 403                         rgb->blue,
 404                         &fmt,
 405                         &rgb->blue_reg)) {
 406                         BREAK_TO_DEBUGGER();
 407                         return false;
 408                 }
 409
 410                 if (!convert_to_custom_float_format(
 411                         rgb->delta_red,
 412                         &fmt,
 413                         &rgb->delta_red_reg)) {
 414                         BREAK_TO_DEBUGGER();
 415                         return false;
 416                 }
 417
 418                 if (!convert_to_custom_float_format(
 419                         rgb->delta_green,
 420                         &fmt,
 421                         &rgb->delta_green_reg)) {
 422                         BREAK_TO_DEBUGGER();
 423                         return false;
 424                 }
 425
 426                 if (!convert_to_custom_float_format(
 427                         rgb->delta_blue,
 428                         &fmt,
 429                         &rgb->delta_blue_reg)) {
 430                         BREAK_TO_DEBUGGER();
 431                         return false;
 432                 }
 433
 434                 ++rgb;
 435                 ++i;
 436         }
 437
 438         return true;
 439 }
 440
 441 static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
 442                 *output_tf, struct pwl_params *regamma_params)
 443 {
 444         struct curve_points *arr_points;
 445         struct pwl_result_data *rgb_resulted;
 446         struct pwl_result_data *rgb;
 447         struct pwl_result_data *rgb_plus_1;
 448         struct fixed31_32 y_r;
 449         struct fixed31_32 y_g;
 450         struct fixed31_32 y_b;
 451         struct fixed31_32 y1_min;
 452         struct fixed31_32 y3_max;
 453
 454         int32_t segment_start, segment_end;
 455         uint32_t i, j, k, seg_distr[16], increment, start_index, hw_points;
 456
 457         if (output_tf == NULL || regamma_params == NULL ||
 458                         output_tf->type == TF_TYPE_BYPASS)
 459                 return false;
 460
 461         arr_points = regamma_params->arr_points;
 462         rgb_resulted = regamma_params->rgb_resulted;
 463         hw_points = 0;
 464
 465         memset(regamma_params, 0, sizeof(struct pwl_params));
 466
 467         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 468                 /* 16 segments
 469                  * segments are from 2^-11 to 2^5
 470                  */
 471                 segment_start = -11;
 472                 segment_end = 5;
 473
 474                 seg_distr[0] = 2;
 475                 seg_distr[1] = 2;
 476                 seg_distr[2] = 2;
 477                 seg_distr[3] = 2;
 478                 seg_distr[4] = 2;
 479                 seg_distr[5] = 2;
 480                 seg_distr[6] = 3;
 481                 seg_distr[7] = 4;
 482                 seg_distr[8] = 4;
 483                 seg_distr[9] = 4;
 484                 seg_distr[10] = 4;
 485                 seg_distr[11] = 5;
 486                 seg_distr[12] = 5;
 487                 seg_distr[13] = 5;
 488                 seg_distr[14] = 5;
 489                 seg_distr[15] = 5;
 490
 491         } else {
 492                 /* 10 segments
 493                  * segment is from 2^-10 to 2^0
 494                  */
 495                 segment_start = -10;
 496                 segment_end = 0;
 497
 498                 seg_distr[0] = 3;
 499                 seg_distr[1] = 4;
 500                 seg_distr[2] = 4;
 501                 seg_distr[3] = 4;
 502                 seg_distr[4] = 4;
 503                 seg_distr[5] = 4;
 504                 seg_distr[6] = 4;
 505                 seg_distr[7] = 4;
 506                 seg_distr[8] = 5;
 507                 seg_distr[9] = 5;
 508                 seg_distr[10] = -1;
 509                 seg_distr[11] = -1;
 510                 seg_distr[12] = -1;
 511                 seg_distr[13] = -1;
 512                 seg_distr[14] = -1;
 513                 seg_distr[15] = -1;
 514         }
 515
 516         for (k = 0; k < 16; k++) {
 517                 if (seg_distr[k] != -1)
 518                         hw_points += (1 << seg_distr[k]);
 519         }
 520
 521         j = 0;
 522         for (k = 0; k < (segment_end - segment_start); k++) {
 523                 increment = 32 / (1 << seg_distr[k]);
 524                 start_index = (segment_start + k + 25) * 32;
 525                 for (i = start_index; i < start_index + 32; i += increment) {
 526                         if (j == hw_points - 1)
 527                                 break;
 528                         rgb_resulted[j].red = output_tf->tf_pts.red[i];
 529                         rgb_resulted[j].green = output_tf->tf_pts.green[i];
 530                         rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
 531                         j++;
 532                 }
 533         }
 534
 535         /* last point */
 536         start_index = (segment_end + 25) * 32;
 537         rgb_resulted[hw_points - 1].red =
 538                         output_tf->tf_pts.red[start_index];
 539         rgb_resulted[hw_points - 1].green =
 540                         output_tf->tf_pts.green[start_index];
 541         rgb_resulted[hw_points - 1].blue =
 542                         output_tf->tf_pts.blue[start_index];
 543
 544         arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
 545                         dal_fixed31_32_from_int(segment_start));
 546         arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
 547                         dal_fixed31_32_from_int(segment_end));
 548         arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
 549                         dal_fixed31_32_from_int(segment_end));
 550
 551         y_r = rgb_resulted[0].red;
 552         y_g = rgb_resulted[0].green;
 553         y_b = rgb_resulted[0].blue;
 554
 555         y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
 556
 557         arr_points[0].y = y1_min;
 558         arr_points[0].slope = dal_fixed31_32_div(
 559                                         arr_points[0].y,
 560                                         arr_points[0].x);
 561
 562         y_r = rgb_resulted[hw_points - 1].red;
 563         y_g = rgb_resulted[hw_points - 1].green;
 564         y_b = rgb_resulted[hw_points - 1].blue;
 565
 566         /* see comment above, m_arrPoints[1].y should be the Y value for the
 567          * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
 568          */
 569         y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
 570
 571         arr_points[1].y = y3_max;
 572         arr_points[2].y = y3_max;
 573
 574         arr_points[1].slope = dal_fixed31_32_zero;
 575         arr_points[2].slope = dal_fixed31_32_zero;
 576
 577         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 578                 /* for PQ, we want to have a straight line from last HW X point,
 579                  * and the slope to be such that we hit 1.0 at 10000 nits.
 580                  */
 581                 const struct fixed31_32 end_value =
 582                                 dal_fixed31_32_from_int(125);
 583
 584                 arr_points[1].slope = dal_fixed31_32_div(
 585                         dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
 586                         dal_fixed31_32_sub(end_value, arr_points[1].x));
 587                 arr_points[2].slope = dal_fixed31_32_div(
 588                         dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
 589                         dal_fixed31_32_sub(end_value, arr_points[1].x));
 590         }
 591
 592         regamma_params->hw_points_num = hw_points;
 593
 594         i = 1;
 595         for (k = 0; k < 16 && i < 16; k++) {
 596                 if (seg_distr[k] != -1) {
 597                         regamma_params->arr_curve_points[k].segments_num =
 598                                         seg_distr[k];
 599                         regamma_params->arr_curve_points[i].offset =
 600                                         regamma_params->arr_curve_points[k].
 601                                         offset + (1 << seg_distr[k]);
 602                 }
 603                 i++;
 604         }
 605
 606         if (seg_distr[k] != -1)
 607                 regamma_params->arr_curve_points[k].segments_num =
 608                                 seg_distr[k];
 609
 610         rgb = rgb_resulted;
 611         rgb_plus_1 = rgb_resulted + 1;
 612
 613         i = 1;
 614
 615         while (i != hw_points + 1) {
 616                 if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
 617                         rgb_plus_1->red = rgb->red;
 618                 if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
 619                         rgb_plus_1->green = rgb->green;
 620                 if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
 621                         rgb_plus_1->blue = rgb->blue;
 622
 623                 rgb->delta_red = dal_fixed31_32_sub(
 624                         rgb_plus_1->red,
 625                         rgb->red);
 626                 rgb->delta_green = dal_fixed31_32_sub(
 627                         rgb_plus_1->green,
 628                         rgb->green);
 629                 rgb->delta_blue = dal_fixed31_32_sub(
 630                         rgb_plus_1->blue,
 631                         rgb->blue);
 632
 633                 ++rgb_plus_1;
 634                 ++rgb;
 635                 ++i;
 636         }
 637
 638         convert_to_custom_float(rgb_resulted, arr_points, hw_points);
 639
 640         return true;
 641 }
 642
 643 static bool dce110_set_output_transfer_func(
 644         struct pipe_ctx *pipe_ctx,
 645         const struct dc_stream_state *stream)
 646 {
 647         struct transform *xfm = pipe_ctx->plane_res.xfm;
 648
 649         xfm->funcs->opp_power_on_regamma_lut(xfm, true);
 650         xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
 651
 652         if (stream->out_transfer_func &&
 653                 stream->out_transfer_func->type ==
 654                         TF_TYPE_PREDEFINED &&
 655                 stream->out_transfer_func->tf ==
 656                         TRANSFER_FUNCTION_SRGB) {
 657                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
 658         } else if (dce110_translate_regamma_to_hw_format(
 659                                 stream->out_transfer_func, &xfm->regamma_params)) {
 660                 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
 661                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
 662         } else {
 663                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
 664         }
 665
 666         xfm->funcs->opp_power_on_regamma_lut(xfm, false);
 667
 668         return true;
 669 }
 670
 671 static enum dc_status bios_parser_crtc_source_select(
 672                 struct pipe_ctx *pipe_ctx)
 673 {
 674         struct dc_bios *dcb;
 675         /* call VBIOS table to set CRTC source for the HW
 676          * encoder block
 677          * note: video bios clears all FMT setting here. */
 678         struct bp_crtc_source_select crtc_source_select = {0};
 679         const struct dc_sink *sink = pipe_ctx->stream->sink;
 680
 681         crtc_source_select.engine_id = pipe_ctx->stream_res.stream_enc->id;
 682         crtc_source_select.controller_id = pipe_ctx->pipe_idx + 1;
 683         /*TODO: Need to un-hardcode color depth, dp_audio and account for
 684          * the case where signal and sink signal is different (translator
 685          * encoder)*/
 686         crtc_source_select.signal = pipe_ctx->stream->signal;
 687         crtc_source_select.enable_dp_audio = false;
 688         crtc_source_select.sink_signal = pipe_ctx->stream->signal;
 689
 690         switch (pipe_ctx->stream->timing.display_color_depth) {
 691         case COLOR_DEPTH_666:
 692                 crtc_source_select.display_output_bit_depth = PANEL_6BIT_COLOR;
 693                 break;
 694         case COLOR_DEPTH_888:
 695                 crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
 696                 break;
 697         case COLOR_DEPTH_101010:
 698                 crtc_source_select.display_output_bit_depth = PANEL_10BIT_COLOR;
 699                 break;
 700         case COLOR_DEPTH_121212:
 701                 crtc_source_select.display_output_bit_depth = PANEL_12BIT_COLOR;
 702                 break;
 703         default:
 704                 BREAK_TO_DEBUGGER();
 705                 crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
 706                 break;
 707         }
 708
 709         dcb = sink->ctx->dc_bios;
 710
 711         if (BP_RESULT_OK != dcb->funcs->crtc_source_select(
 712                 dcb,
 713                 &crtc_source_select)) {
 714                 return DC_ERROR_UNEXPECTED;
 715         }
 716
 717         return DC_OK;
 718 }
 719
 720 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
 721 {
 722         ASSERT(pipe_ctx->stream);
 723
 724         if (pipe_ctx->stream_res.stream_enc == NULL)
 725                 return;  /* this is not root pipe */
 726
 727         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
 728                 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
 729                         pipe_ctx->stream_res.stream_enc,
 730                         &pipe_ctx->stream_res.encoder_info_frame);
 731         else if (dc_is_dp_signal(pipe_ctx->stream->signal))
 732                 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
 733                         pipe_ctx->stream_res.stream_enc,
 734                         &pipe_ctx->stream_res.encoder_info_frame);
 735 }
 736
 737 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
 738 {
 739         enum dc_lane_count lane_count =
 740                 pipe_ctx->stream->sink->link->cur_link_settings.lane_count;
 741
 742         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
 743         struct dc_link *link = pipe_ctx->stream->sink->link;
 744
 745         /* 1. update AVI info frame (HDMI, DP)
 746          * we always need to update info frame
 747         */
 748         uint32_t active_total_with_borders;
 749         uint32_t early_control = 0;
 750         struct timing_generator *tg = pipe_ctx->stream_res.tg;
 751
 752         /* TODOFPGA may change to hwss.update_info_frame */
 753         dce110_update_info_frame(pipe_ctx);
 754         /* enable early control to avoid corruption on DP monitor*/
 755         active_total_with_borders =
 756                         timing->h_addressable
 757                                 + timing->h_border_left
 758                                 + timing->h_border_right;
 759
 760         if (lane_count != 0)
 761                 early_control = active_total_with_borders % lane_count;
 762
 763         if (early_control == 0)
 764                 early_control = lane_count;
 765
 766         tg->funcs->set_early_control(tg, early_control);
 767
 768         /* enable audio only within mode set */
 769         if (pipe_ctx->stream_res.audio != NULL) {
 770                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
 771                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
 772         }
 773
 774         /* For MST, there are multiply stream go to only one link.
 775          * connect DIG back_end to front_end while enable_stream and
 776          * disconnect them during disable_stream
 777          * BY this, it is logic clean to separate stream and link */
 778         link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
 779                                                     pipe_ctx->stream_res.stream_enc->id, true);
 780
 781 }
 782
 783 /*todo: cloned in stream enc, fix*/
 784 static bool is_panel_backlight_on(struct dce_hwseq *hws)
 785 {
 786         uint32_t value;
 787
 788         REG_GET(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, &value);
 789
 790         return value;
 791 }
 792
 793 static bool is_panel_powered_on(struct dce_hwseq *hws)
 794 {
 795         uint32_t value;
 796
 797         REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &value);
 798         return value == 1;
 799 }
 800
 801 static enum bp_result link_transmitter_control(
 802                 struct dc_bios *bios,
 803         struct bp_transmitter_control *cntl)
 804 {
 805         enum bp_result result;
 806
 807         result = bios->funcs->transmitter_control(bios, cntl);
 808
 809         return result;
 810 }
 811
 812 /*
 813  * @brief
 814  * eDP only.
 815  */
 816 void hwss_edp_wait_for_hpd_ready(
 817         struct link_encoder *enc,
 818         bool power_up)
 819 {
 820         struct dc_context *ctx = enc->ctx;
 821         struct graphics_object_id connector = enc->connector;
 822         struct gpio *hpd;
 823         bool edp_hpd_high = false;
 824         uint32_t time_elapsed = 0;
 825         uint32_t timeout = power_up ?
 826                 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
 827
 828         if (dal_graphics_object_id_get_connector_id(connector)
 829                         != CONNECTOR_ID_EDP) {
 830                 BREAK_TO_DEBUGGER();
 831                 return;
 832         }
 833
 834         if (!power_up)
 835                 /*
 836                  * From KV, we will not HPD low after turning off VCC -
 837                  * instead, we will check the SW timer in power_up().
 838                  */
 839                 return;
 840
 841         /*
 842          * When we power on/off the eDP panel,
 843          * we need to wait until SENSE bit is high/low.
 844          */
 845
 846         /* obtain HPD */
 847         /* TODO what to do with this? */
 848         hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);
 849
 850         if (!hpd) {
 851                 BREAK_TO_DEBUGGER();
 852                 return;
 853         }
 854
 855         dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);
 856
 857         /* wait until timeout or panel detected */
 858
 859         do {
 860                 uint32_t detected = 0;
 861
 862                 dal_gpio_get_value(hpd, &detected);
 863
 864                 if (!(detected ^ power_up)) {
 865                         edp_hpd_high = true;
 866                         break;
 867                 }
 868
 869                 msleep(HPD_CHECK_INTERVAL);
 870
 871                 time_elapsed += HPD_CHECK_INTERVAL;
 872         } while (time_elapsed < timeout);
 873
 874         dal_gpio_close(hpd);
 875
 876         dal_gpio_destroy_irq(&hpd);
 877
 878         if (false == edp_hpd_high) {
 879                 dm_logger_write(ctx->logger, LOG_ERROR,
 880                                 "%s: wait timed out!\n", __func__);
 881         }
 882 }
 883
 884 void hwss_edp_power_control(
 885         struct link_encoder *enc,
 886         bool power_up)
 887 {
 888         struct dc_context *ctx = enc->ctx;
 889         struct dce_hwseq *hwseq = ctx->dc->hwseq;
 890         struct bp_transmitter_control cntl = { 0 };
 891         enum bp_result bp_result;
 892
 893
 894         if (dal_graphics_object_id_get_connector_id(enc->connector)
 895                         != CONNECTOR_ID_EDP) {
 896                 BREAK_TO_DEBUGGER();
 897                 return;
 898         }
 899
 900         if (power_up != is_panel_powered_on(hwseq)) {
 901                 /* Send VBIOS command to prompt eDP panel power */
 902
 903                 dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
 904                                 "%s: Panel Power action: %s\n",
 905                                 __func__, (power_up ? "On":"Off"));
 906
 907                 cntl.action = power_up ?
 908                         TRANSMITTER_CONTROL_POWER_ON :
 909                         TRANSMITTER_CONTROL_POWER_OFF;
 910                 cntl.transmitter = enc->transmitter;
 911                 cntl.connector_obj_id = enc->connector;
 912                 cntl.coherent = false;
 913                 cntl.lanes_number = LANE_COUNT_FOUR;
 914                 cntl.hpd_sel = enc->hpd_source;
 915
 916                 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
 917
 918                 if (bp_result != BP_RESULT_OK)
 919                         dm_logger_write(ctx->logger, LOG_ERROR,
 920                                         "%s: Panel Power bp_result: %d\n",
 921                                         __func__, bp_result);
 922         } else {
 923                 dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
 924                                 "%s: Skipping Panel Power action: %s\n",
 925                                 __func__, (power_up ? "On":"Off"));
 926         }
 927
 928         hwss_edp_wait_for_hpd_ready(enc, true);
 929 }
 930
 931 /*todo: cloned in stream enc, fix*/
 932 /*
 933  * @brief
 934  * eDP only. Control the backlight of the eDP panel
 935  */
 936 void hwss_edp_backlight_control(
 937         struct dc_link *link,
 938         bool enable)
 939 {
 940         struct dce_hwseq *hws = link->dc->hwseq;
 941         struct dc_context *ctx = link->dc->ctx;
 942         struct bp_transmitter_control cntl = { 0 };
 943
 944         if (dal_graphics_object_id_get_connector_id(link->link_id)
 945                 != CONNECTOR_ID_EDP) {
 946                 BREAK_TO_DEBUGGER();
 947                 return;
 948         }
 949
 950         if (enable && is_panel_backlight_on(hws)) {
 951                 dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
 952                                 "%s: panel already powered up. Do nothing.\n",
 953                                 __func__);
 954                 return;
 955         }
 956
 957         /* Send VBIOS command to control eDP panel backlight */
 958
 959         dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
 960                         "%s: backlight action: %s\n",
 961                         __func__, (enable ? "On":"Off"));
 962
 963         cntl.action = enable ?
 964                 TRANSMITTER_CONTROL_BACKLIGHT_ON :
 965                 TRANSMITTER_CONTROL_BACKLIGHT_OFF;
 966
 967         /*cntl.engine_id = ctx->engine;*/
 968         cntl.transmitter = link->link_enc->transmitter;
 969         cntl.connector_obj_id = link->link_enc->connector;
 970         /*todo: unhardcode*/
 971         cntl.lanes_number = LANE_COUNT_FOUR;
 972         cntl.hpd_sel = link->link_enc->hpd_source;
 973
 974         /* For eDP, the following delays might need to be considered
 975          * after link training completed:
 976          * idle period - min. accounts for required BS-Idle pattern,
 977          * max. allows for source frame synchronization);
 978          * 50 msec max. delay from valid video data from source
 979          * to video on dislpay or backlight enable.
 980          *
 981          * Disable the delay for now.
 982          * Enable it in the future if necessary.
 983          */
 984         /* dc_service_sleep_in_milliseconds(50); */
 985         link_transmitter_control(link->dc->ctx->dc_bios, &cntl);
 986 }
 987
 988 void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
 989 {
 990         struct dc_stream_state *stream = pipe_ctx->stream;
 991         struct dc_link *link = stream->sink->link;
 992         struct dc *dc = pipe_ctx->stream->ctx->dc;
 993
 994         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
 995                 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
 996                         pipe_ctx->stream_res.stream_enc);
 997
 998         if (dc_is_dp_signal(pipe_ctx->stream->signal))
 999                 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
1000                         pipe_ctx->stream_res.stream_enc);
1001
1002         pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1003                         pipe_ctx->stream_res.stream_enc, true);
1004         if (pipe_ctx->stream_res.audio) {
1005                 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
1006
1007                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1008                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
1009                                         pipe_ctx->stream_res.stream_enc);
1010                 else
1011                         pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(
1012                                         pipe_ctx->stream_res.stream_enc);
1013                 /*don't free audio if it is from retrain or internal disable stream*/
1014                 if (option == FREE_ACQUIRED_RESOURCE && dc->caps.dynamic_audio == true) {
1015                         /*we have to dynamic arbitrate the audio endpoints*/
1016                         pipe_ctx->stream_res.audio = NULL;
1017                         /*we free the resource, need reset is_audio_acquired*/
1018                         update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false);
1019                 }
1020
1021                 /* TODO: notify audio driver for if audio modes list changed
1022                  * add audio mode list change flag */
1023                 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
1024                  * stream->stream_engine_id);
1025                  */
1026         }
1027
1028         /* blank at encoder level */
1029         if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1030                 if (pipe_ctx->stream->sink->link->connector_signal == SIGNAL_TYPE_EDP)
1031                         hwss_edp_backlight_control(link, false);
1032                 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
1033         }
1034         link->link_enc->funcs->connect_dig_be_to_fe(
1035                         link->link_enc,
1036                         pipe_ctx->stream_res.stream_enc->id,
1037                         false);
1038
1039 }
1040
1041 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
1042                 struct dc_link_settings *link_settings)
1043 {
1044         struct encoder_unblank_param params = { { 0 } };
1045         struct dc_link *link = pipe_ctx->stream->sink->link;
1046
1047         /* only 3 items below are used by unblank */
1048         params.pixel_clk_khz =
1049                 pipe_ctx->stream->timing.pix_clk_khz;
1050         params.link_settings.link_rate = link_settings->link_rate;
1051         pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
1052         if (link->connector_signal == SIGNAL_TYPE_EDP)
1053                 hwss_edp_backlight_control(link, true);
1054 }
1055
1056
1057 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
1058 {
1059         if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
1060                 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
1061 }
1062
1063 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
1064 {
1065         switch (crtc_id) {
1066         case CONTROLLER_ID_D0:
1067                 return DTO_SOURCE_ID0;
1068         case CONTROLLER_ID_D1:
1069                 return DTO_SOURCE_ID1;
1070         case CONTROLLER_ID_D2:
1071                 return DTO_SOURCE_ID2;
1072         case CONTROLLER_ID_D3:
1073                 return DTO_SOURCE_ID3;
1074         case CONTROLLER_ID_D4:
1075                 return DTO_SOURCE_ID4;
1076         case CONTROLLER_ID_D5:
1077                 return DTO_SOURCE_ID5;
1078         default:
1079                 return DTO_SOURCE_UNKNOWN;
1080         }
1081 }
1082
1083 static void build_audio_output(
1084         struct dc_state *state,
1085         const struct pipe_ctx *pipe_ctx,
1086         struct audio_output *audio_output)
1087 {
1088         const struct dc_stream_state *stream = pipe_ctx->stream;
1089         audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
1090
1091         audio_output->signal = pipe_ctx->stream->signal;
1092
1093         /* audio_crtc_info  */
1094
1095         audio_output->crtc_info.h_total =
1096                 stream->timing.h_total;
1097
1098         /*
1099          * Audio packets are sent during actual CRTC blank physical signal, we
1100          * need to specify actual active signal portion
1101          */
1102         audio_output->crtc_info.h_active =
1103                         stream->timing.h_addressable
1104                         + stream->timing.h_border_left
1105                         + stream->timing.h_border_right;
1106
1107         audio_output->crtc_info.v_active =
1108                         stream->timing.v_addressable
1109                         + stream->timing.v_border_top
1110                         + stream->timing.v_border_bottom;
1111
1112         audio_output->crtc_info.pixel_repetition = 1;
1113
1114         audio_output->crtc_info.interlaced =
1115                         stream->timing.flags.INTERLACE;
1116
1117         audio_output->crtc_info.refresh_rate =
1118                 (stream->timing.pix_clk_khz*1000)/
1119                 (stream->timing.h_total*stream->timing.v_total);
1120
1121         audio_output->crtc_info.color_depth =
1122                 stream->timing.display_color_depth;
1123
1124         audio_output->crtc_info.requested_pixel_clock =
1125                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
1126
1127         audio_output->crtc_info.calculated_pixel_clock =
1128                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
1129
1130 /*for HDMI, audio ACR is with deep color ratio factor*/
1131         if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&
1132                 audio_output->crtc_info.requested_pixel_clock ==
1133                                 stream->timing.pix_clk_khz) {
1134                 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1135                         audio_output->crtc_info.requested_pixel_clock =
1136                                         audio_output->crtc_info.requested_pixel_clock/2;
1137                         audio_output->crtc_info.calculated_pixel_clock =
1138                                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk/2;
1139
1140                 }
1141         }
1142
1143         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
1144                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1145                 audio_output->pll_info.dp_dto_source_clock_in_khz =
1146                                 state->dis_clk->funcs->get_dp_ref_clk_frequency(
1147                                                 state->dis_clk);
1148         }
1149
1150         audio_output->pll_info.feed_back_divider =
1151                         pipe_ctx->pll_settings.feedback_divider;
1152
1153         audio_output->pll_info.dto_source =
1154                 translate_to_dto_source(
1155                         pipe_ctx->pipe_idx + 1);
1156
1157         /* TODO hard code to enable for now. Need get from stream */
1158         audio_output->pll_info.ss_enabled = true;
1159
1160         audio_output->pll_info.ss_percentage =
1161                         pipe_ctx->pll_settings.ss_percentage;
1162 }
1163
1164 static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
1165                 struct tg_color *color)
1166 {
1167         uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->pipe_idx) / 4;
1168
1169         switch (pipe_ctx->plane_res.scl_data.format) {
1170         case PIXEL_FORMAT_ARGB8888:
1171                 /* set boarder color to red */
1172                 color->color_r_cr = color_value;
1173                 break;
1174
1175         case PIXEL_FORMAT_ARGB2101010:
1176                 /* set boarder color to blue */
1177                 color->color_b_cb = color_value;
1178                 break;
1179         case PIXEL_FORMAT_420BPP8:
1180                 /* set boarder color to green */
1181                 color->color_g_y = color_value;
1182                 break;
1183         case PIXEL_FORMAT_420BPP10:
1184                 /* set boarder color to yellow */
1185                 color->color_g_y = color_value;
1186                 color->color_r_cr = color_value;
1187                 break;
1188         case PIXEL_FORMAT_FP16:
1189                 /* set boarder color to white */
1190                 color->color_r_cr = color_value;
1191                 color->color_b_cb = color_value;
1192                 color->color_g_y = color_value;
1193                 break;
1194         default:
1195                 break;
1196         }
1197 }
1198
1199 static void program_scaler(const struct dc *dc,
1200                 const struct pipe_ctx *pipe_ctx)
1201 {
1202         struct tg_color color = {0};
1203
1204 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1205         /* TOFPGA */
1206         if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
1207                 return;
1208 #endif
1209
1210         if (dc->debug.surface_visual_confirm)
1211                 get_surface_visual_confirm_color(pipe_ctx, &color);
1212         else
1213                 color_space_to_black_color(dc,
1214                                 pipe_ctx->stream->output_color_space,
1215                                 &color);
1216
1217         pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
1218                 pipe_ctx->plane_res.xfm,
1219                 pipe_ctx->plane_res.scl_data.lb_params.depth,
1220                 &pipe_ctx->stream->bit_depth_params);
1221
1222         if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color)
1223                 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
1224                                 pipe_ctx->stream_res.tg,
1225                                 &color);
1226
1227         pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
1228                 &pipe_ctx->plane_res.scl_data);
1229 }
1230
1231 static enum dc_status dce110_prog_pixclk_crtc_otg(
1232                 struct pipe_ctx *pipe_ctx,
1233                 struct dc_state *context,
1234                 struct dc *dc)
1235 {
1236         struct dc_stream_state *stream = pipe_ctx->stream;
1237         struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1238                         pipe_ctx[pipe_ctx->pipe_idx];
1239         struct tg_color black_color = {0};
1240
1241         if (!pipe_ctx_old->stream) {
1242
1243                 /* program blank color */
1244                 color_space_to_black_color(dc,
1245                                 stream->output_color_space, &black_color);
1246                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1247                                 pipe_ctx->stream_res.tg,
1248                                 &black_color);
1249
1250                 /*
1251                  * Must blank CRTC after disabling power gating and before any
1252                  * programming, otherwise CRTC will be hung in bad state
1253                  */
1254                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1255
1256                 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1257                                 pipe_ctx->clock_source,
1258                                 &pipe_ctx->stream_res.pix_clk_params,
1259                                 &pipe_ctx->pll_settings)) {
1260                         BREAK_TO_DEBUGGER();
1261                         return DC_ERROR_UNEXPECTED;
1262                 }
1263
1264                 pipe_ctx->stream_res.tg->funcs->program_timing(
1265                                 pipe_ctx->stream_res.tg,
1266                                 &stream->timing,
1267                                 true);
1268
1269                 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1270                                 pipe_ctx->stream_res.tg,
1271                                 0x182);
1272         }
1273
1274         if (!pipe_ctx_old->stream) {
1275                 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
1276                                 pipe_ctx->stream_res.tg)) {
1277                         BREAK_TO_DEBUGGER();
1278                         return DC_ERROR_UNEXPECTED;
1279                 }
1280         }
1281
1282
1283
1284         return DC_OK;
1285 }
1286
1287 static enum dc_status apply_single_controller_ctx_to_hw(
1288                 struct pipe_ctx *pipe_ctx,
1289                 struct dc_state *context,
1290                 struct dc *dc)
1291 {
1292         struct dc_stream_state *stream = pipe_ctx->stream;
1293         struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1294                         pipe_ctx[pipe_ctx->pipe_idx];
1295
1296         /*  */
1297         dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc);
1298
1299         /* FPGA does not program backend */
1300         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1301                 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1302                 pipe_ctx->stream_res.opp,
1303                 COLOR_SPACE_YCBCR601,
1304                 stream->timing.display_color_depth,
1305                 pipe_ctx->stream->signal);
1306
1307                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1308                         pipe_ctx->stream_res.opp,
1309                         &stream->bit_depth_params,
1310                         &stream->clamping);
1311                 return DC_OK;
1312         }
1313         /* TODO: move to stream encoder */
1314         if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1315                 if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) {
1316                         BREAK_TO_DEBUGGER();
1317                         return DC_ERROR_UNEXPECTED;
1318                 }
1319         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1320                         pipe_ctx->stream_res.opp,
1321                         COLOR_SPACE_YCBCR601,
1322                         stream->timing.display_color_depth,
1323                         pipe_ctx->stream->signal);
1324
1325         if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1326                 stream->sink->link->link_enc->funcs->setup(
1327                         stream->sink->link->link_enc,
1328                         pipe_ctx->stream->signal);
1329
1330         if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1331                 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
1332                 pipe_ctx->stream_res.stream_enc,
1333                 pipe_ctx->stream_res.tg->inst,
1334                 stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
1335
1336
1337         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1338                 pipe_ctx->stream_res.opp,
1339                 &stream->bit_depth_params,
1340                 &stream->clamping);
1341
1342         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1343                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
1344                         pipe_ctx->stream_res.stream_enc,
1345                         &stream->timing,
1346                         stream->output_color_space);
1347
1348         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1349                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
1350                         pipe_ctx->stream_res.stream_enc,
1351                         &stream->timing,
1352                         stream->phy_pix_clk,
1353                         pipe_ctx->stream_res.audio != NULL);
1354
1355         if (dc_is_dvi_signal(pipe_ctx->stream->signal))
1356                 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
1357                         pipe_ctx->stream_res.stream_enc,
1358                         &stream->timing,
1359                         (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
1360                         true : false);
1361
1362         resource_build_info_frame(pipe_ctx);
1363         dce110_update_info_frame(pipe_ctx);
1364         if (!pipe_ctx_old->stream) {
1365                 if (!pipe_ctx->stream->dpms_off)
1366                         core_link_enable_stream(context, pipe_ctx);
1367         }
1368
1369         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
1370
1371         pipe_ctx->stream->sink->link->psr_enabled = false;
1372
1373         return DC_OK;
1374 }
1375
1376 /******************************************************************************/
1377
1378 static void power_down_encoders(struct dc *dc)
1379 {
1380         int i;
1381         enum connector_id connector_id;
1382         enum signal_type signal = SIGNAL_TYPE_NONE;
1383
1384         /* do not know BIOS back-front mapping, simply blank all. It will not
1385          * hurt for non-DP
1386          */
1387         for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1388                 dc->res_pool->stream_enc[i]->funcs->dp_blank(
1389                                         dc->res_pool->stream_enc[i]);
1390         }
1391
1392         for (i = 0; i < dc->link_count; i++) {
1393                 connector_id = dal_graphics_object_id_get_connector_id(dc->links[i]->link_id);
1394                 if ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
1395                         (connector_id == CONNECTOR_ID_EDP)) {
1396
1397                         if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
1398                                 dp_receiver_power_ctrl(dc->links[i], false);
1399                         if (connector_id == CONNECTOR_ID_EDP)
1400                                 signal = SIGNAL_TYPE_EDP;
1401                 }
1402
1403                 dc->links[i]->link_enc->funcs->disable_output(
1404                                 dc->links[i]->link_enc, signal, dc->links[i]);
1405         }
1406 }
1407
1408 static void power_down_controllers(struct dc *dc)
1409 {
1410         int i;
1411
1412         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1413                 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1414                                 dc->res_pool->timing_generators[i]);
1415         }
1416 }
1417
1418 static void power_down_clock_sources(struct dc *dc)
1419 {
1420         int i;
1421
1422         if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1423                 dc->res_pool->dp_clock_source) == false)
1424                 dm_error("Failed to power down pll! (dp clk src)\n");
1425
1426         for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1427                 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1428                                 dc->res_pool->clock_sources[i]) == false)
1429                         dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1430         }
1431 }
1432
1433 static void power_down_all_hw_blocks(struct dc *dc)
1434 {
1435         power_down_encoders(dc);
1436
1437         power_down_controllers(dc);
1438
1439         power_down_clock_sources(dc);
1440
1441 #if defined(CONFIG_DRM_AMD_DC_FBC)
1442         if (dc->fbc_compressor)
1443                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1444 #endif
1445 }
1446
1447 static void disable_vga_and_power_gate_all_controllers(
1448                 struct dc *dc)
1449 {
1450         int i;
1451         struct timing_generator *tg;
1452         struct dc_context *ctx = dc->ctx;
1453
1454         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1455                 tg = dc->res_pool->timing_generators[i];
1456
1457                 if (tg->funcs->disable_vga)
1458                         tg->funcs->disable_vga(tg);
1459
1460                 /* Enable CLOCK gating for each pipe BEFORE controller
1461                  * powergating. */
1462                 enable_display_pipe_clock_gating(ctx,
1463                                 true);
1464
1465                 dc->hwss.power_down_front_end(dc, i);
1466         }
1467 }
1468
1469 /**
1470  * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1471  *  1. Power down all DC HW blocks
1472  *  2. Disable VGA engine on all controllers
1473  *  3. Enable power gating for controller
1474  *  4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1475  */
1476 void dce110_enable_accelerated_mode(struct dc *dc)
1477 {
1478         power_down_all_hw_blocks(dc);
1479
1480         disable_vga_and_power_gate_all_controllers(dc);
1481         bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
1482 }
1483
1484 static uint32_t compute_pstate_blackout_duration(
1485         struct bw_fixed blackout_duration,
1486         const struct dc_stream_state *stream)
1487 {
1488         uint32_t total_dest_line_time_ns;
1489         uint32_t pstate_blackout_duration_ns;
1490
1491         pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1492
1493         total_dest_line_time_ns = 1000000UL *
1494                 stream->timing.h_total /
1495                 stream->timing.pix_clk_khz +
1496                 pstate_blackout_duration_ns;
1497
1498         return total_dest_line_time_ns;
1499 }
1500
1501 void dce110_set_displaymarks(
1502         const struct dc *dc,
1503         struct dc_state *context)
1504 {
1505         uint8_t i, num_pipes;
1506         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1507
1508         for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1509                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1510                 uint32_t total_dest_line_time_ns;
1511
1512                 if (pipe_ctx->stream == NULL)
1513                         continue;
1514
1515                 total_dest_line_time_ns = compute_pstate_blackout_duration(
1516                         dc->bw_vbios->blackout_duration, pipe_ctx->stream);
1517                 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
1518                         pipe_ctx->plane_res.mi,
1519                         context->bw.dce.nbp_state_change_wm_ns[num_pipes],
1520                         context->bw.dce.stutter_exit_wm_ns[num_pipes],
1521                         context->bw.dce.urgent_wm_ns[num_pipes],
1522                         total_dest_line_time_ns);
1523                 if (i == underlay_idx) {
1524                         num_pipes++;
1525                         pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1526                                 pipe_ctx->plane_res.mi,
1527                                 context->bw.dce.nbp_state_change_wm_ns[num_pipes],
1528                                 context->bw.dce.stutter_exit_wm_ns[num_pipes],
1529                                 context->bw.dce.urgent_wm_ns[num_pipes],
1530                                 total_dest_line_time_ns);
1531                 }
1532                 num_pipes++;
1533         }
1534 }
1535
1536 static void set_safe_displaymarks(
1537                 struct resource_context *res_ctx,
1538                 const struct resource_pool *pool)
1539 {
1540         int i;
1541         int underlay_idx = pool->underlay_pipe_index;
1542         struct dce_watermarks max_marks = {
1543                 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1544         struct dce_watermarks nbp_marks = {
1545                 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1546
1547         for (i = 0; i < MAX_PIPES; i++) {
1548                 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
1549                         continue;
1550
1551                 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
1552                                 res_ctx->pipe_ctx[i].plane_res.mi,
1553                                 nbp_marks,
1554                                 max_marks,
1555                                 max_marks,
1556                                 MAX_WATERMARK);
1557
1558                 if (i == underlay_idx)
1559                         res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1560                                 res_ctx->pipe_ctx[i].plane_res.mi,
1561                                 nbp_marks,
1562                                 max_marks,
1563                                 max_marks,
1564                                 MAX_WATERMARK);
1565
1566         }
1567 }
1568
1569 /*******************************************************************************
1570  * Public functions
1571  ******************************************************************************/
1572
1573 static void set_drr(struct pipe_ctx **pipe_ctx,
1574                 int num_pipes, int vmin, int vmax)
1575 {
1576         int i = 0;
1577         struct drr_params params = {0};
1578
1579         params.vertical_total_max = vmax;
1580         params.vertical_total_min = vmin;
1581
1582         /* TODO: If multiple pipes are to be supported, you need
1583          * some GSL stuff
1584          */
1585
1586         for (i = 0; i < num_pipes; i++) {
1587                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, &params);
1588         }
1589 }
1590
1591 static void get_position(struct pipe_ctx **pipe_ctx,
1592                 int num_pipes,
1593                 struct crtc_position *position)
1594 {
1595         int i = 0;
1596
1597         /* TODO: handle pipes > 1
1598          */
1599         for (i = 0; i < num_pipes; i++)
1600                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
1601 }
1602
1603 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1604                 int num_pipes, const struct dc_static_screen_events *events)
1605 {
1606         unsigned int i;
1607         unsigned int value = 0;
1608
1609         if (events->overlay_update)
1610                 value |= 0x100;
1611         if (events->surface_update)
1612                 value |= 0x80;
1613         if (events->cursor_update)
1614                 value |= 0x2;
1615
1616 #if defined(CONFIG_DRM_AMD_DC_FBC)
1617         value |= 0x84;
1618 #endif
1619
1620         for (i = 0; i < num_pipes; i++)
1621                 pipe_ctx[i]->stream_res.tg->funcs->
1622                         set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
1623 }
1624
1625 /* unit: in_khz before mode set, get pixel clock from context. ASIC register
1626  * may not be programmed yet.
1627  * TODO: after mode set, pre_mode_set = false,
1628  * may read PLL register to get pixel clock
1629  */
1630 static uint32_t get_max_pixel_clock_for_all_paths(
1631         struct dc *dc,
1632         struct dc_state *context,
1633         bool pre_mode_set)
1634 {
1635         uint32_t max_pix_clk = 0;
1636         int i;
1637
1638         if (!pre_mode_set) {
1639                 /* TODO: read ASIC register to get pixel clock */
1640                 ASSERT(0);
1641         }
1642
1643         for (i = 0; i < MAX_PIPES; i++) {
1644                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1645
1646                 if (pipe_ctx->stream == NULL)
1647                         continue;
1648
1649                 /* do not check under lay */
1650                 if (pipe_ctx->top_pipe)
1651                         continue;
1652
1653                 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk > max_pix_clk)
1654                         max_pix_clk =
1655                                 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
1656         }
1657
1658         if (max_pix_clk == 0)
1659                 ASSERT(0);
1660
1661         return max_pix_clk;
1662 }
1663
1664 /*
1665  * Find clock state based on clock requested. if clock value is 0, simply
1666  * set clock state as requested without finding clock state by clock value
1667  */
1668
1669 static void apply_min_clocks(
1670         struct dc *dc,
1671         struct dc_state *context,
1672         enum dm_pp_clocks_state *clocks_state,
1673         bool pre_mode_set)
1674 {
1675         struct state_dependent_clocks req_clocks = {0};
1676
1677         if (!pre_mode_set) {
1678                 /* set clock_state without verification */
1679                 if (context->dis_clk->funcs->set_min_clocks_state) {
1680                         context->dis_clk->funcs->set_min_clocks_state(
1681                                                 context->dis_clk, *clocks_state);
1682                         return;
1683                 }
1684
1685                 /* TODO: This is incorrect. Figure out how to fix. */
1686                 context->dis_clk->funcs->apply_clock_voltage_request(
1687                                 context->dis_clk,
1688                                 DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1689                                 context->dis_clk->cur_clocks_value.dispclk_in_khz,
1690                                 pre_mode_set,
1691                                 false);
1692
1693                 context->dis_clk->funcs->apply_clock_voltage_request(
1694                                 context->dis_clk,
1695                                 DM_PP_CLOCK_TYPE_PIXELCLK,
1696                                 context->dis_clk->cur_clocks_value.max_pixelclk_in_khz,
1697                                 pre_mode_set,
1698                                 false);
1699
1700                 context->dis_clk->funcs->apply_clock_voltage_request(
1701                                 context->dis_clk,
1702                                 DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
1703                                 context->dis_clk->cur_clocks_value.max_non_dp_phyclk_in_khz,
1704                                 pre_mode_set,
1705                                 false);
1706                 return;
1707         }
1708
1709         /* get the required state based on state dependent clocks:
1710          * display clock and pixel clock
1711          */
1712         req_clocks.display_clk_khz = context->bw.dce.dispclk_khz;
1713
1714         req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths(
1715                         dc, context, true);
1716
1717         if (context->dis_clk->funcs->get_required_clocks_state) {
1718                 *clocks_state = context->dis_clk->funcs->get_required_clocks_state(
1719                                 context->dis_clk, &req_clocks);
1720                 context->dis_clk->funcs->set_min_clocks_state(
1721                         context->dis_clk, *clocks_state);
1722         } else {
1723                 context->dis_clk->funcs->apply_clock_voltage_request(
1724                                 context->dis_clk,
1725                                 DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1726                                 req_clocks.display_clk_khz,
1727                                 pre_mode_set,
1728                                 false);
1729
1730                 context->dis_clk->funcs->apply_clock_voltage_request(
1731                                 context->dis_clk,
1732                                 DM_PP_CLOCK_TYPE_PIXELCLK,
1733                                 req_clocks.pixel_clk_khz,
1734                                 pre_mode_set,
1735                                 false);
1736
1737                 context->dis_clk->funcs->apply_clock_voltage_request(
1738                                 context->dis_clk,
1739                                 DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
1740                                 req_clocks.pixel_clk_khz,
1741                                 pre_mode_set,
1742                                 false);
1743         }
1744 }
1745
1746 #if defined(CONFIG_DRM_AMD_DC_FBC)
1747
1748 /*
1749  *  Check if FBC can be enabled
1750  */
1751 static enum dc_status validate_fbc(struct dc *dc,
1752                 struct dc_state *context)
1753 {
1754         struct pipe_ctx *pipe_ctx =
1755                               &context->res_ctx.pipe_ctx[0];
1756
1757         ASSERT(dc->fbc_compressor);
1758
1759         /* FBC memory should be allocated */
1760         if (!dc->ctx->fbc_gpu_addr)
1761                 return DC_ERROR_UNEXPECTED;
1762
1763         /* Only supports single display */
1764         if (context->stream_count != 1)
1765                 return DC_ERROR_UNEXPECTED;
1766
1767         /* Only supports eDP */
1768         if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP)
1769                 return DC_ERROR_UNEXPECTED;
1770
1771         /* PSR should not be enabled */
1772         if (pipe_ctx->stream->sink->link->psr_enabled)
1773                 return DC_ERROR_UNEXPECTED;
1774
1775         /* Nothing to compress */
1776         if (!pipe_ctx->plane_state)
1777                 return DC_ERROR_UNEXPECTED;
1778
1779         /* Only for non-linear tiling */
1780         if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
1781                 return DC_ERROR_UNEXPECTED;
1782
1783         return DC_OK;
1784 }
1785
1786 /*
1787  *  Enable FBC
1788  */
1789 static enum dc_status enable_fbc(struct dc *dc,
1790                 struct dc_state *context)
1791 {
1792         enum dc_status status = validate_fbc(dc, context);
1793
1794         if (status == DC_OK) {
1795                 /* Program GRPH COMPRESSED ADDRESS and PITCH */
1796                 struct compr_addr_and_pitch_params params = {0, 0, 0};
1797                 struct compressor *compr = dc->fbc_compressor;
1798                 struct pipe_ctx *pipe_ctx =
1799                                       &context->res_ctx.pipe_ctx[0];
1800
1801                 params.source_view_width =
1802                                 pipe_ctx->stream->timing.h_addressable;
1803                 params.source_view_height =
1804                                 pipe_ctx->stream->timing.v_addressable;
1805
1806                 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
1807
1808                 compr->funcs->surface_address_and_pitch(compr, &params);
1809                 compr->funcs->set_fbc_invalidation_triggers(compr, 1);
1810
1811                 compr->funcs->enable_fbc(compr, &params);
1812         }
1813         return status;
1814 }
1815 #endif
1816
1817 static enum dc_status apply_ctx_to_hw_fpga(
1818                 struct dc *dc,
1819                 struct dc_state *context)
1820 {
1821         enum dc_status status = DC_ERROR_UNEXPECTED;
1822         int i;
1823
1824         for (i = 0; i < MAX_PIPES; i++) {
1825                 struct pipe_ctx *pipe_ctx_old =
1826                                 &dc->current_state->res_ctx.pipe_ctx[i];
1827                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1828
1829                 if (pipe_ctx->stream == NULL)
1830                         continue;
1831
1832                 if (pipe_ctx->stream == pipe_ctx_old->stream)
1833                         continue;
1834
1835                 status = apply_single_controller_ctx_to_hw(
1836                                 pipe_ctx,
1837                                 context,
1838                                 dc);
1839
1840                 if (status != DC_OK)
1841                         return status;
1842         }
1843
1844         return DC_OK;
1845 }
1846
1847 static void dce110_reset_hw_ctx_wrap(
1848                 struct dc *dc,
1849                 struct dc_state *context)
1850 {
1851         int i;
1852
1853         /* Reset old context */
1854         /* look up the targets that have been removed since last commit */
1855         for (i = 0; i < MAX_PIPES; i++) {
1856                 struct pipe_ctx *pipe_ctx_old =
1857                         &dc->current_state->res_ctx.pipe_ctx[i];
1858                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1859
1860                 /* Note: We need to disable output if clock sources change,
1861                  * since bios does optimization and doesn't apply if changing
1862                  * PHY when not already disabled.
1863                  */
1864
1865                 /* Skip underlay pipe since it will be handled in commit surface*/
1866                 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
1867                         continue;
1868
1869                 if (!pipe_ctx->stream ||
1870                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1871                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
1872
1873                         /* Disable if new stream is null. O/w, if stream is
1874                          * disabled already, no need to disable again.
1875                          */
1876                         if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off)
1877                                 core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE);
1878
1879                         pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
1880                         if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
1881                                 dm_error("DC: failed to blank crtc!\n");
1882                                 BREAK_TO_DEBUGGER();
1883                         }
1884                         pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
1885                         pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
1886                                         pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
1887
1888                         if (old_clk)
1889                                 old_clk->funcs->cs_power_down(old_clk);
1890
1891                         dc->hwss.power_down_front_end(dc, pipe_ctx_old->pipe_idx);
1892
1893                         pipe_ctx_old->stream = NULL;
1894                 }
1895         }
1896 }
1897
1898
1899 enum dc_status dce110_apply_ctx_to_hw(
1900                 struct dc *dc,
1901                 struct dc_state *context)
1902 {
1903         struct dc_bios *dcb = dc->ctx->dc_bios;
1904         enum dc_status status;
1905         int i;
1906         enum dm_pp_clocks_state clocks_state = DM_PP_CLOCKS_STATE_INVALID;
1907
1908         /* Reset old context */
1909         /* look up the targets that have been removed since last commit */
1910         dc->hwss.reset_hw_ctx_wrap(dc, context);
1911
1912         /* Skip applying if no targets */
1913         if (context->stream_count <= 0)
1914                 return DC_OK;
1915
1916         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1917                 apply_ctx_to_hw_fpga(dc, context);
1918                 return DC_OK;
1919         }
1920
1921         /* Apply new context */
1922         dcb->funcs->set_scratch_critical_state(dcb, true);
1923
1924         /* below is for real asic only */
1925         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1926                 struct pipe_ctx *pipe_ctx_old =
1927                                         &dc->current_state->res_ctx.pipe_ctx[i];
1928                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1929
1930                 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
1931                         continue;
1932
1933                 if (pipe_ctx->stream == pipe_ctx_old->stream) {
1934                         if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
1935                                 dce_crtc_switch_to_clk_src(dc->hwseq,
1936                                                 pipe_ctx->clock_source, i);
1937                         continue;
1938                 }
1939
1940                 dc->hwss.enable_display_power_gating(
1941                                 dc, i, dc->ctx->dc_bios,
1942                                 PIPE_GATING_CONTROL_DISABLE);
1943         }
1944
1945         set_safe_displaymarks(&context->res_ctx, dc->res_pool);
1946
1947 #if defined(CONFIG_DRM_AMD_DC_FBC)
1948         if (dc->fbc_compressor)
1949                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1950 #endif
1951         /*TODO: when pplib works*/
1952         apply_min_clocks(dc, context, &clocks_state, true);
1953
1954 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1955         if (dc->ctx->dce_version >= DCN_VERSION_1_0) {
1956                 if (context->bw.dcn.calc_clk.fclk_khz
1957                                 > dc->current_state->bw.dcn.cur_clk.fclk_khz) {
1958                         struct dm_pp_clock_for_voltage_req clock;
1959
1960                         clock.clk_type = DM_PP_CLOCK_TYPE_FCLK;
1961                         clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz;
1962                         dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
1963                         dc->current_state->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
1964                         context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
1965                 }
1966                 if (context->bw.dcn.calc_clk.dcfclk_khz
1967                                 > dc->current_state->bw.dcn.cur_clk.dcfclk_khz) {
1968                         struct dm_pp_clock_for_voltage_req clock;
1969
1970                         clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
1971                         clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz;
1972                         dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
1973                         dc->current_state->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
1974                         context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
1975                 }
1976                 if (context->bw.dcn.calc_clk.dispclk_khz
1977                                 > dc->current_state->bw.dcn.cur_clk.dispclk_khz) {
1978                         dc->res_pool->display_clock->funcs->set_clock(
1979                                         dc->res_pool->display_clock,
1980                                         context->bw.dcn.calc_clk.dispclk_khz);
1981                         dc->current_state->bw.dcn.cur_clk.dispclk_khz =
1982                                         context->bw.dcn.calc_clk.dispclk_khz;
1983                         context->bw.dcn.cur_clk.dispclk_khz =
1984                                         context->bw.dcn.calc_clk.dispclk_khz;
1985                 }
1986         } else
1987 #endif
1988         if (context->bw.dce.dispclk_khz
1989                         > dc->current_state->bw.dce.dispclk_khz) {
1990                 dc->res_pool->display_clock->funcs->set_clock(
1991                                 dc->res_pool->display_clock,
1992                                 context->bw.dce.dispclk_khz * 115 / 100);
1993         }
1994         /* program audio wall clock. use HDMI as clock source if HDMI
1995          * audio active. Otherwise, use DP as clock source
1996          * first, loop to find any HDMI audio, if not, loop find DP audio
1997          */
1998         /* Setup audio rate clock source */
1999         /* Issue:
2000         * Audio lag happened on DP monitor when unplug a HDMI monitor
2001         *
2002         * Cause:
2003         * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
2004         * is set to either dto0 or dto1, audio should work fine.
2005         * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
2006         * set to dto0 will cause audio lag.
2007         *
2008         * Solution:
2009         * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
2010         * find first available pipe with audio, setup audio wall DTO per topology
2011         * instead of per pipe.
2012         */
2013         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2014                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2015
2016                 if (pipe_ctx->stream == NULL)
2017                         continue;
2018
2019                 if (pipe_ctx->top_pipe)
2020                         continue;
2021
2022                 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2023                         continue;
2024
2025                 if (pipe_ctx->stream_res.audio != NULL) {
2026                         struct audio_output audio_output;
2027
2028                         build_audio_output(context, pipe_ctx, &audio_output);
2029
2030                         pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2031                                 pipe_ctx->stream_res.audio,
2032                                 pipe_ctx->stream->signal,
2033                                 &audio_output.crtc_info,
2034                                 &audio_output.pll_info);
2035                         break;
2036                 }
2037         }
2038
2039         /* no HDMI audio is found, try DP audio */
2040         if (i == dc->res_pool->pipe_count) {
2041                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2042                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2043
2044                         if (pipe_ctx->stream == NULL)
2045                                 continue;
2046
2047                         if (pipe_ctx->top_pipe)
2048                                 continue;
2049
2050                         if (!dc_is_dp_signal(pipe_ctx->stream->signal))
2051                                 continue;
2052
2053                         if (pipe_ctx->stream_res.audio != NULL) {
2054                                 struct audio_output audio_output;
2055
2056                                 build_audio_output(context, pipe_ctx, &audio_output);
2057
2058                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2059                                         pipe_ctx->stream_res.audio,
2060                                         pipe_ctx->stream->signal,
2061                                         &audio_output.crtc_info,
2062                                         &audio_output.pll_info);
2063                                 break;
2064                         }
2065                 }
2066         }
2067
2068         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2069                 struct pipe_ctx *pipe_ctx_old =
2070                                         &dc->current_state->res_ctx.pipe_ctx[i];
2071                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2072
2073                 if (pipe_ctx->stream == NULL)
2074                         continue;
2075
2076                 if (pipe_ctx->stream == pipe_ctx_old->stream)
2077                         continue;
2078
2079                 if (pipe_ctx->stream && pipe_ctx_old->stream
2080                                 && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
2081                         continue;
2082
2083                 if (pipe_ctx->top_pipe)
2084                         continue;
2085
2086                 if (context->res_ctx.pipe_ctx[i].stream_res.audio != NULL) {
2087
2088                         struct audio_output audio_output;
2089
2090                         build_audio_output(context, pipe_ctx, &audio_output);
2091
2092                         if (dc_is_dp_signal(pipe_ctx->stream->signal))
2093                                 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(
2094                                                 pipe_ctx->stream_res.stream_enc,
2095                                                 pipe_ctx->stream_res.audio->inst,
2096                                                 &pipe_ctx->stream->audio_info);
2097                         else
2098                                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(
2099                                                 pipe_ctx->stream_res.stream_enc,
2100                                                 pipe_ctx->stream_res.audio->inst,
2101                                                 &pipe_ctx->stream->audio_info,
2102                                                 &audio_output.crtc_info);
2103
2104                         pipe_ctx->stream_res.audio->funcs->az_configure(
2105                                         pipe_ctx->stream_res.audio,
2106                                         pipe_ctx->stream->signal,
2107                                         &audio_output.crtc_info,
2108                                         &pipe_ctx->stream->audio_info);
2109                 }
2110
2111                 status = apply_single_controller_ctx_to_hw(
2112                                 pipe_ctx,
2113                                 context,
2114                                 dc);
2115
2116                 if (dc->hwss.power_on_front_end)
2117                         dc->hwss.power_on_front_end(dc, pipe_ctx, context);
2118
2119                 if (DC_OK != status)
2120                         return status;
2121         }
2122
2123         /* pplib is notified if disp_num changed */
2124         dc->hwss.set_bandwidth(dc, context, true);
2125
2126         /* to save power */
2127         apply_min_clocks(dc, context, &clocks_state, false);
2128
2129         dcb->funcs->set_scratch_critical_state(dcb, false);
2130
2131 #if defined(CONFIG_DRM_AMD_DC_FBC)
2132         if (dc->fbc_compressor)
2133                 enable_fbc(dc, context);
2134
2135 #endif
2136
2137         return DC_OK;
2138 }
2139
2140 /*******************************************************************************
2141  * Front End programming
2142  ******************************************************************************/
2143 static void set_default_colors(struct pipe_ctx *pipe_ctx)
2144 {
2145         struct default_adjustment default_adjust = { 0 };
2146
2147         default_adjust.force_hw_default = false;
2148         if (pipe_ctx->plane_state == NULL)
2149                 default_adjust.in_color_space = COLOR_SPACE_SRGB;
2150         else
2151                 default_adjust.in_color_space =
2152                                 pipe_ctx->plane_state->color_space;
2153         if (pipe_ctx->stream == NULL)
2154                 default_adjust.out_color_space = COLOR_SPACE_SRGB;
2155         else
2156                 default_adjust.out_color_space =
2157                                 pipe_ctx->stream->output_color_space;
2158         default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
2159         default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
2160
2161         /* display color depth */
2162         default_adjust.color_depth =
2163                 pipe_ctx->stream->timing.display_color_depth;
2164
2165         /* Lb color depth */
2166         default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
2167
2168         pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
2169                                         pipe_ctx->plane_res.xfm, &default_adjust);
2170 }
2171
2172
2173 /*******************************************************************************
2174  * In order to turn on/off specific surface we will program
2175  * Blender + CRTC
2176  *
2177  * In case that we have two surfaces and they have a different visibility
2178  * we can't turn off the CRTC since it will turn off the entire display
2179  *
2180  * |----------------------------------------------- |
2181  * |bottom pipe|curr pipe  |              |         |
2182  * |Surface    |Surface    | Blender      |  CRCT   |
2183  * |visibility |visibility | Configuration|         |
2184  * |------------------------------------------------|
2185  * |   off     |    off    | CURRENT_PIPE | blank   |
2186  * |   off     |    on     | CURRENT_PIPE | unblank |
2187  * |   on      |    off    | OTHER_PIPE   | unblank |
2188  * |   on      |    on     | BLENDING     | unblank |
2189  * -------------------------------------------------|
2190  *
2191  ******************************************************************************/
2192 static void program_surface_visibility(const struct dc *dc,
2193                 struct pipe_ctx *pipe_ctx)
2194 {
2195         enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
2196         bool blank_target = false;
2197
2198         if (pipe_ctx->bottom_pipe) {
2199
2200                 /* For now we are supporting only two pipes */
2201                 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
2202
2203                 if (pipe_ctx->bottom_pipe->plane_state->visible) {
2204                         if (pipe_ctx->plane_state->visible)
2205                                 blender_mode = BLND_MODE_BLENDING;
2206                         else
2207                                 blender_mode = BLND_MODE_OTHER_PIPE;
2208
2209                 } else if (!pipe_ctx->plane_state->visible)
2210                         blank_target = true;
2211
2212         } else if (!pipe_ctx->plane_state->visible)
2213                 blank_target = true;
2214
2215         dce_set_blender_mode(dc->hwseq, pipe_ctx->pipe_idx, blender_mode);
2216         pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
2217
2218 }
2219
2220 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2221 {
2222         struct xfm_grph_csc_adjustment adjust;
2223         memset(&adjust, 0, sizeof(adjust));
2224         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2225
2226
2227         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2228                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2229                 adjust.temperature_matrix[0] =
2230                                 pipe_ctx->stream->
2231                                 gamut_remap_matrix.matrix[0];
2232                 adjust.temperature_matrix[1] =
2233                                 pipe_ctx->stream->
2234                                 gamut_remap_matrix.matrix[1];
2235                 adjust.temperature_matrix[2] =
2236                                 pipe_ctx->stream->
2237                                 gamut_remap_matrix.matrix[2];
2238                 adjust.temperature_matrix[3] =
2239                                 pipe_ctx->stream->
2240                                 gamut_remap_matrix.matrix[4];
2241                 adjust.temperature_matrix[4] =
2242                                 pipe_ctx->stream->
2243                                 gamut_remap_matrix.matrix[5];
2244                 adjust.temperature_matrix[5] =
2245                                 pipe_ctx->stream->
2246                                 gamut_remap_matrix.matrix[6];
2247                 adjust.temperature_matrix[6] =
2248                                 pipe_ctx->stream->
2249                                 gamut_remap_matrix.matrix[8];
2250                 adjust.temperature_matrix[7] =
2251                                 pipe_ctx->stream->
2252                                 gamut_remap_matrix.matrix[9];
2253                 adjust.temperature_matrix[8] =
2254                                 pipe_ctx->stream->
2255                                 gamut_remap_matrix.matrix[10];
2256         }
2257
2258         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2259 }
2260
2261 /**
2262  * TODO REMOVE, USE UPDATE INSTEAD
2263  */
2264 static void set_plane_config(
2265         const struct dc *dc,
2266         struct pipe_ctx *pipe_ctx,
2267         struct resource_context *res_ctx)
2268 {
2269         struct mem_input *mi = pipe_ctx->plane_res.mi;
2270         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2271         struct xfm_grph_csc_adjustment adjust;
2272         struct out_csc_color_matrix tbl_entry;
2273         unsigned int i;
2274
2275         memset(&adjust, 0, sizeof(adjust));
2276         memset(&tbl_entry, 0, sizeof(tbl_entry));
2277         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2278
2279         dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true);
2280
2281         set_default_colors(pipe_ctx);
2282         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2283                         == true) {
2284                 tbl_entry.color_space =
2285                         pipe_ctx->stream->output_color_space;
2286
2287                 for (i = 0; i < 12; i++)
2288                         tbl_entry.regval[i] =
2289                         pipe_ctx->stream->csc_color_matrix.matrix[i];
2290
2291                 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2292                                 (pipe_ctx->plane_res.xfm, &tbl_entry);
2293         }
2294
2295         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2296                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2297                 adjust.temperature_matrix[0] =
2298                                 pipe_ctx->stream->
2299                                 gamut_remap_matrix.matrix[0];
2300                 adjust.temperature_matrix[1] =
2301                                 pipe_ctx->stream->
2302                                 gamut_remap_matrix.matrix[1];
2303                 adjust.temperature_matrix[2] =
2304                                 pipe_ctx->stream->
2305                                 gamut_remap_matrix.matrix[2];
2306                 adjust.temperature_matrix[3] =
2307                                 pipe_ctx->stream->
2308                                 gamut_remap_matrix.matrix[4];
2309                 adjust.temperature_matrix[4] =
2310                                 pipe_ctx->stream->
2311                                 gamut_remap_matrix.matrix[5];
2312                 adjust.temperature_matrix[5] =
2313                                 pipe_ctx->stream->
2314                                 gamut_remap_matrix.matrix[6];
2315                 adjust.temperature_matrix[6] =
2316                                 pipe_ctx->stream->
2317                                 gamut_remap_matrix.matrix[8];
2318                 adjust.temperature_matrix[7] =
2319                                 pipe_ctx->stream->
2320                                 gamut_remap_matrix.matrix[9];
2321                 adjust.temperature_matrix[8] =
2322                                 pipe_ctx->stream->
2323                                 gamut_remap_matrix.matrix[10];
2324         }
2325
2326         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2327
2328         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2329         program_scaler(dc, pipe_ctx);
2330
2331         program_surface_visibility(dc, pipe_ctx);
2332
2333         mi->funcs->mem_input_program_surface_config(
2334                         mi,
2335                         plane_state->format,
2336                         &plane_state->tiling_info,
2337                         &plane_state->plane_size,
2338                         plane_state->rotation,
2339                         NULL,
2340                         false);
2341         if (mi->funcs->set_blank)
2342                 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2343
2344         if (dc->config.gpu_vm_support)
2345                 mi->funcs->mem_input_program_pte_vm(
2346                                 pipe_ctx->plane_res.mi,
2347                                 plane_state->format,
2348                                 &plane_state->tiling_info,
2349                                 plane_state->rotation);
2350 }
2351
2352 static void update_plane_addr(const struct dc *dc,
2353                 struct pipe_ctx *pipe_ctx)
2354 {
2355         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2356
2357         if (plane_state == NULL)
2358                 return;
2359
2360         pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
2361                         pipe_ctx->plane_res.mi,
2362                         &plane_state->address,
2363                         plane_state->flip_immediate);
2364
2365         plane_state->status.requested_address = plane_state->address;
2366 }
2367
2368 void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2369 {
2370         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2371
2372         if (plane_state == NULL)
2373                 return;
2374
2375         plane_state->status.is_flip_pending =
2376                         pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
2377                                         pipe_ctx->plane_res.mi);
2378
2379         if (plane_state->status.is_flip_pending && !plane_state->visible)
2380                 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
2381
2382         plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
2383         if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2384                         pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
2385                 plane_state->status.is_right_eye =\
2386                                 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2387         }
2388 }
2389
2390 void dce110_power_down(struct dc *dc)
2391 {
2392         power_down_all_hw_blocks(dc);
2393         disable_vga_and_power_gate_all_controllers(dc);
2394 }
2395
2396 static bool wait_for_reset_trigger_to_occur(
2397         struct dc_context *dc_ctx,
2398         struct timing_generator *tg)
2399 {
2400         bool rc = false;
2401
2402         /* To avoid endless loop we wait at most
2403          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2404         const uint32_t frames_to_wait_on_triggered_reset = 10;
2405         uint32_t i;
2406
2407         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2408
2409                 if (!tg->funcs->is_counter_moving(tg)) {
2410                         DC_ERROR("TG counter is not moving!\n");
2411                         break;
2412                 }
2413
2414                 if (tg->funcs->did_triggered_reset_occur(tg)) {
2415                         rc = true;
2416                         /* usually occurs at i=1 */
2417                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2418                                         i);
2419                         break;
2420                 }
2421
2422                 /* Wait for one frame. */
2423                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2424                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2425         }
2426
2427         if (false == rc)
2428                 DC_ERROR("GSL: Timeout on reset trigger!\n");
2429
2430         return rc;
2431 }
2432
2433 /* Enable timing synchronization for a group of Timing Generators. */
2434 static void dce110_enable_timing_synchronization(
2435                 struct dc *dc,
2436                 int group_index,
2437                 int group_size,
2438                 struct pipe_ctx *grouped_pipes[])
2439 {
2440         struct dc_context *dc_ctx = dc->ctx;
2441         struct dcp_gsl_params gsl_params = { 0 };
2442         int i;
2443
2444         DC_SYNC_INFO("GSL: Setting-up...\n");
2445
2446         /* Designate a single TG in the group as a master.
2447          * Since HW doesn't care which one, we always assign
2448          * the 1st one in the group. */
2449         gsl_params.gsl_group = 0;
2450         gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
2451
2452         for (i = 0; i < group_size; i++)
2453                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2454                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2455
2456         /* Reset slave controllers on master VSync */
2457         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2458
2459         for (i = 1 /* skip the master */; i < group_size; i++)
2460                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
2461                                         grouped_pipes[i]->stream_res.tg, gsl_params.gsl_group);
2462
2463
2464
2465         for (i = 1 /* skip the master */; i < group_size; i++) {
2466                 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2467                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2468                 /* Regardless of success of the wait above, remove the reset or
2469                  * the driver will start timing out on Display requests. */
2470                 DC_SYNC_INFO("GSL: disabling trigger-reset.\n");
2471                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(grouped_pipes[i]->stream_res.tg);
2472         }
2473
2474
2475         /* GSL Vblank synchronization is a one time sync mechanism, assumption
2476          * is that the sync'ed displays will not drift out of sync over time*/
2477         DC_SYNC_INFO("GSL: Restoring register states.\n");
2478         for (i = 0; i < group_size; i++)
2479                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2480
2481         DC_SYNC_INFO("GSL: Set-up complete.\n");
2482 }
2483
2484 static void init_hw(struct dc *dc)
2485 {
2486         int i;
2487         struct dc_bios *bp;
2488         struct transform *xfm;
2489         struct abm *abm;
2490
2491         bp = dc->ctx->dc_bios;
2492         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2493                 xfm = dc->res_pool->transforms[i];
2494                 xfm->funcs->transform_reset(xfm);
2495
2496                 dc->hwss.enable_display_power_gating(
2497                                 dc, i, bp,
2498                                 PIPE_GATING_CONTROL_INIT);
2499                 dc->hwss.enable_display_power_gating(
2500                                 dc, i, bp,
2501                                 PIPE_GATING_CONTROL_DISABLE);
2502                 dc->hwss.enable_display_pipe_clock_gating(
2503                         dc->ctx,
2504                         true);
2505         }
2506
2507         dce_clock_gating_power_up(dc->hwseq, false);
2508         /***************************************/
2509
2510         for (i = 0; i < dc->link_count; i++) {
2511                 /****************************************/
2512                 /* Power up AND update implementation according to the
2513                  * required signal (which may be different from the
2514                  * default signal on connector). */
2515                 struct dc_link *link = dc->links[i];
2516                 link->link_enc->funcs->hw_init(link->link_enc);
2517         }
2518
2519         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2520                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2521
2522                 tg->funcs->disable_vga(tg);
2523
2524                 /* Blank controller using driver code instead of
2525                  * command table. */
2526                 tg->funcs->set_blank(tg, true);
2527                 hwss_wait_for_blank_complete(tg);
2528         }
2529
2530         for (i = 0; i < dc->res_pool->audio_count; i++) {
2531                 struct audio *audio = dc->res_pool->audios[i];
2532                 audio->funcs->hw_init(audio);
2533         }
2534
2535         abm = dc->res_pool->abm;
2536         if (abm != NULL) {
2537                 abm->funcs->init_backlight(abm);
2538                 abm->funcs->abm_init(abm);
2539         }
2540 #if defined(CONFIG_DRM_AMD_DC_FBC)
2541         if (dc->fbc_compressor)
2542                 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2543 #endif
2544
2545 }
2546
2547 void dce110_fill_display_configs(
2548         const struct dc_state *context,
2549         struct dm_pp_display_configuration *pp_display_cfg)
2550 {
2551         int j;
2552         int num_cfgs = 0;
2553
2554         for (j = 0; j < context->stream_count; j++) {
2555                 int k;
2556
2557                 const struct dc_stream_state *stream = context->streams[j];
2558                 struct dm_pp_single_disp_config *cfg =
2559                         &pp_display_cfg->disp_configs[num_cfgs];
2560                 const struct pipe_ctx *pipe_ctx = NULL;
2561
2562                 for (k = 0; k < MAX_PIPES; k++)
2563                         if (stream == context->res_ctx.pipe_ctx[k].stream) {
2564                                 pipe_ctx = &context->res_ctx.pipe_ctx[k];
2565                                 break;
2566                         }
2567
2568                 ASSERT(pipe_ctx != NULL);
2569
2570                 num_cfgs++;
2571                 cfg->signal = pipe_ctx->stream->signal;
2572                 cfg->pipe_idx = pipe_ctx->pipe_idx;
2573                 cfg->src_height = stream->src.height;
2574                 cfg->src_width = stream->src.width;
2575                 cfg->ddi_channel_mapping =
2576                         stream->sink->link->ddi_channel_mapping.raw;
2577                 cfg->transmitter =
2578                         stream->sink->link->link_enc->transmitter;
2579                 cfg->link_settings.lane_count =
2580                         stream->sink->link->cur_link_settings.lane_count;
2581                 cfg->link_settings.link_rate =
2582                         stream->sink->link->cur_link_settings.link_rate;
2583                 cfg->link_settings.link_spread =
2584                         stream->sink->link->cur_link_settings.link_spread;
2585                 cfg->sym_clock = stream->phy_pix_clk;
2586                 /* Round v_refresh*/
2587                 cfg->v_refresh = stream->timing.pix_clk_khz * 1000;
2588                 cfg->v_refresh /= stream->timing.h_total;
2589                 cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)
2590                                                         / stream->timing.v_total;
2591         }
2592
2593         pp_display_cfg->display_count = num_cfgs;
2594 }
2595
2596 uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)
2597 {
2598         uint8_t j;
2599         uint32_t min_vertical_blank_time = -1;
2600
2601         for (j = 0; j < context->stream_count; j++) {
2602                 struct dc_stream_state *stream = context->streams[j];
2603                 uint32_t vertical_blank_in_pixels = 0;
2604                 uint32_t vertical_blank_time = 0;
2605
2606                 vertical_blank_in_pixels = stream->timing.h_total *
2607                         (stream->timing.v_total
2608                          - stream->timing.v_addressable);
2609
2610                 vertical_blank_time = vertical_blank_in_pixels
2611                         * 1000 / stream->timing.pix_clk_khz;
2612
2613                 if (min_vertical_blank_time > vertical_blank_time)
2614                         min_vertical_blank_time = vertical_blank_time;
2615         }
2616
2617         return min_vertical_blank_time;
2618 }
2619
2620 static int determine_sclk_from_bounding_box(
2621                 const struct dc *dc,
2622                 int required_sclk)
2623 {
2624         int i;
2625
2626         /*
2627          * Some asics do not give us sclk levels, so we just report the actual
2628          * required sclk
2629          */
2630         if (dc->sclk_lvls.num_levels == 0)
2631                 return required_sclk;
2632
2633         for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
2634                 if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)
2635                         return dc->sclk_lvls.clocks_in_khz[i];
2636         }
2637         /*
2638          * even maximum level could not satisfy requirement, this
2639          * is unexpected at this stage, should have been caught at
2640          * validation time
2641          */
2642         ASSERT(0);
2643         return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
2644 }
2645
2646 static void pplib_apply_display_requirements(
2647         struct dc *dc,
2648         struct dc_state *context)
2649 {
2650         struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
2651
2652         pp_display_cfg->all_displays_in_sync =
2653                 context->bw.dce.all_displays_in_sync;
2654         pp_display_cfg->nb_pstate_switch_disable =
2655                         context->bw.dce.nbp_state_change_enable == false;
2656         pp_display_cfg->cpu_cc6_disable =
2657                         context->bw.dce.cpuc_state_change_enable == false;
2658         pp_display_cfg->cpu_pstate_disable =
2659                         context->bw.dce.cpup_state_change_enable == false;
2660         pp_display_cfg->cpu_pstate_separation_time =
2661                         context->bw.dce.blackout_recovery_time_us;
2662
2663         pp_display_cfg->min_memory_clock_khz = context->bw.dce.yclk_khz
2664                 / MEMORY_TYPE_MULTIPLIER;
2665
2666         pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
2667                         dc,
2668                         context->bw.dce.sclk_khz);
2669
2670         pp_display_cfg->min_engine_clock_deep_sleep_khz
2671                         = context->bw.dce.sclk_deep_sleep_khz;
2672
2673         pp_display_cfg->avail_mclk_switch_time_us =
2674                                                 dce110_get_min_vblank_time_us(context);
2675         /* TODO: dce11.2*/
2676         pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
2677
2678         pp_display_cfg->disp_clk_khz = context->bw.dce.dispclk_khz;
2679
2680         dce110_fill_display_configs(context, pp_display_cfg);
2681
2682         /* TODO: is this still applicable?*/
2683         if (pp_display_cfg->display_count == 1) {
2684                 const struct dc_crtc_timing *timing =
2685                         &context->streams[0]->timing;
2686
2687                 pp_display_cfg->crtc_index =
2688                         pp_display_cfg->disp_configs[0].pipe_idx;
2689                 pp_display_cfg->line_time_in_us = timing->h_total * 1000
2690                                                         / timing->pix_clk_khz;
2691         }
2692
2693         if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
2694                         struct dm_pp_display_configuration)) !=  0)
2695                 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
2696
2697         dc->prev_display_config = *pp_display_cfg;
2698 }
2699
2700 static void dce110_set_bandwidth(
2701                 struct dc *dc,
2702                 struct dc_state *context,
2703                 bool decrease_allowed)
2704 {
2705         dce110_set_displaymarks(dc, context);
2706
2707         if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_state->bw.dce.dispclk_khz) {
2708                 dc->res_pool->display_clock->funcs->set_clock(
2709                                 dc->res_pool->display_clock,
2710                                 context->bw.dce.dispclk_khz * 115 / 100);
2711                 dc->current_state->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz;
2712         }
2713
2714         pplib_apply_display_requirements(dc, context);
2715 }
2716
2717 static void dce110_program_front_end_for_pipe(
2718                 struct dc *dc, struct pipe_ctx *pipe_ctx)
2719 {
2720         struct mem_input *mi = pipe_ctx->plane_res.mi;
2721         struct pipe_ctx *old_pipe = NULL;
2722         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2723         struct xfm_grph_csc_adjustment adjust;
2724         struct out_csc_color_matrix tbl_entry;
2725         struct pipe_ctx *cur_pipe_ctx =
2726                                         &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
2727         unsigned int i;
2728
2729         memset(&tbl_entry, 0, sizeof(tbl_entry));
2730
2731         if (dc->current_state)
2732                 old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
2733
2734         memset(&adjust, 0, sizeof(adjust));
2735         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2736
2737         dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true);
2738
2739         set_default_colors(pipe_ctx);
2740         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2741                         == true) {
2742                 tbl_entry.color_space =
2743                         pipe_ctx->stream->output_color_space;
2744
2745                 for (i = 0; i < 12; i++)
2746                         tbl_entry.regval[i] =
2747                         pipe_ctx->stream->csc_color_matrix.matrix[i];
2748
2749                 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2750                                 (pipe_ctx->plane_res.xfm, &tbl_entry);
2751         }
2752
2753         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2754                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2755                 adjust.temperature_matrix[0] =
2756                                 pipe_ctx->stream->
2757                                 gamut_remap_matrix.matrix[0];
2758                 adjust.temperature_matrix[1] =
2759                                 pipe_ctx->stream->
2760                                 gamut_remap_matrix.matrix[1];
2761                 adjust.temperature_matrix[2] =
2762                                 pipe_ctx->stream->
2763                                 gamut_remap_matrix.matrix[2];
2764                 adjust.temperature_matrix[3] =
2765                                 pipe_ctx->stream->
2766                                 gamut_remap_matrix.matrix[4];
2767                 adjust.temperature_matrix[4] =
2768                                 pipe_ctx->stream->
2769                                 gamut_remap_matrix.matrix[5];
2770                 adjust.temperature_matrix[5] =
2771                                 pipe_ctx->stream->
2772                                 gamut_remap_matrix.matrix[6];
2773                 adjust.temperature_matrix[6] =
2774                                 pipe_ctx->stream->
2775                                 gamut_remap_matrix.matrix[8];
2776                 adjust.temperature_matrix[7] =
2777                                 pipe_ctx->stream->
2778                                 gamut_remap_matrix.matrix[9];
2779                 adjust.temperature_matrix[8] =
2780                                 pipe_ctx->stream->
2781                                 gamut_remap_matrix.matrix[10];
2782         }
2783
2784         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2785
2786         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2787
2788         program_scaler(dc, pipe_ctx);
2789
2790 #if defined(CONFIG_DRM_AMD_DC_FBC)
2791         if (dc->fbc_compressor && old_pipe->stream) {
2792                 if (plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
2793                         dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2794                 else
2795                         enable_fbc(dc, dc->current_state);
2796         }
2797 #endif
2798
2799         mi->funcs->mem_input_program_surface_config(
2800                         mi,
2801                         plane_state->format,
2802                         &plane_state->tiling_info,
2803                         &plane_state->plane_size,
2804                         plane_state->rotation,
2805                         NULL,
2806                         false);
2807         if (mi->funcs->set_blank)
2808                 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2809
2810         if (dc->config.gpu_vm_support)
2811                 mi->funcs->mem_input_program_pte_vm(
2812                                 pipe_ctx->plane_res.mi,
2813                                 plane_state->format,
2814                                 &plane_state->tiling_info,
2815                                 plane_state->rotation);
2816
2817         /* Moved programming gamma from dc to hwss */
2818         if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) {
2819                 dc->hwss.set_input_transfer_func(
2820                                 pipe_ctx, pipe_ctx->plane_state);
2821                 dc->hwss.set_output_transfer_func(
2822                                 pipe_ctx, pipe_ctx->stream);
2823         }
2824
2825         dm_logger_write(dc->ctx->logger, LOG_SURFACE,
2826                         "Pipe:%d 0x%x: addr hi:0x%x, "
2827                         "addr low:0x%x, "
2828                         "src: %d, %d, %d,"
2829                         " %d; dst: %d, %d, %d, %d;"
2830                         "clip: %d, %d, %d, %d\n",
2831                         pipe_ctx->pipe_idx,
2832                         pipe_ctx->plane_state,
2833                         pipe_ctx->plane_state->address.grph.addr.high_part,
2834                         pipe_ctx->plane_state->address.grph.addr.low_part,
2835                         pipe_ctx->plane_state->src_rect.x,
2836                         pipe_ctx->plane_state->src_rect.y,
2837                         pipe_ctx->plane_state->src_rect.width,
2838                         pipe_ctx->plane_state->src_rect.height,
2839                         pipe_ctx->plane_state->dst_rect.x,
2840                         pipe_ctx->plane_state->dst_rect.y,
2841                         pipe_ctx->plane_state->dst_rect.width,
2842                         pipe_ctx->plane_state->dst_rect.height,
2843                         pipe_ctx->plane_state->clip_rect.x,
2844                         pipe_ctx->plane_state->clip_rect.y,
2845                         pipe_ctx->plane_state->clip_rect.width,
2846                         pipe_ctx->plane_state->clip_rect.height);
2847
2848         dm_logger_write(dc->ctx->logger, LOG_SURFACE,
2849                         "Pipe %d: width, height, x, y\n"
2850                         "viewport:%d, %d, %d, %d\n"
2851                         "recout:  %d, %d, %d, %d\n",
2852                         pipe_ctx->pipe_idx,
2853                         pipe_ctx->plane_res.scl_data.viewport.width,
2854                         pipe_ctx->plane_res.scl_data.viewport.height,
2855                         pipe_ctx->plane_res.scl_data.viewport.x,
2856                         pipe_ctx->plane_res.scl_data.viewport.y,
2857                         pipe_ctx->plane_res.scl_data.recout.width,
2858                         pipe_ctx->plane_res.scl_data.recout.height,
2859                         pipe_ctx->plane_res.scl_data.recout.x,
2860                         pipe_ctx->plane_res.scl_data.recout.y);
2861 }
2862
2863 static void dce110_apply_ctx_for_surface(
2864                 struct dc *dc,
2865                 const struct dc_stream_state *stream,
2866                 int num_planes,
2867                 struct dc_state *context)
2868 {
2869         int i;
2870
2871         if (num_planes == 0)
2872                 return;
2873
2874         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2875                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2876                 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2877
2878                 if (stream == pipe_ctx->stream) {
2879                         if (!pipe_ctx->top_pipe &&
2880                                 (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
2881                                 dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
2882                 }
2883         }
2884
2885         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2886                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2887
2888                 if (pipe_ctx->stream != stream)
2889                         continue;
2890
2891                 /* Need to allocate mem before program front end for Fiji */
2892                 if (pipe_ctx->plane_res.mi != NULL)
2893                         pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
2894                                         pipe_ctx->plane_res.mi,
2895                                         pipe_ctx->stream->timing.h_total,
2896                                         pipe_ctx->stream->timing.v_total,
2897                                         pipe_ctx->stream->timing.pix_clk_khz,
2898                                         context->stream_count);
2899
2900                 dce110_program_front_end_for_pipe(dc, pipe_ctx);
2901
2902                 dc->hwss.update_plane_addr(dc, pipe_ctx);
2903
2904                 program_surface_visibility(dc, pipe_ctx);
2905
2906         }
2907
2908         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2909                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2910                 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2911
2912                 if ((stream == pipe_ctx->stream) &&
2913                         (!pipe_ctx->top_pipe) &&
2914                         (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
2915                         dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
2916         }
2917 }
2918
2919 static void dce110_power_down_fe(struct dc *dc, int fe_idx)
2920 {
2921         /* Do not power down fe when stream is active on dce*/
2922         if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
2923                 return;
2924
2925         dc->hwss.enable_display_power_gating(
2926                 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2927
2928         dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
2929                                 dc->res_pool->transforms[fe_idx]);
2930 }
2931
2932 static void dce110_wait_for_mpcc_disconnect(
2933                 struct dc *dc,
2934                 struct resource_pool *res_pool,
2935                 struct pipe_ctx *pipe_ctx)
2936 {
2937         /* do nothing*/
2938 }
2939
2940 static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
2941                 enum dc_color_space colorspace,
2942                 uint16_t *matrix)
2943 {
2944         int i;
2945         struct out_csc_color_matrix tbl_entry;
2946
2947         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2948                                 == true) {
2949                         enum dc_color_space color_space =
2950                                 pipe_ctx->stream->output_color_space;
2951
2952                         //uint16_t matrix[12];
2953                         for (i = 0; i < 12; i++)
2954                                 tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
2955
2956                         tbl_entry.color_space = color_space;
2957                         //tbl_entry.regval = matrix;
2958                         pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.xfm, &tbl_entry);
2959         }
2960 }
2961
2962 static void ready_shared_resources(struct dc *dc, struct dc_state *context) {}
2963
2964 static void optimize_shared_resources(struct dc *dc) {}
2965
2966 static const struct hw_sequencer_funcs dce110_funcs = {
2967         .program_gamut_remap = program_gamut_remap,
2968         .program_csc_matrix = program_csc_matrix,
2969         .init_hw = init_hw,
2970         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2971         .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
2972         .set_plane_config = set_plane_config,
2973         .update_plane_addr = update_plane_addr,
2974         .update_pending_status = dce110_update_pending_status,
2975         .set_input_transfer_func = dce110_set_input_transfer_func,
2976         .set_output_transfer_func = dce110_set_output_transfer_func,
2977         .power_down = dce110_power_down,
2978         .enable_accelerated_mode = dce110_enable_accelerated_mode,
2979         .enable_timing_synchronization = dce110_enable_timing_synchronization,
2980         .update_info_frame = dce110_update_info_frame,
2981         .enable_stream = dce110_enable_stream,
2982         .disable_stream = dce110_disable_stream,
2983         .unblank_stream = dce110_unblank_stream,
2984         .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
2985         .enable_display_power_gating = dce110_enable_display_power_gating,
2986         .power_down_front_end = dce110_power_down_fe,
2987         .pipe_control_lock = dce_pipe_control_lock,
2988         .set_bandwidth = dce110_set_bandwidth,
2989         .set_drr = set_drr,
2990         .get_position = get_position,
2991         .set_static_screen_control = set_static_screen_control,
2992         .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
2993         .prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg,
2994         .setup_stereo = NULL,
2995         .set_avmute = dce110_set_avmute,
2996         .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
2997         .ready_shared_resources = ready_shared_resources,
2998         .optimize_shared_resources = optimize_shared_resources,
2999         .edp_backlight_control = hwss_edp_backlight_control,
3000         .edp_power_control = hwss_edp_power_control,
3001 };
3002
3003 void dce110_hw_sequencer_construct(struct dc *dc)
3004 {
3005         dc->hwss = dce110_funcs;
3006 }
3007