drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include "dm_services.h"
  26 #include "dc.h"
  27 #include "dc_bios_types.h"
  28 #include "core_types.h"
  29 #include "core_status.h"
  30 #include "resource.h"
  31 #include "dm_helpers.h"
  32 #include "dce110_hw_sequencer.h"
  33 #include "dce110_timing_generator.h"
  34 #include "dce/dce_hwseq.h"
  35 #include "gpio_service_interface.h"
  36
  37 #include "dce110_compressor.h"
  38
  39 #include "bios/bios_parser_helper.h"
  40 #include "timing_generator.h"
  41 #include "mem_input.h"
  42 #include "opp.h"
  43 #include "ipp.h"
  44 #include "transform.h"
  45 #include "stream_encoder.h"
  46 #include "link_encoder.h"
  47 #include "link_hwss.h"
  48 #include "clock_source.h"
  49 #include "abm.h"
  50 #include "audio.h"
  51 #include "reg_helper.h"
  52
  53 /* include DCE11 register header files */
  54 #include "dce/dce_11_0_d.h"
  55 #include "dce/dce_11_0_sh_mask.h"
  56 #include "custom_float.h"
  57
  58 #include "atomfirmware.h"
  59
  60 /*
  61  * All values are in milliseconds;
  62  * For eDP, after power-up/power/down,
  63  * 300/500 msec max. delay from LCDVCC to black video generation
  64  */
  65 #define PANEL_POWER_UP_TIMEOUT 300
  66 #define PANEL_POWER_DOWN_TIMEOUT 500
  67 #define HPD_CHECK_INTERVAL 10
  68
  69 #define CTX \
  70         hws->ctx
  71
  72 #define DC_LOGGER_INIT()
  73
  74 #define REG(reg)\
  75         hws->regs->reg
  76
  77 #undef FN
  78 #define FN(reg_name, field_name) \
  79         hws->shifts->field_name, hws->masks->field_name
  80
  81 struct dce110_hw_seq_reg_offsets {
  82         uint32_t crtc;
  83 };
  84
  85 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
  86 {
  87         .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  88 },
  89 {
  90         .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  91 },
  92 {
  93         .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  94 },
  95 {
  96         .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  97 }
  98 };
  99
 100 #define HW_REG_BLND(reg, id)\
 101         (reg + reg_offsets[id].blnd)
 102
 103 #define HW_REG_CRTC(reg, id)\
 104         (reg + reg_offsets[id].crtc)
 105
 106 #define MAX_WATERMARK 0xFFFF
 107 #define SAFE_NBP_MARK 0x7FFF
 108
 109 /*******************************************************************************
 110  * Private definitions
 111  ******************************************************************************/
 112 /***************************PIPE_CONTROL***********************************/
 113 static void dce110_init_pte(struct dc_context *ctx)
 114 {
 115         uint32_t addr;
 116         uint32_t value = 0;
 117         uint32_t chunk_int = 0;
 118         uint32_t chunk_mul = 0;
 119
 120         addr = mmUNP_DVMM_PTE_CONTROL;
 121         value = dm_read_reg(ctx, addr);
 122
 123         set_reg_field_value(
 124                 value,
 125                 0,
 126                 DVMM_PTE_CONTROL,
 127                 DVMM_USE_SINGLE_PTE);
 128
 129         set_reg_field_value(
 130                 value,
 131                 1,
 132                 DVMM_PTE_CONTROL,
 133                 DVMM_PTE_BUFFER_MODE0);
 134
 135         set_reg_field_value(
 136                 value,
 137                 1,
 138                 DVMM_PTE_CONTROL,
 139                 DVMM_PTE_BUFFER_MODE1);
 140
 141         dm_write_reg(ctx, addr, value);
 142
 143         addr = mmDVMM_PTE_REQ;
 144         value = dm_read_reg(ctx, addr);
 145
 146         chunk_int = get_reg_field_value(
 147                 value,
 148                 DVMM_PTE_REQ,
 149                 HFLIP_PTEREQ_PER_CHUNK_INT);
 150
 151         chunk_mul = get_reg_field_value(
 152                 value,
 153                 DVMM_PTE_REQ,
 154                 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 155
 156         if (chunk_int != 0x4 || chunk_mul != 0x4) {
 157
 158                 set_reg_field_value(
 159                         value,
 160                         255,
 161                         DVMM_PTE_REQ,
 162                         MAX_PTEREQ_TO_ISSUE);
 163
 164                 set_reg_field_value(
 165                         value,
 166                         4,
 167                         DVMM_PTE_REQ,
 168                         HFLIP_PTEREQ_PER_CHUNK_INT);
 169
 170                 set_reg_field_value(
 171                         value,
 172                         4,
 173                         DVMM_PTE_REQ,
 174                         HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 175
 176                 dm_write_reg(ctx, addr, value);
 177         }
 178 }
 179 /**************************************************************************/
 180
 181 static void enable_display_pipe_clock_gating(
 182         struct dc_context *ctx,
 183         bool clock_gating)
 184 {
 185         /*TODO*/
 186 }
 187
 188 static bool dce110_enable_display_power_gating(
 189         struct dc *dc,
 190         uint8_t controller_id,
 191         struct dc_bios *dcb,
 192         enum pipe_gating_control power_gating)
 193 {
 194         enum bp_result bp_result = BP_RESULT_OK;
 195         enum bp_pipe_control_action cntl;
 196         struct dc_context *ctx = dc->ctx;
 197         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
 198
 199         if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
 200                 return true;
 201
 202         if (power_gating == PIPE_GATING_CONTROL_INIT)
 203                 cntl = ASIC_PIPE_INIT;
 204         else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
 205                 cntl = ASIC_PIPE_ENABLE;
 206         else
 207                 cntl = ASIC_PIPE_DISABLE;
 208
 209         if (controller_id == underlay_idx)
 210                 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
 211
 212         if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
 213
 214                 bp_result = dcb->funcs->enable_disp_power_gating(
 215                                                 dcb, controller_id + 1, cntl);
 216
 217                 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
 218                  * by default when command table is called
 219                  *
 220                  * Bios parser accepts controller_id = 6 as indicative of
 221                  * underlay pipe in dce110. But we do not support more
 222                  * than 3.
 223                  */
 224                 if (controller_id < CONTROLLER_ID_MAX - 1)
 225                         dm_write_reg(ctx,
 226                                 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
 227                                 0);
 228         }
 229
 230         if (power_gating != PIPE_GATING_CONTROL_ENABLE)
 231                 dce110_init_pte(ctx);
 232
 233         if (bp_result == BP_RESULT_OK)
 234                 return true;
 235         else
 236                 return false;
 237 }
 238
 239 static void build_prescale_params(struct ipp_prescale_params *prescale_params,
 240                 const struct dc_plane_state *plane_state)
 241 {
 242         prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
 243
 244         switch (plane_state->format) {
 245         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 246         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 247                 prescale_params->scale = 0x2020;
 248                 break;
 249         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 250         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 251                 prescale_params->scale = 0x2008;
 252                 break;
 253         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 254         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 255                 prescale_params->scale = 0x2000;
 256                 break;
 257         default:
 258                 ASSERT(false);
 259                 break;
 260         }
 261 }
 262
 263 static bool
 264 dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
 265                                const struct dc_plane_state *plane_state)
 266 {
 267         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
 268         const struct dc_transfer_func *tf = NULL;
 269         struct ipp_prescale_params prescale_params = { 0 };
 270         bool result = true;
 271
 272         if (ipp == NULL)
 273                 return false;
 274
 275         if (plane_state->in_transfer_func)
 276                 tf = plane_state->in_transfer_func;
 277
 278         build_prescale_params(&prescale_params, plane_state);
 279         ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
 280
 281         if (plane_state->gamma_correction &&
 282                         !plane_state->gamma_correction->is_identity &&
 283                         dce_use_lut(plane_state->format))
 284                 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
 285
 286         if (tf == NULL) {
 287                 /* Default case if no input transfer function specified */
 288                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 289         } else if (tf->type == TF_TYPE_PREDEFINED) {
 290                 switch (tf->tf) {
 291                 case TRANSFER_FUNCTION_SRGB:
 292                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 293                         break;
 294                 case TRANSFER_FUNCTION_BT709:
 295                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC);
 296                         break;
 297                 case TRANSFER_FUNCTION_LINEAR:
 298                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 299                         break;
 300                 case TRANSFER_FUNCTION_PQ:
 301                 default:
 302                         result = false;
 303                         break;
 304                 }
 305         } else if (tf->type == TF_TYPE_BYPASS) {
 306                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 307         } else {
 308                 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
 309                 result = false;
 310         }
 311
 312         return result;
 313 }
 314
 315 static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,
 316                                     struct curve_points *arr_points,
 317                                     uint32_t hw_points_num)
 318 {
 319         struct custom_float_format fmt;
 320
 321         struct pwl_result_data *rgb = rgb_resulted;
 322
 323         uint32_t i = 0;
 324
 325         fmt.exponenta_bits = 6;
 326         fmt.mantissa_bits = 12;
 327         fmt.sign = true;
 328
 329         if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
 330                                             &arr_points[0].custom_float_x)) {
 331                 BREAK_TO_DEBUGGER();
 332                 return false;
 333         }
 334
 335         if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
 336                                             &arr_points[0].custom_float_offset)) {
 337                 BREAK_TO_DEBUGGER();
 338                 return false;
 339         }
 340
 341         if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
 342                                             &arr_points[0].custom_float_slope)) {
 343                 BREAK_TO_DEBUGGER();
 344                 return false;
 345         }
 346
 347         fmt.mantissa_bits = 10;
 348         fmt.sign = false;
 349
 350         if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
 351                                             &arr_points[1].custom_float_x)) {
 352                 BREAK_TO_DEBUGGER();
 353                 return false;
 354         }
 355
 356         if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
 357                                             &arr_points[1].custom_float_y)) {
 358                 BREAK_TO_DEBUGGER();
 359                 return false;
 360         }
 361
 362         if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,
 363                                             &arr_points[1].custom_float_slope)) {
 364                 BREAK_TO_DEBUGGER();
 365                 return false;
 366         }
 367
 368         fmt.mantissa_bits = 12;
 369         fmt.sign = true;
 370
 371         while (i != hw_points_num) {
 372                 if (!convert_to_custom_float_format(rgb->red, &fmt,
 373                                                     &rgb->red_reg)) {
 374                         BREAK_TO_DEBUGGER();
 375                         return false;
 376                 }
 377
 378                 if (!convert_to_custom_float_format(rgb->green, &fmt,
 379                                                     &rgb->green_reg)) {
 380                         BREAK_TO_DEBUGGER();
 381                         return false;
 382                 }
 383
 384                 if (!convert_to_custom_float_format(rgb->blue, &fmt,
 385                                                     &rgb->blue_reg)) {
 386                         BREAK_TO_DEBUGGER();
 387                         return false;
 388                 }
 389
 390                 if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
 391                                                     &rgb->delta_red_reg)) {
 392                         BREAK_TO_DEBUGGER();
 393                         return false;
 394                 }
 395
 396                 if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
 397                                                     &rgb->delta_green_reg)) {
 398                         BREAK_TO_DEBUGGER();
 399                         return false;
 400                 }
 401
 402                 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
 403                                                     &rgb->delta_blue_reg)) {
 404                         BREAK_TO_DEBUGGER();
 405                         return false;
 406                 }
 407
 408                 ++rgb;
 409                 ++i;
 410         }
 411
 412         return true;
 413 }
 414
 415 #define MAX_LOW_POINT      25
 416 #define NUMBER_REGIONS     16
 417 #define NUMBER_SW_SEGMENTS 16
 418
 419 static bool
 420 dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
 421                                       struct pwl_params *regamma_params)
 422 {
 423         struct curve_points *arr_points;
 424         struct pwl_result_data *rgb_resulted;
 425         struct pwl_result_data *rgb;
 426         struct pwl_result_data *rgb_plus_1;
 427         struct fixed31_32 y_r;
 428         struct fixed31_32 y_g;
 429         struct fixed31_32 y_b;
 430         struct fixed31_32 y1_min;
 431         struct fixed31_32 y3_max;
 432
 433         int32_t region_start, region_end;
 434         uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points;
 435
 436         if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
 437                 return false;
 438
 439         arr_points = regamma_params->arr_points;
 440         rgb_resulted = regamma_params->rgb_resulted;
 441         hw_points = 0;
 442
 443         memset(regamma_params, 0, sizeof(struct pwl_params));
 444
 445         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 446                 /* 16 segments
 447                  * segments are from 2^-11 to 2^5
 448                  */
 449                 region_start = -11;
 450                 region_end = region_start + NUMBER_REGIONS;
 451
 452                 for (i = 0; i < NUMBER_REGIONS; i++)
 453                         seg_distr[i] = 4;
 454
 455         } else {
 456                 /* 10 segments
 457                  * segment is from 2^-10 to 2^1
 458                  * We include an extra segment for range [2^0, 2^1). This is to
 459                  * ensure that colors with normalized values of 1 don't miss the
 460                  * LUT.
 461                  */
 462                 region_start = -10;
 463                 region_end = 1;
 464
 465                 seg_distr[0] = 4;
 466                 seg_distr[1] = 4;
 467                 seg_distr[2] = 4;
 468                 seg_distr[3] = 4;
 469                 seg_distr[4] = 4;
 470                 seg_distr[5] = 4;
 471                 seg_distr[6] = 4;
 472                 seg_distr[7] = 4;
 473                 seg_distr[8] = 4;
 474                 seg_distr[9] = 4;
 475                 seg_distr[10] = 0;
 476                 seg_distr[11] = -1;
 477                 seg_distr[12] = -1;
 478                 seg_distr[13] = -1;
 479                 seg_distr[14] = -1;
 480                 seg_distr[15] = -1;
 481         }
 482
 483         for (k = 0; k < 16; k++) {
 484                 if (seg_distr[k] != -1)
 485                         hw_points += (1 << seg_distr[k]);
 486         }
 487
 488         j = 0;
 489         for (k = 0; k < (region_end - region_start); k++) {
 490                 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
 491                 start_index = (region_start + k + MAX_LOW_POINT) *
 492                                 NUMBER_SW_SEGMENTS;
 493                 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS;
 494                                 i += increment) {
 495                         if (j == hw_points - 1)
 496                                 break;
 497                         rgb_resulted[j].red = output_tf->tf_pts.red[i];
 498                         rgb_resulted[j].green = output_tf->tf_pts.green[i];
 499                         rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
 500                         j++;
 501                 }
 502         }
 503
 504         /* last point */
 505         start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS;
 506         rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
 507         rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
 508         rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
 509
 510         arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2),
 511                                              dc_fixpt_from_int(region_start));
 512         arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2),
 513                                              dc_fixpt_from_int(region_end));
 514
 515         y_r = rgb_resulted[0].red;
 516         y_g = rgb_resulted[0].green;
 517         y_b = rgb_resulted[0].blue;
 518
 519         y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b));
 520
 521         arr_points[0].y = y1_min;
 522         arr_points[0].slope = dc_fixpt_div(arr_points[0].y,
 523                                                  arr_points[0].x);
 524
 525         y_r = rgb_resulted[hw_points - 1].red;
 526         y_g = rgb_resulted[hw_points - 1].green;
 527         y_b = rgb_resulted[hw_points - 1].blue;
 528
 529         /* see comment above, m_arrPoints[1].y should be the Y value for the
 530          * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
 531          */
 532         y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b));
 533
 534         arr_points[1].y = y3_max;
 535
 536         arr_points[1].slope = dc_fixpt_zero;
 537
 538         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 539                 /* for PQ, we want to have a straight line from last HW X point,
 540                  * and the slope to be such that we hit 1.0 at 10000 nits.
 541                  */
 542                 const struct fixed31_32 end_value = dc_fixpt_from_int(125);
 543
 544                 arr_points[1].slope = dc_fixpt_div(
 545                                 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y),
 546                                 dc_fixpt_sub(end_value, arr_points[1].x));
 547         }
 548
 549         regamma_params->hw_points_num = hw_points;
 550
 551         k = 0;
 552         for (i = 1; i < 16; i++) {
 553                 if (seg_distr[k] != -1) {
 554                         regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 555                         regamma_params->arr_curve_points[i].offset =
 556                                         regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
 557                 }
 558                 k++;
 559         }
 560
 561         if (seg_distr[k] != -1)
 562                 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 563
 564         rgb = rgb_resulted;
 565         rgb_plus_1 = rgb_resulted + 1;
 566
 567         i = 1;
 568
 569         while (i != hw_points + 1) {
 570                 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
 571                         rgb_plus_1->red = rgb->red;
 572                 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
 573                         rgb_plus_1->green = rgb->green;
 574                 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
 575                         rgb_plus_1->blue = rgb->blue;
 576
 577                 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
 578                 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
 579                 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
 580
 581                 ++rgb_plus_1;
 582                 ++rgb;
 583                 ++i;
 584         }
 585
 586         convert_to_custom_float(rgb_resulted, arr_points, hw_points);
 587
 588         return true;
 589 }
 590
 591 static bool
 592 dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
 593                                 const struct dc_stream_state *stream)
 594 {
 595         struct transform *xfm = pipe_ctx->plane_res.xfm;
 596
 597         xfm->funcs->opp_power_on_regamma_lut(xfm, true);
 598         xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
 599
 600         if (stream->out_transfer_func &&
 601             stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
 602             stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) {
 603                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
 604         } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func,
 605                                                          &xfm->regamma_params)) {
 606                 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
 607                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
 608         } else {
 609                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
 610         }
 611
 612         xfm->funcs->opp_power_on_regamma_lut(xfm, false);
 613
 614         return true;
 615 }
 616
 617 static enum dc_status bios_parser_crtc_source_select(
 618                 struct pipe_ctx *pipe_ctx)
 619 {
 620         struct dc_bios *dcb;
 621         /* call VBIOS table to set CRTC source for the HW
 622          * encoder block
 623          * note: video bios clears all FMT setting here. */
 624         struct bp_crtc_source_select crtc_source_select = {0};
 625         const struct dc_sink *sink = pipe_ctx->stream->sink;
 626
 627         crtc_source_select.engine_id = pipe_ctx->stream_res.stream_enc->id;
 628         crtc_source_select.controller_id = pipe_ctx->stream_res.tg->inst + 1;
 629         /*TODO: Need to un-hardcode color depth, dp_audio and account for
 630          * the case where signal and sink signal is different (translator
 631          * encoder)*/
 632         crtc_source_select.signal = pipe_ctx->stream->signal;
 633         crtc_source_select.enable_dp_audio = false;
 634         crtc_source_select.sink_signal = pipe_ctx->stream->signal;
 635
 636         switch (pipe_ctx->stream->timing.display_color_depth) {
 637         case COLOR_DEPTH_666:
 638                 crtc_source_select.display_output_bit_depth = PANEL_6BIT_COLOR;
 639                 break;
 640         case COLOR_DEPTH_888:
 641                 crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
 642                 break;
 643         case COLOR_DEPTH_101010:
 644                 crtc_source_select.display_output_bit_depth = PANEL_10BIT_COLOR;
 645                 break;
 646         case COLOR_DEPTH_121212:
 647                 crtc_source_select.display_output_bit_depth = PANEL_12BIT_COLOR;
 648                 break;
 649         default:
 650                 BREAK_TO_DEBUGGER();
 651                 crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
 652                 break;
 653         }
 654
 655         dcb = sink->ctx->dc_bios;
 656
 657         if (BP_RESULT_OK != dcb->funcs->crtc_source_select(
 658                 dcb,
 659                 &crtc_source_select)) {
 660                 return DC_ERROR_UNEXPECTED;
 661         }
 662
 663         return DC_OK;
 664 }
 665
 666 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
 667 {
 668         bool is_hdmi;
 669         bool is_dp;
 670
 671         ASSERT(pipe_ctx->stream);
 672
 673         if (pipe_ctx->stream_res.stream_enc == NULL)
 674                 return;  /* this is not root pipe */
 675
 676         is_hdmi = dc_is_hdmi_signal(pipe_ctx->stream->signal);
 677         is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
 678
 679         if (!is_hdmi && !is_dp)
 680                 return;
 681
 682         if (is_hdmi)
 683                 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
 684                         pipe_ctx->stream_res.stream_enc,
 685                         &pipe_ctx->stream_res.encoder_info_frame);
 686         else
 687                 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
 688                         pipe_ctx->stream_res.stream_enc,
 689                         &pipe_ctx->stream_res.encoder_info_frame);
 690 }
 691
 692 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
 693 {
 694         enum dc_lane_count lane_count =
 695                 pipe_ctx->stream->sink->link->cur_link_settings.lane_count;
 696
 697         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
 698         struct dc_link *link = pipe_ctx->stream->sink->link;
 699
 700
 701         uint32_t active_total_with_borders;
 702         uint32_t early_control = 0;
 703         struct timing_generator *tg = pipe_ctx->stream_res.tg;
 704
 705         /* For MST, there are multiply stream go to only one link.
 706          * connect DIG back_end to front_end while enable_stream and
 707          * disconnect them during disable_stream
 708          * BY this, it is logic clean to separate stream and link */
 709         link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
 710                                                     pipe_ctx->stream_res.stream_enc->id, true);
 711
 712         /* update AVI info frame (HDMI, DP)*/
 713         /* TODO: FPGA may change to hwss.update_info_frame */
 714         dce110_update_info_frame(pipe_ctx);
 715
 716         /* enable early control to avoid corruption on DP monitor*/
 717         active_total_with_borders =
 718                         timing->h_addressable
 719                                 + timing->h_border_left
 720                                 + timing->h_border_right;
 721
 722         if (lane_count != 0)
 723                 early_control = active_total_with_borders % lane_count;
 724
 725         if (early_control == 0)
 726                 early_control = lane_count;
 727
 728         tg->funcs->set_early_control(tg, early_control);
 729
 730         /* enable audio only within mode set */
 731         if (pipe_ctx->stream_res.audio != NULL) {
 732                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
 733                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
 734         }
 735
 736
 737
 738
 739 }
 740
 741 /*todo: cloned in stream enc, fix*/
 742 static bool is_panel_backlight_on(struct dce_hwseq *hws)
 743 {
 744         uint32_t value;
 745
 746         REG_GET(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, &value);
 747
 748         return value;
 749 }
 750
 751 static bool is_panel_powered_on(struct dce_hwseq *hws)
 752 {
 753         uint32_t pwr_seq_state, dig_on, dig_on_ovrd;
 754
 755
 756         REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state);
 757
 758         REG_GET_2(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, &dig_on, LVTMA_DIGON_OVRD, &dig_on_ovrd);
 759
 760         return (pwr_seq_state == 1) || (dig_on == 1 && dig_on_ovrd == 1);
 761 }
 762
 763 static enum bp_result link_transmitter_control(
 764                 struct dc_bios *bios,
 765         struct bp_transmitter_control *cntl)
 766 {
 767         enum bp_result result;
 768
 769         result = bios->funcs->transmitter_control(bios, cntl);
 770
 771         return result;
 772 }
 773
 774 /*
 775  * @brief
 776  * eDP only.
 777  */
 778 void hwss_edp_wait_for_hpd_ready(
 779                 struct dc_link *link,
 780                 bool power_up)
 781 {
 782         struct dc_context *ctx = link->ctx;
 783         struct graphics_object_id connector = link->link_enc->connector;
 784         struct gpio *hpd;
 785         bool edp_hpd_high = false;
 786         uint32_t time_elapsed = 0;
 787         uint32_t timeout = power_up ?
 788                 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
 789
 790         if (dal_graphics_object_id_get_connector_id(connector)
 791                         != CONNECTOR_ID_EDP) {
 792                 BREAK_TO_DEBUGGER();
 793                 return;
 794         }
 795
 796         if (!power_up)
 797                 /*
 798                  * From KV, we will not HPD low after turning off VCC -
 799                  * instead, we will check the SW timer in power_up().
 800                  */
 801                 return;
 802
 803         /*
 804          * When we power on/off the eDP panel,
 805          * we need to wait until SENSE bit is high/low.
 806          */
 807
 808         /* obtain HPD */
 809         /* TODO what to do with this? */
 810         hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);
 811
 812         if (!hpd) {
 813                 BREAK_TO_DEBUGGER();
 814                 return;
 815         }
 816
 817         dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);
 818
 819         /* wait until timeout or panel detected */
 820
 821         do {
 822                 uint32_t detected = 0;
 823
 824                 dal_gpio_get_value(hpd, &detected);
 825
 826                 if (!(detected ^ power_up)) {
 827                         edp_hpd_high = true;
 828                         break;
 829                 }
 830
 831                 msleep(HPD_CHECK_INTERVAL);
 832
 833                 time_elapsed += HPD_CHECK_INTERVAL;
 834         } while (time_elapsed < timeout);
 835
 836         dal_gpio_close(hpd);
 837
 838         dal_gpio_destroy_irq(&hpd);
 839
 840         if (false == edp_hpd_high) {
 841                 DC_LOG_ERROR(
 842                                 "%s: wait timed out!\n", __func__);
 843         }
 844 }
 845
 846 void hwss_edp_power_control(
 847                 struct dc_link *link,
 848                 bool power_up)
 849 {
 850         struct dc_context *ctx = link->ctx;
 851         struct dce_hwseq *hwseq = ctx->dc->hwseq;
 852         struct bp_transmitter_control cntl = { 0 };
 853         enum bp_result bp_result;
 854
 855
 856         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 857                         != CONNECTOR_ID_EDP) {
 858                 BREAK_TO_DEBUGGER();
 859                 return;
 860         }
 861
 862         if (power_up != is_panel_powered_on(hwseq)) {
 863                 /* Send VBIOS command to prompt eDP panel power */
 864                 if (power_up) {
 865                         unsigned long long current_ts = dm_get_timestamp(ctx);
 866                         unsigned long long duration_in_ms =
 867                                         div64_u64(dm_get_elapse_time_in_ns(
 868                                                         ctx,
 869                                                         current_ts,
 870                                                         link->link_trace.time_stamp.edp_poweroff), 1000000);
 871                         unsigned long long wait_time_ms = 0;
 872
 873                         /* max 500ms from LCDVDD off to on */
 874                         unsigned long long edp_poweroff_time_ms = 500;
 875
 876                         if (link->local_sink != NULL)
 877                                 edp_poweroff_time_ms =
 878                                                 500 + link->local_sink->edid_caps.panel_patch.extra_t12_ms;
 879                         if (link->link_trace.time_stamp.edp_poweroff == 0)
 880                                 wait_time_ms = edp_poweroff_time_ms;
 881                         else if (duration_in_ms < edp_poweroff_time_ms)
 882                                 wait_time_ms = edp_poweroff_time_ms - duration_in_ms;
 883
 884                         if (wait_time_ms) {
 885                                 msleep(wait_time_ms);
 886                                 dm_output_to_console("%s: wait %lld ms to power on eDP.\n",
 887                                                 __func__, wait_time_ms);
 888                         }
 889
 890                 }
 891
 892                 DC_LOG_HW_RESUME_S3(
 893                                 "%s: Panel Power action: %s\n",
 894                                 __func__, (power_up ? "On":"Off"));
 895
 896                 cntl.action = power_up ?
 897                         TRANSMITTER_CONTROL_POWER_ON :
 898                         TRANSMITTER_CONTROL_POWER_OFF;
 899                 cntl.transmitter = link->link_enc->transmitter;
 900                 cntl.connector_obj_id = link->link_enc->connector;
 901                 cntl.coherent = false;
 902                 cntl.lanes_number = LANE_COUNT_FOUR;
 903                 cntl.hpd_sel = link->link_enc->hpd_source;
 904                 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
 905
 906                 if (!power_up)
 907                         /*save driver power off time stamp*/
 908                         link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx);
 909                 else
 910                         link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx);
 911
 912                 if (bp_result != BP_RESULT_OK)
 913                         DC_LOG_ERROR(
 914                                         "%s: Panel Power bp_result: %d\n",
 915                                         __func__, bp_result);
 916         } else {
 917                 DC_LOG_HW_RESUME_S3(
 918                                 "%s: Skipping Panel Power action: %s\n",
 919                                 __func__, (power_up ? "On":"Off"));
 920         }
 921 }
 922
 923 /*todo: cloned in stream enc, fix*/
 924 /*
 925  * @brief
 926  * eDP only. Control the backlight of the eDP panel
 927  */
 928 void hwss_edp_backlight_control(
 929                 struct dc_link *link,
 930                 bool enable)
 931 {
 932         struct dc_context *ctx = link->ctx;
 933         struct dce_hwseq *hws = ctx->dc->hwseq;
 934         struct bp_transmitter_control cntl = { 0 };
 935
 936         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 937                 != CONNECTOR_ID_EDP) {
 938                 BREAK_TO_DEBUGGER();
 939                 return;
 940         }
 941
 942         if (enable && is_panel_backlight_on(hws)) {
 943                 DC_LOG_HW_RESUME_S3(
 944                                 "%s: panel already powered up. Do nothing.\n",
 945                                 __func__);
 946                 return;
 947         }
 948
 949         /* Send VBIOS command to control eDP panel backlight */
 950
 951         DC_LOG_HW_RESUME_S3(
 952                         "%s: backlight action: %s\n",
 953                         __func__, (enable ? "On":"Off"));
 954
 955         cntl.action = enable ?
 956                 TRANSMITTER_CONTROL_BACKLIGHT_ON :
 957                 TRANSMITTER_CONTROL_BACKLIGHT_OFF;
 958
 959         /*cntl.engine_id = ctx->engine;*/
 960         cntl.transmitter = link->link_enc->transmitter;
 961         cntl.connector_obj_id = link->link_enc->connector;
 962         /*todo: unhardcode*/
 963         cntl.lanes_number = LANE_COUNT_FOUR;
 964         cntl.hpd_sel = link->link_enc->hpd_source;
 965         cntl.signal = SIGNAL_TYPE_EDP;
 966
 967         /* For eDP, the following delays might need to be considered
 968          * after link training completed:
 969          * idle period - min. accounts for required BS-Idle pattern,
 970          * max. allows for source frame synchronization);
 971          * 50 msec max. delay from valid video data from source
 972          * to video on dislpay or backlight enable.
 973          *
 974          * Disable the delay for now.
 975          * Enable it in the future if necessary.
 976          */
 977         /* dc_service_sleep_in_milliseconds(50); */
 978                 /*edp 1.2*/
 979         if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
 980                 edp_receiver_ready_T7(link);
 981         link_transmitter_control(ctx->dc_bios, &cntl);
 982         /*edp 1.2*/
 983         if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF)
 984                 edp_receiver_ready_T9(link);
 985 }
 986
 987 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
 988 {
 989         struct dc *core_dc = pipe_ctx->stream->ctx->dc;
 990         /* notify audio driver for audio modes of monitor */
 991         struct pp_smu_funcs_rv *pp_smu = core_dc->res_pool->pp_smu;
 992         unsigned int i, num_audio = 1;
 993
 994         if (pipe_ctx->stream_res.audio) {
 995                 for (i = 0; i < MAX_PIPES; i++) {
 996                         /*current_state not updated yet*/
 997                         if (core_dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
 998                                 num_audio++;
 999                 }
1000
1001                 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
1002
1003                 if (num_audio >= 1 && pp_smu != NULL && pp_smu->set_pme_wa_enable != NULL)
1004                         /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1005                         pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);
1006                 /* un-mute audio */
1007                 /* TODO: audio should be per stream rather than per link */
1008                 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1009                         pipe_ctx->stream_res.stream_enc, false);
1010         }
1011 }
1012
1013 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option)
1014 {
1015         struct dc *dc = pipe_ctx->stream->ctx->dc;
1016
1017         pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1018                         pipe_ctx->stream_res.stream_enc, true);
1019         if (pipe_ctx->stream_res.audio) {
1020                 struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;
1021
1022                 if (option != KEEP_ACQUIRED_RESOURCE ||
1023                                 !dc->debug.az_endpoint_mute_only) {
1024                         /*only disalbe az_endpoint if power down or free*/
1025                         pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
1026                 }
1027
1028                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1029                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
1030                                         pipe_ctx->stream_res.stream_enc);
1031                 else
1032                         pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(
1033                                         pipe_ctx->stream_res.stream_enc);
1034                 /*don't free audio if it is from retrain or internal disable stream*/
1035                 if (option == FREE_ACQUIRED_RESOURCE && dc->caps.dynamic_audio == true) {
1036                         /*we have to dynamic arbitrate the audio endpoints*/
1037                         /*we free the resource, need reset is_audio_acquired*/
1038                         update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false);
1039                         pipe_ctx->stream_res.audio = NULL;
1040                 }
1041                 if (pp_smu != NULL && pp_smu->set_pme_wa_enable != NULL)
1042                         /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1043                         pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);
1044
1045                 /* TODO: notify audio driver for if audio modes list changed
1046                  * add audio mode list change flag */
1047                 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
1048                  * stream->stream_engine_id);
1049                  */
1050         }
1051 }
1052
1053 void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
1054 {
1055         struct dc_stream_state *stream = pipe_ctx->stream;
1056         struct dc_link *link = stream->sink->link;
1057         struct dc *dc = pipe_ctx->stream->ctx->dc;
1058
1059         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1060                 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
1061                         pipe_ctx->stream_res.stream_enc);
1062
1063         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1064                 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
1065                         pipe_ctx->stream_res.stream_enc);
1066
1067         dc->hwss.disable_audio_stream(pipe_ctx, option);
1068
1069         link->link_enc->funcs->connect_dig_be_to_fe(
1070                         link->link_enc,
1071                         pipe_ctx->stream_res.stream_enc->id,
1072                         false);
1073
1074 }
1075
1076 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
1077                 struct dc_link_settings *link_settings)
1078 {
1079         struct encoder_unblank_param params = { { 0 } };
1080         struct dc_stream_state *stream = pipe_ctx->stream;
1081         struct dc_link *link = stream->sink->link;
1082
1083         /* only 3 items below are used by unblank */
1084         params.pixel_clk_khz =
1085                 pipe_ctx->stream->timing.pix_clk_khz;
1086         params.link_settings.link_rate = link_settings->link_rate;
1087
1088         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1089                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
1090
1091         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1092                 link->dc->hwss.edp_backlight_control(link, true);
1093         }
1094 }
1095 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
1096 {
1097         struct dc_stream_state *stream = pipe_ctx->stream;
1098         struct dc_link *link = stream->sink->link;
1099
1100         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1101                 link->dc->hwss.edp_backlight_control(link, false);
1102                 dc_link_set_abm_disable(link);
1103         }
1104
1105         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1106                 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
1107 }
1108
1109
1110 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
1111 {
1112         if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
1113                 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
1114 }
1115
1116 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
1117 {
1118         switch (crtc_id) {
1119         case CONTROLLER_ID_D0:
1120                 return DTO_SOURCE_ID0;
1121         case CONTROLLER_ID_D1:
1122                 return DTO_SOURCE_ID1;
1123         case CONTROLLER_ID_D2:
1124                 return DTO_SOURCE_ID2;
1125         case CONTROLLER_ID_D3:
1126                 return DTO_SOURCE_ID3;
1127         case CONTROLLER_ID_D4:
1128                 return DTO_SOURCE_ID4;
1129         case CONTROLLER_ID_D5:
1130                 return DTO_SOURCE_ID5;
1131         default:
1132                 return DTO_SOURCE_UNKNOWN;
1133         }
1134 }
1135
1136 static void build_audio_output(
1137         struct dc_state *state,
1138         const struct pipe_ctx *pipe_ctx,
1139         struct audio_output *audio_output)
1140 {
1141         const struct dc_stream_state *stream = pipe_ctx->stream;
1142         audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
1143
1144         audio_output->signal = pipe_ctx->stream->signal;
1145
1146         /* audio_crtc_info  */
1147
1148         audio_output->crtc_info.h_total =
1149                 stream->timing.h_total;
1150
1151         /*
1152          * Audio packets are sent during actual CRTC blank physical signal, we
1153          * need to specify actual active signal portion
1154          */
1155         audio_output->crtc_info.h_active =
1156                         stream->timing.h_addressable
1157                         + stream->timing.h_border_left
1158                         + stream->timing.h_border_right;
1159
1160         audio_output->crtc_info.v_active =
1161                         stream->timing.v_addressable
1162                         + stream->timing.v_border_top
1163                         + stream->timing.v_border_bottom;
1164
1165         audio_output->crtc_info.pixel_repetition = 1;
1166
1167         audio_output->crtc_info.interlaced =
1168                         stream->timing.flags.INTERLACE;
1169
1170         audio_output->crtc_info.refresh_rate =
1171                 (stream->timing.pix_clk_khz*1000)/
1172                 (stream->timing.h_total*stream->timing.v_total);
1173
1174         audio_output->crtc_info.color_depth =
1175                 stream->timing.display_color_depth;
1176
1177         audio_output->crtc_info.requested_pixel_clock =
1178                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
1179
1180         audio_output->crtc_info.calculated_pixel_clock =
1181                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
1182
1183 /*for HDMI, audio ACR is with deep color ratio factor*/
1184         if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&
1185                 audio_output->crtc_info.requested_pixel_clock ==
1186                                 stream->timing.pix_clk_khz) {
1187                 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1188                         audio_output->crtc_info.requested_pixel_clock =
1189                                         audio_output->crtc_info.requested_pixel_clock/2;
1190                         audio_output->crtc_info.calculated_pixel_clock =
1191                                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk/2;
1192
1193                 }
1194         }
1195
1196         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
1197                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1198                 audio_output->pll_info.dp_dto_source_clock_in_khz =
1199                                 state->dccg->funcs->get_dp_ref_clk_frequency(
1200                                                 state->dccg);
1201         }
1202
1203         audio_output->pll_info.feed_back_divider =
1204                         pipe_ctx->pll_settings.feedback_divider;
1205
1206         audio_output->pll_info.dto_source =
1207                 translate_to_dto_source(
1208                         pipe_ctx->stream_res.tg->inst + 1);
1209
1210         /* TODO hard code to enable for now. Need get from stream */
1211         audio_output->pll_info.ss_enabled = true;
1212
1213         audio_output->pll_info.ss_percentage =
1214                         pipe_ctx->pll_settings.ss_percentage;
1215 }
1216
1217 static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
1218                 struct tg_color *color)
1219 {
1220         uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;
1221
1222         switch (pipe_ctx->plane_res.scl_data.format) {
1223         case PIXEL_FORMAT_ARGB8888:
1224                 /* set boarder color to red */
1225                 color->color_r_cr = color_value;
1226                 break;
1227
1228         case PIXEL_FORMAT_ARGB2101010:
1229                 /* set boarder color to blue */
1230                 color->color_b_cb = color_value;
1231                 break;
1232         case PIXEL_FORMAT_420BPP8:
1233                 /* set boarder color to green */
1234                 color->color_g_y = color_value;
1235                 break;
1236         case PIXEL_FORMAT_420BPP10:
1237                 /* set boarder color to yellow */
1238                 color->color_g_y = color_value;
1239                 color->color_r_cr = color_value;
1240                 break;
1241         case PIXEL_FORMAT_FP16:
1242                 /* set boarder color to white */
1243                 color->color_r_cr = color_value;
1244                 color->color_b_cb = color_value;
1245                 color->color_g_y = color_value;
1246                 break;
1247         default:
1248                 break;
1249         }
1250 }
1251
1252 static void program_scaler(const struct dc *dc,
1253                 const struct pipe_ctx *pipe_ctx)
1254 {
1255         struct tg_color color = {0};
1256
1257 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1258         /* TOFPGA */
1259         if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
1260                 return;
1261 #endif
1262
1263         if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
1264                 get_surface_visual_confirm_color(pipe_ctx, &color);
1265         else
1266                 color_space_to_black_color(dc,
1267                                 pipe_ctx->stream->output_color_space,
1268                                 &color);
1269
1270         pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
1271                 pipe_ctx->plane_res.xfm,
1272                 pipe_ctx->plane_res.scl_data.lb_params.depth,
1273                 &pipe_ctx->stream->bit_depth_params);
1274
1275         if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {
1276                 /*
1277                  * The way 420 is packed, 2 channels carry Y component, 1 channel
1278                  * alternate between Cb and Cr, so both channels need the pixel
1279                  * value for Y
1280                  */
1281                 if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1282                         color.color_r_cr = color.color_g_y;
1283
1284                 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
1285                                 pipe_ctx->stream_res.tg,
1286                                 &color);
1287         }
1288
1289         pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
1290                 &pipe_ctx->plane_res.scl_data);
1291 }
1292
1293 static enum dc_status dce110_enable_stream_timing(
1294                 struct pipe_ctx *pipe_ctx,
1295                 struct dc_state *context,
1296                 struct dc *dc)
1297 {
1298         struct dc_stream_state *stream = pipe_ctx->stream;
1299         struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1300                         pipe_ctx[pipe_ctx->pipe_idx];
1301         struct tg_color black_color = {0};
1302         struct drr_params params = {0};
1303         unsigned int event_triggers = 0;
1304
1305         if (!pipe_ctx_old->stream) {
1306
1307                 /* program blank color */
1308                 color_space_to_black_color(dc,
1309                                 stream->output_color_space, &black_color);
1310                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1311                                 pipe_ctx->stream_res.tg,
1312                                 &black_color);
1313
1314                 /*
1315                  * Must blank CRTC after disabling power gating and before any
1316                  * programming, otherwise CRTC will be hung in bad state
1317                  */
1318                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1319
1320                 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1321                                 pipe_ctx->clock_source,
1322                                 &pipe_ctx->stream_res.pix_clk_params,
1323                                 &pipe_ctx->pll_settings)) {
1324                         BREAK_TO_DEBUGGER();
1325                         return DC_ERROR_UNEXPECTED;
1326                 }
1327
1328                 pipe_ctx->stream_res.tg->funcs->program_timing(
1329                                 pipe_ctx->stream_res.tg,
1330                                 &stream->timing,
1331                                 true);
1332
1333                 params.vertical_total_min = stream->adjust.v_total_min;
1334                 params.vertical_total_max = stream->adjust.v_total_max;
1335                 if (pipe_ctx->stream_res.tg->funcs->set_drr)
1336                         pipe_ctx->stream_res.tg->funcs->set_drr(
1337                                 pipe_ctx->stream_res.tg, &params);
1338
1339                 // DRR should set trigger event to monitor surface update event
1340                 if (stream->adjust.v_total_min != 0 &&
1341                                 stream->adjust.v_total_max != 0)
1342                         event_triggers = 0x80;
1343                 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
1344                         pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1345                                 pipe_ctx->stream_res.tg, event_triggers);
1346         }
1347
1348         if (!pipe_ctx_old->stream) {
1349                 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
1350                                 pipe_ctx->stream_res.tg)) {
1351                         BREAK_TO_DEBUGGER();
1352                         return DC_ERROR_UNEXPECTED;
1353                 }
1354         }
1355
1356         return DC_OK;
1357 }
1358
1359 static enum dc_status apply_single_controller_ctx_to_hw(
1360                 struct pipe_ctx *pipe_ctx,
1361                 struct dc_state *context,
1362                 struct dc *dc)
1363 {
1364         struct dc_stream_state *stream = pipe_ctx->stream;
1365
1366         if (pipe_ctx->stream_res.audio != NULL) {
1367                 struct audio_output audio_output;
1368
1369                 build_audio_output(context, pipe_ctx, &audio_output);
1370
1371                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1372                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(
1373                                         pipe_ctx->stream_res.stream_enc,
1374                                         pipe_ctx->stream_res.audio->inst,
1375                                         &pipe_ctx->stream->audio_info);
1376                 else
1377                         pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(
1378                                         pipe_ctx->stream_res.stream_enc,
1379                                         pipe_ctx->stream_res.audio->inst,
1380                                         &pipe_ctx->stream->audio_info,
1381                                         &audio_output.crtc_info);
1382
1383                 pipe_ctx->stream_res.audio->funcs->az_configure(
1384                                 pipe_ctx->stream_res.audio,
1385                                 pipe_ctx->stream->signal,
1386                                 &audio_output.crtc_info,
1387                                 &pipe_ctx->stream->audio_info);
1388         }
1389
1390         /*  */
1391         dc->hwss.enable_stream_timing(pipe_ctx, context, dc);
1392
1393         /* TODO: move to stream encoder */
1394         if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1395                 if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) {
1396                         BREAK_TO_DEBUGGER();
1397                         return DC_ERROR_UNEXPECTED;
1398                 }
1399
1400         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1401                         pipe_ctx->stream_res.opp,
1402                         COLOR_SPACE_YCBCR601,
1403                         stream->timing.display_color_depth,
1404                         pipe_ctx->stream->signal);
1405
1406         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1407                 pipe_ctx->stream_res.opp,
1408                 &stream->bit_depth_params,
1409                 &stream->clamping);
1410
1411         if (!stream->dpms_off)
1412                 core_link_enable_stream(context, pipe_ctx);
1413
1414         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
1415
1416         pipe_ctx->stream->sink->link->psr_enabled = false;
1417
1418         return DC_OK;
1419 }
1420
1421 /******************************************************************************/
1422
1423 static void power_down_encoders(struct dc *dc)
1424 {
1425         int i;
1426         enum connector_id connector_id;
1427         enum signal_type signal = SIGNAL_TYPE_NONE;
1428
1429         /* do not know BIOS back-front mapping, simply blank all. It will not
1430          * hurt for non-DP
1431          */
1432         for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1433                 dc->res_pool->stream_enc[i]->funcs->dp_blank(
1434                                         dc->res_pool->stream_enc[i]);
1435         }
1436
1437         for (i = 0; i < dc->link_count; i++) {
1438                 connector_id = dal_graphics_object_id_get_connector_id(dc->links[i]->link_id);
1439                 if ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
1440                         (connector_id == CONNECTOR_ID_EDP)) {
1441
1442                         if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
1443                                 dp_receiver_power_ctrl(dc->links[i], false);
1444                         if (connector_id == CONNECTOR_ID_EDP)
1445                                 signal = SIGNAL_TYPE_EDP;
1446                 }
1447
1448                 dc->links[i]->link_enc->funcs->disable_output(
1449                                 dc->links[i]->link_enc, signal);
1450         }
1451 }
1452
1453 static void power_down_controllers(struct dc *dc)
1454 {
1455         int i;
1456
1457         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1458                 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1459                                 dc->res_pool->timing_generators[i]);
1460         }
1461 }
1462
1463 static void power_down_clock_sources(struct dc *dc)
1464 {
1465         int i;
1466
1467         if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1468                 dc->res_pool->dp_clock_source) == false)
1469                 dm_error("Failed to power down pll! (dp clk src)\n");
1470
1471         for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1472                 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1473                                 dc->res_pool->clock_sources[i]) == false)
1474                         dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1475         }
1476 }
1477
1478 static void power_down_all_hw_blocks(struct dc *dc)
1479 {
1480         power_down_encoders(dc);
1481
1482         power_down_controllers(dc);
1483
1484         power_down_clock_sources(dc);
1485
1486         if (dc->fbc_compressor)
1487                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1488 }
1489
1490 static void disable_vga_and_power_gate_all_controllers(
1491                 struct dc *dc)
1492 {
1493         int i;
1494         struct timing_generator *tg;
1495         struct dc_context *ctx = dc->ctx;
1496
1497         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1498                 tg = dc->res_pool->timing_generators[i];
1499
1500                 if (tg->funcs->disable_vga)
1501                         tg->funcs->disable_vga(tg);
1502         }
1503         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1504                 /* Enable CLOCK gating for each pipe BEFORE controller
1505                  * powergating. */
1506                 enable_display_pipe_clock_gating(ctx,
1507                                 true);
1508
1509                 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
1510                 dc->hwss.disable_plane(dc,
1511                         &dc->current_state->res_ctx.pipe_ctx[i]);
1512         }
1513 }
1514
1515 static struct dc_link *get_link_for_edp(struct dc *dc)
1516 {
1517         int i;
1518
1519         for (i = 0; i < dc->link_count; i++) {
1520                 if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP)
1521                         return dc->links[i];
1522         }
1523         return NULL;
1524 }
1525
1526 static struct dc_link *get_link_for_edp_not_in_use(
1527                 struct dc *dc,
1528                 struct dc_state *context)
1529 {
1530         int i;
1531         struct dc_link *link = NULL;
1532
1533         /* check if eDP panel is suppose to be set mode, if yes, no need to disable */
1534         for (i = 0; i < context->stream_count; i++) {
1535                 if (context->streams[i]->signal == SIGNAL_TYPE_EDP)
1536                         return NULL;
1537         }
1538
1539         /* check if there is an eDP panel not in use */
1540         for (i = 0; i < dc->link_count; i++) {
1541                 if (dc->links[i]->local_sink &&
1542                         dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1543                         link = dc->links[i];
1544                         break;
1545                 }
1546         }
1547
1548         return link;
1549 }
1550
1551 /**
1552  * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1553  *  1. Power down all DC HW blocks
1554  *  2. Disable VGA engine on all controllers
1555  *  3. Enable power gating for controller
1556  *  4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1557  */
1558 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
1559 {
1560         int i;
1561         struct dc_link *edp_link_to_turnoff = NULL;
1562         struct dc_link *edp_link = get_link_for_edp(dc);
1563         struct dc_bios *bios = dc->ctx->dc_bios;
1564         bool can_edp_fast_boot_optimize = false;
1565         bool apply_edp_fast_boot_optimization = false;
1566
1567         if (edp_link) {
1568                 /* this seems to cause blank screens on DCE8 */
1569                 if ((dc->ctx->dce_version == DCE_VERSION_8_0) ||
1570                     (dc->ctx->dce_version == DCE_VERSION_8_1) ||
1571                     (dc->ctx->dce_version == DCE_VERSION_8_3))
1572                         can_edp_fast_boot_optimize = false;
1573                 else
1574                         can_edp_fast_boot_optimize =
1575                                 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc);
1576         }
1577
1578         if (can_edp_fast_boot_optimize)
1579                 edp_link_to_turnoff = get_link_for_edp_not_in_use(dc, context);
1580
1581         /* if OS doesn't light up eDP and eDP link is available, we want to disable
1582          * If resume from S4/S5, should optimization.
1583          */
1584         if (can_edp_fast_boot_optimize && !edp_link_to_turnoff) {
1585                 /* Find eDP stream and set optimization flag */
1586                 for (i = 0; i < context->stream_count; i++) {
1587                         if (context->streams[i]->signal == SIGNAL_TYPE_EDP) {
1588                                 context->streams[i]->apply_edp_fast_boot_optimization = true;
1589                                 apply_edp_fast_boot_optimization = true;
1590
1591                                 /* When after S4 and S5, vbios may post edp and previous dpms_off
1592                                  * doesn't make sense.
1593                                  * Update dpms_off state to align hw and sw state via check
1594                                  * vBios scratch register.
1595                                  */
1596                                 if (bios->funcs->is_active_display)     {
1597                                         const struct connector_device_tag_info *device_tag = &(edp_link->device_tag);
1598
1599                                         if (bios->funcs->is_active_display(bios,
1600                                                         context->streams[i]->signal,
1601                                                         device_tag))
1602                                                 context->streams[i]->dpms_off = false;
1603                                 }
1604                         }
1605                 }
1606         }
1607
1608         if (!apply_edp_fast_boot_optimization) {
1609                 if (edp_link_to_turnoff) {
1610                         /*turn off backlight before DP_blank and encoder powered down*/
1611                         dc->hwss.edp_backlight_control(edp_link_to_turnoff, false);
1612                 }
1613                 /*resume from S3, no vbios posting, no need to power down again*/
1614                 power_down_all_hw_blocks(dc);
1615                 disable_vga_and_power_gate_all_controllers(dc);
1616                 if (edp_link_to_turnoff)
1617                         dc->hwss.edp_power_control(edp_link_to_turnoff, false);
1618         }
1619         bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
1620 }
1621
1622 static uint32_t compute_pstate_blackout_duration(
1623         struct bw_fixed blackout_duration,
1624         const struct dc_stream_state *stream)
1625 {
1626         uint32_t total_dest_line_time_ns;
1627         uint32_t pstate_blackout_duration_ns;
1628
1629         pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1630
1631         total_dest_line_time_ns = 1000000UL *
1632                 stream->timing.h_total /
1633                 stream->timing.pix_clk_khz +
1634                 pstate_blackout_duration_ns;
1635
1636         return total_dest_line_time_ns;
1637 }
1638
1639 static void dce110_set_displaymarks(
1640         const struct dc *dc,
1641         struct dc_state *context)
1642 {
1643         uint8_t i, num_pipes;
1644         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1645
1646         for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1647                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1648                 uint32_t total_dest_line_time_ns;
1649
1650                 if (pipe_ctx->stream == NULL)
1651                         continue;
1652
1653                 total_dest_line_time_ns = compute_pstate_blackout_duration(
1654                         dc->bw_vbios->blackout_duration, pipe_ctx->stream);
1655                 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
1656                         pipe_ctx->plane_res.mi,
1657                         context->bw.dce.nbp_state_change_wm_ns[num_pipes],
1658                         context->bw.dce.stutter_exit_wm_ns[num_pipes],
1659                         context->bw.dce.stutter_entry_wm_ns[num_pipes],
1660                         context->bw.dce.urgent_wm_ns[num_pipes],
1661                         total_dest_line_time_ns);
1662                 if (i == underlay_idx) {
1663                         num_pipes++;
1664                         pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1665                                 pipe_ctx->plane_res.mi,
1666                                 context->bw.dce.nbp_state_change_wm_ns[num_pipes],
1667                                 context->bw.dce.stutter_exit_wm_ns[num_pipes],
1668                                 context->bw.dce.urgent_wm_ns[num_pipes],
1669                                 total_dest_line_time_ns);
1670                 }
1671                 num_pipes++;
1672         }
1673 }
1674
1675 void dce110_set_safe_displaymarks(
1676                 struct resource_context *res_ctx,
1677                 const struct resource_pool *pool)
1678 {
1679         int i;
1680         int underlay_idx = pool->underlay_pipe_index;
1681         struct dce_watermarks max_marks = {
1682                 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1683         struct dce_watermarks nbp_marks = {
1684                 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1685         struct dce_watermarks min_marks = { 0, 0, 0, 0};
1686
1687         for (i = 0; i < MAX_PIPES; i++) {
1688                 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
1689                         continue;
1690
1691                 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
1692                                 res_ctx->pipe_ctx[i].plane_res.mi,
1693                                 nbp_marks,
1694                                 max_marks,
1695                                 min_marks,
1696                                 max_marks,
1697                                 MAX_WATERMARK);
1698
1699                 if (i == underlay_idx)
1700                         res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1701                                 res_ctx->pipe_ctx[i].plane_res.mi,
1702                                 nbp_marks,
1703                                 max_marks,
1704                                 max_marks,
1705                                 MAX_WATERMARK);
1706
1707         }
1708 }
1709
1710 /*******************************************************************************
1711  * Public functions
1712  ******************************************************************************/
1713
1714 static void set_drr(struct pipe_ctx **pipe_ctx,
1715                 int num_pipes, int vmin, int vmax)
1716 {
1717         int i = 0;
1718         struct drr_params params = {0};
1719         // DRR should set trigger event to monitor surface update event
1720         unsigned int event_triggers = 0x80;
1721
1722         params.vertical_total_max = vmax;
1723         params.vertical_total_min = vmin;
1724
1725         /* TODO: If multiple pipes are to be supported, you need
1726          * some GSL stuff. Static screen triggers may be programmed differently
1727          * as well.
1728          */
1729         for (i = 0; i < num_pipes; i++) {
1730                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
1731                         pipe_ctx[i]->stream_res.tg, &params);
1732
1733                 if (vmax != 0 && vmin != 0)
1734                         pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
1735                                         pipe_ctx[i]->stream_res.tg,
1736                                         event_triggers);
1737         }
1738 }
1739
1740 static void get_position(struct pipe_ctx **pipe_ctx,
1741                 int num_pipes,
1742                 struct crtc_position *position)
1743 {
1744         int i = 0;
1745
1746         /* TODO: handle pipes > 1
1747          */
1748         for (i = 0; i < num_pipes; i++)
1749                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
1750 }
1751
1752 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1753                 int num_pipes, const struct dc_static_screen_events *events)
1754 {
1755         unsigned int i;
1756         unsigned int value = 0;
1757
1758         if (events->overlay_update)
1759                 value |= 0x100;
1760         if (events->surface_update)
1761                 value |= 0x80;
1762         if (events->cursor_update)
1763                 value |= 0x2;
1764         if (events->force_trigger)
1765                 value |= 0x1;
1766
1767         if (num_pipes) {
1768                 struct dc *dc = pipe_ctx[0]->stream->ctx->dc;
1769
1770                 if (dc->fbc_compressor)
1771                         value |= 0x84;
1772         }
1773
1774         for (i = 0; i < num_pipes; i++)
1775                 pipe_ctx[i]->stream_res.tg->funcs->
1776                         set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
1777 }
1778
1779 /*
1780  *  Check if FBC can be enabled
1781  */
1782 static bool should_enable_fbc(struct dc *dc,
1783                 struct dc_state *context,
1784                 uint32_t *pipe_idx)
1785 {
1786         uint32_t i;
1787         struct pipe_ctx *pipe_ctx = NULL;
1788         struct resource_context *res_ctx = &context->res_ctx;
1789         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1790
1791
1792         ASSERT(dc->fbc_compressor);
1793
1794         /* FBC memory should be allocated */
1795         if (!dc->ctx->fbc_gpu_addr)
1796                 return false;
1797
1798         /* Only supports single display */
1799         if (context->stream_count != 1)
1800                 return false;
1801
1802         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1803                 if (res_ctx->pipe_ctx[i].stream) {
1804
1805                         pipe_ctx = &res_ctx->pipe_ctx[i];
1806
1807                         if (!pipe_ctx)
1808                                 continue;
1809
1810                         /* fbc not applicable on underlay pipe */
1811                         if (pipe_ctx->pipe_idx != underlay_idx) {
1812                                 *pipe_idx = i;
1813                                 break;
1814                         }
1815                 }
1816         }
1817
1818         if (i == dc->res_pool->pipe_count)
1819                 return false;
1820
1821         if (!pipe_ctx->stream->sink)
1822                 return false;
1823
1824         if (!pipe_ctx->stream->sink->link)
1825                 return false;
1826
1827         /* Only supports eDP */
1828         if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP)
1829                 return false;
1830
1831         /* PSR should not be enabled */
1832         if (pipe_ctx->stream->sink->link->psr_enabled)
1833                 return false;
1834
1835         /* Nothing to compress */
1836         if (!pipe_ctx->plane_state)
1837                 return false;
1838
1839         /* Only for non-linear tiling */
1840         if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
1841                 return false;
1842
1843         return true;
1844 }
1845
1846 /*
1847  *  Enable FBC
1848  */
1849 static void enable_fbc(
1850                 struct dc *dc,
1851                 struct dc_state *context)
1852 {
1853         uint32_t pipe_idx = 0;
1854
1855         if (should_enable_fbc(dc, context, &pipe_idx)) {
1856                 /* Program GRPH COMPRESSED ADDRESS and PITCH */
1857                 struct compr_addr_and_pitch_params params = {0, 0, 0};
1858                 struct compressor *compr = dc->fbc_compressor;
1859                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1860
1861                 params.source_view_width = pipe_ctx->stream->timing.h_addressable;
1862                 params.source_view_height = pipe_ctx->stream->timing.v_addressable;
1863                 params.inst = pipe_ctx->stream_res.tg->inst;
1864                 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
1865
1866                 compr->funcs->surface_address_and_pitch(compr, &params);
1867                 compr->funcs->set_fbc_invalidation_triggers(compr, 1);
1868
1869                 compr->funcs->enable_fbc(compr, &params);
1870         }
1871 }
1872
1873 static void dce110_reset_hw_ctx_wrap(
1874                 struct dc *dc,
1875                 struct dc_state *context)
1876 {
1877         int i;
1878
1879         /* Reset old context */
1880         /* look up the targets that have been removed since last commit */
1881         for (i = 0; i < MAX_PIPES; i++) {
1882                 struct pipe_ctx *pipe_ctx_old =
1883                         &dc->current_state->res_ctx.pipe_ctx[i];
1884                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1885
1886                 /* Note: We need to disable output if clock sources change,
1887                  * since bios does optimization and doesn't apply if changing
1888                  * PHY when not already disabled.
1889                  */
1890
1891                 /* Skip underlay pipe since it will be handled in commit surface*/
1892                 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
1893                         continue;
1894
1895                 if (!pipe_ctx->stream ||
1896                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1897                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
1898
1899                         /* Disable if new stream is null. O/w, if stream is
1900                          * disabled already, no need to disable again.
1901                          */
1902                         if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off)
1903                                 core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE);
1904
1905                         pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
1906                         if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
1907                                 dm_error("DC: failed to blank crtc!\n");
1908                                 BREAK_TO_DEBUGGER();
1909                         }
1910                         pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
1911                         pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
1912                                         pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
1913
1914                         if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx,
1915                                                                                 dc->res_pool,
1916                                                                                 old_clk))
1917                                 old_clk->funcs->cs_power_down(old_clk);
1918
1919                         dc->hwss.disable_plane(dc, pipe_ctx_old);
1920
1921                         pipe_ctx_old->stream = NULL;
1922                 }
1923         }
1924 }
1925
1926 static void dce110_setup_audio_dto(
1927                 struct dc *dc,
1928                 struct dc_state *context)
1929 {
1930         int i;
1931
1932         /* program audio wall clock. use HDMI as clock source if HDMI
1933          * audio active. Otherwise, use DP as clock source
1934          * first, loop to find any HDMI audio, if not, loop find DP audio
1935          */
1936         /* Setup audio rate clock source */
1937         /* Issue:
1938         * Audio lag happened on DP monitor when unplug a HDMI monitor
1939         *
1940         * Cause:
1941         * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
1942         * is set to either dto0 or dto1, audio should work fine.
1943         * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
1944         * set to dto0 will cause audio lag.
1945         *
1946         * Solution:
1947         * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
1948         * find first available pipe with audio, setup audio wall DTO per topology
1949         * instead of per pipe.
1950         */
1951         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1952                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1953
1954                 if (pipe_ctx->stream == NULL)
1955                         continue;
1956
1957                 if (pipe_ctx->top_pipe)
1958                         continue;
1959
1960                 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
1961                         continue;
1962
1963                 if (pipe_ctx->stream_res.audio != NULL) {
1964                         struct audio_output audio_output;
1965
1966                         build_audio_output(context, pipe_ctx, &audio_output);
1967
1968                         pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
1969                                 pipe_ctx->stream_res.audio,
1970                                 pipe_ctx->stream->signal,
1971                                 &audio_output.crtc_info,
1972                                 &audio_output.pll_info);
1973                         break;
1974                 }
1975         }
1976
1977         /* no HDMI audio is found, try DP audio */
1978         if (i == dc->res_pool->pipe_count) {
1979                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1980                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1981
1982                         if (pipe_ctx->stream == NULL)
1983                                 continue;
1984
1985                         if (pipe_ctx->top_pipe)
1986                                 continue;
1987
1988                         if (!dc_is_dp_signal(pipe_ctx->stream->signal))
1989                                 continue;
1990
1991                         if (pipe_ctx->stream_res.audio != NULL) {
1992                                 struct audio_output audio_output;
1993
1994                                 build_audio_output(context, pipe_ctx, &audio_output);
1995
1996                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
1997                                         pipe_ctx->stream_res.audio,
1998                                         pipe_ctx->stream->signal,
1999                                         &audio_output.crtc_info,
2000                                         &audio_output.pll_info);
2001                                 break;
2002                         }
2003                 }
2004         }
2005 }
2006
2007 enum dc_status dce110_apply_ctx_to_hw(
2008                 struct dc *dc,
2009                 struct dc_state *context)
2010 {
2011         struct dc_bios *dcb = dc->ctx->dc_bios;
2012         enum dc_status status;
2013         int i;
2014
2015         /* Reset old context */
2016         /* look up the targets that have been removed since last commit */
2017         dc->hwss.reset_hw_ctx_wrap(dc, context);
2018
2019         /* Skip applying if no targets */
2020         if (context->stream_count <= 0)
2021                 return DC_OK;
2022
2023         /* Apply new context */
2024         dcb->funcs->set_scratch_critical_state(dcb, true);
2025
2026         /* below is for real asic only */
2027         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2028                 struct pipe_ctx *pipe_ctx_old =
2029                                         &dc->current_state->res_ctx.pipe_ctx[i];
2030                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2031
2032                 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
2033                         continue;
2034
2035                 if (pipe_ctx->stream == pipe_ctx_old->stream) {
2036                         if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
2037                                 dce_crtc_switch_to_clk_src(dc->hwseq,
2038                                                 pipe_ctx->clock_source, i);
2039                         continue;
2040                 }
2041
2042                 dc->hwss.enable_display_power_gating(
2043                                 dc, i, dc->ctx->dc_bios,
2044                                 PIPE_GATING_CONTROL_DISABLE);
2045         }
2046
2047         if (dc->fbc_compressor)
2048                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2049
2050         dce110_setup_audio_dto(dc, context);
2051
2052         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2053                 struct pipe_ctx *pipe_ctx_old =
2054                                         &dc->current_state->res_ctx.pipe_ctx[i];
2055                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2056
2057                 if (pipe_ctx->stream == NULL)
2058                         continue;
2059
2060                 if (pipe_ctx->stream == pipe_ctx_old->stream)
2061                         continue;
2062
2063                 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
2064                         continue;
2065
2066                 if (pipe_ctx->top_pipe)
2067                         continue;
2068
2069                 status = apply_single_controller_ctx_to_hw(
2070                                 pipe_ctx,
2071                                 context,
2072                                 dc);
2073
2074                 if (DC_OK != status)
2075                         return status;
2076         }
2077
2078         if (dc->fbc_compressor)
2079                 enable_fbc(dc, dc->current_state);
2080
2081         dcb->funcs->set_scratch_critical_state(dcb, false);
2082
2083         return DC_OK;
2084 }
2085
2086 /*******************************************************************************
2087  * Front End programming
2088  ******************************************************************************/
2089 static void set_default_colors(struct pipe_ctx *pipe_ctx)
2090 {
2091         struct default_adjustment default_adjust = { 0 };
2092
2093         default_adjust.force_hw_default = false;
2094         default_adjust.in_color_space = pipe_ctx->plane_state->color_space;
2095         default_adjust.out_color_space = pipe_ctx->stream->output_color_space;
2096         default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
2097         default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
2098
2099         /* display color depth */
2100         default_adjust.color_depth =
2101                 pipe_ctx->stream->timing.display_color_depth;
2102
2103         /* Lb color depth */
2104         default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
2105
2106         pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
2107                                         pipe_ctx->plane_res.xfm, &default_adjust);
2108 }
2109
2110
2111 /*******************************************************************************
2112  * In order to turn on/off specific surface we will program
2113  * Blender + CRTC
2114  *
2115  * In case that we have two surfaces and they have a different visibility
2116  * we can't turn off the CRTC since it will turn off the entire display
2117  *
2118  * |----------------------------------------------- |
2119  * |bottom pipe|curr pipe  |              |         |
2120  * |Surface    |Surface    | Blender      |  CRCT   |
2121  * |visibility |visibility | Configuration|         |
2122  * |------------------------------------------------|
2123  * |   off     |    off    | CURRENT_PIPE | blank   |
2124  * |   off     |    on     | CURRENT_PIPE | unblank |
2125  * |   on      |    off    | OTHER_PIPE   | unblank |
2126  * |   on      |    on     | BLENDING     | unblank |
2127  * -------------------------------------------------|
2128  *
2129  ******************************************************************************/
2130 static void program_surface_visibility(const struct dc *dc,
2131                 struct pipe_ctx *pipe_ctx)
2132 {
2133         enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
2134         bool blank_target = false;
2135
2136         if (pipe_ctx->bottom_pipe) {
2137
2138                 /* For now we are supporting only two pipes */
2139                 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
2140
2141                 if (pipe_ctx->bottom_pipe->plane_state->visible) {
2142                         if (pipe_ctx->plane_state->visible)
2143                                 blender_mode = BLND_MODE_BLENDING;
2144                         else
2145                                 blender_mode = BLND_MODE_OTHER_PIPE;
2146
2147                 } else if (!pipe_ctx->plane_state->visible)
2148                         blank_target = true;
2149
2150         } else if (!pipe_ctx->plane_state->visible)
2151                 blank_target = true;
2152
2153         dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);
2154         pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
2155
2156 }
2157
2158 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2159 {
2160         int i = 0;
2161         struct xfm_grph_csc_adjustment adjust;
2162         memset(&adjust, 0, sizeof(adjust));
2163         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2164
2165
2166         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2167                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2168
2169                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2170                         adjust.temperature_matrix[i] =
2171                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2172         }
2173
2174         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2175 }
2176 static void update_plane_addr(const struct dc *dc,
2177                 struct pipe_ctx *pipe_ctx)
2178 {
2179         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2180
2181         if (plane_state == NULL)
2182                 return;
2183
2184         pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
2185                         pipe_ctx->plane_res.mi,
2186                         &plane_state->address,
2187                         plane_state->flip_immediate);
2188
2189         plane_state->status.requested_address = plane_state->address;
2190 }
2191
2192 static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2193 {
2194         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2195
2196         if (plane_state == NULL)
2197                 return;
2198
2199         plane_state->status.is_flip_pending =
2200                         pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
2201                                         pipe_ctx->plane_res.mi);
2202
2203         if (plane_state->status.is_flip_pending && !plane_state->visible)
2204                 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
2205
2206         plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
2207         if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2208                         pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
2209                 plane_state->status.is_right_eye =\
2210                                 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2211         }
2212 }
2213
2214 void dce110_power_down(struct dc *dc)
2215 {
2216         power_down_all_hw_blocks(dc);
2217         disable_vga_and_power_gate_all_controllers(dc);
2218 }
2219
2220 static bool wait_for_reset_trigger_to_occur(
2221         struct dc_context *dc_ctx,
2222         struct timing_generator *tg)
2223 {
2224         bool rc = false;
2225
2226         /* To avoid endless loop we wait at most
2227          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2228         const uint32_t frames_to_wait_on_triggered_reset = 10;
2229         uint32_t i;
2230
2231         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2232
2233                 if (!tg->funcs->is_counter_moving(tg)) {
2234                         DC_ERROR("TG counter is not moving!\n");
2235                         break;
2236                 }
2237
2238                 if (tg->funcs->did_triggered_reset_occur(tg)) {
2239                         rc = true;
2240                         /* usually occurs at i=1 */
2241                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2242                                         i);
2243                         break;
2244                 }
2245
2246                 /* Wait for one frame. */
2247                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2248                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2249         }
2250
2251         if (false == rc)
2252                 DC_ERROR("GSL: Timeout on reset trigger!\n");
2253
2254         return rc;
2255 }
2256
2257 /* Enable timing synchronization for a group of Timing Generators. */
2258 static void dce110_enable_timing_synchronization(
2259                 struct dc *dc,
2260                 int group_index,
2261                 int group_size,
2262                 struct pipe_ctx *grouped_pipes[])
2263 {
2264         struct dc_context *dc_ctx = dc->ctx;
2265         struct dcp_gsl_params gsl_params = { 0 };
2266         int i;
2267
2268         DC_SYNC_INFO("GSL: Setting-up...\n");
2269
2270         /* Designate a single TG in the group as a master.
2271          * Since HW doesn't care which one, we always assign
2272          * the 1st one in the group. */
2273         gsl_params.gsl_group = 0;
2274         gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
2275
2276         for (i = 0; i < group_size; i++)
2277                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2278                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2279
2280         /* Reset slave controllers on master VSync */
2281         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2282
2283         for (i = 1 /* skip the master */; i < group_size; i++)
2284                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
2285                                 grouped_pipes[i]->stream_res.tg,
2286                                 gsl_params.gsl_group);
2287
2288         for (i = 1 /* skip the master */; i < group_size; i++) {
2289                 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2290                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2291                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
2292                                 grouped_pipes[i]->stream_res.tg);
2293         }
2294
2295         /* GSL Vblank synchronization is a one time sync mechanism, assumption
2296          * is that the sync'ed displays will not drift out of sync over time*/
2297         DC_SYNC_INFO("GSL: Restoring register states.\n");
2298         for (i = 0; i < group_size; i++)
2299                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2300
2301         DC_SYNC_INFO("GSL: Set-up complete.\n");
2302 }
2303
2304 static void dce110_enable_per_frame_crtc_position_reset(
2305                 struct dc *dc,
2306                 int group_size,
2307                 struct pipe_ctx *grouped_pipes[])
2308 {
2309         struct dc_context *dc_ctx = dc->ctx;
2310         struct dcp_gsl_params gsl_params = { 0 };
2311         int i;
2312
2313         gsl_params.gsl_group = 0;
2314         gsl_params.gsl_master = 0;
2315
2316         for (i = 0; i < group_size; i++)
2317                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2318                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2319
2320         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2321
2322         for (i = 1; i < group_size; i++)
2323                 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
2324                                 grouped_pipes[i]->stream_res.tg,
2325                                 gsl_params.gsl_master,
2326                                 &grouped_pipes[i]->stream->triggered_crtc_reset);
2327
2328         DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2329         for (i = 1; i < group_size; i++)
2330                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2331
2332         for (i = 0; i < group_size; i++)
2333                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2334
2335 }
2336
2337 static void init_hw(struct dc *dc)
2338 {
2339         int i;
2340         struct dc_bios *bp;
2341         struct transform *xfm;
2342         struct abm *abm;
2343
2344         bp = dc->ctx->dc_bios;
2345         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2346                 xfm = dc->res_pool->transforms[i];
2347                 xfm->funcs->transform_reset(xfm);
2348
2349                 dc->hwss.enable_display_power_gating(
2350                                 dc, i, bp,
2351                                 PIPE_GATING_CONTROL_INIT);
2352                 dc->hwss.enable_display_power_gating(
2353                                 dc, i, bp,
2354                                 PIPE_GATING_CONTROL_DISABLE);
2355                 dc->hwss.enable_display_pipe_clock_gating(
2356                         dc->ctx,
2357                         true);
2358         }
2359
2360         dce_clock_gating_power_up(dc->hwseq, false);
2361         /***************************************/
2362
2363         for (i = 0; i < dc->link_count; i++) {
2364                 /****************************************/
2365                 /* Power up AND update implementation according to the
2366                  * required signal (which may be different from the
2367                  * default signal on connector). */
2368                 struct dc_link *link = dc->links[i];
2369
2370                 if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
2371                         dc->hwss.edp_power_control(link, true);
2372
2373                 link->link_enc->funcs->hw_init(link->link_enc);
2374         }
2375
2376         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2377                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2378
2379                 tg->funcs->disable_vga(tg);
2380
2381                 /* Blank controller using driver code instead of
2382                  * command table. */
2383                 tg->funcs->set_blank(tg, true);
2384                 hwss_wait_for_blank_complete(tg);
2385         }
2386
2387         for (i = 0; i < dc->res_pool->audio_count; i++) {
2388                 struct audio *audio = dc->res_pool->audios[i];
2389                 audio->funcs->hw_init(audio);
2390         }
2391
2392         abm = dc->res_pool->abm;
2393         if (abm != NULL) {
2394                 abm->funcs->init_backlight(abm);
2395                 abm->funcs->abm_init(abm);
2396         }
2397
2398         if (dc->fbc_compressor)
2399                 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2400
2401 }
2402
2403
2404 void dce110_prepare_bandwidth(
2405                 struct dc *dc,
2406                 struct dc_state *context)
2407 {
2408         struct clk_mgr *dccg = dc->res_pool->clk_mgr;
2409
2410         dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
2411
2412         dccg->funcs->update_clocks(
2413                         dccg,
2414                         context,
2415                         false);
2416 }
2417
2418 void dce110_optimize_bandwidth(
2419                 struct dc *dc,
2420                 struct dc_state *context)
2421 {
2422         struct clk_mgr *dccg = dc->res_pool->clk_mgr;
2423
2424         dce110_set_displaymarks(dc, context);
2425
2426         dccg->funcs->update_clocks(
2427                         dccg,
2428                         context,
2429                         true);
2430 }
2431
2432 static void dce110_program_front_end_for_pipe(
2433                 struct dc *dc, struct pipe_ctx *pipe_ctx)
2434 {
2435         struct mem_input *mi = pipe_ctx->plane_res.mi;
2436         struct pipe_ctx *old_pipe = NULL;
2437         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2438         struct xfm_grph_csc_adjustment adjust;
2439         struct out_csc_color_matrix tbl_entry;
2440         unsigned int i;
2441         DC_LOGGER_INIT();
2442         memset(&tbl_entry, 0, sizeof(tbl_entry));
2443
2444         if (dc->current_state)
2445                 old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
2446
2447         memset(&adjust, 0, sizeof(adjust));
2448         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2449
2450         dce_enable_fe_clock(dc->hwseq, mi->inst, true);
2451
2452         set_default_colors(pipe_ctx);
2453         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2454                         == true) {
2455                 tbl_entry.color_space =
2456                         pipe_ctx->stream->output_color_space;
2457
2458                 for (i = 0; i < 12; i++)
2459                         tbl_entry.regval[i] =
2460                         pipe_ctx->stream->csc_color_matrix.matrix[i];
2461
2462                 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2463                                 (pipe_ctx->plane_res.xfm, &tbl_entry);
2464         }
2465
2466         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2467                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2468
2469                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2470                         adjust.temperature_matrix[i] =
2471                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2472         }
2473
2474         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2475
2476         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2477
2478         program_scaler(dc, pipe_ctx);
2479
2480         mi->funcs->mem_input_program_surface_config(
2481                         mi,
2482                         plane_state->format,
2483                         &plane_state->tiling_info,
2484                         &plane_state->plane_size,
2485                         plane_state->rotation,
2486                         NULL,
2487                         false);
2488         if (mi->funcs->set_blank)
2489                 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2490
2491         if (dc->config.gpu_vm_support)
2492                 mi->funcs->mem_input_program_pte_vm(
2493                                 pipe_ctx->plane_res.mi,
2494                                 plane_state->format,
2495                                 &plane_state->tiling_info,
2496                                 plane_state->rotation);
2497
2498         /* Moved programming gamma from dc to hwss */
2499         if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2500                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2501                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
2502                 dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
2503
2504         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2505                 dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
2506
2507         DC_LOG_SURFACE(
2508                         "Pipe:%d %p: addr hi:0x%x, "
2509                         "addr low:0x%x, "
2510                         "src: %d, %d, %d,"
2511                         " %d; dst: %d, %d, %d, %d;"
2512                         "clip: %d, %d, %d, %d\n",
2513                         pipe_ctx->pipe_idx,
2514                         (void *) pipe_ctx->plane_state,
2515                         pipe_ctx->plane_state->address.grph.addr.high_part,
2516                         pipe_ctx->plane_state->address.grph.addr.low_part,
2517                         pipe_ctx->plane_state->src_rect.x,
2518                         pipe_ctx->plane_state->src_rect.y,
2519                         pipe_ctx->plane_state->src_rect.width,
2520                         pipe_ctx->plane_state->src_rect.height,
2521                         pipe_ctx->plane_state->dst_rect.x,
2522                         pipe_ctx->plane_state->dst_rect.y,
2523                         pipe_ctx->plane_state->dst_rect.width,
2524                         pipe_ctx->plane_state->dst_rect.height,
2525                         pipe_ctx->plane_state->clip_rect.x,
2526                         pipe_ctx->plane_state->clip_rect.y,
2527                         pipe_ctx->plane_state->clip_rect.width,
2528                         pipe_ctx->plane_state->clip_rect.height);
2529
2530         DC_LOG_SURFACE(
2531                         "Pipe %d: width, height, x, y\n"
2532                         "viewport:%d, %d, %d, %d\n"
2533                         "recout:  %d, %d, %d, %d\n",
2534                         pipe_ctx->pipe_idx,
2535                         pipe_ctx->plane_res.scl_data.viewport.width,
2536                         pipe_ctx->plane_res.scl_data.viewport.height,
2537                         pipe_ctx->plane_res.scl_data.viewport.x,
2538                         pipe_ctx->plane_res.scl_data.viewport.y,
2539                         pipe_ctx->plane_res.scl_data.recout.width,
2540                         pipe_ctx->plane_res.scl_data.recout.height,
2541                         pipe_ctx->plane_res.scl_data.recout.x,
2542                         pipe_ctx->plane_res.scl_data.recout.y);
2543 }
2544
2545 static void dce110_apply_ctx_for_surface(
2546                 struct dc *dc,
2547                 const struct dc_stream_state *stream,
2548                 int num_planes,
2549                 struct dc_state *context)
2550 {
2551         int i;
2552
2553         if (num_planes == 0)
2554                 return;
2555
2556         if (dc->fbc_compressor)
2557                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2558
2559         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2560                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2561                 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2562
2563                 if (stream == pipe_ctx->stream) {
2564                         if (!pipe_ctx->top_pipe &&
2565                                 (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
2566                                 dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
2567                 }
2568         }
2569
2570         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2571                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2572
2573                 if (pipe_ctx->stream != stream)
2574                         continue;
2575
2576                 /* Need to allocate mem before program front end for Fiji */
2577                 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
2578                                 pipe_ctx->plane_res.mi,
2579                                 pipe_ctx->stream->timing.h_total,
2580                                 pipe_ctx->stream->timing.v_total,
2581                                 pipe_ctx->stream->timing.pix_clk_khz,
2582                                 context->stream_count);
2583
2584                 dce110_program_front_end_for_pipe(dc, pipe_ctx);
2585
2586                 dc->hwss.update_plane_addr(dc, pipe_ctx);
2587
2588                 program_surface_visibility(dc, pipe_ctx);
2589
2590         }
2591
2592         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2593                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2594                 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2595
2596                 if ((stream == pipe_ctx->stream) &&
2597                         (!pipe_ctx->top_pipe) &&
2598                         (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
2599                         dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
2600         }
2601
2602         if (dc->fbc_compressor)
2603                 enable_fbc(dc, dc->current_state);
2604 }
2605
2606 static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
2607 {
2608         int fe_idx = pipe_ctx->plane_res.mi ?
2609                 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;
2610
2611         /* Do not power down fe when stream is active on dce*/
2612         if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
2613                 return;
2614
2615         dc->hwss.enable_display_power_gating(
2616                 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2617
2618         dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
2619                                 dc->res_pool->transforms[fe_idx]);
2620 }
2621
2622 static void dce110_wait_for_mpcc_disconnect(
2623                 struct dc *dc,
2624                 struct resource_pool *res_pool,
2625                 struct pipe_ctx *pipe_ctx)
2626 {
2627         /* do nothing*/
2628 }
2629
2630 void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
2631 {
2632         struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2633         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
2634         struct mem_input *mi = pipe_ctx->plane_res.mi;
2635         struct dc_cursor_mi_param param = {
2636                 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz,
2637                 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,
2638                 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2639                 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2640                 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2641                 .rotation = pipe_ctx->plane_state->rotation,
2642                 .mirror = pipe_ctx->plane_state->horizontal_mirror
2643         };
2644
2645         if (pipe_ctx->plane_state->address.type
2646                         == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2647                 pos_cpy.enable = false;
2648
2649         if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
2650                 pos_cpy.enable = false;
2651
2652         if (ipp->funcs->ipp_cursor_set_position)
2653                 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
2654         if (mi->funcs->set_cursor_position)
2655                 mi->funcs->set_cursor_position(mi, &pos_cpy, &param);
2656 }
2657
2658 void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2659 {
2660         struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2661
2662         if (pipe_ctx->plane_res.ipp &&
2663             pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
2664                 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
2665                                 pipe_ctx->plane_res.ipp, attributes);
2666
2667         if (pipe_ctx->plane_res.mi &&
2668             pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
2669                 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
2670                                 pipe_ctx->plane_res.mi, attributes);
2671
2672         if (pipe_ctx->plane_res.xfm &&
2673             pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
2674                 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
2675                                 pipe_ctx->plane_res.xfm, attributes);
2676 }
2677
2678 static const struct hw_sequencer_funcs dce110_funcs = {
2679         .program_gamut_remap = program_gamut_remap,
2680         .init_hw = init_hw,
2681         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2682         .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
2683         .update_plane_addr = update_plane_addr,
2684         .update_pending_status = dce110_update_pending_status,
2685         .set_input_transfer_func = dce110_set_input_transfer_func,
2686         .set_output_transfer_func = dce110_set_output_transfer_func,
2687         .power_down = dce110_power_down,
2688         .enable_accelerated_mode = dce110_enable_accelerated_mode,
2689         .enable_timing_synchronization = dce110_enable_timing_synchronization,
2690         .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,
2691         .update_info_frame = dce110_update_info_frame,
2692         .enable_stream = dce110_enable_stream,
2693         .disable_stream = dce110_disable_stream,
2694         .unblank_stream = dce110_unblank_stream,
2695         .blank_stream = dce110_blank_stream,
2696         .enable_audio_stream = dce110_enable_audio_stream,
2697         .disable_audio_stream = dce110_disable_audio_stream,
2698         .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
2699         .enable_display_power_gating = dce110_enable_display_power_gating,
2700         .disable_plane = dce110_power_down_fe,
2701         .pipe_control_lock = dce_pipe_control_lock,
2702         .prepare_bandwidth = dce110_prepare_bandwidth,
2703         .optimize_bandwidth = dce110_optimize_bandwidth,
2704         .set_drr = set_drr,
2705         .get_position = get_position,
2706         .set_static_screen_control = set_static_screen_control,
2707         .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
2708         .enable_stream_timing = dce110_enable_stream_timing,
2709         .setup_stereo = NULL,
2710         .set_avmute = dce110_set_avmute,
2711         .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
2712         .edp_backlight_control = hwss_edp_backlight_control,
2713         .edp_power_control = hwss_edp_power_control,
2714         .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
2715         .set_cursor_position = dce110_set_cursor_position,
2716         .set_cursor_attribute = dce110_set_cursor_attribute
2717 };
2718
2719 void dce110_hw_sequencer_construct(struct dc *dc)
2720 {
2721         dc->hwss = dce110_funcs;
2722 }
2723