drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dc_bios_types.h"
  27 #include "dce_stream_encoder.h"
  28 #include "reg_helper.h"
  29 #define DC_LOGGER \
  30                 enc110->base.ctx->logger
  31 enum DP_PIXEL_ENCODING {
  32 DP_PIXEL_ENCODING_RGB444                 = 0x00000000,
  33 DP_PIXEL_ENCODING_YCBCR422               = 0x00000001,
  34 DP_PIXEL_ENCODING_YCBCR444               = 0x00000002,
  35 DP_PIXEL_ENCODING_RGB_WIDE_GAMUT         = 0x00000003,
  36 DP_PIXEL_ENCODING_Y_ONLY                 = 0x00000004,
  37 DP_PIXEL_ENCODING_YCBCR420               = 0x00000005,
  38 DP_PIXEL_ENCODING_RESERVED               = 0x00000006,
  39 };
  40
  41
  42 enum DP_COMPONENT_DEPTH {
  43 DP_COMPONENT_DEPTH_6BPC                  = 0x00000000,
  44 DP_COMPONENT_DEPTH_8BPC                  = 0x00000001,
  45 DP_COMPONENT_DEPTH_10BPC                 = 0x00000002,
  46 DP_COMPONENT_DEPTH_12BPC                 = 0x00000003,
  47 DP_COMPONENT_DEPTH_16BPC                 = 0x00000004,
  48 DP_COMPONENT_DEPTH_RESERVED              = 0x00000005,
  49 };
  50
  51
  52 #define REG(reg)\
  53         (enc110->regs->reg)
  54
  55 #undef FN
  56 #define FN(reg_name, field_name) \
  57         enc110->se_shift->field_name, enc110->se_mask->field_name
  58
  59 #define VBI_LINE_0 0
  60 #define DP_BLANK_MAX_RETRY 20
  61 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
  62
  63 #ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK
  64         #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK       0x00000010L
  65         #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK         0x00000300L
  66         #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT     0x00000004
  67         #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT       0x00000008
  68 #endif
  69
  70 enum {
  71         DP_MST_UPDATE_MAX_RETRY = 50
  72 };
  73
  74 #define DCE110_SE(audio)\
  75         container_of(audio, struct dce110_stream_encoder, base)
  76
  77 #define CTX \
  78         enc110->base.ctx
  79
  80 static void dce110_update_generic_info_packet(
  81         struct dce110_stream_encoder *enc110,
  82         uint32_t packet_index,
  83         const struct encoder_info_packet *info_packet)
  84 {
  85         uint32_t regval;
  86         /* TODOFPGA Figure out a proper number for max_retries polling for lock
  87          * use 50 for now.
  88          */
  89         uint32_t max_retries = 50;
  90
  91         /*we need turn on clock before programming AFMT block*/
  92         REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
  93
  94         if (REG(AFMT_VBI_PACKET_CONTROL1)) {
  95                 if (packet_index >= 8)
  96                         ASSERT(0);
  97
  98                 /* poll dig_update_lock is not locked -> asic internal signal
  99                  * assume otg master lock will unlock it
 100                  */
 101 /*              REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
 102                                 0, 10, max_retries);*/
 103
 104                 /* check if HW reading GSP memory */
 105                 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
 106                                 0, 10, max_retries);
 107
 108                 /* HW does is not reading GSP memory not reading too long ->
 109                  * something wrong. clear GPS memory access and notify?
 110                  * hw SW is writing to GSP memory
 111                  */
 112                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
 113         }
 114         /* choose which generic packet to use */
 115         {
 116                 regval = REG_READ(AFMT_VBI_PACKET_CONTROL);
 117                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
 118                                 AFMT_GENERIC_INDEX, packet_index);
 119         }
 120
 121         /* write generic packet header
 122          * (4th byte is for GENERIC0 only) */
 123         {
 124                 REG_SET_4(AFMT_GENERIC_HDR, 0,
 125                                 AFMT_GENERIC_HB0, info_packet->hb0,
 126                                 AFMT_GENERIC_HB1, info_packet->hb1,
 127                                 AFMT_GENERIC_HB2, info_packet->hb2,
 128                                 AFMT_GENERIC_HB3, info_packet->hb3);
 129         }
 130
 131         /* write generic packet contents
 132          * (we never use last 4 bytes)
 133          * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers */
 134         {
 135                 const uint32_t *content =
 136                         (const uint32_t *) &info_packet->sb[0];
 137
 138                 REG_WRITE(AFMT_GENERIC_0, *content++);
 139                 REG_WRITE(AFMT_GENERIC_1, *content++);
 140                 REG_WRITE(AFMT_GENERIC_2, *content++);
 141                 REG_WRITE(AFMT_GENERIC_3, *content++);
 142                 REG_WRITE(AFMT_GENERIC_4, *content++);
 143                 REG_WRITE(AFMT_GENERIC_5, *content++);
 144                 REG_WRITE(AFMT_GENERIC_6, *content++);
 145                 REG_WRITE(AFMT_GENERIC_7, *content);
 146         }
 147
 148         if (!REG(AFMT_VBI_PACKET_CONTROL1)) {
 149                 /* force double-buffered packet update */
 150                 REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL,
 151                         AFMT_GENERIC0_UPDATE, (packet_index == 0),
 152                         AFMT_GENERIC2_UPDATE, (packet_index == 2));
 153         }
 154 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 155         if (REG(AFMT_VBI_PACKET_CONTROL1)) {
 156                 switch (packet_index) {
 157                 case 0:
 158                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 159                                         AFMT_GENERIC0_FRAME_UPDATE, 1);
 160                         break;
 161                 case 1:
 162                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 163                                         AFMT_GENERIC1_FRAME_UPDATE, 1);
 164                         break;
 165                 case 2:
 166                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 167                                         AFMT_GENERIC2_FRAME_UPDATE, 1);
 168                         break;
 169                 case 3:
 170                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 171                                         AFMT_GENERIC3_FRAME_UPDATE, 1);
 172                         break;
 173                 case 4:
 174                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 175                                         AFMT_GENERIC4_FRAME_UPDATE, 1);
 176                         break;
 177                 case 5:
 178                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 179                                         AFMT_GENERIC5_FRAME_UPDATE, 1);
 180                         break;
 181                 case 6:
 182                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 183                                         AFMT_GENERIC6_FRAME_UPDATE, 1);
 184                         break;
 185                 case 7:
 186                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 187                                         AFMT_GENERIC7_FRAME_UPDATE, 1);
 188                         break;
 189                 default:
 190                         break;
 191                 }
 192         }
 193 #endif
 194 }
 195
 196 static void dce110_update_hdmi_info_packet(
 197         struct dce110_stream_encoder *enc110,
 198         uint32_t packet_index,
 199         const struct encoder_info_packet *info_packet)
 200 {
 201         uint32_t cont, send, line;
 202
 203         if (info_packet->valid) {
 204                 dce110_update_generic_info_packet(
 205                         enc110,
 206                         packet_index,
 207                         info_packet);
 208
 209                 /* enable transmission of packet(s) -
 210                  * packet transmission begins on the next frame */
 211                 cont = 1;
 212                 /* send packet(s) every frame */
 213                 send = 1;
 214                 /* select line number to send packets on */
 215                 line = 2;
 216         } else {
 217                 cont = 0;
 218                 send = 0;
 219                 line = 0;
 220         }
 221
 222         /* choose which generic packet control to use */
 223         switch (packet_index) {
 224         case 0:
 225                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
 226                                 HDMI_GENERIC0_CONT, cont,
 227                                 HDMI_GENERIC0_SEND, send,
 228                                 HDMI_GENERIC0_LINE, line);
 229                 break;
 230         case 1:
 231                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
 232                                 HDMI_GENERIC1_CONT, cont,
 233                                 HDMI_GENERIC1_SEND, send,
 234                                 HDMI_GENERIC1_LINE, line);
 235                 break;
 236         case 2:
 237                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
 238                                 HDMI_GENERIC0_CONT, cont,
 239                                 HDMI_GENERIC0_SEND, send,
 240                                 HDMI_GENERIC0_LINE, line);
 241                 break;
 242         case 3:
 243                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
 244                                 HDMI_GENERIC1_CONT, cont,
 245                                 HDMI_GENERIC1_SEND, send,
 246                                 HDMI_GENERIC1_LINE, line);
 247                 break;
 248 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 249         case 4:
 250                 if (REG(HDMI_GENERIC_PACKET_CONTROL2))
 251                         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
 252                                         HDMI_GENERIC0_CONT, cont,
 253                                         HDMI_GENERIC0_SEND, send,
 254                                         HDMI_GENERIC0_LINE, line);
 255                 break;
 256         case 5:
 257                 if (REG(HDMI_GENERIC_PACKET_CONTROL2))
 258                         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
 259                                         HDMI_GENERIC1_CONT, cont,
 260                                         HDMI_GENERIC1_SEND, send,
 261                                         HDMI_GENERIC1_LINE, line);
 262                 break;
 263         case 6:
 264                 if (REG(HDMI_GENERIC_PACKET_CONTROL3))
 265                         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
 266                                         HDMI_GENERIC0_CONT, cont,
 267                                         HDMI_GENERIC0_SEND, send,
 268                                         HDMI_GENERIC0_LINE, line);
 269                 break;
 270         case 7:
 271                 if (REG(HDMI_GENERIC_PACKET_CONTROL3))
 272                         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
 273                                         HDMI_GENERIC1_CONT, cont,
 274                                         HDMI_GENERIC1_SEND, send,
 275                                         HDMI_GENERIC1_LINE, line);
 276                 break;
 277 #endif
 278         default:
 279                 /* invalid HW packet index */
 280                 DC_LOG_WARNING(
 281                         "Invalid HW packet index: %s()\n",
 282                         __func__);
 283                 return;
 284         }
 285 }
 286
 287 /* setup stream encoder in dp mode */
 288 static void dce110_stream_encoder_dp_set_stream_attribute(
 289         struct stream_encoder *enc,
 290         struct dc_crtc_timing *crtc_timing,
 291         enum dc_color_space output_color_space)
 292 {
 293 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 294         uint32_t h_active_start;
 295         uint32_t v_active_start;
 296         uint32_t misc0 = 0;
 297         uint32_t misc1 = 0;
 298         uint32_t h_blank;
 299         uint32_t h_back_porch;
 300         uint8_t synchronous_clock = 0; /* asynchronous mode */
 301         uint8_t colorimetry_bpc;
 302         uint8_t dynamic_range_rgb = 0; /*full range*/
 303         uint8_t dynamic_range_ycbcr = 1; /*bt709*/
 304 #endif
 305
 306         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 307
 308 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 309         if (REG(DP_DB_CNTL))
 310                 REG_UPDATE(DP_DB_CNTL, DP_DB_DISABLE, 1);
 311 #endif
 312
 313         /* set pixel encoding */
 314         switch (crtc_timing->pixel_encoding) {
 315         case PIXEL_ENCODING_YCBCR422:
 316                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 317                                 DP_PIXEL_ENCODING_YCBCR422);
 318                 break;
 319         case PIXEL_ENCODING_YCBCR444:
 320                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 321                                 DP_PIXEL_ENCODING_YCBCR444);
 322
 323                 if (crtc_timing->flags.Y_ONLY)
 324                         if (crtc_timing->display_color_depth != COLOR_DEPTH_666)
 325                                 /* HW testing only, no use case yet.
 326                                  * Color depth of Y-only could be
 327                                  * 8, 10, 12, 16 bits */
 328                                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 329                                                 DP_PIXEL_ENCODING_Y_ONLY);
 330                 /* Note: DP_MSA_MISC1 bit 7 is the indicator
 331                  * of Y-only mode.
 332                  * This bit is set in HW if register
 333                  * DP_PIXEL_ENCODING is programmed to 0x4 */
 334                 break;
 335         case PIXEL_ENCODING_YCBCR420:
 336                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 337                                 DP_PIXEL_ENCODING_YCBCR420);
 338                 if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
 339                         REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
 340
 341 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 342                 if (enc110->se_mask->DP_VID_N_MUL)
 343                         REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
 344 #endif
 345                 break;
 346         default:
 347                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 348                                 DP_PIXEL_ENCODING_RGB444);
 349                 break;
 350         }
 351
 352 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 353         if (REG(DP_MSA_MISC))
 354                 misc1 = REG_READ(DP_MSA_MISC);
 355 #endif
 356
 357         /* set color depth */
 358
 359         switch (crtc_timing->display_color_depth) {
 360         case COLOR_DEPTH_666:
 361                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 362                                 0);
 363                 break;
 364         case COLOR_DEPTH_888:
 365                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 366                                 DP_COMPONENT_DEPTH_8BPC);
 367                 break;
 368         case COLOR_DEPTH_101010:
 369                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 370                                 DP_COMPONENT_DEPTH_10BPC);
 371
 372                 break;
 373         case COLOR_DEPTH_121212:
 374                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 375                                 DP_COMPONENT_DEPTH_12BPC);
 376                 break;
 377         default:
 378                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 379                                 DP_COMPONENT_DEPTH_6BPC);
 380                 break;
 381         }
 382
 383         /* set dynamic range and YCbCr range */
 384
 385
 386 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 387         switch (crtc_timing->display_color_depth) {
 388         case COLOR_DEPTH_666:
 389                 colorimetry_bpc = 0;
 390                 break;
 391         case COLOR_DEPTH_888:
 392                 colorimetry_bpc = 1;
 393                 break;
 394         case COLOR_DEPTH_101010:
 395                 colorimetry_bpc = 2;
 396                 break;
 397         case COLOR_DEPTH_121212:
 398                 colorimetry_bpc = 3;
 399                 break;
 400         default:
 401                 colorimetry_bpc = 0;
 402                 break;
 403         }
 404
 405         misc0 = misc0 | synchronous_clock;
 406         misc0 = colorimetry_bpc << 5;
 407
 408         if (REG(DP_MSA_TIMING_PARAM1)) {
 409                 switch (output_color_space) {
 410                 case COLOR_SPACE_SRGB:
 411                         misc0 = misc0 | 0x0;
 412                         misc1 = misc1 & ~0x80; /* bit7 = 0*/
 413                         dynamic_range_rgb = 0; /*full range*/
 414                         break;
 415                 case COLOR_SPACE_SRGB_LIMITED:
 416                         misc0 = misc0 | 0x8; /* bit3=1 */
 417                         misc1 = misc1 & ~0x80; /* bit7 = 0*/
 418                         dynamic_range_rgb = 1; /*limited range*/
 419                         break;
 420                 case COLOR_SPACE_YCBCR601:
 421                 case COLOR_SPACE_YCBCR601_LIMITED:
 422                         misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
 423                         misc1 = misc1 & ~0x80; /* bit7 = 0*/
 424                         dynamic_range_ycbcr = 0; /*bt601*/
 425                         if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
 426                                 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
 427                         else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
 428                                 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
 429                         break;
 430                 case COLOR_SPACE_YCBCR709:
 431                 case COLOR_SPACE_YCBCR709_LIMITED:
 432                         misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
 433                         misc1 = misc1 & ~0x80; /* bit7 = 0*/
 434                         dynamic_range_ycbcr = 1; /*bt709*/
 435                         if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
 436                                 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
 437                         else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
 438                                 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
 439                         break;
 440                 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
 441                         dynamic_range_rgb = 1; /*limited range*/
 442                         break;
 443                 case COLOR_SPACE_2020_RGB_FULLRANGE:
 444                 case COLOR_SPACE_2020_YCBCR:
 445                 case COLOR_SPACE_XR_RGB:
 446                 case COLOR_SPACE_MSREF_SCRGB:
 447                 case COLOR_SPACE_ADOBERGB:
 448                 case COLOR_SPACE_DCIP3:
 449                 case COLOR_SPACE_XV_YCC_709:
 450                 case COLOR_SPACE_XV_YCC_601:
 451                 case COLOR_SPACE_DISPLAYNATIVE:
 452                 case COLOR_SPACE_DOLBYVISION:
 453                 case COLOR_SPACE_APPCTRL:
 454                 case COLOR_SPACE_CUSTOMPOINTS:
 455                 case COLOR_SPACE_UNKNOWN:
 456                         /* do nothing */
 457                         break;
 458                 }
 459                 if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE)
 460                         REG_UPDATE_2(
 461                                 DP_PIXEL_FORMAT,
 462                                 DP_DYN_RANGE, dynamic_range_rgb,
 463                                 DP_YCBCR_RANGE, dynamic_range_ycbcr);
 464
 465 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 466                 if (REG(DP_MSA_COLORIMETRY))
 467                         REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
 468
 469                 if (REG(DP_MSA_MISC))
 470                         REG_WRITE(DP_MSA_MISC, misc1);   /* MSA_MISC1 */
 471
 472         /* dcn new register
 473          * dc_crtc_timing is vesa dmt struct. data from edid
 474          */
 475                 if (REG(DP_MSA_TIMING_PARAM1))
 476                         REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
 477                                         DP_MSA_HTOTAL, crtc_timing->h_total,
 478                                         DP_MSA_VTOTAL, crtc_timing->v_total);
 479 #endif
 480
 481                 /* calcuate from vesa timing parameters
 482                  * h_active_start related to leading edge of sync
 483                  */
 484
 485                 h_blank = crtc_timing->h_total - crtc_timing->h_border_left -
 486                                 crtc_timing->h_addressable - crtc_timing->h_border_right;
 487
 488                 h_back_porch = h_blank - crtc_timing->h_front_porch -
 489                                 crtc_timing->h_sync_width;
 490
 491                 /* start at begining of left border */
 492                 h_active_start = crtc_timing->h_sync_width + h_back_porch;
 493
 494
 495                 v_active_start = crtc_timing->v_total - crtc_timing->v_border_top -
 496                                 crtc_timing->v_addressable - crtc_timing->v_border_bottom -
 497                                 crtc_timing->v_front_porch;
 498
 499
 500 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 501                 /* start at begining of left border */
 502                 if (REG(DP_MSA_TIMING_PARAM2))
 503                         REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
 504                                 DP_MSA_HSTART, h_active_start,
 505                                 DP_MSA_VSTART, v_active_start);
 506
 507                 if (REG(DP_MSA_TIMING_PARAM3))
 508                         REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
 509                                         DP_MSA_HSYNCWIDTH,
 510                                         crtc_timing->h_sync_width,
 511                                         DP_MSA_HSYNCPOLARITY,
 512                                         !crtc_timing->flags.HSYNC_POSITIVE_POLARITY,
 513                                         DP_MSA_VSYNCWIDTH,
 514                                         crtc_timing->v_sync_width,
 515                                         DP_MSA_VSYNCPOLARITY,
 516                                         !crtc_timing->flags.VSYNC_POSITIVE_POLARITY);
 517
 518                 /* HWDITH include border or overscan */
 519                 if (REG(DP_MSA_TIMING_PARAM4))
 520                         REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
 521                                 DP_MSA_HWIDTH, crtc_timing->h_border_left +
 522                                 crtc_timing->h_addressable + crtc_timing->h_border_right,
 523                                 DP_MSA_VHEIGHT, crtc_timing->v_border_top +
 524                                 crtc_timing->v_addressable + crtc_timing->v_border_bottom);
 525 #endif
 526         }
 527 #endif
 528 }
 529
 530 static void dce110_stream_encoder_set_stream_attribute_helper(
 531                 struct dce110_stream_encoder *enc110,
 532                 struct dc_crtc_timing *crtc_timing)
 533 {
 534         if (enc110->regs->TMDS_CNTL) {
 535                 switch (crtc_timing->pixel_encoding) {
 536                 case PIXEL_ENCODING_YCBCR422:
 537                         REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1);
 538                         break;
 539                 default:
 540                         REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0);
 541                         break;
 542                 }
 543                 REG_UPDATE(TMDS_CNTL, TMDS_COLOR_FORMAT, 0);
 544         } else if (enc110->regs->DIG_FE_CNTL) {
 545                 switch (crtc_timing->pixel_encoding) {
 546                 case PIXEL_ENCODING_YCBCR422:
 547                         REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
 548                         break;
 549                 default:
 550                         REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
 551                         break;
 552                 }
 553                 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
 554         }
 555
 556 }
 557
 558 /* setup stream encoder in hdmi mode */
 559 static void dce110_stream_encoder_hdmi_set_stream_attribute(
 560         struct stream_encoder *enc,
 561         struct dc_crtc_timing *crtc_timing,
 562         int actual_pix_clk_khz,
 563         bool enable_audio)
 564 {
 565         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 566         struct bp_encoder_control cntl = {0};
 567
 568         cntl.action = ENCODER_CONTROL_SETUP;
 569         cntl.engine_id = enc110->base.id;
 570         cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 571         cntl.enable_dp_audio = enable_audio;
 572         cntl.pixel_clock = actual_pix_clk_khz;
 573         cntl.lanes_number = LANE_COUNT_FOUR;
 574
 575         if (enc110->base.bp->funcs->encoder_control(
 576                         enc110->base.bp, &cntl) != BP_RESULT_OK)
 577                 return;
 578
 579         dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
 580
 581         /* setup HDMI engine */
 582         if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
 583                 REG_UPDATE_3(HDMI_CONTROL,
 584                         HDMI_PACKET_GEN_VERSION, 1,
 585                         HDMI_KEEPOUT_MODE, 1,
 586                         HDMI_DEEP_COLOR_ENABLE, 0);
 587         } else if (enc110->regs->DIG_FE_CNTL) {
 588                 REG_UPDATE_5(HDMI_CONTROL,
 589                         HDMI_PACKET_GEN_VERSION, 1,
 590                         HDMI_KEEPOUT_MODE, 1,
 591                         HDMI_DEEP_COLOR_ENABLE, 0,
 592                         HDMI_DATA_SCRAMBLE_EN, 0,
 593                         HDMI_CLOCK_CHANNEL_RATE, 0);
 594         }
 595
 596         switch (crtc_timing->display_color_depth) {
 597         case COLOR_DEPTH_888:
 598                 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
 599                 break;
 600         case COLOR_DEPTH_101010:
 601                 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
 602                         REG_UPDATE_2(HDMI_CONTROL,
 603                                         HDMI_DEEP_COLOR_DEPTH, 1,
 604                                         HDMI_DEEP_COLOR_ENABLE, 0);
 605                 } else {
 606                         REG_UPDATE_2(HDMI_CONTROL,
 607                                         HDMI_DEEP_COLOR_DEPTH, 1,
 608                                         HDMI_DEEP_COLOR_ENABLE, 1);
 609                         }
 610                 break;
 611         case COLOR_DEPTH_121212:
 612                 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
 613                         REG_UPDATE_2(HDMI_CONTROL,
 614                                         HDMI_DEEP_COLOR_DEPTH, 2,
 615                                         HDMI_DEEP_COLOR_ENABLE, 0);
 616                 } else {
 617                         REG_UPDATE_2(HDMI_CONTROL,
 618                                         HDMI_DEEP_COLOR_DEPTH, 2,
 619                                         HDMI_DEEP_COLOR_ENABLE, 1);
 620                         }
 621                 break;
 622         case COLOR_DEPTH_161616:
 623                 REG_UPDATE_2(HDMI_CONTROL,
 624                                 HDMI_DEEP_COLOR_DEPTH, 3,
 625                                 HDMI_DEEP_COLOR_ENABLE, 1);
 626                 break;
 627         default:
 628                 break;
 629         }
 630
 631         if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
 632                 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
 633                         /* enable HDMI data scrambler
 634                          * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
 635                          * Clock channel frequency is 1/4 of character rate.
 636                          */
 637                         REG_UPDATE_2(HDMI_CONTROL,
 638                                 HDMI_DATA_SCRAMBLE_EN, 1,
 639                                 HDMI_CLOCK_CHANNEL_RATE, 1);
 640                 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
 641
 642                         /* TODO: New feature for DCE11, still need to implement */
 643
 644                         /* enable HDMI data scrambler
 645                          * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
 646                          * Clock channel frequency is the same
 647                          * as character rate
 648                          */
 649                         REG_UPDATE_2(HDMI_CONTROL,
 650                                 HDMI_DATA_SCRAMBLE_EN, 1,
 651                                 HDMI_CLOCK_CHANNEL_RATE, 0);
 652                 }
 653         }
 654
 655         REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
 656                 HDMI_GC_CONT, 1,
 657                 HDMI_GC_SEND, 1,
 658                 HDMI_NULL_SEND, 1);
 659
 660         /* following belongs to audio */
 661         REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
 662
 663         REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
 664
 665         REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
 666                                 VBI_LINE_0 + 2);
 667
 668         REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
 669
 670 }
 671
 672 /* setup stream encoder in dvi mode */
 673 static void dce110_stream_encoder_dvi_set_stream_attribute(
 674         struct stream_encoder *enc,
 675         struct dc_crtc_timing *crtc_timing,
 676         bool is_dual_link)
 677 {
 678         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 679         struct bp_encoder_control cntl = {0};
 680
 681         cntl.action = ENCODER_CONTROL_SETUP;
 682         cntl.engine_id = enc110->base.id;
 683         cntl.signal = is_dual_link ?
 684                         SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
 685         cntl.enable_dp_audio = false;
 686         cntl.pixel_clock = crtc_timing->pix_clk_khz;
 687         cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
 688
 689         if (enc110->base.bp->funcs->encoder_control(
 690                         enc110->base.bp, &cntl) != BP_RESULT_OK)
 691                 return;
 692
 693         ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
 694         ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
 695         dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
 696 }
 697
 698 static void dce110_stream_encoder_set_mst_bandwidth(
 699         struct stream_encoder *enc,
 700         struct fixed31_32 avg_time_slots_per_mtp)
 701 {
 702         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 703         uint32_t x = dal_fixed31_32_floor(
 704                 avg_time_slots_per_mtp);
 705         uint32_t y = dal_fixed31_32_ceil(
 706                 dal_fixed31_32_shl(
 707                         dal_fixed31_32_sub_int(
 708                                 avg_time_slots_per_mtp,
 709                                 x),
 710                         26));
 711
 712         {
 713                 REG_SET_2(DP_MSE_RATE_CNTL, 0,
 714                         DP_MSE_RATE_X, x,
 715                         DP_MSE_RATE_Y, y);
 716         }
 717
 718         /* wait for update to be completed on the link */
 719         /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
 720         /* is reset to 0 (not pending) */
 721         REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
 722                         0,
 723                         10, DP_MST_UPDATE_MAX_RETRY);
 724 }
 725
 726 static void dce110_stream_encoder_update_hdmi_info_packets(
 727         struct stream_encoder *enc,
 728         const struct encoder_info_frame *info_frame)
 729 {
 730         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 731
 732         if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
 733                         enc110->se_mask->HDMI_AVI_INFO_SEND) {
 734
 735                 if (info_frame->avi.valid) {
 736                         const uint32_t *content =
 737                                 (const uint32_t *) &info_frame->avi.sb[0];
 738
 739                         REG_WRITE(AFMT_AVI_INFO0, content[0]);
 740
 741                         REG_WRITE(AFMT_AVI_INFO1, content[1]);
 742
 743                         REG_WRITE(AFMT_AVI_INFO2, content[2]);
 744
 745                         REG_WRITE(AFMT_AVI_INFO3, content[3]);
 746
 747                         REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION,
 748                                                 info_frame->avi.hb1);
 749
 750                         REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
 751                                         HDMI_AVI_INFO_SEND, 1,
 752                                         HDMI_AVI_INFO_CONT, 1);
 753
 754                         REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE,
 755                                                         VBI_LINE_0 + 2);
 756
 757                 } else {
 758                         REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
 759                                 HDMI_AVI_INFO_SEND, 0,
 760                                 HDMI_AVI_INFO_CONT, 0);
 761                 }
 762         }
 763
 764         if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
 765                         enc110->se_mask->HDMI_AVI_INFO_SEND) {
 766                 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor);
 767                 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut);
 768                 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd);
 769                 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd);
 770         }
 771
 772 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 773         if (enc110->se_mask->HDMI_DB_DISABLE) {
 774                 /* for bring up, disable dp double  TODO */
 775                 if (REG(HDMI_DB_CONTROL))
 776                         REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
 777
 778                 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->avi);
 779                 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->vendor);
 780                 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->gamut);
 781                 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd);
 782                 dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd);
 783         }
 784 #endif
 785 }
 786
 787 static void dce110_stream_encoder_stop_hdmi_info_packets(
 788         struct stream_encoder *enc)
 789 {
 790         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 791
 792         /* stop generic packets 0 & 1 on HDMI */
 793         REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
 794                 HDMI_GENERIC1_CONT, 0,
 795                 HDMI_GENERIC1_LINE, 0,
 796                 HDMI_GENERIC1_SEND, 0,
 797                 HDMI_GENERIC0_CONT, 0,
 798                 HDMI_GENERIC0_LINE, 0,
 799                 HDMI_GENERIC0_SEND, 0);
 800
 801         /* stop generic packets 2 & 3 on HDMI */
 802         REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
 803                 HDMI_GENERIC0_CONT, 0,
 804                 HDMI_GENERIC0_LINE, 0,
 805                 HDMI_GENERIC0_SEND, 0,
 806                 HDMI_GENERIC1_CONT, 0,
 807                 HDMI_GENERIC1_LINE, 0,
 808                 HDMI_GENERIC1_SEND, 0);
 809
 810 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 811         /* stop generic packets 2 & 3 on HDMI */
 812         if (REG(HDMI_GENERIC_PACKET_CONTROL2))
 813                 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
 814                         HDMI_GENERIC0_CONT, 0,
 815                         HDMI_GENERIC0_LINE, 0,
 816                         HDMI_GENERIC0_SEND, 0,
 817                         HDMI_GENERIC1_CONT, 0,
 818                         HDMI_GENERIC1_LINE, 0,
 819                         HDMI_GENERIC1_SEND, 0);
 820
 821         if (REG(HDMI_GENERIC_PACKET_CONTROL3))
 822                 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
 823                         HDMI_GENERIC0_CONT, 0,
 824                         HDMI_GENERIC0_LINE, 0,
 825                         HDMI_GENERIC0_SEND, 0,
 826                         HDMI_GENERIC1_CONT, 0,
 827                         HDMI_GENERIC1_LINE, 0,
 828                         HDMI_GENERIC1_SEND, 0);
 829 #endif
 830 }
 831
 832 static void dce110_stream_encoder_update_dp_info_packets(
 833         struct stream_encoder *enc,
 834         const struct encoder_info_frame *info_frame)
 835 {
 836         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 837         uint32_t value = REG_READ(DP_SEC_CNTL);
 838
 839         if (info_frame->vsc.valid)
 840                 dce110_update_generic_info_packet(
 841                                         enc110,
 842                                         0,  /* packetIndex */
 843                                         &info_frame->vsc);
 844
 845         if (info_frame->spd.valid)
 846                 dce110_update_generic_info_packet(
 847                                 enc110,
 848                                 2,  /* packetIndex */
 849                                 &info_frame->spd);
 850
 851         if (info_frame->hdrsmd.valid)
 852                 dce110_update_generic_info_packet(
 853                                 enc110,
 854                                 3,  /* packetIndex */
 855                                 &info_frame->hdrsmd);
 856
 857         /* enable/disable transmission of packet(s).
 858         *  If enabled, packet transmission begins on the next frame
 859         */
 860         REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
 861         REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
 862         REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
 863
 864         /* This bit is the master enable bit.
 865         * When enabling secondary stream engine,
 866         * this master bit must also be set.
 867         * This register shared with audio info frame.
 868         * Therefore we need to enable master bit
 869         * if at least on of the fields is not 0
 870         */
 871         if (value)
 872                 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
 873 }
 874
 875 static void dce110_stream_encoder_stop_dp_info_packets(
 876         struct stream_encoder *enc)
 877 {
 878         /* stop generic packets on DP */
 879         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 880         uint32_t value = REG_READ(DP_SEC_CNTL);
 881
 882         if (enc110->se_mask->DP_SEC_AVI_ENABLE) {
 883                 REG_SET_7(DP_SEC_CNTL, 0,
 884                         DP_SEC_GSP0_ENABLE, 0,
 885                         DP_SEC_GSP1_ENABLE, 0,
 886                         DP_SEC_GSP2_ENABLE, 0,
 887                         DP_SEC_GSP3_ENABLE, 0,
 888                         DP_SEC_AVI_ENABLE, 0,
 889                         DP_SEC_MPG_ENABLE, 0,
 890                         DP_SEC_STREAM_ENABLE, 0);
 891         }
 892
 893 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 894         if (enc110->se_mask->DP_SEC_GSP7_ENABLE) {
 895                 REG_SET_10(DP_SEC_CNTL, 0,
 896                         DP_SEC_GSP0_ENABLE, 0,
 897                         DP_SEC_GSP1_ENABLE, 0,
 898                         DP_SEC_GSP2_ENABLE, 0,
 899                         DP_SEC_GSP3_ENABLE, 0,
 900                         DP_SEC_GSP4_ENABLE, 0,
 901                         DP_SEC_GSP5_ENABLE, 0,
 902                         DP_SEC_GSP6_ENABLE, 0,
 903                         DP_SEC_GSP7_ENABLE, 0,
 904                         DP_SEC_MPG_ENABLE, 0,
 905                         DP_SEC_STREAM_ENABLE, 0);
 906         }
 907 #endif
 908         /* this register shared with audio info frame.
 909          * therefore we need to keep master enabled
 910          * if at least one of the fields is not 0 */
 911
 912         if (value)
 913                 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
 914
 915 }
 916
 917 static void dce110_stream_encoder_dp_blank(
 918         struct stream_encoder *enc)
 919 {
 920         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 921         uint32_t retries = 0;
 922         uint32_t  reg1 = 0;
 923         uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
 924
 925         /* Note: For CZ, we are changing driver default to disable
 926          * stream deferred to next VBLANK. If results are positive, we
 927          * will make the same change to all DCE versions. There are a
 928          * handful of panels that cannot handle disable stream at
 929          * HBLANK and will result in a white line flash across the
 930          * screen on stream disable. */
 931         REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1);
 932         if ((reg1 & 0x1) == 0)
 933                 /*stream not enabled*/
 934                 return;
 935         /* Specify the video stream disable point
 936          * (2 = start of the next vertical blank) */
 937         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
 938         /* Larger delay to wait until VBLANK - use max retry of
 939         * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
 940         * a little more because we may not trust delay accuracy.
 941         */
 942         max_retries = DP_BLANK_MAX_RETRY * 150;
 943
 944         /* disable DP stream */
 945         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
 946
 947         /* the encoder stops sending the video stream
 948         * at the start of the vertical blanking.
 949         * Poll for DP_VID_STREAM_STATUS == 0
 950         */
 951
 952         REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
 953                         0,
 954                         10, max_retries);
 955
 956         ASSERT(retries <= max_retries);
 957
 958         /* Tell the DP encoder to ignore timing from CRTC, must be done after
 959         * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
 960         * complete, stream status will be stuck in video stream enabled state,
 961         * i.e. DP_VID_STREAM_STATUS stuck at 1.
 962         */
 963
 964         REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
 965 }
 966
 967 /* output video stream to link encoder */
 968 static void dce110_stream_encoder_dp_unblank(
 969         struct stream_encoder *enc,
 970         const struct encoder_unblank_param *param)
 971 {
 972         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 973
 974         if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
 975                 uint32_t n_vid = 0x8000;
 976                 uint32_t m_vid;
 977
 978                 /* M / N = Fstream / Flink
 979                 * m_vid / n_vid = pixel rate / link rate
 980                 */
 981
 982                 uint64_t m_vid_l = n_vid;
 983
 984                 m_vid_l *= param->pixel_clk_khz;
 985                 m_vid_l = div_u64(m_vid_l,
 986                         param->link_settings.link_rate
 987                                 * LINK_RATE_REF_FREQ_IN_KHZ);
 988
 989                 m_vid = (uint32_t) m_vid_l;
 990
 991                 /* enable auto measurement */
 992
 993                 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
 994
 995                 /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
 996                  * therefore program initial value for Mvid and Nvid
 997                  */
 998
 999                 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
1000
1001                 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
1002
1003                 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);
1004         }
1005
1006         /* set DIG_START to 0x1 to resync FIFO */
1007
1008         REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
1009
1010         /* switch DP encoder to CRTC data */
1011
1012         REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
1013
1014         /* wait 100us for DIG/DP logic to prime
1015         * (i.e. a few video lines)
1016         */
1017         udelay(100);
1018
1019         /* the hardware would start sending video at the start of the next DP
1020         * frame (i.e. rising edge of the vblank).
1021         * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
1022         * register has no effect on enable transition! HW always guarantees
1023         * VID_STREAM enable at start of next frame, and this is not
1024         * programmable
1025         */
1026
1027         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
1028 }
1029
1030 static void dce110_stream_encoder_set_avmute(
1031         struct stream_encoder *enc,
1032         bool enable)
1033 {
1034         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1035         unsigned int value = enable ? 1 : 0;
1036
1037         REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
1038 }
1039
1040
1041 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
1042 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
1043
1044 #include "include/audio_types.h"
1045
1046 /**
1047 * speakersToChannels
1048 *
1049 * @brief
1050 *  translate speakers to channels
1051 *
1052 *  FL  - Front Left
1053 *  FR  - Front Right
1054 *  RL  - Rear Left
1055 *  RR  - Rear Right
1056 *  RC  - Rear Center
1057 *  FC  - Front Center
1058 *  FLC - Front Left Center
1059 *  FRC - Front Right Center
1060 *  RLC - Rear Left Center
1061 *  RRC - Rear Right Center
1062 *  LFE - Low Freq Effect
1063 *
1064 *               FC
1065 *          FLC      FRC
1066 *    FL                    FR
1067 *
1068 *                    LFE
1069 *              ()
1070 *
1071 *
1072 *    RL                    RR
1073 *          RLC      RRC
1074 *               RC
1075 *
1076 *             ch  8   7   6   5   4   3   2   1
1077 * 0b00000011      -   -   -   -   -   -   FR  FL
1078 * 0b00000111      -   -   -   -   -   LFE FR  FL
1079 * 0b00001011      -   -   -   -   FC  -   FR  FL
1080 * 0b00001111      -   -   -   -   FC  LFE FR  FL
1081 * 0b00010011      -   -   -   RC  -   -   FR  FL
1082 * 0b00010111      -   -   -   RC  -   LFE FR  FL
1083 * 0b00011011      -   -   -   RC  FC  -   FR  FL
1084 * 0b00011111      -   -   -   RC  FC  LFE FR  FL
1085 * 0b00110011      -   -   RR  RL  -   -   FR  FL
1086 * 0b00110111      -   -   RR  RL  -   LFE FR  FL
1087 * 0b00111011      -   -   RR  RL  FC  -   FR  FL
1088 * 0b00111111      -   -   RR  RL  FC  LFE FR  FL
1089 * 0b01110011      -   RC  RR  RL  -   -   FR  FL
1090 * 0b01110111      -   RC  RR  RL  -   LFE FR  FL
1091 * 0b01111011      -   RC  RR  RL  FC  -   FR  FL
1092 * 0b01111111      -   RC  RR  RL  FC  LFE FR  FL
1093 * 0b11110011      RRC RLC RR  RL  -   -   FR  FL
1094 * 0b11110111      RRC RLC RR  RL  -   LFE FR  FL
1095 * 0b11111011      RRC RLC RR  RL  FC  -   FR  FL
1096 * 0b11111111      RRC RLC RR  RL  FC  LFE FR  FL
1097 * 0b11000011      FRC FLC -   -   -   -   FR  FL
1098 * 0b11000111      FRC FLC -   -   -   LFE FR  FL
1099 * 0b11001011      FRC FLC -   -   FC  -   FR  FL
1100 * 0b11001111      FRC FLC -   -   FC  LFE FR  FL
1101 * 0b11010011      FRC FLC -   RC  -   -   FR  FL
1102 * 0b11010111      FRC FLC -   RC  -   LFE FR  FL
1103 * 0b11011011      FRC FLC -   RC  FC  -   FR  FL
1104 * 0b11011111      FRC FLC -   RC  FC  LFE FR  FL
1105 * 0b11110011      FRC FLC RR  RL  -   -   FR  FL
1106 * 0b11110111      FRC FLC RR  RL  -   LFE FR  FL
1107 * 0b11111011      FRC FLC RR  RL  FC  -   FR  FL
1108 * 0b11111111      FRC FLC RR  RL  FC  LFE FR  FL
1109 *
1110 * @param
1111 *  speakers - speaker information as it comes from CEA audio block
1112 */
1113 /* translate speakers to channels */
1114
1115 union audio_cea_channels {
1116         uint8_t all;
1117         struct audio_cea_channels_bits {
1118                 uint32_t FL:1;
1119                 uint32_t FR:1;
1120                 uint32_t LFE:1;
1121                 uint32_t FC:1;
1122                 uint32_t RL_RC:1;
1123                 uint32_t RR:1;
1124                 uint32_t RC_RLC_FLC:1;
1125                 uint32_t RRC_FRC:1;
1126         } channels;
1127 };
1128
1129 struct audio_clock_info {
1130         /* pixel clock frequency*/
1131         uint32_t pixel_clock_in_10khz;
1132         /* N - 32KHz audio */
1133         uint32_t n_32khz;
1134         /* CTS - 32KHz audio*/
1135         uint32_t cts_32khz;
1136         uint32_t n_44khz;
1137         uint32_t cts_44khz;
1138         uint32_t n_48khz;
1139         uint32_t cts_48khz;
1140 };
1141
1142 /* 25.2MHz/1.001*/
1143 /* 25.2MHz/1.001*/
1144 /* 25.2MHz*/
1145 /* 27MHz */
1146 /* 27MHz*1.001*/
1147 /* 27MHz*1.001*/
1148 /* 54MHz*/
1149 /* 54MHz*1.001*/
1150 /* 74.25MHz/1.001*/
1151 /* 74.25MHz*/
1152 /* 148.5MHz/1.001*/
1153 /* 148.5MHz*/
1154
1155 static const struct audio_clock_info audio_clock_info_table[16] = {
1156         {2517, 4576, 28125, 7007, 31250, 6864, 28125},
1157         {2518, 4576, 28125, 7007, 31250, 6864, 28125},
1158         {2520, 4096, 25200, 6272, 28000, 6144, 25200},
1159         {2700, 4096, 27000, 6272, 30000, 6144, 27000},
1160         {2702, 4096, 27027, 6272, 30030, 6144, 27027},
1161         {2703, 4096, 27027, 6272, 30030, 6144, 27027},
1162         {5400, 4096, 54000, 6272, 60000, 6144, 54000},
1163         {5405, 4096, 54054, 6272, 60060, 6144, 54054},
1164         {7417, 11648, 210937, 17836, 234375, 11648, 140625},
1165         {7425, 4096, 74250, 6272, 82500, 6144, 74250},
1166         {14835, 11648, 421875, 8918, 234375, 5824, 140625},
1167         {14850, 4096, 148500, 6272, 165000, 6144, 148500},
1168         {29670, 5824, 421875, 4459, 234375, 5824, 281250},
1169         {29700, 3072, 222750, 4704, 247500, 5120, 247500},
1170         {59340, 5824, 843750, 8918, 937500, 5824, 562500},
1171         {59400, 3072, 445500, 9408, 990000, 6144, 594000}
1172 };
1173
1174 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
1175         {2517,  9152,  84375,  7007,  48875,  9152,  56250},
1176         {2518,  9152,  84375,  7007,  48875,  9152,  56250},
1177         {2520,  4096,  37800,  6272,  42000,  6144,  37800},
1178         {2700,  4096,  40500,  6272,  45000,  6144,  40500},
1179         {2702,  8192,  81081,  6272,  45045,  8192,  54054},
1180         {2703,  8192,  81081,  6272,  45045,  8192,  54054},
1181         {5400,  4096,  81000,  6272,  90000,  6144,  81000},
1182         {5405,  4096,  81081,  6272,  90090,  6144,  81081},
1183         {7417, 11648, 316406, 17836, 351562, 11648, 210937},
1184         {7425, 4096, 111375,  6272, 123750,  6144, 111375},
1185         {14835, 11648, 632812, 17836, 703125, 11648, 421875},
1186         {14850, 4096, 222750,  6272, 247500,  6144, 222750},
1187         {29670, 5824, 632812,  8918, 703125,  5824, 421875},
1188         {29700, 4096, 445500,  4704, 371250,  5120, 371250}
1189 };
1190
1191 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
1192         {2517,  4576,  56250,  7007,  62500,  6864,  56250},
1193         {2518,  4576,  56250,  7007,  62500,  6864,  56250},
1194         {2520,  4096,  50400,  6272,  56000,  6144,  50400},
1195         {2700,  4096,  54000,  6272,  60000,  6144,  54000},
1196         {2702,  4096,  54054,  6267,  60060,  8192,  54054},
1197         {2703,  4096,  54054,  6272,  60060,  8192,  54054},
1198         {5400,  4096, 108000,  6272, 120000,  6144, 108000},
1199         {5405,  4096, 108108,  6272, 120120,  6144, 108108},
1200         {7417, 11648, 421875, 17836, 468750, 11648, 281250},
1201         {7425,  4096, 148500,  6272, 165000,  6144, 148500},
1202         {14835, 11648, 843750,  8918, 468750, 11648, 281250},
1203         {14850, 4096, 297000,  6272, 330000,  6144, 297000},
1204         {29670, 5824, 843750,  4459, 468750,  5824, 562500},
1205         {29700, 3072, 445500,  4704, 495000,  5120, 495000}
1206
1207
1208 };
1209
1210 static union audio_cea_channels speakers_to_channels(
1211         struct audio_speaker_flags speaker_flags)
1212 {
1213         union audio_cea_channels cea_channels = {0};
1214
1215         /* these are one to one */
1216         cea_channels.channels.FL = speaker_flags.FL_FR;
1217         cea_channels.channels.FR = speaker_flags.FL_FR;
1218         cea_channels.channels.LFE = speaker_flags.LFE;
1219         cea_channels.channels.FC = speaker_flags.FC;
1220
1221         /* if Rear Left and Right exist move RC speaker to channel 7
1222          * otherwise to channel 5
1223          */
1224         if (speaker_flags.RL_RR) {
1225                 cea_channels.channels.RL_RC = speaker_flags.RL_RR;
1226                 cea_channels.channels.RR = speaker_flags.RL_RR;
1227                 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
1228         } else {
1229                 cea_channels.channels.RL_RC = speaker_flags.RC;
1230         }
1231
1232         /* FRONT Left Right Center and REAR Left Right Center are exclusive */
1233         if (speaker_flags.FLC_FRC) {
1234                 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
1235                 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
1236         } else {
1237                 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
1238                 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
1239         }
1240
1241         return cea_channels;
1242 }
1243
1244 static uint32_t calc_max_audio_packets_per_line(
1245         const struct audio_crtc_info *crtc_info)
1246 {
1247         uint32_t max_packets_per_line;
1248
1249         max_packets_per_line =
1250                 crtc_info->h_total - crtc_info->h_active;
1251
1252         if (crtc_info->pixel_repetition)
1253                 max_packets_per_line *= crtc_info->pixel_repetition;
1254
1255         /* for other hdmi features */
1256         max_packets_per_line -= 58;
1257         /* for Control Period */
1258         max_packets_per_line -= 16;
1259         /* Number of Audio Packets per Line */
1260         max_packets_per_line /= 32;
1261
1262         return max_packets_per_line;
1263 }
1264
1265 static void get_audio_clock_info(
1266         enum dc_color_depth color_depth,
1267         uint32_t crtc_pixel_clock_in_khz,
1268         uint32_t actual_pixel_clock_in_khz,
1269         struct audio_clock_info *audio_clock_info)
1270 {
1271         const struct audio_clock_info *clock_info;
1272         uint32_t index;
1273         uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10;
1274         uint32_t audio_array_size;
1275
1276         switch (color_depth) {
1277         case COLOR_DEPTH_161616:
1278                 clock_info = audio_clock_info_table_48bpc;
1279                 audio_array_size = ARRAY_SIZE(
1280                                 audio_clock_info_table_48bpc);
1281                 break;
1282         case COLOR_DEPTH_121212:
1283                 clock_info = audio_clock_info_table_36bpc;
1284                 audio_array_size = ARRAY_SIZE(
1285                                 audio_clock_info_table_36bpc);
1286                 break;
1287         default:
1288                 clock_info = audio_clock_info_table;
1289                 audio_array_size = ARRAY_SIZE(
1290                                 audio_clock_info_table);
1291                 break;
1292         }
1293
1294         if (clock_info != NULL) {
1295                 /* search for exact pixel clock in table */
1296                 for (index = 0; index < audio_array_size; index++) {
1297                         if (clock_info[index].pixel_clock_in_10khz >
1298                                 crtc_pixel_clock_in_10khz)
1299                                 break;  /* not match */
1300                         else if (clock_info[index].pixel_clock_in_10khz ==
1301                                         crtc_pixel_clock_in_10khz) {
1302                                 /* match found */
1303                                 *audio_clock_info = clock_info[index];
1304                                 return;
1305                         }
1306                 }
1307         }
1308
1309         /* not found */
1310         if (actual_pixel_clock_in_khz == 0)
1311                 actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz;
1312
1313         /* See HDMI spec  the table entry under
1314          *  pixel clock of "Other". */
1315         audio_clock_info->pixel_clock_in_10khz =
1316                         actual_pixel_clock_in_khz / 10;
1317         audio_clock_info->cts_32khz = actual_pixel_clock_in_khz;
1318         audio_clock_info->cts_44khz = actual_pixel_clock_in_khz;
1319         audio_clock_info->cts_48khz = actual_pixel_clock_in_khz;
1320
1321         audio_clock_info->n_32khz = 4096;
1322         audio_clock_info->n_44khz = 6272;
1323         audio_clock_info->n_48khz = 6144;
1324 }
1325
1326 static void dce110_se_audio_setup(
1327         struct stream_encoder *enc,
1328         unsigned int az_inst,
1329         struct audio_info *audio_info)
1330 {
1331         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1332
1333         uint32_t speakers = 0;
1334         uint32_t channels = 0;
1335
1336         ASSERT(audio_info);
1337         if (audio_info == NULL)
1338                 /* This should not happen.it does so we don't get BSOD*/
1339                 return;
1340
1341         speakers = audio_info->flags.info.ALLSPEAKERS;
1342         channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
1343
1344         /* setup the audio stream source select (audio -> dig mapping) */
1345         REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
1346
1347         /* Channel allocation */
1348         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
1349 }
1350
1351 static void dce110_se_setup_hdmi_audio(
1352         struct stream_encoder *enc,
1353         const struct audio_crtc_info *crtc_info)
1354 {
1355         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1356
1357         struct audio_clock_info audio_clock_info = {0};
1358         uint32_t max_packets_per_line;
1359
1360         /* For now still do calculation, although this field is ignored when
1361         above HDMI_PACKET_GEN_VERSION set to 1 */
1362         max_packets_per_line = calc_max_audio_packets_per_line(crtc_info);
1363
1364         /* HDMI_AUDIO_PACKET_CONTROL */
1365         REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL,
1366                         HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line,
1367                         HDMI_AUDIO_DELAY_EN, 1);
1368
1369         /* AFMT_AUDIO_PACKET_CONTROL */
1370         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1371
1372         /* AFMT_AUDIO_PACKET_CONTROL2 */
1373         REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1374                         AFMT_AUDIO_LAYOUT_OVRD, 0,
1375                         AFMT_60958_OSF_OVRD, 0);
1376
1377         /* HDMI_ACR_PACKET_CONTROL */
1378         REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
1379                         HDMI_ACR_AUTO_SEND, 1,
1380                         HDMI_ACR_SOURCE, 0,
1381                         HDMI_ACR_AUDIO_PRIORITY, 0);
1382
1383         /* Program audio clock sample/regeneration parameters */
1384         get_audio_clock_info(crtc_info->color_depth,
1385                              crtc_info->requested_pixel_clock,
1386                              crtc_info->calculated_pixel_clock,
1387                              &audio_clock_info);
1388         DC_LOG_HW_AUDIO(
1389                         "\n%s:Input::requested_pixel_clock = %d"        \
1390                         "calculated_pixel_clock = %d \n", __func__,     \
1391                         crtc_info->requested_pixel_clock,               \
1392                         crtc_info->calculated_pixel_clock);
1393
1394         /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
1395         REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
1396
1397         /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
1398         REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
1399
1400         /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
1401         REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
1402
1403         /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
1404         REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
1405
1406         /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
1407         REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
1408
1409         /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
1410         REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
1411
1412         /* Video driver cannot know in advance which sample rate will
1413            be used by HD Audio driver
1414            HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
1415            programmed below in interruppt callback */
1416
1417         /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
1418         AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1419         REG_UPDATE_2(AFMT_60958_0,
1420                         AFMT_60958_CS_CHANNEL_NUMBER_L, 1,
1421                         AFMT_60958_CS_CLOCK_ACCURACY, 0);
1422
1423         /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
1424         REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1425
1426         /*AFMT_60958_2 now keep this settings until
1427          *  Programming guide comes out*/
1428         REG_UPDATE_6(AFMT_60958_2,
1429                         AFMT_60958_CS_CHANNEL_NUMBER_2, 3,
1430                         AFMT_60958_CS_CHANNEL_NUMBER_3, 4,
1431                         AFMT_60958_CS_CHANNEL_NUMBER_4, 5,
1432                         AFMT_60958_CS_CHANNEL_NUMBER_5, 6,
1433                         AFMT_60958_CS_CHANNEL_NUMBER_6, 7,
1434                         AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1435 }
1436
1437 static void dce110_se_setup_dp_audio(
1438         struct stream_encoder *enc)
1439 {
1440         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1441
1442         /* --- DP Audio packet configurations --- */
1443
1444         /* ATP Configuration */
1445         REG_SET(DP_SEC_AUD_N, 0,
1446                         DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
1447
1448         /* Async/auto-calc timestamp mode */
1449         REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
1450                         DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
1451
1452         /* --- The following are the registers
1453          *  copied from the SetupHDMI --- */
1454
1455         /* AFMT_AUDIO_PACKET_CONTROL */
1456         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1457
1458         /* AFMT_AUDIO_PACKET_CONTROL2 */
1459         /* Program the ATP and AIP next */
1460         REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1461                         AFMT_AUDIO_LAYOUT_OVRD, 0,
1462                         AFMT_60958_OSF_OVRD, 0);
1463
1464         /* AFMT_INFOFRAME_CONTROL0 */
1465         REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1466
1467         /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1468         REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
1469 }
1470
1471 static void dce110_se_enable_audio_clock(
1472         struct stream_encoder *enc,
1473         bool enable)
1474 {
1475         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1476
1477         if (REG(AFMT_CNTL) == 0)
1478                 return;   /* DCE8/10 does not have this register */
1479
1480         REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
1481
1482         /* wait for AFMT clock to turn on,
1483          * expectation: this should complete in 1-2 reads
1484          *
1485          * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
1486          *
1487          * TODO: wait for clock_on does not work well. May need HW
1488          * program sequence. But audio seems work normally even without wait
1489          * for clock_on status change
1490          */
1491 }
1492
1493 static void dce110_se_enable_dp_audio(
1494         struct stream_encoder *enc)
1495 {
1496         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1497
1498         /* Enable Audio packets */
1499         REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1500
1501         /* Program the ATP and AIP next */
1502         REG_UPDATE_2(DP_SEC_CNTL,
1503                         DP_SEC_ATP_ENABLE, 1,
1504                         DP_SEC_AIP_ENABLE, 1);
1505
1506         /* Program STREAM_ENABLE after all the other enables. */
1507         REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1508 }
1509
1510 static void dce110_se_disable_dp_audio(
1511         struct stream_encoder *enc)
1512 {
1513         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1514         uint32_t value = REG_READ(DP_SEC_CNTL);
1515
1516         /* Disable Audio packets */
1517         REG_UPDATE_5(DP_SEC_CNTL,
1518                         DP_SEC_ASP_ENABLE, 0,
1519                         DP_SEC_ATP_ENABLE, 0,
1520                         DP_SEC_AIP_ENABLE, 0,
1521                         DP_SEC_ACM_ENABLE, 0,
1522                         DP_SEC_STREAM_ENABLE, 0);
1523
1524         /* This register shared with encoder info frame. Therefore we need to
1525         keep master enabled if at least on of the fields is not 0 */
1526         if (value != 0)
1527                 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1528
1529 }
1530
1531 void dce110_se_audio_mute_control(
1532         struct stream_encoder *enc,
1533         bool mute)
1534 {
1535         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1536
1537         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
1538 }
1539
1540 void dce110_se_dp_audio_setup(
1541         struct stream_encoder *enc,
1542         unsigned int az_inst,
1543         struct audio_info *info)
1544 {
1545         dce110_se_audio_setup(enc, az_inst, info);
1546 }
1547
1548 void dce110_se_dp_audio_enable(
1549         struct stream_encoder *enc)
1550 {
1551         dce110_se_enable_audio_clock(enc, true);
1552         dce110_se_setup_dp_audio(enc);
1553         dce110_se_enable_dp_audio(enc);
1554 }
1555
1556 void dce110_se_dp_audio_disable(
1557         struct stream_encoder *enc)
1558 {
1559         dce110_se_disable_dp_audio(enc);
1560         dce110_se_enable_audio_clock(enc, false);
1561 }
1562
1563 void dce110_se_hdmi_audio_setup(
1564         struct stream_encoder *enc,
1565         unsigned int az_inst,
1566         struct audio_info *info,
1567         struct audio_crtc_info *audio_crtc_info)
1568 {
1569         dce110_se_enable_audio_clock(enc, true);
1570         dce110_se_setup_hdmi_audio(enc, audio_crtc_info);
1571         dce110_se_audio_setup(enc, az_inst, info);
1572 }
1573
1574 void dce110_se_hdmi_audio_disable(
1575         struct stream_encoder *enc)
1576 {
1577         dce110_se_enable_audio_clock(enc, false);
1578 }
1579
1580
1581 static void setup_stereo_sync(
1582         struct stream_encoder *enc,
1583         int tg_inst, bool enable)
1584 {
1585         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1586         REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1587         REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
1588 }
1589
1590
1591 static const struct stream_encoder_funcs dce110_str_enc_funcs = {
1592         .dp_set_stream_attribute =
1593                 dce110_stream_encoder_dp_set_stream_attribute,
1594         .hdmi_set_stream_attribute =
1595                 dce110_stream_encoder_hdmi_set_stream_attribute,
1596         .dvi_set_stream_attribute =
1597                 dce110_stream_encoder_dvi_set_stream_attribute,
1598         .set_mst_bandwidth =
1599                 dce110_stream_encoder_set_mst_bandwidth,
1600         .update_hdmi_info_packets =
1601                 dce110_stream_encoder_update_hdmi_info_packets,
1602         .stop_hdmi_info_packets =
1603                 dce110_stream_encoder_stop_hdmi_info_packets,
1604         .update_dp_info_packets =
1605                 dce110_stream_encoder_update_dp_info_packets,
1606         .stop_dp_info_packets =
1607                 dce110_stream_encoder_stop_dp_info_packets,
1608         .dp_blank =
1609                 dce110_stream_encoder_dp_blank,
1610         .dp_unblank =
1611                 dce110_stream_encoder_dp_unblank,
1612         .audio_mute_control = dce110_se_audio_mute_control,
1613
1614         .dp_audio_setup = dce110_se_dp_audio_setup,
1615         .dp_audio_enable = dce110_se_dp_audio_enable,
1616         .dp_audio_disable = dce110_se_dp_audio_disable,
1617
1618         .hdmi_audio_setup = dce110_se_hdmi_audio_setup,
1619         .hdmi_audio_disable = dce110_se_hdmi_audio_disable,
1620         .setup_stereo_sync  = setup_stereo_sync,
1621         .set_avmute = dce110_stream_encoder_set_avmute,
1622
1623 };
1624
1625 void dce110_stream_encoder_construct(
1626         struct dce110_stream_encoder *enc110,
1627         struct dc_context *ctx,
1628         struct dc_bios *bp,
1629         enum engine_id eng_id,
1630         const struct dce110_stream_enc_registers *regs,
1631         const struct dce_stream_encoder_shift *se_shift,
1632         const struct dce_stream_encoder_mask *se_mask)
1633 {
1634         enc110->base.funcs = &dce110_str_enc_funcs;
1635         enc110->base.ctx = ctx;
1636         enc110->base.id = eng_id;
1637         enc110->base.bp = bp;
1638         enc110->regs = regs;
1639         enc110->se_shift = se_shift;
1640         enc110->se_mask = se_mask;
1641 }