2 * Copyright 2012-14 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #ifndef DC_INTERFACE_H_
27 #define DC_INTERFACE_H_
30 #include "grph_object_defs.h"
31 #include "logger_types.h"
32 #include "gpio_types.h"
33 #include "link_service_types.h"
34 #include "grph_object_ctrl_defs.h"
35 #include <inc/hw/opp.h>
37 #include "inc/hw_sequencer.h"
38 #include "inc/compressor.h"
39 #include "dml/display_mode_lib.h"
41 #define DC_VER "3.1.59"
43 #define MAX_SURFACES 3
45 #define MAX_SINKS_PER_LINK 4
48 /*******************************************************************************
49 * Display Core Interfaces
50 ******************************************************************************/
55 unsigned int interface_version;
60 struct dmcu_version dmcu_version;
67 uint32_t max_slave_planes;
69 uint32_t max_downscale_ratio;
70 uint32_t i2c_speed_in_khz;
71 uint32_t dmdata_alloc_size;
72 unsigned int max_cursor_size;
73 unsigned int max_video_width;
74 int linear_pitch_alignment;
79 bool post_blend_color_processing;
80 bool force_dp_tps4_for_cp2520;
83 struct dc_dcc_surface_param {
84 struct dc_size surface_size;
85 enum surface_pixel_format format;
86 enum swizzle_mode_values swizzle_mode;
87 enum dc_scan_direction scan;
90 struct dc_dcc_setting {
91 unsigned int max_compressed_blk_size;
92 unsigned int max_uncompressed_blk_size;
93 bool independent_64b_blks;
96 struct dc_surface_dcc_cap {
99 struct dc_dcc_setting rgb;
103 struct dc_dcc_setting luma;
104 struct dc_dcc_setting chroma;
109 bool const_color_support;
112 struct dc_static_screen_events {
120 /* Surface update type is used by dc_update_surfaces_and_stream
121 * The update type is determined at the very beginning of the function based
122 * on parameters passed in and decides how much programming (or updating) is
123 * going to be done during the call.
125 * UPDATE_TYPE_FAST is used for really fast updates that do not require much
126 * logical calculations or hardware register programming. This update MUST be
127 * ISR safe on windows. Currently fast update will only be used to flip surface
130 * UPDATE_TYPE_MED is used for slower updates which require significant hw
131 * re-programming however do not affect bandwidth consumption or clock
132 * requirements. At present, this is the level at which front end updates
133 * that do not require us to run bw_calcs happen. These are in/out transfer func
134 * updates, viewport offset changes, recout size changes and pixel depth changes.
135 * This update can be done at ISR, but we want to minimize how often this happens.
137 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
138 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
139 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
140 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
141 * a full update. This cannot be done at ISR level and should be a rare event.
142 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
143 * underscan we don't expect to see this call at all.
146 enum surface_update_type {
147 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
148 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/
149 UPDATE_TYPE_FULL, /* may need to shuffle resources */
152 /* Forward declaration*/
154 struct dc_plane_state;
158 struct dc_cap_funcs {
159 bool (*get_dcc_compression_cap)(const struct dc *dc,
160 const struct dc_dcc_surface_param *input,
161 struct dc_surface_dcc_cap *output);
164 struct link_training_settings;
167 /* Structure to hold configuration flags set by dm at dc creation. */
170 bool disable_disp_pll_sharing;
173 enum visual_confirm {
174 VISUAL_CONFIRM_DISABLE = 0,
175 VISUAL_CONFIRM_SURFACE = 1,
176 VISUAL_CONFIRM_HDR = 2,
182 DCC_HALF_REQ_DISALBE = 2,
185 enum pipe_split_policy {
186 MPC_SPLIT_DYNAMIC = 0,
188 MPC_SPLIT_AVOID_MULT_DISP = 2,
191 enum wm_report_mode {
192 WM_REPORT_DEFAULT = 0,
193 WM_REPORT_OVERRIDE = 1,
197 * For any clocks that may differ per pipe
198 * only the max is stored in this structure
202 int max_supported_dppclk_khz;
206 int dcfclk_deep_sleep_khz;
211 struct dc_debug_options {
212 enum visual_confirm visual_confirm;
218 bool validation_trace;
219 bool bandwidth_calcs_trace;
220 int max_downscale_src_width;
222 /* stutter efficiency related */
223 bool disable_stutter;
225 enum dcc_option disable_dcc;
226 enum pipe_split_policy pipe_split_policy;
227 bool force_single_disp_pipe_split;
228 bool voltage_align_fclk;
230 bool disable_dfs_bypass;
231 bool disable_dpp_power_gate;
232 bool disable_hubp_power_gate;
233 bool disable_pplib_wm_range;
234 enum wm_report_mode pplib_wm_report_mode;
235 unsigned int min_disp_clk_khz;
236 int sr_exit_time_dpm0_ns;
237 int sr_enter_plus_exit_time_dpm0_ns;
239 int sr_enter_plus_exit_time_ns;
240 int urgent_latency_ns;
241 int percent_of_ideal_drambw;
242 int dram_clock_change_latency_ns;
243 bool optimized_watermark;
245 bool disable_pplib_clock_request;
246 bool disable_clock_gate;
249 bool force_abm_enable;
250 bool disable_hbup_pg;
252 bool disable_stereo_support;
254 bool performance_trace;
255 bool az_endpoint_mute_only;
256 bool always_use_regamma;
257 bool p010_mpo_support;
258 bool recovery_enabled;
259 bool avoid_vbios_exec_table;
260 bool scl_reset_length10;
262 bool skip_detection_link_training;
265 struct dc_debug_data {
266 uint32_t ltFailCount;
267 uint32_t i2cErrorCount;
268 uint32_t auxErrorCount;
273 struct resource_pool;
276 struct dc_versions versions;
278 struct dc_cap_funcs cap_funcs;
279 struct dc_config config;
280 struct dc_debug_options debug;
281 struct dc_context *ctx;
284 struct dc_link *links[MAX_PIPES * 2];
286 struct dc_state *current_state;
287 struct resource_pool *res_pool;
289 /* Display Engine Clock levels */
290 struct dm_pp_clock_levels sclk_lvls;
292 /* Inputs into BW and WM calculations. */
293 struct bw_calcs_dceip *bw_dceip;
294 struct bw_calcs_vbios *bw_vbios;
296 struct dcn_soc_bounding_box *dcn_soc;
297 struct dcn_ip_params *dcn_ip;
298 struct display_mode_lib dml;
302 struct hw_sequencer_funcs hwss;
303 struct dce_hwseq *hwseq;
305 /* temp store of dm_pp_display_configuration
306 * to compare to see if display config changed
308 struct dm_pp_display_configuration prev_display_config;
310 bool optimized_required;
312 bool apply_edp_fast_boot_optimization;
315 struct compressor *fbc_compressor;
317 struct dc_debug_data debug_data;
320 enum frame_buffer_mode {
321 FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
322 FRAME_BUFFER_MODE_ZFB_ONLY,
323 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
326 struct dchub_init_data {
327 int64_t zfb_phys_addr_base;
328 int64_t zfb_mc_base_addr;
329 uint64_t zfb_size_in_byte;
330 enum frame_buffer_mode fb_mode;
331 bool dchub_initialzied;
332 bool dchub_info_valid;
335 struct dc_init_data {
336 struct hw_asic_id asic_id;
337 void *driver; /* ctx */
338 struct cgs_device *cgs_device;
340 int num_virtual_links;
342 * If 'vbios_override' not NULL, it will be called instead
343 * of the real VBIOS. Intended use is Diagnostics on FPGA.
345 struct dc_bios *vbios_override;
346 enum dce_environment dce_environment;
348 struct dc_config flags;
352 struct dc *dc_create(const struct dc_init_data *init_params);
354 void dc_destroy(struct dc **dc);
356 /*******************************************************************************
358 ******************************************************************************/
361 TRANSFER_FUNC_POINTS = 1025
364 struct dc_hdr_static_metadata {
365 /* display chromaticities and white point in units of 0.00001 */
366 unsigned int chromaticity_green_x;
367 unsigned int chromaticity_green_y;
368 unsigned int chromaticity_blue_x;
369 unsigned int chromaticity_blue_y;
370 unsigned int chromaticity_red_x;
371 unsigned int chromaticity_red_y;
372 unsigned int chromaticity_white_point_x;
373 unsigned int chromaticity_white_point_y;
375 uint32_t min_luminance;
376 uint32_t max_luminance;
377 uint32_t maximum_content_light_level;
378 uint32_t maximum_frame_average_light_level;
381 enum dc_transfer_func_type {
383 TF_TYPE_DISTRIBUTED_POINTS,
388 struct dc_transfer_func_distributed_points {
389 struct fixed31_32 red[TRANSFER_FUNC_POINTS];
390 struct fixed31_32 green[TRANSFER_FUNC_POINTS];
391 struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
393 uint16_t end_exponent;
394 uint16_t x_point_at_y1_red;
395 uint16_t x_point_at_y1_green;
396 uint16_t x_point_at_y1_blue;
399 enum dc_transfer_func_predefined {
400 TRANSFER_FUNCTION_SRGB,
401 TRANSFER_FUNCTION_BT709,
402 TRANSFER_FUNCTION_PQ,
403 TRANSFER_FUNCTION_LINEAR,
404 TRANSFER_FUNCTION_UNITY,
405 TRANSFER_FUNCTION_HLG,
406 TRANSFER_FUNCTION_HLG12,
407 TRANSFER_FUNCTION_GAMMA22
410 struct dc_transfer_func {
411 struct kref refcount;
412 enum dc_transfer_func_type type;
413 enum dc_transfer_func_predefined tf;
414 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
415 uint32_t sdr_ref_white_level;
416 struct dc_context *ctx;
418 struct pwl_params pwl;
419 struct dc_transfer_func_distributed_points tf_pts;
424 * This structure is filled in by dc_surface_get_status and contains
425 * the last requested address and the currently active address so the called
426 * can determine if there are any outstanding flips
428 struct dc_plane_status {
429 struct dc_plane_address requested_address;
430 struct dc_plane_address current_address;
431 bool is_flip_pending;
435 union surface_update_flags {
439 uint32_t dcc_change:1;
440 uint32_t color_space_change:1;
441 uint32_t horizontal_mirror_change:1;
442 uint32_t per_pixel_alpha_change:1;
443 uint32_t rotation_change:1;
444 uint32_t swizzle_change:1;
445 uint32_t scaling_change:1;
446 uint32_t position_change:1;
447 uint32_t in_transfer_func_change:1;
448 uint32_t input_csc_change:1;
449 uint32_t coeff_reduction_change:1;
450 uint32_t output_tf_change:1;
451 uint32_t pixel_format_change:1;
454 uint32_t new_plane:1;
455 uint32_t bpp_change:1;
456 uint32_t gamma_change:1;
457 uint32_t bandwidth_change:1;
458 uint32_t clock_change:1;
459 uint32_t stereo_format_change:1;
460 uint32_t full_update:1;
466 struct dc_plane_state {
467 struct dc_plane_address address;
468 struct dc_plane_flip_time time;
469 struct scaling_taps scaling_quality;
470 struct rect src_rect;
471 struct rect dst_rect;
472 struct rect clip_rect;
474 union plane_size plane_size;
475 union dc_tiling_info tiling_info;
477 struct dc_plane_dcc_param dcc;
479 struct dc_gamma *gamma_correction;
480 struct dc_transfer_func *in_transfer_func;
481 struct dc_bias_and_scale *bias_and_scale;
482 struct dc_csc_transform input_csc_color_matrix;
483 struct fixed31_32 coeff_reduction_factor;
484 uint32_t sdr_white_level;
486 // TODO: No longer used, remove
487 struct dc_hdr_static_metadata hdr_static_ctx;
489 enum dc_color_space color_space;
491 enum surface_pixel_format format;
492 enum dc_rotation_angle rotation;
493 enum plane_stereo_format stereo_format;
495 bool is_tiling_rotated;
496 bool per_pixel_alpha;
499 bool horizontal_mirror;
501 union surface_update_flags update_flags;
502 /* private to DC core */
503 struct dc_plane_status status;
504 struct dc_context *ctx;
506 /* private to dc_surface.c */
507 enum dc_irq_source irq_source;
508 struct kref refcount;
511 struct dc_plane_info {
512 union plane_size plane_size;
513 union dc_tiling_info tiling_info;
514 struct dc_plane_dcc_param dcc;
515 enum surface_pixel_format format;
516 enum dc_rotation_angle rotation;
517 enum plane_stereo_format stereo_format;
518 enum dc_color_space color_space;
519 unsigned int sdr_white_level;
520 bool horizontal_mirror;
522 bool per_pixel_alpha;
523 bool input_csc_enabled;
526 struct dc_scaling_info {
527 struct rect src_rect;
528 struct rect dst_rect;
529 struct rect clip_rect;
530 struct scaling_taps scaling_quality;
533 struct dc_surface_update {
534 struct dc_plane_state *surface;
536 /* isr safe update parameters. null means no updates */
537 const struct dc_flip_addrs *flip_addr;
538 const struct dc_plane_info *plane_info;
539 const struct dc_scaling_info *scaling_info;
541 /* following updates require alloc/sleep/spin that is not isr safe,
542 * null means no updates
544 const struct dc_gamma *gamma;
545 const struct dc_transfer_func *in_transfer_func;
547 const struct dc_csc_transform *input_csc_color_matrix;
548 const struct fixed31_32 *coeff_reduction_factor;
552 * Create a new surface with default parameters;
554 struct dc_plane_state *dc_create_plane_state(struct dc *dc);
555 const struct dc_plane_status *dc_plane_get_status(
556 const struct dc_plane_state *plane_state);
558 void dc_plane_state_retain(struct dc_plane_state *plane_state);
559 void dc_plane_state_release(struct dc_plane_state *plane_state);
561 void dc_gamma_retain(struct dc_gamma *dc_gamma);
562 void dc_gamma_release(struct dc_gamma **dc_gamma);
563 struct dc_gamma *dc_create_gamma(void);
565 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
566 void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
567 struct dc_transfer_func *dc_create_transfer_func(void);
570 * This structure holds a surface address. There could be multiple addresses
571 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such
572 * as frame durations and DCC format can also be set.
574 struct dc_flip_addrs {
575 struct dc_plane_address address;
576 unsigned int flip_timestamp_in_us;
578 /* TODO: add flip duration for FreeSync */
581 bool dc_post_update_surfaces_to_stream(
584 #include "dc_stream.h"
587 * Structure to store surface/stream associations for validation
589 struct dc_validation_set {
590 struct dc_stream_state *stream;
591 struct dc_plane_state *plane_states[MAX_SURFACES];
595 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
597 enum dc_status dc_validate_global_state(
599 struct dc_state *new_ctx);
602 void dc_resource_state_construct(
604 struct dc_state *dst_ctx);
606 void dc_resource_state_copy_construct(
607 const struct dc_state *src_ctx,
608 struct dc_state *dst_ctx);
610 void dc_resource_state_copy_construct_current(
612 struct dc_state *dst_ctx);
614 void dc_resource_state_destruct(struct dc_state *context);
617 * TODO update to make it about validation sets
618 * Set up streams and links associated to drive sinks
619 * The streams parameter is an absolute set of all active streams.
622 * Phy, Encoder, Timing Generator are programmed and enabled.
623 * New streams are enabled with blank stream; no memory read.
625 bool dc_commit_state(struct dc *dc, struct dc_state *context);
628 struct dc_state *dc_create_state(void);
629 void dc_retain_state(struct dc_state *context);
630 void dc_release_state(struct dc_state *context);
632 /*******************************************************************************
634 ******************************************************************************/
637 union dpcd_rev dpcd_rev;
638 union max_lane_count max_ln_count;
639 union max_down_spread max_down_spread;
641 /* dongle type (DP converter, CV smart dongle) */
642 enum display_dongle_type dongle_type;
643 /* Dongle's downstream count. */
644 union sink_count sink_count;
645 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
646 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
647 struct dc_dongle_caps dongle_caps;
649 uint32_t sink_dev_id;
650 int8_t sink_dev_id_str[6];
651 int8_t sink_hw_revision;
652 int8_t sink_fw_revision[2];
654 uint32_t branch_dev_id;
655 int8_t branch_dev_name[6];
656 int8_t branch_hw_revision;
657 int8_t branch_fw_revision[2];
659 bool allow_invalid_MSA_timing_param;
661 bool dpcd_display_control_capable;
666 /*******************************************************************************
667 * Sink Interfaces - A sink corresponds to a display output device
668 ******************************************************************************/
670 struct dc_container_id {
671 // 128bit GUID in binary form
672 unsigned char guid[16];
673 // 8 byte port ID -> ELD.PortID
674 unsigned int portId[2];
675 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
676 unsigned short manufacturerName;
677 // 2 byte product code -> ELD.ProductCode
678 unsigned short productCode;
684 * The sink structure contains EDID and other display device properties
687 enum signal_type sink_signal;
688 struct dc_edid dc_edid; /* raw edid */
689 struct dc_edid_caps edid_caps; /* parse display caps */
690 struct dc_container_id *dc_container_id;
691 uint32_t dongle_max_pix_clk;
693 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
694 bool converter_disable_audio;
696 /* private to DC core */
697 struct dc_link *link;
698 struct dc_context *ctx;
702 /* private to dc_sink.c */
703 // refcount must be the last member in dc_sink, since we want the
704 // sink structure to be logically cloneable up to (but not including)
706 struct kref refcount;
709 void dc_sink_retain(struct dc_sink *sink);
710 void dc_sink_release(struct dc_sink *sink);
712 struct dc_sink_init_data {
713 enum signal_type sink_signal;
714 struct dc_link *link;
715 uint32_t dongle_max_pix_clk;
716 bool converter_disable_audio;
719 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
721 /* Newer interfaces */
723 struct dc_plane_address address;
724 struct dc_cursor_attributes attributes;
728 /*******************************************************************************
729 * Interrupt interfaces
730 ******************************************************************************/
731 enum dc_irq_source dc_interrupt_to_irq_source(
735 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
736 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
737 enum dc_irq_source dc_get_hpd_irq_source_at_index(
738 struct dc *dc, uint32_t link_index);
740 /*******************************************************************************
742 ******************************************************************************/
744 void dc_set_power_state(
746 enum dc_acpi_cm_power_state power_state);
747 void dc_resume(struct dc *dc);
749 #endif /* DC_INTERFACE_H_ */