2 * Copyright 2012-14 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #ifndef DC_INTERFACE_H_
27 #define DC_INTERFACE_H_
30 #include "grph_object_defs.h"
31 #include "logger_types.h"
32 #include "gpio_types.h"
33 #include "link_service_types.h"
34 #include "grph_object_ctrl_defs.h"
35 #include <inc/hw/opp.h>
37 #include "inc/hw_sequencer.h"
38 #include "inc/compressor.h"
39 #include "dml/display_mode_lib.h"
41 #define DC_VER "3.1.68"
43 #define MAX_SURFACES 3
45 #define MAX_SINKS_PER_LINK 4
47 /*******************************************************************************
48 * Display Core Interfaces
49 ******************************************************************************/
54 unsigned int interface_version;
59 struct dmcu_version dmcu_version;
66 uint32_t max_slave_planes;
68 uint32_t max_downscale_ratio;
69 uint32_t i2c_speed_in_khz;
70 uint32_t dmdata_alloc_size;
71 unsigned int max_cursor_size;
72 unsigned int max_video_width;
73 int linear_pitch_alignment;
78 bool post_blend_color_processing;
79 bool force_dp_tps4_for_cp2520;
80 bool disable_dp_clk_share;
81 bool psp_setup_panel_mode;
84 struct dc_dcc_surface_param {
85 struct dc_size surface_size;
86 enum surface_pixel_format format;
87 enum swizzle_mode_values swizzle_mode;
88 enum dc_scan_direction scan;
91 struct dc_dcc_setting {
92 unsigned int max_compressed_blk_size;
93 unsigned int max_uncompressed_blk_size;
94 bool independent_64b_blks;
97 struct dc_surface_dcc_cap {
100 struct dc_dcc_setting rgb;
104 struct dc_dcc_setting luma;
105 struct dc_dcc_setting chroma;
110 bool const_color_support;
113 struct dc_static_screen_events {
121 /* Surface update type is used by dc_update_surfaces_and_stream
122 * The update type is determined at the very beginning of the function based
123 * on parameters passed in and decides how much programming (or updating) is
124 * going to be done during the call.
126 * UPDATE_TYPE_FAST is used for really fast updates that do not require much
127 * logical calculations or hardware register programming. This update MUST be
128 * ISR safe on windows. Currently fast update will only be used to flip surface
131 * UPDATE_TYPE_MED is used for slower updates which require significant hw
132 * re-programming however do not affect bandwidth consumption or clock
133 * requirements. At present, this is the level at which front end updates
134 * that do not require us to run bw_calcs happen. These are in/out transfer func
135 * updates, viewport offset changes, recout size changes and pixel depth changes.
136 * This update can be done at ISR, but we want to minimize how often this happens.
138 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
139 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
140 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
141 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
142 * a full update. This cannot be done at ISR level and should be a rare event.
143 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
144 * underscan we don't expect to see this call at all.
147 enum surface_update_type {
148 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
149 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/
150 UPDATE_TYPE_FULL, /* may need to shuffle resources */
153 /* Forward declaration*/
155 struct dc_plane_state;
159 struct dc_cap_funcs {
160 bool (*get_dcc_compression_cap)(const struct dc *dc,
161 const struct dc_dcc_surface_param *input,
162 struct dc_surface_dcc_cap *output);
165 struct link_training_settings;
168 /* Structure to hold configuration flags set by dm at dc creation. */
171 bool disable_disp_pll_sharing;
174 enum visual_confirm {
175 VISUAL_CONFIRM_DISABLE = 0,
176 VISUAL_CONFIRM_SURFACE = 1,
177 VISUAL_CONFIRM_HDR = 2,
183 DCC_HALF_REQ_DISALBE = 2,
186 enum pipe_split_policy {
187 MPC_SPLIT_DYNAMIC = 0,
189 MPC_SPLIT_AVOID_MULT_DISP = 2,
192 enum wm_report_mode {
193 WM_REPORT_DEFAULT = 0,
194 WM_REPORT_OVERRIDE = 1,
198 * For any clocks that may differ per pipe
199 * only the max is stored in this structure
203 int max_supported_dppclk_khz;
207 int dcfclk_deep_sleep_khz;
213 struct dc_debug_options {
214 enum visual_confirm visual_confirm;
220 bool validation_trace;
221 bool bandwidth_calcs_trace;
222 int max_downscale_src_width;
224 /* stutter efficiency related */
225 bool disable_stutter;
227 enum dcc_option disable_dcc;
228 enum pipe_split_policy pipe_split_policy;
229 bool force_single_disp_pipe_split;
230 bool voltage_align_fclk;
232 bool disable_dfs_bypass;
233 bool disable_dpp_power_gate;
234 bool disable_hubp_power_gate;
235 bool disable_pplib_wm_range;
236 enum wm_report_mode pplib_wm_report_mode;
237 unsigned int min_disp_clk_khz;
238 int sr_exit_time_dpm0_ns;
239 int sr_enter_plus_exit_time_dpm0_ns;
241 int sr_enter_plus_exit_time_ns;
242 int urgent_latency_ns;
243 int percent_of_ideal_drambw;
244 int dram_clock_change_latency_ns;
245 bool optimized_watermark;
247 bool disable_pplib_clock_request;
248 bool disable_clock_gate;
251 bool force_abm_enable;
252 bool disable_hbup_pg;
254 bool disable_stereo_support;
256 bool performance_trace;
257 bool az_endpoint_mute_only;
258 bool always_use_regamma;
259 bool p010_mpo_support;
260 bool recovery_enabled;
261 bool avoid_vbios_exec_table;
262 bool scl_reset_length10;
264 bool skip_detection_link_training;
267 struct dc_debug_data {
268 uint32_t ltFailCount;
269 uint32_t i2cErrorCount;
270 uint32_t auxErrorCount;
275 struct resource_pool;
278 struct dc_versions versions;
280 struct dc_cap_funcs cap_funcs;
281 struct dc_config config;
282 struct dc_debug_options debug;
283 struct dc_context *ctx;
286 struct dc_link *links[MAX_PIPES * 2];
288 struct dc_state *current_state;
289 struct resource_pool *res_pool;
291 /* Display Engine Clock levels */
292 struct dm_pp_clock_levels sclk_lvls;
294 /* Inputs into BW and WM calculations. */
295 struct bw_calcs_dceip *bw_dceip;
296 struct bw_calcs_vbios *bw_vbios;
297 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
298 struct dcn_soc_bounding_box *dcn_soc;
299 struct dcn_ip_params *dcn_ip;
300 struct display_mode_lib dml;
304 struct hw_sequencer_funcs hwss;
305 struct dce_hwseq *hwseq;
307 /* temp store of dm_pp_display_configuration
308 * to compare to see if display config changed
310 struct dm_pp_display_configuration prev_display_config;
312 bool optimized_required;
315 struct compressor *fbc_compressor;
317 struct dc_debug_data debug_data;
319 const char *build_id;
322 enum frame_buffer_mode {
323 FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
324 FRAME_BUFFER_MODE_ZFB_ONLY,
325 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
328 struct dchub_init_data {
329 int64_t zfb_phys_addr_base;
330 int64_t zfb_mc_base_addr;
331 uint64_t zfb_size_in_byte;
332 enum frame_buffer_mode fb_mode;
333 bool dchub_initialzied;
334 bool dchub_info_valid;
337 struct dc_init_data {
338 struct hw_asic_id asic_id;
339 void *driver; /* ctx */
340 struct cgs_device *cgs_device;
342 int num_virtual_links;
344 * If 'vbios_override' not NULL, it will be called instead
345 * of the real VBIOS. Intended use is Diagnostics on FPGA.
347 struct dc_bios *vbios_override;
348 enum dce_environment dce_environment;
350 struct dc_config flags;
354 struct dc *dc_create(const struct dc_init_data *init_params);
356 void dc_destroy(struct dc **dc);
358 /*******************************************************************************
360 ******************************************************************************/
363 TRANSFER_FUNC_POINTS = 1025
366 struct dc_hdr_static_metadata {
367 /* display chromaticities and white point in units of 0.00001 */
368 unsigned int chromaticity_green_x;
369 unsigned int chromaticity_green_y;
370 unsigned int chromaticity_blue_x;
371 unsigned int chromaticity_blue_y;
372 unsigned int chromaticity_red_x;
373 unsigned int chromaticity_red_y;
374 unsigned int chromaticity_white_point_x;
375 unsigned int chromaticity_white_point_y;
377 uint32_t min_luminance;
378 uint32_t max_luminance;
379 uint32_t maximum_content_light_level;
380 uint32_t maximum_frame_average_light_level;
383 enum dc_transfer_func_type {
385 TF_TYPE_DISTRIBUTED_POINTS,
390 struct dc_transfer_func_distributed_points {
391 struct fixed31_32 red[TRANSFER_FUNC_POINTS];
392 struct fixed31_32 green[TRANSFER_FUNC_POINTS];
393 struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
395 uint16_t end_exponent;
396 uint16_t x_point_at_y1_red;
397 uint16_t x_point_at_y1_green;
398 uint16_t x_point_at_y1_blue;
401 enum dc_transfer_func_predefined {
402 TRANSFER_FUNCTION_SRGB,
403 TRANSFER_FUNCTION_BT709,
404 TRANSFER_FUNCTION_PQ,
405 TRANSFER_FUNCTION_LINEAR,
406 TRANSFER_FUNCTION_UNITY,
407 TRANSFER_FUNCTION_HLG,
408 TRANSFER_FUNCTION_HLG12,
409 TRANSFER_FUNCTION_GAMMA22
412 struct dc_transfer_func {
413 struct kref refcount;
414 enum dc_transfer_func_type type;
415 enum dc_transfer_func_predefined tf;
416 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
417 uint32_t sdr_ref_white_level;
418 struct dc_context *ctx;
420 struct pwl_params pwl;
421 struct dc_transfer_func_distributed_points tf_pts;
426 * This structure is filled in by dc_surface_get_status and contains
427 * the last requested address and the currently active address so the called
428 * can determine if there are any outstanding flips
430 struct dc_plane_status {
431 struct dc_plane_address requested_address;
432 struct dc_plane_address current_address;
433 bool is_flip_pending;
437 union surface_update_flags {
441 uint32_t dcc_change:1;
442 uint32_t color_space_change:1;
443 uint32_t horizontal_mirror_change:1;
444 uint32_t per_pixel_alpha_change:1;
445 uint32_t global_alpha_change:1;
446 uint32_t rotation_change:1;
447 uint32_t swizzle_change:1;
448 uint32_t scaling_change:1;
449 uint32_t position_change:1;
450 uint32_t in_transfer_func_change:1;
451 uint32_t input_csc_change:1;
452 uint32_t coeff_reduction_change:1;
453 uint32_t output_tf_change:1;
454 uint32_t pixel_format_change:1;
457 uint32_t new_plane:1;
458 uint32_t bpp_change:1;
459 uint32_t gamma_change:1;
460 uint32_t bandwidth_change:1;
461 uint32_t clock_change:1;
462 uint32_t stereo_format_change:1;
463 uint32_t full_update:1;
469 struct dc_plane_state {
470 struct dc_plane_address address;
471 struct dc_plane_flip_time time;
472 struct scaling_taps scaling_quality;
473 struct rect src_rect;
474 struct rect dst_rect;
475 struct rect clip_rect;
477 union plane_size plane_size;
478 union dc_tiling_info tiling_info;
480 struct dc_plane_dcc_param dcc;
482 struct dc_gamma *gamma_correction;
483 struct dc_transfer_func *in_transfer_func;
484 struct dc_bias_and_scale *bias_and_scale;
485 struct dc_csc_transform input_csc_color_matrix;
486 struct fixed31_32 coeff_reduction_factor;
487 uint32_t sdr_white_level;
489 // TODO: No longer used, remove
490 struct dc_hdr_static_metadata hdr_static_ctx;
492 enum dc_color_space color_space;
494 enum surface_pixel_format format;
495 enum dc_rotation_angle rotation;
496 enum plane_stereo_format stereo_format;
498 bool is_tiling_rotated;
499 bool per_pixel_alpha;
501 int global_alpha_value;
504 bool horizontal_mirror;
506 union surface_update_flags update_flags;
507 /* private to DC core */
508 struct dc_plane_status status;
509 struct dc_context *ctx;
511 /* private to dc_surface.c */
512 enum dc_irq_source irq_source;
513 struct kref refcount;
516 struct dc_plane_info {
517 union plane_size plane_size;
518 union dc_tiling_info tiling_info;
519 struct dc_plane_dcc_param dcc;
520 enum surface_pixel_format format;
521 enum dc_rotation_angle rotation;
522 enum plane_stereo_format stereo_format;
523 enum dc_color_space color_space;
524 unsigned int sdr_white_level;
525 bool horizontal_mirror;
527 bool per_pixel_alpha;
529 int global_alpha_value;
530 bool input_csc_enabled;
533 struct dc_scaling_info {
534 struct rect src_rect;
535 struct rect dst_rect;
536 struct rect clip_rect;
537 struct scaling_taps scaling_quality;
540 struct dc_surface_update {
541 struct dc_plane_state *surface;
543 /* isr safe update parameters. null means no updates */
544 const struct dc_flip_addrs *flip_addr;
545 const struct dc_plane_info *plane_info;
546 const struct dc_scaling_info *scaling_info;
548 /* following updates require alloc/sleep/spin that is not isr safe,
549 * null means no updates
551 const struct dc_gamma *gamma;
552 const struct dc_transfer_func *in_transfer_func;
554 const struct dc_csc_transform *input_csc_color_matrix;
555 const struct fixed31_32 *coeff_reduction_factor;
559 * Create a new surface with default parameters;
561 struct dc_plane_state *dc_create_plane_state(struct dc *dc);
562 const struct dc_plane_status *dc_plane_get_status(
563 const struct dc_plane_state *plane_state);
565 void dc_plane_state_retain(struct dc_plane_state *plane_state);
566 void dc_plane_state_release(struct dc_plane_state *plane_state);
568 void dc_gamma_retain(struct dc_gamma *dc_gamma);
569 void dc_gamma_release(struct dc_gamma **dc_gamma);
570 struct dc_gamma *dc_create_gamma(void);
572 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
573 void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
574 struct dc_transfer_func *dc_create_transfer_func(void);
577 * This structure holds a surface address. There could be multiple addresses
578 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such
579 * as frame durations and DCC format can also be set.
581 struct dc_flip_addrs {
582 struct dc_plane_address address;
583 unsigned int flip_timestamp_in_us;
585 /* TODO: add flip duration for FreeSync */
588 bool dc_post_update_surfaces_to_stream(
591 #include "dc_stream.h"
594 * Structure to store surface/stream associations for validation
596 struct dc_validation_set {
597 struct dc_stream_state *stream;
598 struct dc_plane_state *plane_states[MAX_SURFACES];
602 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
604 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
606 enum dc_status dc_validate_global_state(
608 struct dc_state *new_ctx);
611 void dc_resource_state_construct(
613 struct dc_state *dst_ctx);
615 void dc_resource_state_copy_construct(
616 const struct dc_state *src_ctx,
617 struct dc_state *dst_ctx);
619 void dc_resource_state_copy_construct_current(
621 struct dc_state *dst_ctx);
623 void dc_resource_state_destruct(struct dc_state *context);
626 * TODO update to make it about validation sets
627 * Set up streams and links associated to drive sinks
628 * The streams parameter is an absolute set of all active streams.
631 * Phy, Encoder, Timing Generator are programmed and enabled.
632 * New streams are enabled with blank stream; no memory read.
634 bool dc_commit_state(struct dc *dc, struct dc_state *context);
637 struct dc_state *dc_create_state(void);
638 void dc_retain_state(struct dc_state *context);
639 void dc_release_state(struct dc_state *context);
641 /*******************************************************************************
643 ******************************************************************************/
646 union dpcd_rev dpcd_rev;
647 union max_lane_count max_ln_count;
648 union max_down_spread max_down_spread;
650 /* dongle type (DP converter, CV smart dongle) */
651 enum display_dongle_type dongle_type;
652 /* Dongle's downstream count. */
653 union sink_count sink_count;
654 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
655 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
656 struct dc_dongle_caps dongle_caps;
658 uint32_t sink_dev_id;
659 int8_t sink_dev_id_str[6];
660 int8_t sink_hw_revision;
661 int8_t sink_fw_revision[2];
663 uint32_t branch_dev_id;
664 int8_t branch_dev_name[6];
665 int8_t branch_hw_revision;
666 int8_t branch_fw_revision[2];
668 bool allow_invalid_MSA_timing_param;
670 bool dpcd_display_control_capable;
675 /*******************************************************************************
676 * Sink Interfaces - A sink corresponds to a display output device
677 ******************************************************************************/
679 struct dc_container_id {
680 // 128bit GUID in binary form
681 unsigned char guid[16];
682 // 8 byte port ID -> ELD.PortID
683 unsigned int portId[2];
684 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
685 unsigned short manufacturerName;
686 // 2 byte product code -> ELD.ProductCode
687 unsigned short productCode;
693 * The sink structure contains EDID and other display device properties
696 enum signal_type sink_signal;
697 struct dc_edid dc_edid; /* raw edid */
698 struct dc_edid_caps edid_caps; /* parse display caps */
699 struct dc_container_id *dc_container_id;
700 uint32_t dongle_max_pix_clk;
702 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
703 bool converter_disable_audio;
705 /* private to DC core */
706 struct dc_link *link;
707 struct dc_context *ctx;
711 /* private to dc_sink.c */
712 // refcount must be the last member in dc_sink, since we want the
713 // sink structure to be logically cloneable up to (but not including)
715 struct kref refcount;
718 void dc_sink_retain(struct dc_sink *sink);
719 void dc_sink_release(struct dc_sink *sink);
721 struct dc_sink_init_data {
722 enum signal_type sink_signal;
723 struct dc_link *link;
724 uint32_t dongle_max_pix_clk;
725 bool converter_disable_audio;
728 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
730 /* Newer interfaces */
732 struct dc_plane_address address;
733 struct dc_cursor_attributes attributes;
737 /*******************************************************************************
738 * Interrupt interfaces
739 ******************************************************************************/
740 enum dc_irq_source dc_interrupt_to_irq_source(
744 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
745 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
746 enum dc_irq_source dc_get_hpd_irq_source_at_index(
747 struct dc *dc, uint32_t link_index);
749 /*******************************************************************************
751 ******************************************************************************/
753 void dc_set_power_state(
755 enum dc_acpi_cm_power_state power_state);
756 void dc_resume(struct dc *dc);
758 #endif /* DC_INTERFACE_H_ */