1 /* Copyright 2015 Advanced Micro Devices, Inc. */
2 #include "dm_services.h"
4 #include "dc_link_dp.h"
5 #include "dm_helpers.h"
8 #include "inc/core_types.h"
10 #include "dc_link_ddc.h"
11 #include "core_status.h"
12 #include "dpcd_defs.h"
18 /* maximum pre emphasis level allowed for each voltage swing level*/
19 static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
23 PRE_EMPHASIS_DISABLED };
26 POST_LT_ADJ_REQ_LIMIT = 6,
27 POST_LT_ADJ_REQ_TIMEOUT = 200
31 LINK_TRAINING_MAX_RETRY_COUNT = 5,
32 /* to avoid infinite loop where-in the receiver
33 * switches between different VS
35 LINK_TRAINING_MAX_CR_RETRY = 100
38 static bool decide_fallback_link_setting(
39 struct dc_link_settings initial_link_settings,
40 struct dc_link_settings *current_link_setting,
41 enum link_training_result training_result);
42 static struct dc_link_settings get_common_supported_link_settings(
43 struct dc_link_settings link_setting_a,
44 struct dc_link_settings link_setting_b);
46 static void wait_for_training_aux_rd_interval(
48 uint32_t default_wait_in_micro_secs)
50 union training_aux_rd_interval training_rd_interval;
52 /* overwrite the delay if rev > 1.1*/
53 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
54 /* DP 1.2 or later - retrieve delay through
55 * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
58 DP_TRAINING_AUX_RD_INTERVAL,
59 (uint8_t *)&training_rd_interval,
60 sizeof(training_rd_interval));
62 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
63 default_wait_in_micro_secs =
64 training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
67 udelay(default_wait_in_micro_secs);
69 DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
71 default_wait_in_micro_secs);
74 static void dpcd_set_training_pattern(
76 union dpcd_training_pattern dpcd_pattern)
80 DP_TRAINING_PATTERN_SET,
84 DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
86 DP_TRAINING_PATTERN_SET,
87 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
90 static void dpcd_set_link_settings(
92 const struct link_training_settings *lt_settings)
94 uint8_t rate = (uint8_t)
95 (lt_settings->link_settings.link_rate);
97 union down_spread_ctrl downspread = { {0} };
98 union lane_count_set lane_count_set = { {0} };
99 uint8_t link_set_buffer[2];
101 downspread.raw = (uint8_t)
102 (lt_settings->link_settings.link_spread);
104 lane_count_set.bits.LANE_COUNT_SET =
105 lt_settings->link_settings.lane_count;
107 lane_count_set.bits.ENHANCED_FRAMING = 1;
109 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
110 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
112 link_set_buffer[0] = rate;
113 link_set_buffer[1] = lane_count_set.raw;
115 core_link_write_dpcd(link, DP_LINK_BW_SET,
117 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
118 &downspread.raw, sizeof(downspread));
120 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x\n %x spread = %x\n",
123 lt_settings->link_settings.link_rate,
125 lt_settings->link_settings.lane_count,
127 lt_settings->link_settings.link_spread);
131 static enum dpcd_training_patterns
132 hw_training_pattern_to_dpcd_training_pattern(
133 struct dc_link *link,
134 enum hw_dp_training_pattern pattern)
136 enum dpcd_training_patterns dpcd_tr_pattern =
137 DPCD_TRAINING_PATTERN_VIDEOIDLE;
140 case HW_DP_TRAINING_PATTERN_1:
141 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
143 case HW_DP_TRAINING_PATTERN_2:
144 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
146 case HW_DP_TRAINING_PATTERN_3:
147 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
149 case HW_DP_TRAINING_PATTERN_4:
150 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
154 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
159 return dpcd_tr_pattern;
163 static void dpcd_set_lt_pattern_and_lane_settings(
164 struct dc_link *link,
165 const struct link_training_settings *lt_settings,
166 enum hw_dp_training_pattern pattern)
168 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
169 const uint32_t dpcd_base_lt_offset =
170 DP_TRAINING_PATTERN_SET;
171 uint8_t dpcd_lt_buffer[5] = {0};
172 union dpcd_training_pattern dpcd_pattern = { {0} };
174 uint32_t size_in_bytes;
175 bool edp_workaround = false; /* TODO link_prop.INTERNAL */
177 /*****************************************************************
178 * DpcdAddress_TrainingPatternSet
179 *****************************************************************/
180 dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
181 hw_training_pattern_to_dpcd_training_pattern(link, pattern);
183 dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - dpcd_base_lt_offset]
186 DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
188 DP_TRAINING_PATTERN_SET,
189 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
191 /*****************************************************************
192 * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
193 *****************************************************************/
194 for (lane = 0; lane <
195 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
197 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
198 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
199 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
200 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
202 dpcd_lane[lane].bits.MAX_SWING_REACHED =
203 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
204 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
205 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
206 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
207 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
210 /* concatinate everything into one buffer*/
212 size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
216 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - dpcd_base_lt_offset],
220 DC_LOG_HW_LINK_TRAINING("%s:\n %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
222 DP_TRAINING_LANE0_SET,
223 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
224 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
225 dpcd_lane[0].bits.MAX_SWING_REACHED,
226 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
228 if (edp_workaround) {
229 /* for eDP write in 2 parts because the 5-byte burst is
230 * causing issues on some eDP panels (EPR#366724)
232 core_link_write_dpcd(
234 DP_TRAINING_PATTERN_SET,
236 sizeof(dpcd_pattern.raw));
238 core_link_write_dpcd(
240 DP_TRAINING_LANE0_SET,
241 (uint8_t *)(dpcd_lane),
245 /* write it all in (1 + number-of-lanes)-byte burst*/
246 core_link_write_dpcd(
250 size_in_bytes + sizeof(dpcd_pattern.raw));
252 link->cur_lane_setting = lt_settings->lane_settings[0];
255 static bool is_cr_done(enum dc_lane_count ln_count,
256 union lane_status *dpcd_lane_status)
260 /*LANEx_CR_DONE bits All 1's?*/
261 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
262 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
269 static bool is_ch_eq_done(enum dc_lane_count ln_count,
270 union lane_status *dpcd_lane_status,
271 union lane_align_status_updated *lane_status_updated)
275 if (!lane_status_updated->bits.INTERLANE_ALIGN_DONE)
278 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
279 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0 ||
280 !dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
288 static void update_drive_settings(
289 struct link_training_settings *dest,
290 struct link_training_settings src)
293 for (lane = 0; lane < src.link_settings.lane_count; lane++) {
294 dest->lane_settings[lane].VOLTAGE_SWING =
295 src.lane_settings[lane].VOLTAGE_SWING;
296 dest->lane_settings[lane].PRE_EMPHASIS =
297 src.lane_settings[lane].PRE_EMPHASIS;
298 dest->lane_settings[lane].POST_CURSOR2 =
299 src.lane_settings[lane].POST_CURSOR2;
303 static uint8_t get_nibble_at_index(const uint8_t *buf,
307 nibble = buf[index / 2];
317 static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
318 enum dc_voltage_swing voltage)
320 enum dc_pre_emphasis pre_emphasis;
321 pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
323 if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
324 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
330 static void find_max_drive_settings(
331 const struct link_training_settings *link_training_setting,
332 struct link_training_settings *max_lt_setting)
335 struct dc_lane_settings max_requested;
337 max_requested.VOLTAGE_SWING =
338 link_training_setting->
339 lane_settings[0].VOLTAGE_SWING;
340 max_requested.PRE_EMPHASIS =
341 link_training_setting->
342 lane_settings[0].PRE_EMPHASIS;
343 /*max_requested.postCursor2 =
344 * link_training_setting->laneSettings[0].postCursor2;*/
346 /* Determine what the maximum of the requested settings are*/
347 for (lane = 1; lane < link_training_setting->link_settings.lane_count;
349 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
350 max_requested.VOLTAGE_SWING)
352 max_requested.VOLTAGE_SWING =
353 link_training_setting->
354 lane_settings[lane].VOLTAGE_SWING;
356 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
357 max_requested.PRE_EMPHASIS)
358 max_requested.PRE_EMPHASIS =
359 link_training_setting->
360 lane_settings[lane].PRE_EMPHASIS;
363 if (link_training_setting->laneSettings[lane].postCursor2 >
364 max_requested.postCursor2)
366 max_requested.postCursor2 =
367 link_training_setting->laneSettings[lane].postCursor2;
372 /* make sure the requested settings are
373 * not higher than maximum settings*/
374 if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
375 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
377 if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
378 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
380 if (max_requested.postCursor2 > PostCursor2_MaxLevel)
381 max_requested.postCursor2 = PostCursor2_MaxLevel;
384 /* make sure the pre-emphasis matches the voltage swing*/
385 if (max_requested.PRE_EMPHASIS >
386 get_max_pre_emphasis_for_voltage_swing(
387 max_requested.VOLTAGE_SWING))
388 max_requested.PRE_EMPHASIS =
389 get_max_pre_emphasis_for_voltage_swing(
390 max_requested.VOLTAGE_SWING);
393 * Post Cursor2 levels are completely independent from
394 * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
395 * can only be applied to each allowable combination of voltage
396 * swing and pre-emphasis levels */
397 /* if ( max_requested.postCursor2 >
398 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
399 * max_requested.postCursor2 =
400 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
403 max_lt_setting->link_settings.link_rate =
404 link_training_setting->link_settings.link_rate;
405 max_lt_setting->link_settings.lane_count =
406 link_training_setting->link_settings.lane_count;
407 max_lt_setting->link_settings.link_spread =
408 link_training_setting->link_settings.link_spread;
410 for (lane = 0; lane <
411 link_training_setting->link_settings.lane_count;
413 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
414 max_requested.VOLTAGE_SWING;
415 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
416 max_requested.PRE_EMPHASIS;
417 /*max_lt_setting->laneSettings[lane].postCursor2 =
418 * max_requested.postCursor2;
424 static void get_lane_status_and_drive_settings(
425 struct dc_link *link,
426 const struct link_training_settings *link_training_setting,
427 union lane_status *ln_status,
428 union lane_align_status_updated *ln_status_updated,
429 struct link_training_settings *req_settings)
431 uint8_t dpcd_buf[6] = {0};
432 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
433 struct link_training_settings request_settings = { {0} };
436 memset(req_settings, '\0', sizeof(struct link_training_settings));
441 (uint8_t *)(dpcd_buf),
444 for (lane = 0; lane <
445 (uint32_t)(link_training_setting->link_settings.lane_count);
448 ln_status[lane].raw =
449 get_nibble_at_index(&dpcd_buf[0], lane);
450 dpcd_lane_adjust[lane].raw =
451 get_nibble_at_index(&dpcd_buf[4], lane);
454 ln_status_updated->raw = dpcd_buf[2];
456 DC_LOG_HW_LINK_TRAINING("%s:\n%x Lane01Status = %x\n %x Lane23Status = %x\n ",
458 DP_LANE0_1_STATUS, dpcd_buf[0],
459 DP_LANE2_3_STATUS, dpcd_buf[1]);
461 DC_LOG_HW_LINK_TRAINING("%s:\n %x Lane01AdjustRequest = %x\n %x Lane23AdjustRequest = %x\n",
463 DP_ADJUST_REQUEST_LANE0_1,
465 DP_ADJUST_REQUEST_LANE2_3,
468 /*copy to req_settings*/
469 request_settings.link_settings.lane_count =
470 link_training_setting->link_settings.lane_count;
471 request_settings.link_settings.link_rate =
472 link_training_setting->link_settings.link_rate;
473 request_settings.link_settings.link_spread =
474 link_training_setting->link_settings.link_spread;
476 for (lane = 0; lane <
477 (uint32_t)(link_training_setting->link_settings.lane_count);
480 request_settings.lane_settings[lane].VOLTAGE_SWING =
481 (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
483 request_settings.lane_settings[lane].PRE_EMPHASIS =
484 (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
488 /*Note: for postcursor2, read adjusted
489 * postcursor2 settings from*/
490 /*DpcdAddress_AdjustRequestPostCursor2 =
491 *0x020C (not implemented yet)*/
493 /* we find the maximum of the requested settings across all lanes*/
494 /* and set this maximum for all lanes*/
495 find_max_drive_settings(&request_settings, req_settings);
497 /* if post cursor 2 is needed in the future,
498 * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
503 static void dpcd_set_lane_settings(
504 struct dc_link *link,
505 const struct link_training_settings *link_training_setting)
507 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
510 for (lane = 0; lane <
511 (uint32_t)(link_training_setting->
512 link_settings.lane_count);
514 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
515 (uint8_t)(link_training_setting->
516 lane_settings[lane].VOLTAGE_SWING);
517 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
518 (uint8_t)(link_training_setting->
519 lane_settings[lane].PRE_EMPHASIS);
520 dpcd_lane[lane].bits.MAX_SWING_REACHED =
521 (link_training_setting->
522 lane_settings[lane].VOLTAGE_SWING ==
523 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
524 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
525 (link_training_setting->
526 lane_settings[lane].PRE_EMPHASIS ==
527 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
530 core_link_write_dpcd(link,
531 DP_TRAINING_LANE0_SET,
532 (uint8_t *)(dpcd_lane),
533 link_training_setting->link_settings.lane_count);
536 if (LTSettings.link.rate == LinkRate_High2)
538 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
539 for ( uint32_t lane = 0;
540 lane < lane_count_DPMax; lane++)
542 dpcd_lane2[lane].bits.post_cursor2_set =
543 static_cast<unsigned char>(
544 LTSettings.laneSettings[lane].postCursor2);
545 dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
547 m_pDpcdAccessSrv->WriteDpcdData(
548 DpcdAddress_Lane0Set2,
549 reinterpret_cast<unsigned char*>(dpcd_lane2),
550 LTSettings.link.lanes);
554 DC_LOG_HW_LINK_TRAINING("%s\n %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
556 DP_TRAINING_LANE0_SET,
557 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
558 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
559 dpcd_lane[0].bits.MAX_SWING_REACHED,
560 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
562 link->cur_lane_setting = link_training_setting->lane_settings[0];
566 static bool is_max_vs_reached(
567 const struct link_training_settings *lt_settings)
570 for (lane = 0; lane <
571 (uint32_t)(lt_settings->link_settings.lane_count);
573 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
574 == VOLTAGE_SWING_MAX_LEVEL)
581 void dc_link_dp_set_drive_settings(
582 struct dc_link *link,
583 struct link_training_settings *lt_settings)
585 /* program ASIC PHY settings*/
586 dp_set_hw_lane_settings(link, lt_settings);
588 /* Notify DP sink the PHY settings from source */
589 dpcd_set_lane_settings(link, lt_settings);
592 static bool perform_post_lt_adj_req_sequence(
593 struct dc_link *link,
594 struct link_training_settings *lt_settings)
596 enum dc_lane_count lane_count =
597 lt_settings->link_settings.lane_count;
599 uint32_t adj_req_count;
600 uint32_t adj_req_timer;
601 bool req_drv_setting_changed;
604 req_drv_setting_changed = false;
605 for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
608 req_drv_setting_changed = false;
610 for (adj_req_timer = 0;
611 adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
614 struct link_training_settings req_settings;
615 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
616 union lane_align_status_updated
617 dpcd_lane_status_updated;
619 get_lane_status_and_drive_settings(
623 &dpcd_lane_status_updated,
626 if (dpcd_lane_status_updated.bits.
627 POST_LT_ADJ_REQ_IN_PROGRESS == 0)
630 if (!is_cr_done(lane_count, dpcd_lane_status))
636 &dpcd_lane_status_updated))
639 for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
642 lane_settings[lane].VOLTAGE_SWING !=
643 req_settings.lane_settings[lane].
645 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
646 req_settings.lane_settings[lane].PRE_EMPHASIS) {
648 req_drv_setting_changed = true;
653 if (req_drv_setting_changed) {
654 update_drive_settings(
655 lt_settings, req_settings);
657 dc_link_dp_set_drive_settings(link,
665 if (!req_drv_setting_changed) {
666 DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
673 DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
681 static enum hw_dp_training_pattern get_supported_tp(struct dc_link *link)
683 enum hw_dp_training_pattern highest_tp = HW_DP_TRAINING_PATTERN_2;
684 struct encoder_feature_support *features = &link->link_enc->features;
685 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
687 if (features->flags.bits.IS_TPS3_CAPABLE)
688 highest_tp = HW_DP_TRAINING_PATTERN_3;
690 if (features->flags.bits.IS_TPS4_CAPABLE)
691 highest_tp = HW_DP_TRAINING_PATTERN_4;
693 if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
694 highest_tp >= HW_DP_TRAINING_PATTERN_4)
695 return HW_DP_TRAINING_PATTERN_4;
697 if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
698 highest_tp >= HW_DP_TRAINING_PATTERN_3)
699 return HW_DP_TRAINING_PATTERN_3;
701 return HW_DP_TRAINING_PATTERN_2;
704 static enum link_training_result get_cr_failure(enum dc_lane_count ln_count,
705 union lane_status *dpcd_lane_status)
707 enum link_training_result result = LINK_TRAINING_SUCCESS;
709 if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
710 result = LINK_TRAINING_CR_FAIL_LANE0;
711 else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
712 result = LINK_TRAINING_CR_FAIL_LANE1;
713 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
714 result = LINK_TRAINING_CR_FAIL_LANE23;
715 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
716 result = LINK_TRAINING_CR_FAIL_LANE23;
720 static enum link_training_result perform_channel_equalization_sequence(
721 struct dc_link *link,
722 struct link_training_settings *lt_settings)
724 struct link_training_settings req_settings;
725 enum hw_dp_training_pattern hw_tr_pattern;
726 uint32_t retries_ch_eq;
727 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
728 union lane_align_status_updated dpcd_lane_status_updated = { {0} };
729 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
731 hw_tr_pattern = get_supported_tp(link);
733 dp_set_hw_training_pattern(link, hw_tr_pattern);
735 for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
738 dp_set_hw_lane_settings(link, lt_settings);
742 /* EPR #361076 - write as a 5-byte burst,
743 * but only for the 1-st iteration*/
744 dpcd_set_lt_pattern_and_lane_settings(
749 dpcd_set_lane_settings(link, lt_settings);
751 /* 3. wait for receiver to lock-on*/
752 wait_for_training_aux_rd_interval(link, 400);
754 /* 4. Read lane status and requested
755 * drive settings as set by the sink*/
757 get_lane_status_and_drive_settings(
761 &dpcd_lane_status_updated,
764 /* 5. check CR done*/
765 if (!is_cr_done(lane_count, dpcd_lane_status))
766 return LINK_TRAINING_EQ_FAIL_CR;
768 /* 6. check CHEQ done*/
769 if (is_ch_eq_done(lane_count,
771 &dpcd_lane_status_updated))
772 return LINK_TRAINING_SUCCESS;
774 /* 7. update VS/PE/PC2 in lt_settings*/
775 update_drive_settings(lt_settings, req_settings);
778 return LINK_TRAINING_EQ_FAIL_EQ;
782 static enum link_training_result perform_clock_recovery_sequence(
783 struct dc_link *link,
784 struct link_training_settings *lt_settings)
787 uint32_t retry_count;
789 struct link_training_settings req_settings;
790 enum dc_lane_count lane_count =
791 lt_settings->link_settings.lane_count;
792 enum hw_dp_training_pattern hw_tr_pattern = HW_DP_TRAINING_PATTERN_1;
793 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
794 union lane_align_status_updated dpcd_lane_status_updated;
798 /* initial drive setting (VS/PE/PC2)*/
799 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
800 lt_settings->lane_settings[lane].VOLTAGE_SWING =
801 VOLTAGE_SWING_LEVEL0;
802 lt_settings->lane_settings[lane].PRE_EMPHASIS =
803 PRE_EMPHASIS_DISABLED;
804 lt_settings->lane_settings[lane].POST_CURSOR2 =
805 POST_CURSOR2_DISABLED;
808 dp_set_hw_training_pattern(link, hw_tr_pattern);
810 /* najeeb - The synaptics MST hub can put the LT in
811 * infinite loop by switching the VS
813 /* between level 0 and level 1 continuously, here
814 * we try for CR lock for LinkTrainingMaxCRRetry count*/
815 while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
816 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
818 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
819 memset(&dpcd_lane_status_updated, '\0',
820 sizeof(dpcd_lane_status_updated));
822 /* 1. call HWSS to set lane settings*/
823 dp_set_hw_lane_settings(
827 /* 2. update DPCD of the receiver*/
829 /* EPR #361076 - write as a 5-byte burst,
830 * but only for the 1-st iteration.*/
831 dpcd_set_lt_pattern_and_lane_settings(
836 dpcd_set_lane_settings(
840 /* 3. wait receiver to lock-on*/
841 wait_for_training_aux_rd_interval(
845 /* 4. Read lane status and requested drive
846 * settings as set by the sink
848 get_lane_status_and_drive_settings(
852 &dpcd_lane_status_updated,
855 /* 5. check CR done*/
856 if (is_cr_done(lane_count, dpcd_lane_status))
857 return LINK_TRAINING_SUCCESS;
859 /* 6. max VS reached*/
860 if (is_max_vs_reached(lt_settings))
864 /* Note: VS same for all lanes,
865 * so comparing first lane is sufficient*/
866 if (lt_settings->lane_settings[0].VOLTAGE_SWING ==
867 req_settings.lane_settings[0].VOLTAGE_SWING)
872 /* 8. update VS/PE/PC2 in lt_settings*/
873 update_drive_settings(lt_settings, req_settings);
878 if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
880 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
882 LINK_TRAINING_MAX_CR_RETRY);
886 return get_cr_failure(lane_count, dpcd_lane_status);
889 static inline enum link_training_result perform_link_training_int(
890 struct dc_link *link,
891 struct link_training_settings *lt_settings,
892 enum link_training_result status)
894 union lane_count_set lane_count_set = { {0} };
895 union dpcd_training_pattern dpcd_pattern = { {0} };
897 /* 3. set training not in progress*/
898 dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
899 dpcd_set_training_pattern(link, dpcd_pattern);
901 /* 4. mainlink output idle pattern*/
902 dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
905 * 5. post training adjust if required
906 * If the upstream DPTX and downstream DPRX both support TPS4,
907 * TPS4 must be used instead of POST_LT_ADJ_REQ.
909 if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
910 get_supported_tp(link) == HW_DP_TRAINING_PATTERN_4)
913 if (status == LINK_TRAINING_SUCCESS &&
914 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
915 status = LINK_TRAINING_LQA_FAIL;
917 lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
918 lane_count_set.bits.ENHANCED_FRAMING = 1;
919 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
921 core_link_write_dpcd(
925 sizeof(lane_count_set));
930 enum link_training_result dc_link_dp_perform_link_training(
931 struct dc_link *link,
932 const struct dc_link_settings *link_setting,
933 bool skip_video_pattern)
935 enum link_training_result status = LINK_TRAINING_SUCCESS;
937 char *link_rate = "Unknown";
938 char *lt_result = "Unknown";
940 struct link_training_settings lt_settings;
942 memset(<_settings, '\0', sizeof(lt_settings));
944 lt_settings.link_settings.link_rate = link_setting->link_rate;
945 lt_settings.link_settings.lane_count = link_setting->lane_count;
947 /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
949 /* TODO hard coded to SS for now
950 * lt_settings.link_settings.link_spread =
951 * dal_display_path_is_ss_supported(
952 * path_mode->display_path) ?
953 * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
954 * LINK_SPREAD_DISABLED;
957 lt_settings.link_settings.link_spread = LINK_SPREAD_DISABLED;
959 lt_settings.link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
961 /* 1. set link rate, lane count and spread*/
962 dpcd_set_link_settings(link, <_settings);
964 /* 2. perform link training (set link training done
965 * to false is done as well)*/
966 status = perform_clock_recovery_sequence(link, <_settings);
967 if (status == LINK_TRAINING_SUCCESS) {
968 status = perform_channel_equalization_sequence(link,
972 if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
973 status = perform_link_training_int(link,
978 /* 6. print status message*/
979 switch (lt_settings.link_settings.link_rate) {
987 case LINK_RATE_HIGH2:
993 case LINK_RATE_HIGH3:
1001 case LINK_TRAINING_SUCCESS:
1004 case LINK_TRAINING_CR_FAIL_LANE0:
1005 lt_result = "CR failed lane0";
1007 case LINK_TRAINING_CR_FAIL_LANE1:
1008 lt_result = "CR failed lane1";
1010 case LINK_TRAINING_CR_FAIL_LANE23:
1011 lt_result = "CR failed lane23";
1013 case LINK_TRAINING_EQ_FAIL_CR:
1014 lt_result = "CR failed in EQ";
1016 case LINK_TRAINING_EQ_FAIL_EQ:
1017 lt_result = "EQ failed";
1019 case LINK_TRAINING_LQA_FAIL:
1020 lt_result = "LQA failed";
1026 /* Connectivity log: link training */
1027 CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d",
1029 lt_settings.link_settings.lane_count,
1031 lt_settings.lane_settings[0].VOLTAGE_SWING,
1032 lt_settings.lane_settings[0].PRE_EMPHASIS);
1034 if (status != LINK_TRAINING_SUCCESS)
1035 link->ctx->dc->debug_data.ltFailCount++;
1041 bool perform_link_training_with_retries(
1042 struct dc_link *link,
1043 const struct dc_link_settings *link_setting,
1044 bool skip_video_pattern,
1048 uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1050 for (j = 0; j < attempts; ++j) {
1052 if (dc_link_dp_perform_link_training(
1055 skip_video_pattern) == LINK_TRAINING_SUCCESS)
1058 msleep(delay_between_attempts);
1059 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1065 static struct dc_link_settings get_max_link_cap(struct dc_link *link)
1067 /* Set Default link settings */
1068 struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,
1069 LINK_SPREAD_05_DOWNSPREAD_30KHZ};
1071 /* Higher link settings based on feature supported */
1072 if (link->link_enc->features.flags.bits.IS_HBR2_CAPABLE)
1073 max_link_cap.link_rate = LINK_RATE_HIGH2;
1075 if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
1076 max_link_cap.link_rate = LINK_RATE_HIGH3;
1078 /* Lower link settings based on sink's link cap */
1079 if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
1080 max_link_cap.lane_count =
1081 link->reported_link_cap.lane_count;
1082 if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
1083 max_link_cap.link_rate =
1084 link->reported_link_cap.link_rate;
1085 if (link->reported_link_cap.link_spread <
1086 max_link_cap.link_spread)
1087 max_link_cap.link_spread =
1088 link->reported_link_cap.link_spread;
1089 return max_link_cap;
1092 static enum dc_status read_hpd_rx_irq_data(
1093 struct dc_link *link,
1094 union hpd_irq_data *irq_data)
1096 static enum dc_status retval;
1098 /* The HW reads 16 bytes from 200h on HPD,
1099 * but if we get an AUX_DEFER, the HW cannot retry
1100 * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
1101 * fail, so we now explicitly read 6 bytes which is
1102 * the req from the above mentioned test cases.
1104 * For DP 1.4 we need to read those from 2002h range.
1106 if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
1107 retval = core_link_read_dpcd(
1111 sizeof(union hpd_irq_data));
1113 /* Read 14 bytes in a single read and then copy only the required fields.
1114 * This is more efficient than doing it in two separate AUX reads. */
1116 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
1118 retval = core_link_read_dpcd(
1124 if (retval != DC_OK)
1127 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
1128 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
1129 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
1130 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
1131 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
1132 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
1138 static bool hpd_rx_irq_check_link_loss_status(
1139 struct dc_link *link,
1140 union hpd_irq_data *hpd_irq_dpcd_data)
1142 uint8_t irq_reg_rx_power_state = 0;
1143 enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
1144 union lane_status lane_status;
1146 bool sink_status_changed;
1149 sink_status_changed = false;
1150 return_code = false;
1152 if (link->cur_link_settings.lane_count == 0)
1155 /*1. Check that Link Status changed, before re-training.*/
1157 /*parse lane status*/
1158 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1159 /* check status of lanes 0,1
1160 * changed DpcdAddress_Lane01Status (0x202)
1162 lane_status.raw = get_nibble_at_index(
1163 &hpd_irq_dpcd_data->bytes.lane01_status.raw,
1166 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1167 !lane_status.bits.CR_DONE_0 ||
1168 !lane_status.bits.SYMBOL_LOCKED_0) {
1169 /* if one of the channel equalization, clock
1170 * recovery or symbol lock is dropped
1171 * consider it as (link has been
1172 * dropped) dp sink status has changed
1174 sink_status_changed = true;
1179 /* Check interlane align.*/
1180 if (sink_status_changed ||
1181 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
1183 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
1187 /*2. Check that we can handle interrupt: Not in FS DOS,
1188 * Not in "Display Timeout" state, Link is trained.
1190 dpcd_result = core_link_read_dpcd(link,
1192 &irq_reg_rx_power_state,
1193 sizeof(irq_reg_rx_power_state));
1195 if (dpcd_result != DC_OK) {
1196 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
1199 if (irq_reg_rx_power_state != DP_SET_POWER_D0)
1200 return_code = false;
1207 bool dp_verify_link_cap(
1208 struct dc_link *link,
1209 struct dc_link_settings *known_limit_link_setting,
1212 struct dc_link_settings max_link_cap = {0};
1213 struct dc_link_settings cur_link_setting = {0};
1214 struct dc_link_settings *cur = &cur_link_setting;
1215 struct dc_link_settings initial_link_settings = {0};
1217 bool skip_link_training;
1218 bool skip_video_pattern;
1219 struct clock_source *dp_cs;
1220 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
1221 enum link_training_result status;
1222 union hpd_irq_data irq_data;
1224 if (link->dc->debug.skip_detection_link_training) {
1225 link->verified_link_cap = *known_limit_link_setting;
1229 memset(&irq_data, 0, sizeof(irq_data));
1231 skip_link_training = false;
1233 max_link_cap = get_max_link_cap(link);
1235 /* TODO implement override and monitor patch later */
1237 /* try to train the link from high to low to
1238 * find the physical link capability
1240 /* disable PHY done possible by BIOS, will be done by driver itself */
1241 dp_disable_link_phy(link, link->connector_signal);
1243 dp_cs = link->dc->res_pool->dp_clock_source;
1246 dp_cs_id = dp_cs->id;
1249 * dp clock source is not initialized for some reason.
1250 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1255 /* link training starts with the maximum common settings
1256 * supported by both sink and ASIC.
1258 initial_link_settings = get_common_supported_link_settings(
1259 *known_limit_link_setting,
1261 cur_link_setting = initial_link_settings;
1263 skip_video_pattern = true;
1265 if (cur->link_rate == LINK_RATE_LOW)
1266 skip_video_pattern = false;
1270 link->connector_signal,
1275 if (skip_link_training)
1278 status = dc_link_dp_perform_link_training(
1281 skip_video_pattern);
1282 if (status == LINK_TRAINING_SUCCESS)
1289 link->verified_link_cap = *cur;
1291 if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK)
1292 if (hpd_rx_irq_check_link_loss_status(
1297 /* always disable the link before trying another
1298 * setting or before returning we'll enable it later
1299 * based on the actual mode we're driving
1301 dp_disable_link_phy(link, link->connector_signal);
1302 } while (!success && decide_fallback_link_setting(
1303 initial_link_settings, cur, status));
1305 /* Link Training failed for all Link Settings
1306 * (Lane Count is still unknown)
1309 /* If all LT fails for all settings,
1310 * set verified = failed safe (1 lane low)
1312 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
1313 link->verified_link_cap.link_rate = LINK_RATE_LOW;
1315 link->verified_link_cap.link_spread =
1316 LINK_SPREAD_DISABLED;
1323 static struct dc_link_settings get_common_supported_link_settings(
1324 struct dc_link_settings link_setting_a,
1325 struct dc_link_settings link_setting_b)
1327 struct dc_link_settings link_settings = {0};
1329 link_settings.lane_count =
1330 (link_setting_a.lane_count <=
1331 link_setting_b.lane_count) ?
1332 link_setting_a.lane_count :
1333 link_setting_b.lane_count;
1334 link_settings.link_rate =
1335 (link_setting_a.link_rate <=
1336 link_setting_b.link_rate) ?
1337 link_setting_a.link_rate :
1338 link_setting_b.link_rate;
1339 link_settings.link_spread = LINK_SPREAD_DISABLED;
1341 /* in DP compliance test, DPR-120 may have
1342 * a random value in its MAX_LINK_BW dpcd field.
1343 * We map it to the maximum supported link rate that
1344 * is smaller than MAX_LINK_BW in this case.
1346 if (link_settings.link_rate > LINK_RATE_HIGH3) {
1347 link_settings.link_rate = LINK_RATE_HIGH3;
1348 } else if (link_settings.link_rate < LINK_RATE_HIGH3
1349 && link_settings.link_rate > LINK_RATE_HIGH2) {
1350 link_settings.link_rate = LINK_RATE_HIGH2;
1351 } else if (link_settings.link_rate < LINK_RATE_HIGH2
1352 && link_settings.link_rate > LINK_RATE_HIGH) {
1353 link_settings.link_rate = LINK_RATE_HIGH;
1354 } else if (link_settings.link_rate < LINK_RATE_HIGH
1355 && link_settings.link_rate > LINK_RATE_LOW) {
1356 link_settings.link_rate = LINK_RATE_LOW;
1357 } else if (link_settings.link_rate < LINK_RATE_LOW) {
1358 link_settings.link_rate = LINK_RATE_UNKNOWN;
1361 return link_settings;
1364 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
1366 return lane_count <= LANE_COUNT_ONE;
1369 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
1371 return link_rate <= LINK_RATE_LOW;
1374 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
1376 switch (lane_count) {
1377 case LANE_COUNT_FOUR:
1378 return LANE_COUNT_TWO;
1379 case LANE_COUNT_TWO:
1380 return LANE_COUNT_ONE;
1381 case LANE_COUNT_ONE:
1382 return LANE_COUNT_UNKNOWN;
1384 return LANE_COUNT_UNKNOWN;
1388 static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
1390 switch (link_rate) {
1391 case LINK_RATE_HIGH3:
1392 return LINK_RATE_HIGH2;
1393 case LINK_RATE_HIGH2:
1394 return LINK_RATE_HIGH;
1395 case LINK_RATE_HIGH:
1396 return LINK_RATE_LOW;
1398 return LINK_RATE_UNKNOWN;
1400 return LINK_RATE_UNKNOWN;
1404 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
1406 switch (lane_count) {
1407 case LANE_COUNT_ONE:
1408 return LANE_COUNT_TWO;
1409 case LANE_COUNT_TWO:
1410 return LANE_COUNT_FOUR;
1412 return LANE_COUNT_UNKNOWN;
1416 static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
1418 switch (link_rate) {
1420 return LINK_RATE_HIGH;
1421 case LINK_RATE_HIGH:
1422 return LINK_RATE_HIGH2;
1423 case LINK_RATE_HIGH2:
1424 return LINK_RATE_HIGH3;
1426 return LINK_RATE_UNKNOWN;
1431 * function: set link rate and lane count fallback based
1432 * on current link setting and last link training result
1434 * true - link setting could be set
1435 * false - has reached minimum setting
1436 * and no further fallback could be done
1438 static bool decide_fallback_link_setting(
1439 struct dc_link_settings initial_link_settings,
1440 struct dc_link_settings *current_link_setting,
1441 enum link_training_result training_result)
1443 if (!current_link_setting)
1446 switch (training_result) {
1447 case LINK_TRAINING_CR_FAIL_LANE0:
1448 case LINK_TRAINING_CR_FAIL_LANE1:
1449 case LINK_TRAINING_CR_FAIL_LANE23:
1450 case LINK_TRAINING_LQA_FAIL:
1452 if (!reached_minimum_link_rate
1453 (current_link_setting->link_rate)) {
1454 current_link_setting->link_rate =
1456 current_link_setting->link_rate);
1457 } else if (!reached_minimum_lane_count
1458 (current_link_setting->lane_count)) {
1459 current_link_setting->link_rate =
1460 initial_link_settings.link_rate;
1461 if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
1463 else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
1464 current_link_setting->lane_count =
1466 else if (training_result ==
1467 LINK_TRAINING_CR_FAIL_LANE23)
1468 current_link_setting->lane_count =
1471 current_link_setting->lane_count =
1473 current_link_setting->lane_count);
1479 case LINK_TRAINING_EQ_FAIL_EQ:
1481 if (!reached_minimum_lane_count
1482 (current_link_setting->lane_count)) {
1483 current_link_setting->lane_count =
1485 current_link_setting->lane_count);
1486 } else if (!reached_minimum_link_rate
1487 (current_link_setting->link_rate)) {
1488 current_link_setting->link_rate =
1490 current_link_setting->link_rate);
1496 case LINK_TRAINING_EQ_FAIL_CR:
1498 if (!reached_minimum_link_rate
1499 (current_link_setting->link_rate)) {
1500 current_link_setting->link_rate =
1502 current_link_setting->link_rate);
1514 static uint32_t bandwidth_in_kbps_from_timing(
1515 const struct dc_crtc_timing *timing)
1517 uint32_t bits_per_channel = 0;
1520 switch (timing->display_color_depth) {
1521 case COLOR_DEPTH_666:
1522 bits_per_channel = 6;
1524 case COLOR_DEPTH_888:
1525 bits_per_channel = 8;
1527 case COLOR_DEPTH_101010:
1528 bits_per_channel = 10;
1530 case COLOR_DEPTH_121212:
1531 bits_per_channel = 12;
1533 case COLOR_DEPTH_141414:
1534 bits_per_channel = 14;
1536 case COLOR_DEPTH_161616:
1537 bits_per_channel = 16;
1543 ASSERT(bits_per_channel != 0);
1545 kbps = timing->pix_clk_khz;
1546 kbps *= bits_per_channel;
1548 if (timing->flags.Y_ONLY != 1) {
1549 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
1551 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1553 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
1554 kbps = kbps * 2 / 3;
1561 static uint32_t bandwidth_in_kbps_from_link_settings(
1562 const struct dc_link_settings *link_setting)
1564 uint32_t link_rate_in_kbps = link_setting->link_rate *
1565 LINK_RATE_REF_FREQ_IN_KHZ;
1567 uint32_t lane_count = link_setting->lane_count;
1568 uint32_t kbps = link_rate_in_kbps;
1571 kbps *= 8; /* 8 bits per byte*/
1577 bool dp_validate_mode_timing(
1578 struct dc_link *link,
1579 const struct dc_crtc_timing *timing)
1584 const struct dc_link_settings *link_setting;
1586 /*always DP fail safe mode*/
1587 if (timing->pix_clk_khz == (uint32_t) 25175 &&
1588 timing->h_addressable == (uint32_t) 640 &&
1589 timing->v_addressable == (uint32_t) 480)
1592 /* We always use verified link settings */
1593 link_setting = &link->verified_link_cap;
1595 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
1596 /*if (flags.DYNAMIC_VALIDATION == 1 &&
1597 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
1598 link_setting = &link->verified_link_cap;
1601 req_bw = bandwidth_in_kbps_from_timing(timing);
1602 max_bw = bandwidth_in_kbps_from_link_settings(link_setting);
1604 if (req_bw <= max_bw) {
1605 /* remember the biggest mode here, during
1606 * initial link training (to get
1607 * verified_link_cap), LS sends event about
1608 * cannot train at reported cap to upper
1609 * layer and upper layer will re-enumerate modes.
1610 * this is not necessary if the lower
1611 * verified_link_cap is enough to drive
1614 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
1615 /* if (flags.DYNAMIC_VALIDATION == 1)
1616 dpsst->max_req_bw_for_verified_linkcap = dal_max(
1617 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
1623 void decide_link_settings(struct dc_stream_state *stream,
1624 struct dc_link_settings *link_setting)
1627 struct dc_link_settings initial_link_setting = {
1628 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED};
1629 struct dc_link_settings current_link_setting =
1630 initial_link_setting;
1631 struct dc_link *link;
1635 req_bw = bandwidth_in_kbps_from_timing(&stream->timing);
1637 link = stream->sink->link;
1639 /* if preferred is specified through AMDDP, use it, if it's enough
1642 if (link->preferred_link_setting.lane_count !=
1643 LANE_COUNT_UNKNOWN &&
1644 link->preferred_link_setting.link_rate !=
1645 LINK_RATE_UNKNOWN) {
1646 *link_setting = link->preferred_link_setting;
1650 /* MST doesn't perform link training for now
1651 * TODO: add MST specific link training routine
1653 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1654 *link_setting = link->verified_link_cap;
1658 /* EDP use the link cap setting */
1659 if (stream->sink->sink_signal == SIGNAL_TYPE_EDP) {
1660 *link_setting = link->verified_link_cap;
1664 /* search for the minimum link setting that:
1665 * 1. is supported according to the link training result
1666 * 2. could support the b/w requested by the timing
1668 while (current_link_setting.link_rate <=
1669 link->verified_link_cap.link_rate) {
1670 link_bw = bandwidth_in_kbps_from_link_settings(
1671 ¤t_link_setting);
1672 if (req_bw <= link_bw) {
1673 *link_setting = current_link_setting;
1677 if (current_link_setting.lane_count <
1678 link->verified_link_cap.lane_count) {
1679 current_link_setting.lane_count =
1680 increase_lane_count(
1681 current_link_setting.lane_count);
1683 current_link_setting.link_rate =
1685 current_link_setting.link_rate);
1686 current_link_setting.lane_count =
1687 initial_link_setting.lane_count;
1691 BREAK_TO_DEBUGGER();
1692 ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
1694 *link_setting = link->verified_link_cap;
1697 /*************************Short Pulse IRQ***************************/
1698 static bool allow_hpd_rx_irq(const struct dc_link *link)
1701 * Don't handle RX IRQ unless one of following is met:
1702 * 1) The link is established (cur_link_settings != unknown)
1703 * 2) We kicked off MST detection
1704 * 3) We know we're dealing with an active dongle
1707 if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1708 (link->type == dc_connection_mst_branch) ||
1709 is_dp_active_dongle(link))
1715 static bool handle_hpd_irq_psr_sink(const struct dc_link *link)
1717 union dpcd_psr_configuration psr_configuration;
1719 if (!link->psr_enabled)
1722 dm_helpers_dp_read_dpcd(
1725 368,/*DpcdAddress_PSR_Enable_Cfg*/
1726 &psr_configuration.raw,
1727 sizeof(psr_configuration.raw));
1730 if (psr_configuration.bits.ENABLE) {
1731 unsigned char dpcdbuf[3] = {0};
1732 union psr_error_status psr_error_status;
1733 union psr_sink_psr_status psr_sink_psr_status;
1735 dm_helpers_dp_read_dpcd(
1738 0x2006, /*DpcdAddress_PSR_Error_Status*/
1739 (unsigned char *) dpcdbuf,
1742 /*DPCD 2006h ERROR STATUS*/
1743 psr_error_status.raw = dpcdbuf[0];
1744 /*DPCD 2008h SINK PANEL SELF REFRESH STATUS*/
1745 psr_sink_psr_status.raw = dpcdbuf[2];
1747 if (psr_error_status.bits.LINK_CRC_ERROR ||
1748 psr_error_status.bits.RFB_STORAGE_ERROR) {
1749 /* Acknowledge and clear error bits */
1750 dm_helpers_dp_write_dpcd(
1753 8198,/*DpcdAddress_PSR_Error_Status*/
1754 &psr_error_status.raw,
1755 sizeof(psr_error_status.raw));
1757 /* PSR error, disable and re-enable PSR */
1758 dc_link_set_psr_enable(link, false, true);
1759 dc_link_set_psr_enable(link, true, true);
1762 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
1763 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
1764 /* No error is detect, PSR is active.
1765 * We should return with IRQ_HPD handled without
1766 * checking for loss of sync since PSR would have
1767 * powered down main link.
1775 static void dp_test_send_link_training(struct dc_link *link)
1777 struct dc_link_settings link_settings = {0};
1779 core_link_read_dpcd(
1782 (unsigned char *)(&link_settings.lane_count),
1784 core_link_read_dpcd(
1787 (unsigned char *)(&link_settings.link_rate),
1790 /* Set preferred link settings */
1791 link->verified_link_cap.lane_count = link_settings.lane_count;
1792 link->verified_link_cap.link_rate = link_settings.link_rate;
1794 dp_retrain_link_dp_test(link, &link_settings, false);
1797 /* TODO Raven hbr2 compliance eye output is unstable
1798 * (toggling on and off) with debugger break
1799 * This caueses intermittent PHY automation failure
1800 * Need to look into the root cause */
1801 static void dp_test_send_phy_test_pattern(struct dc_link *link)
1803 union phy_test_pattern dpcd_test_pattern;
1804 union lane_adjust dpcd_lane_adjustment[2];
1805 unsigned char dpcd_post_cursor_2_adjustment = 0;
1806 unsigned char test_80_bit_pattern[
1807 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
1808 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
1809 enum dp_test_pattern test_pattern;
1810 struct dc_link_training_settings link_settings;
1811 union lane_adjust dpcd_lane_adjust;
1813 struct link_training_settings link_training_settings;
1816 dpcd_test_pattern.raw = 0;
1817 memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
1818 memset(&link_settings, 0, sizeof(link_settings));
1820 /* get phy test pattern and pattern parameters from DP receiver */
1821 core_link_read_dpcd(
1823 DP_TEST_PHY_PATTERN,
1824 &dpcd_test_pattern.raw,
1825 sizeof(dpcd_test_pattern));
1826 core_link_read_dpcd(
1828 DP_ADJUST_REQUEST_LANE0_1,
1829 &dpcd_lane_adjustment[0].raw,
1830 sizeof(dpcd_lane_adjustment));
1832 /*get post cursor 2 parameters
1833 * For DP 1.1a or eariler, this DPCD register's value is 0
1834 * For DP 1.2 or later:
1835 * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
1836 * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
1838 core_link_read_dpcd(
1840 DP_ADJUST_REQUEST_POST_CURSOR2,
1841 &dpcd_post_cursor_2_adjustment,
1842 sizeof(dpcd_post_cursor_2_adjustment));
1844 /* translate request */
1845 switch (dpcd_test_pattern.bits.PATTERN) {
1846 case PHY_TEST_PATTERN_D10_2:
1847 test_pattern = DP_TEST_PATTERN_D102;
1849 case PHY_TEST_PATTERN_SYMBOL_ERROR:
1850 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
1852 case PHY_TEST_PATTERN_PRBS7:
1853 test_pattern = DP_TEST_PATTERN_PRBS7;
1855 case PHY_TEST_PATTERN_80BIT_CUSTOM:
1856 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
1858 case PHY_TEST_PATTERN_CP2520_1:
1859 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
1860 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
1861 DP_TEST_PATTERN_TRAINING_PATTERN4 :
1862 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
1864 case PHY_TEST_PATTERN_CP2520_2:
1865 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
1866 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
1867 DP_TEST_PATTERN_TRAINING_PATTERN4 :
1868 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
1870 case PHY_TEST_PATTERN_CP2520_3:
1871 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
1874 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
1878 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM)
1879 core_link_read_dpcd(
1881 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
1882 test_80_bit_pattern,
1883 sizeof(test_80_bit_pattern));
1885 /* prepare link training settings */
1886 link_settings.link = link->cur_link_settings;
1888 for (lane = 0; lane <
1889 (unsigned int)(link->cur_link_settings.lane_count);
1891 dpcd_lane_adjust.raw =
1892 get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
1893 link_settings.lane_settings[lane].VOLTAGE_SWING =
1894 (enum dc_voltage_swing)
1895 (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
1896 link_settings.lane_settings[lane].PRE_EMPHASIS =
1897 (enum dc_pre_emphasis)
1898 (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
1899 link_settings.lane_settings[lane].POST_CURSOR2 =
1900 (enum dc_post_cursor2)
1901 ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
1904 for (i = 0; i < 4; i++)
1905 link_training_settings.lane_settings[i] =
1906 link_settings.lane_settings[i];
1907 link_training_settings.link_settings = link_settings.link;
1908 link_training_settings.allow_invalid_msa_timing_param = false;
1909 /*Usage: Measure DP physical lane signal
1910 * by DP SI test equipment automatically.
1911 * PHY test pattern request is generated by equipment via HPD interrupt.
1912 * HPD needs to be active all the time. HPD should be active
1913 * all the time. Do not touch it.
1914 * forward request to DS
1916 dc_link_dp_set_test_pattern(
1919 &link_training_settings,
1920 test_80_bit_pattern,
1921 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
1922 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1);
1925 static void dp_test_send_link_test_pattern(struct dc_link *link)
1927 union link_test_pattern dpcd_test_pattern;
1928 union test_misc dpcd_test_params;
1929 enum dp_test_pattern test_pattern;
1931 memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
1932 memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
1934 /* get link test pattern and pattern parameters */
1935 core_link_read_dpcd(
1938 &dpcd_test_pattern.raw,
1939 sizeof(dpcd_test_pattern));
1940 core_link_read_dpcd(
1943 &dpcd_test_params.raw,
1944 sizeof(dpcd_test_params));
1946 switch (dpcd_test_pattern.bits.PATTERN) {
1947 case LINK_TEST_PATTERN_COLOR_RAMP:
1948 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
1950 case LINK_TEST_PATTERN_VERTICAL_BARS:
1951 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
1952 break; /* black and white */
1953 case LINK_TEST_PATTERN_COLOR_SQUARES:
1954 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
1955 TEST_DYN_RANGE_VESA ?
1956 DP_TEST_PATTERN_COLOR_SQUARES :
1957 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
1960 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
1964 dc_link_dp_set_test_pattern(
1972 static void handle_automated_test(struct dc_link *link)
1974 union test_request test_request;
1975 union test_response test_response;
1977 memset(&test_request, 0, sizeof(test_request));
1978 memset(&test_response, 0, sizeof(test_response));
1980 core_link_read_dpcd(
1984 sizeof(union test_request));
1985 if (test_request.bits.LINK_TRAINING) {
1986 /* ACK first to let DP RX test box monitor LT sequence */
1987 test_response.bits.ACK = 1;
1988 core_link_write_dpcd(
1992 sizeof(test_response));
1993 dp_test_send_link_training(link);
1994 /* no acknowledge request is needed again */
1995 test_response.bits.ACK = 0;
1997 if (test_request.bits.LINK_TEST_PATTRN) {
1998 dp_test_send_link_test_pattern(link);
1999 test_response.bits.ACK = 1;
2001 if (test_request.bits.PHY_TEST_PATTERN) {
2002 dp_test_send_phy_test_pattern(link);
2003 test_response.bits.ACK = 1;
2005 if (!test_request.raw)
2006 /* no requests, revert all test signals
2007 * TODO: revert all test signals
2009 test_response.bits.ACK = 1;
2010 /* send request acknowledgment */
2011 if (test_response.bits.ACK)
2012 core_link_write_dpcd(
2016 sizeof(test_response));
2019 bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
2021 union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
2022 union device_service_irq device_service_clear = { { 0 } };
2023 enum dc_status result;
2025 bool status = false;
2028 *out_link_loss = false;
2029 /* For use cases related to down stream connection status change,
2030 * PSR and device auto test, refer to function handle_sst_hpd_irq
2033 DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
2034 __func__, link->link_index);
2037 /* All the "handle_hpd_irq_xxx()" methods
2038 * should be called only after
2039 * dal_dpsst_ls_read_hpd_irq_data
2040 * Order of calls is important too
2042 result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
2043 if (out_hpd_irq_dpcd_data)
2044 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
2046 if (result != DC_OK) {
2047 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
2052 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
2053 device_service_clear.bits.AUTOMATED_TEST = 1;
2054 core_link_write_dpcd(
2056 DP_DEVICE_SERVICE_IRQ_VECTOR,
2057 &device_service_clear.raw,
2058 sizeof(device_service_clear.raw));
2059 device_service_clear.raw = 0;
2060 handle_automated_test(link);
2064 if (!allow_hpd_rx_irq(link)) {
2065 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
2066 __func__, link->link_index);
2070 if (handle_hpd_irq_psr_sink(link))
2071 /* PSR-related error was detected and handled */
2074 /* If PSR-related error handled, Main link may be off,
2075 * so do not handle as a normal sink status change interrupt.
2078 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
2081 /* check if we have MST msg and return since we poll for it */
2082 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
2085 /* For now we only handle 'Downstream port status' case.
2086 * If we got sink count changed it means
2087 * Downstream port status changed,
2088 * then DM should call DC to do the detection. */
2089 if (hpd_rx_irq_check_link_loss_status(
2091 &hpd_irq_dpcd_data)) {
2092 /* Connectivity log: link loss */
2093 CONN_DATA_LINK_LOSS(link,
2094 hpd_irq_dpcd_data.raw,
2095 sizeof(hpd_irq_dpcd_data),
2098 perform_link_training_with_retries(link,
2099 &link->cur_link_settings,
2100 true, LINK_TRAINING_ATTEMPTS);
2104 *out_link_loss = true;
2107 if (link->type == dc_connection_active_dongle &&
2108 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
2109 != link->dpcd_sink_count)
2112 /* reasons for HPD RX:
2113 * 1. Link Loss - ie Re-train the Link
2114 * 2. MST sideband message
2115 * 3. Automated Test - ie. Internal Commit
2116 * 4. CP (copy protection) - (not interesting for DM???)
2118 * 6. Downstream Port status changed
2119 * -ie. Detect - this the only one
2120 * which is interesting for DM because
2121 * it must call dc_link_detect.
2126 /*query dpcd for version and mst cap addresses*/
2127 bool is_mst_supported(struct dc_link *link)
2130 enum dc_status st = DC_OK;
2137 st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
2140 if (st == DC_OK && rev.raw >= DPCD_REV_12) {
2142 st = core_link_read_dpcd(link, DP_MSTM_CAP,
2143 &cap.raw, sizeof(cap));
2144 if (st == DC_OK && cap.bits.MST_CAP == 1)
2151 bool is_dp_active_dongle(const struct dc_link *link)
2153 enum display_dongle_type dongle_type = link->dpcd_caps.dongle_type;
2155 return (dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) ||
2156 (dongle_type == DISPLAY_DONGLE_DP_DVI_CONVERTER) ||
2157 (dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER);
2160 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
2163 case DOWN_STREAM_MAX_8BPC:
2165 case DOWN_STREAM_MAX_10BPC:
2167 case DOWN_STREAM_MAX_12BPC:
2169 case DOWN_STREAM_MAX_16BPC:
2178 static void get_active_converter_info(
2179 uint8_t data, struct dc_link *link)
2181 union dp_downstream_port_present ds_port = { .byte = data };
2183 /* decode converter info*/
2184 if (!ds_port.fields.PORT_PRESENT) {
2185 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
2186 ddc_service_set_dongle_type(link->ddc,
2187 link->dpcd_caps.dongle_type);
2191 switch (ds_port.fields.PORT_TYPE) {
2192 case DOWNSTREAM_VGA:
2193 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
2195 case DOWNSTREAM_DVI_HDMI:
2196 /* At this point we don't know is it DVI or HDMI,
2198 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
2201 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
2205 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
2206 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
2207 union dwnstream_port_caps_byte0 *port_caps =
2208 (union dwnstream_port_caps_byte0 *)det_caps;
2209 core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
2210 det_caps, sizeof(det_caps));
2212 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
2213 case DOWN_STREAM_DETAILED_VGA:
2214 link->dpcd_caps.dongle_type =
2215 DISPLAY_DONGLE_DP_VGA_CONVERTER;
2217 case DOWN_STREAM_DETAILED_DVI:
2218 link->dpcd_caps.dongle_type =
2219 DISPLAY_DONGLE_DP_DVI_CONVERTER;
2221 case DOWN_STREAM_DETAILED_HDMI:
2222 link->dpcd_caps.dongle_type =
2223 DISPLAY_DONGLE_DP_HDMI_CONVERTER;
2225 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
2226 if (ds_port.fields.DETAILED_CAPS) {
2228 union dwnstream_port_caps_byte3_hdmi
2229 hdmi_caps = {.raw = det_caps[3] };
2230 union dwnstream_port_caps_byte2
2231 hdmi_color_caps = {.raw = det_caps[2] };
2232 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk =
2233 det_caps[1] * 25000;
2235 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
2236 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
2237 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
2238 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
2239 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
2240 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
2241 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
2242 hdmi_caps.bits.YCrCr422_CONVERSION;
2243 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
2244 hdmi_caps.bits.YCrCr420_CONVERSION;
2246 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
2247 translate_dpcd_max_bpc(
2248 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
2250 if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk != 0)
2251 link->dpcd_caps.dongle_caps.extendedCapValid = true;
2258 ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
2261 struct dp_device_vendor_id dp_id;
2263 /* read IEEE branch device id */
2264 core_link_read_dpcd(
2270 link->dpcd_caps.branch_dev_id =
2271 (dp_id.ieee_oui[0] << 16) +
2272 (dp_id.ieee_oui[1] << 8) +
2276 link->dpcd_caps.branch_dev_name,
2277 dp_id.ieee_device_id,
2278 sizeof(dp_id.ieee_device_id));
2282 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
2284 core_link_read_dpcd(
2286 DP_BRANCH_REVISION_START,
2287 (uint8_t *)&dp_hw_fw_revision,
2288 sizeof(dp_hw_fw_revision));
2290 link->dpcd_caps.branch_hw_revision =
2291 dp_hw_fw_revision.ieee_hw_rev;
2294 link->dpcd_caps.branch_fw_revision,
2295 dp_hw_fw_revision.ieee_fw_rev,
2296 sizeof(dp_hw_fw_revision.ieee_fw_rev));
2300 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
2304 union dp_downstream_port_present ds_port = { 0 };
2306 if (!link->dpcd_caps.dpcd_rev.raw) {
2308 dp_receiver_power_ctrl(link, true);
2309 core_link_read_dpcd(link, DP_DPCD_REV,
2311 link->dpcd_caps.dpcd_rev.raw = dpcd_data[
2314 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
2317 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
2320 if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
2321 switch (link->dpcd_caps.branch_dev_id) {
2322 /* Some active dongles (DP-VGA, DP-DLDVI converters) power down
2323 * all internal circuits including AUX communication preventing
2324 * reading DPCD table and EDID (spec violation).
2325 * Encoder will skip DP RX power down on disable_output to
2326 * keep receiver powered all the time.*/
2327 case DP_BRANCH_DEVICE_ID_1:
2328 case DP_BRANCH_DEVICE_ID_4:
2329 link->wa_flags.dp_keep_receiver_powered = true;
2332 /* TODO: May need work around for other dongles. */
2334 link->wa_flags.dp_keep_receiver_powered = false;
2338 link->wa_flags.dp_keep_receiver_powered = false;
2341 static bool retrieve_link_cap(struct dc_link *link)
2343 uint8_t dpcd_data[DP_ADAPTER_CAP - DP_DPCD_REV + 1];
2345 struct dp_device_vendor_id sink_id;
2346 union down_stream_port_count down_strm_port_count;
2347 union edp_configuration_cap edp_config_cap;
2348 union dp_downstream_port_present ds_port = { 0 };
2349 enum dc_status status = DC_ERROR_UNEXPECTED;
2350 uint32_t read_dpcd_retry_cnt = 3;
2352 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
2354 memset(dpcd_data, '\0', sizeof(dpcd_data));
2355 memset(&down_strm_port_count,
2356 '\0', sizeof(union down_stream_port_count));
2357 memset(&edp_config_cap, '\0',
2358 sizeof(union edp_configuration_cap));
2360 for (i = 0; i < read_dpcd_retry_cnt; i++) {
2361 status = core_link_read_dpcd(
2366 if (status == DC_OK)
2370 if (status != DC_OK) {
2371 dm_error("%s: Read dpcd data failed.\n", __func__);
2376 union training_aux_rd_interval aux_rd_interval;
2378 aux_rd_interval.raw =
2379 dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
2381 if (aux_rd_interval.bits.EXT_RECIEVER_CAP_FIELD_PRESENT == 1) {
2382 uint8_t ext_cap_data[16];
2384 memset(ext_cap_data, '\0', sizeof(ext_cap_data));
2385 for (i = 0; i < read_dpcd_retry_cnt; i++) {
2386 status = core_link_read_dpcd(
2390 sizeof(ext_cap_data));
2391 if (status == DC_OK) {
2392 memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
2396 if (status != DC_OK)
2397 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
2401 link->dpcd_caps.dpcd_rev.raw =
2402 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
2404 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
2407 get_active_converter_info(ds_port.byte, link);
2409 dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
2411 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
2414 link->dpcd_caps.allow_invalid_MSA_timing_param =
2415 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
2417 link->dpcd_caps.max_ln_count.raw = dpcd_data[
2418 DP_MAX_LANE_COUNT - DP_DPCD_REV];
2420 link->dpcd_caps.max_down_spread.raw = dpcd_data[
2421 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
2423 link->reported_link_cap.lane_count =
2424 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
2425 link->reported_link_cap.link_rate = dpcd_data[
2426 DP_MAX_LINK_RATE - DP_DPCD_REV];
2427 link->reported_link_cap.link_spread =
2428 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
2429 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
2431 edp_config_cap.raw = dpcd_data[
2432 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
2433 link->dpcd_caps.panel_mode_edp =
2434 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
2435 link->dpcd_caps.dpcd_display_control_capable =
2436 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
2438 link->test_pattern_enabled = false;
2439 link->compliance_test_state.raw = 0;
2441 /* read sink count */
2442 core_link_read_dpcd(link,
2444 &link->dpcd_caps.sink_count.raw,
2445 sizeof(link->dpcd_caps.sink_count.raw));
2447 /* read sink ieee oui */
2448 core_link_read_dpcd(link,
2450 (uint8_t *)(&sink_id),
2453 link->dpcd_caps.sink_dev_id =
2454 (sink_id.ieee_oui[0] << 16) +
2455 (sink_id.ieee_oui[1] << 8) +
2456 (sink_id.ieee_oui[2]);
2459 link->dpcd_caps.sink_dev_id_str,
2460 sink_id.ieee_device_id,
2461 sizeof(sink_id.ieee_device_id));
2463 core_link_read_dpcd(
2465 DP_SINK_HW_REVISION_START,
2466 (uint8_t *)&dp_hw_fw_revision,
2467 sizeof(dp_hw_fw_revision));
2469 link->dpcd_caps.sink_hw_revision =
2470 dp_hw_fw_revision.ieee_hw_rev;
2473 link->dpcd_caps.sink_fw_revision,
2474 dp_hw_fw_revision.ieee_fw_rev,
2475 sizeof(dp_hw_fw_revision.ieee_fw_rev));
2477 /* Connectivity log: detection */
2478 CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
2483 bool detect_dp_sink_caps(struct dc_link *link)
2485 return retrieve_link_cap(link);
2487 /* dc init_hw has power encoder using default
2488 * signal for connector. For native DP, no
2489 * need to power up encoder again. If not native
2490 * DP, hw_init may need check signal or power up
2493 /* TODO save sink caps in link->sink */
2496 void detect_edp_sink_caps(struct dc_link *link)
2498 retrieve_link_cap(link);
2500 if (link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)
2501 link->reported_link_cap.link_rate = LINK_RATE_HIGH2;
2503 link->verified_link_cap = link->reported_link_cap;
2506 void dc_link_dp_enable_hpd(const struct dc_link *link)
2508 struct link_encoder *encoder = link->link_enc;
2510 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
2511 encoder->funcs->enable_hpd(encoder);
2514 void dc_link_dp_disable_hpd(const struct dc_link *link)
2516 struct link_encoder *encoder = link->link_enc;
2518 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
2519 encoder->funcs->disable_hpd(encoder);
2522 static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
2524 if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
2525 test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
2526 test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
2532 static void set_crtc_test_pattern(struct dc_link *link,
2533 struct pipe_ctx *pipe_ctx,
2534 enum dp_test_pattern test_pattern)
2536 enum controller_dp_test_pattern controller_test_pattern;
2537 enum dc_color_depth color_depth = pipe_ctx->
2538 stream->timing.display_color_depth;
2539 struct bit_depth_reduction_params params;
2541 memset(¶ms, 0, sizeof(params));
2543 switch (test_pattern) {
2544 case DP_TEST_PATTERN_COLOR_SQUARES:
2545 controller_test_pattern =
2546 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
2548 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
2549 controller_test_pattern =
2550 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
2552 case DP_TEST_PATTERN_VERTICAL_BARS:
2553 controller_test_pattern =
2554 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
2556 case DP_TEST_PATTERN_HORIZONTAL_BARS:
2557 controller_test_pattern =
2558 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
2560 case DP_TEST_PATTERN_COLOR_RAMP:
2561 controller_test_pattern =
2562 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
2565 controller_test_pattern =
2566 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
2570 switch (test_pattern) {
2571 case DP_TEST_PATTERN_COLOR_SQUARES:
2572 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
2573 case DP_TEST_PATTERN_VERTICAL_BARS:
2574 case DP_TEST_PATTERN_HORIZONTAL_BARS:
2575 case DP_TEST_PATTERN_COLOR_RAMP:
2577 /* disable bit depth reduction */
2578 pipe_ctx->stream->bit_depth_params = params;
2579 pipe_ctx->stream_res.opp->funcs->
2580 opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, ¶ms);
2581 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
2582 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
2583 controller_test_pattern, color_depth);
2586 case DP_TEST_PATTERN_VIDEO_MODE:
2588 /* restore bitdepth reduction */
2589 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
2591 pipe_ctx->stream->bit_depth_params = params;
2592 pipe_ctx->stream_res.opp->funcs->
2593 opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, ¶ms);
2594 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
2595 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
2596 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2606 bool dc_link_dp_set_test_pattern(
2607 struct dc_link *link,
2608 enum dp_test_pattern test_pattern,
2609 const struct link_training_settings *p_link_settings,
2610 const unsigned char *p_custom_pattern,
2611 unsigned int cust_pattern_size)
2613 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2614 struct pipe_ctx *pipe_ctx = &pipes[0];
2617 unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
2618 union dpcd_training_pattern training_pattern;
2619 enum dpcd_phy_test_patterns pattern;
2621 memset(&training_pattern, 0, sizeof(training_pattern));
2623 for (i = 0; i < MAX_PIPES; i++) {
2624 if (pipes[i].stream->sink->link == link) {
2625 pipe_ctx = &pipes[i];
2630 /* Reset CRTC Test Pattern if it is currently running and request
2631 * is VideoMode Reset DP Phy Test Pattern if it is currently running
2632 * and request is VideoMode
2634 if (link->test_pattern_enabled && test_pattern ==
2635 DP_TEST_PATTERN_VIDEO_MODE) {
2636 /* Set CRTC Test Pattern */
2637 set_crtc_test_pattern(link, pipe_ctx, test_pattern);
2638 dp_set_hw_test_pattern(link, test_pattern,
2639 (uint8_t *)p_custom_pattern,
2640 (uint32_t)cust_pattern_size);
2642 /* Unblank Stream */
2643 link->dc->hwss.unblank_stream(
2645 &link->verified_link_cap);
2646 /* TODO:m_pHwss->MuteAudioEndpoint
2647 * (pPathMode->pDisplayPath, false);
2650 /* Reset Test Pattern state */
2651 link->test_pattern_enabled = false;
2656 /* Check for PHY Test Patterns */
2657 if (is_dp_phy_pattern(test_pattern)) {
2658 /* Set DPCD Lane Settings before running test pattern */
2659 if (p_link_settings != NULL) {
2660 dp_set_hw_lane_settings(link, p_link_settings);
2661 dpcd_set_lane_settings(link, p_link_settings);
2664 /* Blank stream if running test pattern */
2665 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
2668 * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
2671 pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
2674 dp_set_hw_test_pattern(link, test_pattern,
2675 (uint8_t *)p_custom_pattern,
2676 (uint32_t)cust_pattern_size);
2678 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
2679 /* Set Test Pattern state */
2680 link->test_pattern_enabled = true;
2681 if (p_link_settings != NULL)
2682 dpcd_set_link_settings(link,
2686 switch (test_pattern) {
2687 case DP_TEST_PATTERN_VIDEO_MODE:
2688 pattern = PHY_TEST_PATTERN_NONE;
2690 case DP_TEST_PATTERN_D102:
2691 pattern = PHY_TEST_PATTERN_D10_2;
2693 case DP_TEST_PATTERN_SYMBOL_ERROR:
2694 pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
2696 case DP_TEST_PATTERN_PRBS7:
2697 pattern = PHY_TEST_PATTERN_PRBS7;
2699 case DP_TEST_PATTERN_80BIT_CUSTOM:
2700 pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
2702 case DP_TEST_PATTERN_CP2520_1:
2703 pattern = PHY_TEST_PATTERN_CP2520_1;
2705 case DP_TEST_PATTERN_CP2520_2:
2706 pattern = PHY_TEST_PATTERN_CP2520_2;
2708 case DP_TEST_PATTERN_CP2520_3:
2709 pattern = PHY_TEST_PATTERN_CP2520_3;
2715 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
2716 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
2719 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
2720 /* tell receiver that we are sending qualification
2721 * pattern DP 1.2 or later - DP receiver's link quality
2722 * pattern is set using DPCD LINK_QUAL_LANEx_SET
2723 * register (0x10B~0x10E)\
2725 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
2726 link_qual_pattern[lane] =
2727 (unsigned char)(pattern);
2729 core_link_write_dpcd(link,
2730 DP_LINK_QUAL_LANE0_SET,
2732 sizeof(link_qual_pattern));
2733 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
2734 link->dpcd_caps.dpcd_rev.raw == 0) {
2735 /* tell receiver that we are sending qualification
2736 * pattern DP 1.1a or earlier - DP receiver's link
2737 * quality pattern is set using
2738 * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
2739 * register (0x102). We will use v_1.3 when we are
2740 * setting test pattern for DP 1.1.
2742 core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
2743 &training_pattern.raw,
2744 sizeof(training_pattern));
2745 training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
2746 core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
2747 &training_pattern.raw,
2748 sizeof(training_pattern));
2752 set_crtc_test_pattern(link, pipe_ctx, test_pattern);
2753 /* Set Test Pattern state */
2754 link->test_pattern_enabled = true;
2760 void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
2762 unsigned char mstmCntl;
2764 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
2766 mstmCntl |= DP_MST_EN;
2768 mstmCntl &= (~DP_MST_EN);
2770 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);