drivers/gpu/drm/amd/display/dc/core/dc_link.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "atom.h"
  28 #include "dm_helpers.h"
  29 #include "dc.h"
  30 #include "grph_object_id.h"
  31 #include "gpio_service_interface.h"
  32 #include "core_status.h"
  33 #include "dc_link_dp.h"
  34 #include "dc_link_ddc.h"
  35 #include "link_hwss.h"
  36 #include "opp.h"
  37
  38 #include "link_encoder.h"
  39 #include "hw_sequencer.h"
  40 #include "resource.h"
  41 #include "abm.h"
  42 #include "fixed31_32.h"
  43 #include "dpcd_defs.h"
  44 #include "dmcu.h"
  45
  46 #include "dce/dce_11_0_d.h"
  47 #include "dce/dce_11_0_enum.h"
  48 #include "dce/dce_11_0_sh_mask.h"
  49
  50 #define DC_LOGGER_INIT(logger)
  51
  52
  53 #define LINK_INFO(...) \
  54         DC_LOG_HW_HOTPLUG(  \
  55                 __VA_ARGS__)
  56
  57 #define RETIMER_REDRIVER_INFO(...) \
  58         DC_LOG_RETIMER_REDRIVER(  \
  59                 __VA_ARGS__)
  60 /*******************************************************************************
  61  * Private structures
  62  ******************************************************************************/
  63
  64 enum {
  65         LINK_RATE_REF_FREQ_IN_MHZ = 27,
  66         PEAK_FACTOR_X1000 = 1006,
  67         /*
  68         * Some receivers fail to train on first try and are good
  69         * on subsequent tries. 2 retries should be plenty. If we
  70         * don't have a successful training then we don't expect to
  71         * ever get one.
  72         */
  73         LINK_TRAINING_MAX_VERIFY_RETRY = 2
  74 };
  75
  76 /*******************************************************************************
  77  * Private functions
  78  ******************************************************************************/
  79 static void destruct(struct dc_link *link)
  80 {
  81         int i;
  82
  83         if (link->ddc)
  84                 dal_ddc_service_destroy(&link->ddc);
  85
  86         if(link->link_enc)
  87                 link->link_enc->funcs->destroy(&link->link_enc);
  88
  89         if (link->local_sink)
  90                 dc_sink_release(link->local_sink);
  91
  92         for (i = 0; i < link->sink_count; ++i)
  93                 dc_sink_release(link->remote_sinks[i]);
  94 }
  95
  96 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
  97                 struct graphics_object_id link_id,
  98                 struct gpio_service *gpio_service)
  99 {
 100         enum bp_result bp_result;
 101         struct graphics_object_hpd_info hpd_info;
 102         struct gpio_pin_info pin_info;
 103
 104         if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
 105                 return NULL;
 106
 107         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
 108                 hpd_info.hpd_int_gpio_uid, &pin_info);
 109
 110         if (bp_result != BP_RESULT_OK) {
 111                 ASSERT(bp_result == BP_RESULT_NORECORD);
 112                 return NULL;
 113         }
 114
 115         return dal_gpio_service_create_irq(
 116                 gpio_service,
 117                 pin_info.offset,
 118                 pin_info.mask);
 119 }
 120
 121 /*
 122  *  Function: program_hpd_filter
 123  *
 124  *  @brief
 125  *     Programs HPD filter on associated HPD line
 126  *
 127  *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 128  *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 129  *
 130  *  @return
 131  *     true on success, false otherwise
 132  */
 133 static bool program_hpd_filter(
 134         const struct dc_link *link)
 135 {
 136         bool result = false;
 137
 138         struct gpio *hpd;
 139
 140         int delay_on_connect_in_ms = 0;
 141         int delay_on_disconnect_in_ms = 0;
 142
 143         if (link->is_hpd_filter_disabled)
 144                 return false;
 145         /* Verify feature is supported */
 146         switch (link->connector_signal) {
 147         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 148         case SIGNAL_TYPE_DVI_DUAL_LINK:
 149         case SIGNAL_TYPE_HDMI_TYPE_A:
 150                 /* Program hpd filter */
 151                 delay_on_connect_in_ms = 500;
 152                 delay_on_disconnect_in_ms = 100;
 153                 break;
 154         case SIGNAL_TYPE_DISPLAY_PORT:
 155         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 156                 /* Program hpd filter to allow DP signal to settle */
 157                 /* 500: not able to detect MST <-> SST switch as HPD is low for
 158                  *      only 100ms on DELL U2413
 159                  * 0:   some passive dongle still show aux mode instead of i2c
 160                  * 20-50:not enough to hide bouncing HPD with passive dongle.
 161                  *      also see intermittent i2c read issues.
 162                  */
 163                 delay_on_connect_in_ms = 80;
 164                 delay_on_disconnect_in_ms = 0;
 165                 break;
 166         case SIGNAL_TYPE_LVDS:
 167         case SIGNAL_TYPE_EDP:
 168         default:
 169                 /* Don't program hpd filter */
 170                 return false;
 171         }
 172
 173         /* Obtain HPD handle */
 174         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 175
 176         if (!hpd)
 177                 return result;
 178
 179         /* Setup HPD filtering */
 180         if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 181                 struct gpio_hpd_config config;
 182
 183                 config.delay_on_connect = delay_on_connect_in_ms;
 184                 config.delay_on_disconnect = delay_on_disconnect_in_ms;
 185
 186                 dal_irq_setup_hpd_filter(hpd, &config);
 187
 188                 dal_gpio_close(hpd);
 189
 190                 result = true;
 191         } else {
 192                 ASSERT_CRITICAL(false);
 193         }
 194
 195         /* Release HPD handle */
 196         dal_gpio_destroy_irq(&hpd);
 197
 198         return result;
 199 }
 200
 201 /**
 202  * dc_link_detect_sink() - Determine if there is a sink connected
 203  *
 204  * @type: Returned connection type
 205  * Does not detect downstream devices, such as MST sinks
 206  * or display connected through active dongles
 207  */
 208 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 209 {
 210         uint32_t is_hpd_high = 0;
 211         struct gpio *hpd_pin;
 212
 213         if (link->connector_signal == SIGNAL_TYPE_LVDS) {
 214                 *type = dc_connection_single;
 215                 return true;
 216         }
 217
 218         if (link->connector_signal == SIGNAL_TYPE_EDP)
 219                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 220
 221         /* todo: may need to lock gpio access */
 222         hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 223         if (hpd_pin == NULL)
 224                 goto hpd_gpio_failure;
 225
 226         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 227         dal_gpio_get_value(hpd_pin, &is_hpd_high);
 228         dal_gpio_close(hpd_pin);
 229         dal_gpio_destroy_irq(&hpd_pin);
 230
 231         if (is_hpd_high) {
 232                 *type = dc_connection_single;
 233                 /* TODO: need to do the actual detection */
 234         } else {
 235                 *type = dc_connection_none;
 236         }
 237
 238         return true;
 239
 240 hpd_gpio_failure:
 241         return false;
 242 }
 243
 244 static enum ddc_transaction_type get_ddc_transaction_type(
 245                 enum signal_type sink_signal)
 246 {
 247         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 248
 249         switch (sink_signal) {
 250         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 251         case SIGNAL_TYPE_DVI_DUAL_LINK:
 252         case SIGNAL_TYPE_HDMI_TYPE_A:
 253         case SIGNAL_TYPE_LVDS:
 254         case SIGNAL_TYPE_RGB:
 255                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
 256                 break;
 257
 258         case SIGNAL_TYPE_DISPLAY_PORT:
 259         case SIGNAL_TYPE_EDP:
 260                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 261                 break;
 262
 263         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 264                 /* MST does not use I2COverAux, but there is the
 265                  * SPECIAL use case for "immediate dwnstrm device
 266                  * access" (EPR#370830). */
 267                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 268                 break;
 269
 270         default:
 271                 break;
 272         }
 273
 274         return transaction_type;
 275 }
 276
 277 static enum signal_type get_basic_signal_type(
 278         struct graphics_object_id encoder,
 279         struct graphics_object_id downstream)
 280 {
 281         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 282                 switch (downstream.id) {
 283                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 284                         switch (encoder.id) {
 285                         case ENCODER_ID_INTERNAL_DAC1:
 286                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 287                         case ENCODER_ID_INTERNAL_DAC2:
 288                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 289                                 return SIGNAL_TYPE_RGB;
 290                         default:
 291                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 292                         }
 293                 break;
 294                 case CONNECTOR_ID_DUAL_LINK_DVII:
 295                 {
 296                         switch (encoder.id) {
 297                         case ENCODER_ID_INTERNAL_DAC1:
 298                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 299                         case ENCODER_ID_INTERNAL_DAC2:
 300                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 301                                 return SIGNAL_TYPE_RGB;
 302                         default:
 303                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 304                         }
 305                 }
 306                 break;
 307                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 308                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 309                 case CONNECTOR_ID_DUAL_LINK_DVID:
 310                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 311                 case CONNECTOR_ID_VGA:
 312                         return SIGNAL_TYPE_RGB;
 313                 case CONNECTOR_ID_HDMI_TYPE_A:
 314                         return SIGNAL_TYPE_HDMI_TYPE_A;
 315                 case CONNECTOR_ID_LVDS:
 316                         return SIGNAL_TYPE_LVDS;
 317                 case CONNECTOR_ID_DISPLAY_PORT:
 318                         return SIGNAL_TYPE_DISPLAY_PORT;
 319                 case CONNECTOR_ID_EDP:
 320                         return SIGNAL_TYPE_EDP;
 321                 default:
 322                         return SIGNAL_TYPE_NONE;
 323                 }
 324         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 325                 switch (downstream.id) {
 326                 case ENCODER_ID_EXTERNAL_NUTMEG:
 327                 case ENCODER_ID_EXTERNAL_TRAVIS:
 328                         return SIGNAL_TYPE_DISPLAY_PORT;
 329                 default:
 330                         return SIGNAL_TYPE_NONE;
 331                 }
 332         }
 333
 334         return SIGNAL_TYPE_NONE;
 335 }
 336
 337 /**
 338  * dc_link_is_dp_sink_present() - Check if there is a native DP
 339  * or passive DP-HDMI dongle connected
 340  */
 341 bool dc_link_is_dp_sink_present(struct dc_link *link)
 342 {
 343         enum gpio_result gpio_result;
 344         uint32_t clock_pin = 0;
 345         uint8_t retry = 0;
 346         struct ddc *ddc;
 347
 348         enum connector_id connector_id =
 349                 dal_graphics_object_id_get_connector_id(link->link_id);
 350
 351         bool present =
 352                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 353                 (connector_id == CONNECTOR_ID_EDP));
 354
 355         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 356
 357         if (!ddc) {
 358                 BREAK_TO_DEBUGGER();
 359                 return present;
 360         }
 361
 362         /* Open GPIO and set it to I2C mode */
 363         /* Note: this GpioMode_Input will be converted
 364          * to GpioConfigType_I2cAuxDualMode in GPIO component,
 365          * which indicates we need additional delay */
 366
 367         if (GPIO_RESULT_OK != dal_ddc_open(
 368                 ddc, GPIO_MODE_INPUT, GPIO_DDC_CONFIG_TYPE_MODE_I2C)) {
 369                 dal_gpio_destroy_ddc(&ddc);
 370
 371                 return present;
 372         }
 373
 374         /*
 375          * Read GPIO: DP sink is present if both clock and data pins are zero
 376          *
 377          * [W/A] plug-unplug DP cable, sometimes customer board has
 378          * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
 379          * then monitor can't br light up. Add retry 3 times
 380          * But in real passive dongle, it need additional 3ms to detect
 381          */
 382         do {
 383                 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 384                 ASSERT(gpio_result == GPIO_RESULT_OK);
 385                 if (clock_pin)
 386                         udelay(1000);
 387                 else
 388                         break;
 389         } while (retry++ < 3);
 390
 391         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 392
 393         dal_ddc_close(ddc);
 394
 395         return present;
 396 }
 397
 398 /*
 399  * @brief
 400  * Detect output sink type
 401  */
 402 static enum signal_type link_detect_sink(
 403         struct dc_link *link,
 404         enum dc_detect_reason reason)
 405 {
 406         enum signal_type result = get_basic_signal_type(
 407                 link->link_enc->id, link->link_id);
 408
 409         /* Internal digital encoder will detect only dongles
 410          * that require digital signal */
 411
 412         /* Detection mechanism is different
 413          * for different native connectors.
 414          * LVDS connector supports only LVDS signal;
 415          * PCIE is a bus slot, the actual connector needs to be detected first;
 416          * eDP connector supports only eDP signal;
 417          * HDMI should check straps for audio */
 418
 419         /* PCIE detects the actual connector on add-on board */
 420
 421         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 422                 /* ZAZTODO implement PCIE add-on card detection */
 423         }
 424
 425         switch (link->link_id.id) {
 426         case CONNECTOR_ID_HDMI_TYPE_A: {
 427                 /* check audio support:
 428                  * if native HDMI is not supported, switch to DVI */
 429                 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 430
 431                 if (!aud_support->hdmi_audio_native)
 432                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 433                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 434         }
 435         break;
 436         case CONNECTOR_ID_DISPLAY_PORT: {
 437                 /* DP HPD short pulse. Passive DP dongle will not
 438                  * have short pulse
 439                  */
 440                 if (reason != DETECT_REASON_HPDRX) {
 441                         /* Check whether DP signal detected: if not -
 442                          * we assume signal is DVI; it could be corrected
 443                          * to HDMI after dongle detection
 444                          */
 445                         if (!dm_helpers_is_dp_sink_present(link))
 446                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 447                 }
 448         }
 449         break;
 450         default:
 451         break;
 452         }
 453
 454         return result;
 455 }
 456
 457 static enum signal_type decide_signal_from_strap_and_dongle_type(
 458                 enum display_dongle_type dongle_type,
 459                 struct audio_support *audio_support)
 460 {
 461         enum signal_type signal = SIGNAL_TYPE_NONE;
 462
 463         switch (dongle_type) {
 464         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 465                 if (audio_support->hdmi_audio_on_dongle)
 466                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 467                 else
 468                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 469                 break;
 470         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 471                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 472                 break;
 473         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 474                 if (audio_support->hdmi_audio_native)
 475                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 476                 else
 477                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 478                 break;
 479         default:
 480                 signal = SIGNAL_TYPE_NONE;
 481                 break;
 482         }
 483
 484         return signal;
 485 }
 486
 487 static enum signal_type dp_passive_dongle_detection(
 488                 struct ddc_service *ddc,
 489                 struct display_sink_capability *sink_cap,
 490                 struct audio_support *audio_support)
 491 {
 492         dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
 493                                                 ddc, sink_cap);
 494         return decide_signal_from_strap_and_dongle_type(
 495                         sink_cap->dongle_type,
 496                         audio_support);
 497 }
 498
 499 static void link_disconnect_sink(struct dc_link *link)
 500 {
 501         if (link->local_sink) {
 502                 dc_sink_release(link->local_sink);
 503                 link->local_sink = NULL;
 504         }
 505
 506         link->dpcd_sink_count = 0;
 507 }
 508
 509 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 510 {
 511         dc_sink_release(link->local_sink);
 512         link->local_sink = prev_sink;
 513 }
 514
 515
 516 static bool detect_dp(
 517         struct dc_link *link,
 518         struct display_sink_capability *sink_caps,
 519         bool *converter_disable_audio,
 520         struct audio_support *audio_support,
 521         enum dc_detect_reason reason)
 522 {
 523         bool boot = false;
 524         sink_caps->signal = link_detect_sink(link, reason);
 525         sink_caps->transaction_type =
 526                 get_ddc_transaction_type(sink_caps->signal);
 527
 528         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 529                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 530                 if (!detect_dp_sink_caps(link))
 531                         return false;
 532
 533                 if (is_mst_supported(link)) {
 534                         sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
 535                         link->type = dc_connection_mst_branch;
 536
 537                         dal_ddc_service_set_transaction_type(
 538                                                         link->ddc,
 539                                                         sink_caps->transaction_type);
 540
 541                         /*
 542                          * This call will initiate MST topology discovery. Which
 543                          * will detect MST ports and add new DRM connector DRM
 544                          * framework. Then read EDID via remote i2c over aux. In
 545                          * the end, will notify DRM detect result and save EDID
 546                          * into DRM framework.
 547                          *
 548                          * .detect is called by .fill_modes.
 549                          * .fill_modes is called by user mode ioctl
 550                          * DRM_IOCTL_MODE_GETCONNECTOR.
 551                          *
 552                          * .get_modes is called by .fill_modes.
 553                          *
 554                          * call .get_modes, AMDGPU DM implementation will create
 555                          * new dc_sink and add to dc_link. For long HPD plug
 556                          * in/out, MST has its own handle.
 557                          *
 558                          * Therefore, just after dc_create, link->sink is not
 559                          * created for MST until user mode app calls
 560                          * DRM_IOCTL_MODE_GETCONNECTOR.
 561                          *
 562                          * Need check ->sink usages in case ->sink = NULL
 563                          * TODO: s3 resume check
 564                          */
 565                         if (reason == DETECT_REASON_BOOT)
 566                                 boot = true;
 567
 568                         dm_helpers_dp_update_branch_info(
 569                                 link->ctx,
 570                                 link);
 571
 572                         if (!dm_helpers_dp_mst_start_top_mgr(
 573                                 link->ctx,
 574                                 link, boot)) {
 575                                 /* MST not supported */
 576                                 link->type = dc_connection_single;
 577                                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 578                         }
 579                 }
 580
 581                 if (link->type != dc_connection_mst_branch &&
 582                         is_dp_active_dongle(link)) {
 583                         /* DP active dongles */
 584                         link->type = dc_connection_active_dongle;
 585                         if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
 586                                 /*
 587                                  * active dongle unplug processing for short irq
 588                                  */
 589                                 link_disconnect_sink(link);
 590                                 return true;
 591                         }
 592
 593                         if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER)
 594                                 *converter_disable_audio = true;
 595                 }
 596         } else {
 597                 /* DP passive dongles */
 598                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 599                                 sink_caps,
 600                                 audio_support);
 601         }
 602
 603         return true;
 604 }
 605
 606 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 607 {
 608         if (old_edid->length != new_edid->length)
 609                 return false;
 610
 611         if (new_edid->length == 0)
 612                 return false;
 613
 614         return (memcmp(old_edid->raw_edid, new_edid->raw_edid, new_edid->length) == 0);
 615 }
 616
 617 /**
 618  * dc_link_detect() - Detect if a sink is attached to a given link
 619  *
 620  * link->local_sink is created or destroyed as needed.
 621  *
 622  * This does not create remote sinks but will trigger DM
 623  * to start MST detection if a branch is detected.
 624  */
 625 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
 626 {
 627         struct dc_sink_init_data sink_init_data = { 0 };
 628         struct display_sink_capability sink_caps = { 0 };
 629         uint8_t i;
 630         bool converter_disable_audio = false;
 631         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 632         bool same_edid = false;
 633         enum dc_edid_status edid_status;
 634         struct dc_context *dc_ctx = link->ctx;
 635         struct dc_sink *sink = NULL;
 636         struct dc_sink *prev_sink = NULL;
 637         struct dpcd_caps prev_dpcd_caps;
 638         bool same_dpcd = true;
 639         enum dc_connection_type new_connection_type = dc_connection_none;
 640         DC_LOGGER_INIT(link->ctx->logger);
 641         if (link->connector_signal == SIGNAL_TYPE_VIRTUAL)
 642                 return false;
 643
 644         if (false == dc_link_detect_sink(link, &new_connection_type)) {
 645                 BREAK_TO_DEBUGGER();
 646                 return false;
 647         }
 648
 649         if (link->connector_signal == SIGNAL_TYPE_EDP &&
 650                         link->local_sink)
 651                 return true;
 652
 653         if (link->connector_signal == SIGNAL_TYPE_LVDS &&
 654                         link->local_sink)
 655                 return true;
 656
 657         prev_sink = link->local_sink;
 658         if (prev_sink != NULL) {
 659                 dc_sink_retain(prev_sink);
 660                 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
 661         }
 662         link_disconnect_sink(link);
 663
 664         if (new_connection_type != dc_connection_none) {
 665                 link->type = new_connection_type;
 666
 667                 /* From Disconnected-to-Connected. */
 668                 switch (link->connector_signal) {
 669                 case SIGNAL_TYPE_HDMI_TYPE_A: {
 670                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 671                         if (aud_support->hdmi_audio_native)
 672                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 673                         else
 674                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 675                         break;
 676                 }
 677
 678                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
 679                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 680                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 681                         break;
 682                 }
 683
 684                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
 685                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 686                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 687                         break;
 688                 }
 689
 690                 case SIGNAL_TYPE_LVDS: {
 691                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 692                         sink_caps.signal = SIGNAL_TYPE_LVDS;
 693                         break;
 694                 }
 695
 696                 case SIGNAL_TYPE_EDP: {
 697                         detect_edp_sink_caps(link);
 698                         sink_caps.transaction_type =
 699                                 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 700                         sink_caps.signal = SIGNAL_TYPE_EDP;
 701                         break;
 702                 }
 703
 704                 case SIGNAL_TYPE_DISPLAY_PORT: {
 705                         if (!detect_dp(
 706                                 link,
 707                                 &sink_caps,
 708                                 &converter_disable_audio,
 709                                 aud_support, reason)) {
 710                                 if (prev_sink != NULL)
 711                                         dc_sink_release(prev_sink);
 712                                 return false;
 713                         }
 714
 715                         // Check if dpcp block is the same
 716                         if (prev_sink != NULL) {
 717                                 if (memcmp(&link->dpcd_caps, &prev_dpcd_caps, sizeof(struct dpcd_caps)))
 718                                         same_dpcd = false;
 719                         }
 720                         /* Active dongle plug in without display or downstream unplug*/
 721                         if (link->type == dc_connection_active_dongle
 722                                         && link->dpcd_caps.sink_count.
 723                                         bits.SINK_COUNT == 0) {
 724                                 if (prev_sink != NULL) {
 725                                         /* Downstream unplug */
 726                                         dc_sink_release(prev_sink);
 727                                 } else {
 728                                         /* Empty dongle plug in */
 729                                         for (i = 0; i < LINK_TRAINING_MAX_VERIFY_RETRY; i++) {
 730                                                 int fail_count = 0;
 731
 732                                                 dp_verify_link_cap(link,
 733                                                                   &link->reported_link_cap,
 734                                                                   &fail_count);
 735
 736                                                 if (fail_count == 0)
 737                                                         break;
 738                                         }
 739                                 }
 740                                 return true;
 741                         }
 742
 743                         if (link->type == dc_connection_mst_branch) {
 744                                 LINK_INFO("link=%d, mst branch is now Connected\n",
 745                                         link->link_index);
 746                                 /* Need to setup mst link_cap struct here
 747                                  * otherwise dc_link_detect() will leave mst link_cap
 748                                  * empty which leads to allocate_mst_payload() has "0"
 749                                  * pbn_per_slot value leading to exception on dc_fixpt_div()
 750                                  */
 751                                 link->verified_link_cap = link->reported_link_cap;
 752                                 if (prev_sink != NULL)
 753                                         dc_sink_release(prev_sink);
 754                                 return false;
 755                         }
 756
 757                         break;
 758                 }
 759
 760                 default:
 761                         DC_ERROR("Invalid connector type! signal:%d\n",
 762                                 link->connector_signal);
 763                         if (prev_sink != NULL)
 764                                 dc_sink_release(prev_sink);
 765                         return false;
 766                 } /* switch() */
 767
 768                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
 769                         link->dpcd_sink_count = link->dpcd_caps.sink_count.
 770                                         bits.SINK_COUNT;
 771                 else
 772                         link->dpcd_sink_count = 1;
 773
 774                 dal_ddc_service_set_transaction_type(
 775                                                 link->ddc,
 776                                                 sink_caps.transaction_type);
 777
 778                 link->aux_mode = dal_ddc_service_is_in_aux_transaction_mode(
 779                                 link->ddc);
 780
 781                 sink_init_data.link = link;
 782                 sink_init_data.sink_signal = sink_caps.signal;
 783
 784                 sink = dc_sink_create(&sink_init_data);
 785                 if (!sink) {
 786                         DC_ERROR("Failed to create sink!\n");
 787                         if (prev_sink != NULL)
 788                                 dc_sink_release(prev_sink);
 789                         return false;
 790                 }
 791
 792                 sink->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
 793                 sink->converter_disable_audio = converter_disable_audio;
 794
 795                 link->local_sink = sink;
 796
 797                 edid_status = dm_helpers_read_local_edid(
 798                                 link->ctx,
 799                                 link,
 800                                 sink);
 801
 802                 switch (edid_status) {
 803                 case EDID_BAD_CHECKSUM:
 804                         DC_LOG_ERROR("EDID checksum invalid.\n");
 805                         break;
 806                 case EDID_NO_RESPONSE:
 807                         DC_LOG_ERROR("No EDID read.\n");
 808
 809                         /*
 810                          * Abort detection for non-DP connectors if we have
 811                          * no EDID
 812                          *
 813                          * DP needs to report as connected if HDP is high
 814                          * even if we have no EDID in order to go to
 815                          * fail-safe mode
 816                          */
 817                         if (dc_is_hdmi_signal(link->connector_signal) ||
 818                             dc_is_dvi_signal(link->connector_signal)) {
 819                                 if (prev_sink != NULL)
 820                                         dc_sink_release(prev_sink);
 821
 822                                 return false;
 823                         }
 824                 default:
 825                         break;
 826                 }
 827
 828                 // Check if edid is the same
 829                 if ((prev_sink != NULL) && ((edid_status == EDID_THE_SAME) || (edid_status == EDID_OK)))
 830                         same_edid = is_same_edid(&prev_sink->dc_edid, &sink->dc_edid);
 831
 832                 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 833                         sink_caps.transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX &&
 834                         reason != DETECT_REASON_HPDRX) {
 835                         /*
 836                          * TODO debug why Dell 2413 doesn't like
 837                          *  two link trainings
 838                          */
 839
 840                         /* deal with non-mst cases */
 841                         for (i = 0; i < LINK_TRAINING_MAX_VERIFY_RETRY; i++) {
 842                                 int fail_count = 0;
 843
 844                                 dp_verify_link_cap(link,
 845                                                   &link->reported_link_cap,
 846                                                   &fail_count);
 847
 848                                 if (fail_count == 0)
 849                                         break;
 850                         }
 851
 852                 } else {
 853                         // If edid is the same, then discard new sink and revert back to original sink
 854                         if (same_edid) {
 855                                 link_disconnect_remap(prev_sink, link);
 856                                 sink = prev_sink;
 857                                 prev_sink = NULL;
 858
 859                         }
 860                 }
 861
 862                 /* HDMI-DVI Dongle */
 863                 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
 864                                 !sink->edid_caps.edid_hdmi)
 865                         sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 866
 867                 /* Connectivity log: detection */
 868                 for (i = 0; i < sink->dc_edid.length / EDID_BLOCK_SIZE; i++) {
 869                         CONN_DATA_DETECT(link,
 870                                         &sink->dc_edid.raw_edid[i * EDID_BLOCK_SIZE],
 871                                         EDID_BLOCK_SIZE,
 872                                         "%s: [Block %d] ", sink->edid_caps.display_name, i);
 873                 }
 874
 875                 DC_LOG_DETECTION_EDID_PARSER("%s: "
 876                         "manufacturer_id = %X, "
 877                         "product_id = %X, "
 878                         "serial_number = %X, "
 879                         "manufacture_week = %d, "
 880                         "manufacture_year = %d, "
 881                         "display_name = %s, "
 882                         "speaker_flag = %d, "
 883                         "audio_mode_count = %d\n",
 884                         __func__,
 885                         sink->edid_caps.manufacturer_id,
 886                         sink->edid_caps.product_id,
 887                         sink->edid_caps.serial_number,
 888                         sink->edid_caps.manufacture_week,
 889                         sink->edid_caps.manufacture_year,
 890                         sink->edid_caps.display_name,
 891                         sink->edid_caps.speaker_flags,
 892                         sink->edid_caps.audio_mode_count);
 893
 894                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
 895                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
 896                                 "format_code = %d, "
 897                                 "channel_count = %d, "
 898                                 "sample_rate = %d, "
 899                                 "sample_size = %d\n",
 900                                 __func__,
 901                                 i,
 902                                 sink->edid_caps.audio_modes[i].format_code,
 903                                 sink->edid_caps.audio_modes[i].channel_count,
 904                                 sink->edid_caps.audio_modes[i].sample_rate,
 905                                 sink->edid_caps.audio_modes[i].sample_size);
 906                 }
 907
 908         } else {
 909                 /* From Connected-to-Disconnected. */
 910                 if (link->type == dc_connection_mst_branch) {
 911                         LINK_INFO("link=%d, mst branch is now Disconnected\n",
 912                                 link->link_index);
 913
 914                         dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
 915
 916                         link->mst_stream_alloc_table.stream_count = 0;
 917                         memset(link->mst_stream_alloc_table.stream_allocations, 0, sizeof(link->mst_stream_alloc_table.stream_allocations));
 918                 }
 919
 920                 link->type = dc_connection_none;
 921                 sink_caps.signal = SIGNAL_TYPE_NONE;
 922         }
 923
 924         LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n",
 925                 link->link_index, sink,
 926                 (sink_caps.signal == SIGNAL_TYPE_NONE ?
 927                         "Disconnected":"Connected"), prev_sink,
 928                         same_dpcd, same_edid);
 929
 930         if (prev_sink != NULL)
 931                 dc_sink_release(prev_sink);
 932
 933         return true;
 934 }
 935
 936 bool dc_link_get_hpd_state(struct dc_link *dc_link)
 937 {
 938         struct gpio *hpd_pin;
 939         uint32_t state;
 940
 941         hpd_pin = get_hpd_gpio(dc_link->ctx->dc_bios,
 942                                         dc_link->link_id, dc_link->ctx->gpio_service);
 943         if (hpd_pin == NULL)
 944                 ASSERT(false);
 945
 946         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 947         dal_gpio_get_value(hpd_pin, &state);
 948         dal_gpio_close(hpd_pin);
 949         dal_gpio_destroy_irq(&hpd_pin);
 950
 951         return state;
 952 }
 953
 954 static enum hpd_source_id get_hpd_line(
 955                 struct dc_link *link)
 956 {
 957         struct gpio *hpd;
 958         enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
 959
 960         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 961
 962         if (hpd) {
 963                 switch (dal_irq_get_source(hpd)) {
 964                 case DC_IRQ_SOURCE_HPD1:
 965                         hpd_id = HPD_SOURCEID1;
 966                 break;
 967                 case DC_IRQ_SOURCE_HPD2:
 968                         hpd_id = HPD_SOURCEID2;
 969                 break;
 970                 case DC_IRQ_SOURCE_HPD3:
 971                         hpd_id = HPD_SOURCEID3;
 972                 break;
 973                 case DC_IRQ_SOURCE_HPD4:
 974                         hpd_id = HPD_SOURCEID4;
 975                 break;
 976                 case DC_IRQ_SOURCE_HPD5:
 977                         hpd_id = HPD_SOURCEID5;
 978                 break;
 979                 case DC_IRQ_SOURCE_HPD6:
 980                         hpd_id = HPD_SOURCEID6;
 981                 break;
 982                 default:
 983                         BREAK_TO_DEBUGGER();
 984                 break;
 985                 }
 986
 987                 dal_gpio_destroy_irq(&hpd);
 988         }
 989
 990         return hpd_id;
 991 }
 992
 993 static enum channel_id get_ddc_line(struct dc_link *link)
 994 {
 995         struct ddc *ddc;
 996         enum channel_id channel = CHANNEL_ID_UNKNOWN;
 997
 998         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 999
1000         if (ddc) {
1001                 switch (dal_ddc_get_line(ddc)) {
1002                 case GPIO_DDC_LINE_DDC1:
1003                         channel = CHANNEL_ID_DDC1;
1004                         break;
1005                 case GPIO_DDC_LINE_DDC2:
1006                         channel = CHANNEL_ID_DDC2;
1007                         break;
1008                 case GPIO_DDC_LINE_DDC3:
1009                         channel = CHANNEL_ID_DDC3;
1010                         break;
1011                 case GPIO_DDC_LINE_DDC4:
1012                         channel = CHANNEL_ID_DDC4;
1013                         break;
1014                 case GPIO_DDC_LINE_DDC5:
1015                         channel = CHANNEL_ID_DDC5;
1016                         break;
1017                 case GPIO_DDC_LINE_DDC6:
1018                         channel = CHANNEL_ID_DDC6;
1019                         break;
1020                 case GPIO_DDC_LINE_DDC_VGA:
1021                         channel = CHANNEL_ID_DDC_VGA;
1022                         break;
1023                 case GPIO_DDC_LINE_I2C_PAD:
1024                         channel = CHANNEL_ID_I2C_PAD;
1025                         break;
1026                 default:
1027                         BREAK_TO_DEBUGGER();
1028                         break;
1029                 }
1030         }
1031
1032         return channel;
1033 }
1034
1035 static enum transmitter translate_encoder_to_transmitter(
1036         struct graphics_object_id encoder)
1037 {
1038         switch (encoder.id) {
1039         case ENCODER_ID_INTERNAL_UNIPHY:
1040                 switch (encoder.enum_id) {
1041                 case ENUM_ID_1:
1042                         return TRANSMITTER_UNIPHY_A;
1043                 case ENUM_ID_2:
1044                         return TRANSMITTER_UNIPHY_B;
1045                 default:
1046                         return TRANSMITTER_UNKNOWN;
1047                 }
1048         break;
1049         case ENCODER_ID_INTERNAL_UNIPHY1:
1050                 switch (encoder.enum_id) {
1051                 case ENUM_ID_1:
1052                         return TRANSMITTER_UNIPHY_C;
1053                 case ENUM_ID_2:
1054                         return TRANSMITTER_UNIPHY_D;
1055                 default:
1056                         return TRANSMITTER_UNKNOWN;
1057                 }
1058         break;
1059         case ENCODER_ID_INTERNAL_UNIPHY2:
1060                 switch (encoder.enum_id) {
1061                 case ENUM_ID_1:
1062                         return TRANSMITTER_UNIPHY_E;
1063                 case ENUM_ID_2:
1064                         return TRANSMITTER_UNIPHY_F;
1065                 default:
1066                         return TRANSMITTER_UNKNOWN;
1067                 }
1068         break;
1069         case ENCODER_ID_INTERNAL_UNIPHY3:
1070                 switch (encoder.enum_id) {
1071                 case ENUM_ID_1:
1072                         return TRANSMITTER_UNIPHY_G;
1073                 default:
1074                         return TRANSMITTER_UNKNOWN;
1075                 }
1076         break;
1077         case ENCODER_ID_EXTERNAL_NUTMEG:
1078                 switch (encoder.enum_id) {
1079                 case ENUM_ID_1:
1080                         return TRANSMITTER_NUTMEG_CRT;
1081                 default:
1082                         return TRANSMITTER_UNKNOWN;
1083                 }
1084         break;
1085         case ENCODER_ID_EXTERNAL_TRAVIS:
1086                 switch (encoder.enum_id) {
1087                 case ENUM_ID_1:
1088                         return TRANSMITTER_TRAVIS_CRT;
1089                 case ENUM_ID_2:
1090                         return TRANSMITTER_TRAVIS_LCD;
1091                 default:
1092                         return TRANSMITTER_UNKNOWN;
1093                 }
1094         break;
1095         default:
1096                 return TRANSMITTER_UNKNOWN;
1097         }
1098 }
1099
1100 static bool construct(
1101         struct dc_link *link,
1102         const struct link_init_data *init_params)
1103 {
1104         uint8_t i;
1105         struct gpio *hpd_gpio = NULL;
1106         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1107         struct dc_context *dc_ctx = init_params->ctx;
1108         struct encoder_init_data enc_init_data = { 0 };
1109         struct integrated_info info = {{{ 0 }}};
1110         struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1111         const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1112         DC_LOGGER_INIT(dc_ctx->logger);
1113
1114         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1115         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1116
1117         link->link_status.dpcd_caps = &link->dpcd_caps;
1118
1119         link->dc = init_params->dc;
1120         link->ctx = dc_ctx;
1121         link->link_index = init_params->link_index;
1122
1123         link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index);
1124
1125         if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1126                 dm_error("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1127                          __func__, init_params->connector_index,
1128                          link->link_id.type, OBJECT_TYPE_CONNECTOR);
1129                 goto create_fail;
1130         }
1131
1132         if (link->dc->res_pool->funcs->link_init)
1133                 link->dc->res_pool->funcs->link_init(link);
1134
1135         hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
1136
1137         if (hpd_gpio != NULL)
1138                 link->irq_source_hpd = dal_irq_get_source(hpd_gpio);
1139
1140         switch (link->link_id.id) {
1141         case CONNECTOR_ID_HDMI_TYPE_A:
1142                 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1143
1144                 break;
1145         case CONNECTOR_ID_SINGLE_LINK_DVID:
1146         case CONNECTOR_ID_SINGLE_LINK_DVII:
1147                 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1148                 break;
1149         case CONNECTOR_ID_DUAL_LINK_DVID:
1150         case CONNECTOR_ID_DUAL_LINK_DVII:
1151                 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1152                 break;
1153         case CONNECTOR_ID_DISPLAY_PORT:
1154                 link->connector_signal =        SIGNAL_TYPE_DISPLAY_PORT;
1155
1156                 if (hpd_gpio != NULL)
1157                         link->irq_source_hpd_rx =
1158                                         dal_irq_get_rx_source(hpd_gpio);
1159
1160                 break;
1161         case CONNECTOR_ID_EDP:
1162                 link->connector_signal = SIGNAL_TYPE_EDP;
1163
1164                 if (hpd_gpio != NULL) {
1165                         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1166                         link->irq_source_hpd_rx =
1167                                         dal_irq_get_rx_source(hpd_gpio);
1168                 }
1169                 break;
1170         case CONNECTOR_ID_LVDS:
1171                 link->connector_signal = SIGNAL_TYPE_LVDS;
1172                 break;
1173         default:
1174                 DC_LOG_WARNING("Unsupported Connector type:%d!\n", link->link_id.id);
1175                 goto create_fail;
1176         }
1177
1178         if (hpd_gpio != NULL) {
1179                 dal_gpio_destroy_irq(&hpd_gpio);
1180                 hpd_gpio = NULL;
1181         }
1182
1183         /* TODO: #DAL3 Implement id to str function.*/
1184         LINK_INFO("Connector[%d] description:"
1185                         "signal %d\n",
1186                         init_params->connector_index,
1187                         link->connector_signal);
1188
1189         ddc_service_init_data.ctx = link->ctx;
1190         ddc_service_init_data.id = link->link_id;
1191         ddc_service_init_data.link = link;
1192         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1193
1194         if (link->ddc == NULL) {
1195                 DC_ERROR("Failed to create ddc_service!\n");
1196                 goto ddc_create_fail;
1197         }
1198
1199         link->ddc_hw_inst =
1200                 dal_ddc_get_line(
1201                         dal_ddc_service_get_ddc_pin(link->ddc));
1202
1203         enc_init_data.ctx = dc_ctx;
1204         bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0, &enc_init_data.encoder);
1205         enc_init_data.connector = link->link_id;
1206         enc_init_data.channel = get_ddc_line(link);
1207         enc_init_data.hpd_source = get_hpd_line(link);
1208
1209         link->hpd_src = enc_init_data.hpd_source;
1210
1211         enc_init_data.transmitter =
1212                         translate_encoder_to_transmitter(enc_init_data.encoder);
1213         link->link_enc = link->dc->res_pool->funcs->link_enc_create(
1214                                                                 &enc_init_data);
1215
1216         if( link->link_enc == NULL) {
1217                 DC_ERROR("Failed to create link encoder!\n");
1218                 goto link_enc_create_fail;
1219         }
1220
1221         link->link_enc_hw_inst = link->link_enc->transmitter;
1222
1223         for (i = 0; i < 4; i++) {
1224                 if (BP_RESULT_OK !=
1225                                 bp_funcs->get_device_tag(dc_ctx->dc_bios, link->link_id, i, &link->device_tag)) {
1226                         DC_ERROR("Failed to find device tag!\n");
1227                         goto device_tag_fail;
1228                 }
1229
1230                 /* Look for device tag that matches connector signal,
1231                  * CRT for rgb, LCD for other supported signal tyes
1232                  */
1233                 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios, link->device_tag.dev_id))
1234                         continue;
1235                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT
1236                         && link->connector_signal != SIGNAL_TYPE_RGB)
1237                         continue;
1238                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD
1239                         && link->connector_signal == SIGNAL_TYPE_RGB)
1240                         continue;
1241                 break;
1242         }
1243
1244         if (bios->integrated_info)
1245                 info = *bios->integrated_info;
1246
1247         /* Look for channel mapping corresponding to connector and device tag */
1248         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1249                 struct external_display_path *path =
1250                         &info.ext_disp_conn_info.path[i];
1251                 if (path->device_connector_id.enum_id == link->link_id.enum_id
1252                         && path->device_connector_id.id == link->link_id.id
1253                         && path->device_connector_id.type == link->link_id.type) {
1254
1255                         if (link->device_tag.acpi_device != 0
1256                                 && path->device_acpi_enum == link->device_tag.acpi_device) {
1257                                 link->ddi_channel_mapping = path->channel_mapping;
1258                                 link->chip_caps = path->caps;
1259                         } else if (path->device_tag ==
1260                                         link->device_tag.dev_id.raw_device_tag) {
1261                                 link->ddi_channel_mapping = path->channel_mapping;
1262                                 link->chip_caps = path->caps;
1263                         }
1264                         break;
1265                 }
1266         }
1267
1268         /*
1269          * TODO check if GPIO programmed correctly
1270          *
1271          * If GPIO isn't programmed correctly HPD might not rise or drain
1272          * fast enough, leading to bounces.
1273          */
1274         program_hpd_filter(link);
1275
1276         return true;
1277 device_tag_fail:
1278         link->link_enc->funcs->destroy(&link->link_enc);
1279 link_enc_create_fail:
1280         dal_ddc_service_destroy(&link->ddc);
1281 ddc_create_fail:
1282 create_fail:
1283
1284         if (hpd_gpio != NULL) {
1285                 dal_gpio_destroy_irq(&hpd_gpio);
1286         }
1287
1288         return false;
1289 }
1290
1291 /*******************************************************************************
1292  * Public functions
1293  ******************************************************************************/
1294 struct dc_link *link_create(const struct link_init_data *init_params)
1295 {
1296         struct dc_link *link =
1297                         kzalloc(sizeof(*link), GFP_KERNEL);
1298
1299         if (NULL == link)
1300                 goto alloc_fail;
1301
1302         if (false == construct(link, init_params))
1303                 goto construct_fail;
1304
1305         return link;
1306
1307 construct_fail:
1308         kfree(link);
1309
1310 alloc_fail:
1311         return NULL;
1312 }
1313
1314 void link_destroy(struct dc_link **link)
1315 {
1316         destruct(*link);
1317         kfree(*link);
1318         *link = NULL;
1319 }
1320
1321 static void dpcd_configure_panel_mode(
1322         struct dc_link *link,
1323         enum dp_panel_mode panel_mode)
1324 {
1325         union dpcd_edp_config edp_config_set;
1326         bool panel_mode_edp = false;
1327         DC_LOGGER_INIT(link->ctx->logger);
1328
1329         memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
1330
1331         if (DP_PANEL_MODE_DEFAULT != panel_mode) {
1332
1333                 switch (panel_mode) {
1334                 case DP_PANEL_MODE_EDP:
1335                 case DP_PANEL_MODE_SPECIAL:
1336                         panel_mode_edp = true;
1337                         break;
1338
1339                 default:
1340                         break;
1341                 }
1342
1343                 /*set edp panel mode in receiver*/
1344                 core_link_read_dpcd(
1345                         link,
1346                         DP_EDP_CONFIGURATION_SET,
1347                         &edp_config_set.raw,
1348                         sizeof(edp_config_set.raw));
1349
1350                 if (edp_config_set.bits.PANEL_MODE_EDP
1351                         != panel_mode_edp) {
1352                         enum ddc_result result = DDC_RESULT_UNKNOWN;
1353
1354                         edp_config_set.bits.PANEL_MODE_EDP =
1355                         panel_mode_edp;
1356                         result = core_link_write_dpcd(
1357                                 link,
1358                                 DP_EDP_CONFIGURATION_SET,
1359                                 &edp_config_set.raw,
1360                                 sizeof(edp_config_set.raw));
1361
1362                         ASSERT(result == DDC_RESULT_SUCESSFULL);
1363                 }
1364         }
1365         DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
1366                         "eDP panel mode enabled: %d \n",
1367                         link->link_index,
1368                         link->dpcd_caps.panel_mode_edp,
1369                         panel_mode_edp);
1370 }
1371
1372 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1373 {
1374         struct dc_stream_state *stream = pipe_ctx->stream;
1375         struct dc_link *link = stream->sink->link;
1376         union down_spread_ctrl old_downspread;
1377         union down_spread_ctrl new_downspread;
1378
1379         core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1380                         &old_downspread.raw, sizeof(old_downspread));
1381
1382         new_downspread.raw = old_downspread.raw;
1383
1384         new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1385                         (stream->ignore_msa_timing_param) ? 1 : 0;
1386
1387         if (new_downspread.raw != old_downspread.raw) {
1388                 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1389                         &new_downspread.raw, sizeof(new_downspread));
1390         }
1391 }
1392
1393 static enum dc_status enable_link_dp(
1394                 struct dc_state *state,
1395                 struct pipe_ctx *pipe_ctx)
1396 {
1397         struct dc_stream_state *stream = pipe_ctx->stream;
1398         enum dc_status status;
1399         bool skip_video_pattern;
1400         struct dc_link *link = stream->sink->link;
1401         struct dc_link_settings link_settings = {0};
1402         enum dp_panel_mode panel_mode;
1403
1404         /* get link settings for video mode timing */
1405         decide_link_settings(stream, &link_settings);
1406
1407         pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1408                         link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1409         state->dccg->funcs->update_clocks(state->dccg, state, false);
1410
1411         dp_enable_link_phy(
1412                 link,
1413                 pipe_ctx->stream->signal,
1414                 pipe_ctx->clock_source->id,
1415                 &link_settings);
1416
1417         if (stream->sink->edid_caps.panel_patch.dppowerup_delay > 0) {
1418                 int delay_dp_power_up_in_ms = stream->sink->edid_caps.panel_patch.dppowerup_delay;
1419
1420                 msleep(delay_dp_power_up_in_ms);
1421         }
1422
1423         panel_mode = dp_get_panel_mode(link);
1424         dpcd_configure_panel_mode(link, panel_mode);
1425
1426         skip_video_pattern = true;
1427
1428         if (link_settings.link_rate == LINK_RATE_LOW)
1429                         skip_video_pattern = false;
1430
1431         if (perform_link_training_with_retries(
1432                         link,
1433                         &link_settings,
1434                         skip_video_pattern,
1435                         LINK_TRAINING_ATTEMPTS)) {
1436                 link->cur_link_settings = link_settings;
1437                 status = DC_OK;
1438         }
1439         else
1440                 status = DC_FAIL_DP_LINK_TRAINING;
1441
1442         return status;
1443 }
1444
1445 static enum dc_status enable_link_edp(
1446                 struct dc_state *state,
1447                 struct pipe_ctx *pipe_ctx)
1448 {
1449         enum dc_status status;
1450         struct dc_stream_state *stream = pipe_ctx->stream;
1451         struct dc_link *link = stream->sink->link;
1452         /*in case it is not on*/
1453         link->dc->hwss.edp_power_control(link, true);
1454         link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1455
1456         status = enable_link_dp(state, pipe_ctx);
1457
1458
1459         return status;
1460 }
1461
1462 static enum dc_status enable_link_dp_mst(
1463                 struct dc_state *state,
1464                 struct pipe_ctx *pipe_ctx)
1465 {
1466         struct dc_link *link = pipe_ctx->stream->sink->link;
1467
1468         /* sink signal type after MST branch is MST. Multiple MST sinks
1469          * share one link. Link DP PHY is enable or training only once.
1470          */
1471         if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
1472                 return DC_OK;
1473
1474         /* clear payload table */
1475         dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
1476
1477         /* set the sink to MST mode before enabling the link */
1478         dp_enable_mst_on_sink(link, true);
1479
1480         return enable_link_dp(state, pipe_ctx);
1481 }
1482
1483 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
1484                 enum engine_id eng_id,
1485                 struct ext_hdmi_settings *settings)
1486 {
1487         bool result = false;
1488         int i = 0;
1489         struct integrated_info *integrated_info =
1490                         pipe_ctx->stream->ctx->dc_bios->integrated_info;
1491
1492         if (integrated_info == NULL)
1493                 return false;
1494
1495         /*
1496          * Get retimer settings from sbios for passing SI eye test for DCE11
1497          * The setting values are varied based on board revision and port id
1498          * Therefore the setting values of each ports is passed by sbios.
1499          */
1500
1501         // Check if current bios contains ext Hdmi settings
1502         if (integrated_info->gpu_cap_info & 0x20) {
1503                 switch (eng_id) {
1504                 case ENGINE_ID_DIGA:
1505                         settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
1506                         settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
1507                         settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
1508                         memmove(settings->reg_settings,
1509                                         integrated_info->dp0_ext_hdmi_reg_settings,
1510                                         sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
1511                         memmove(settings->reg_settings_6g,
1512                                         integrated_info->dp0_ext_hdmi_6g_reg_settings,
1513                                         sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
1514                         result = true;
1515                         break;
1516                 case ENGINE_ID_DIGB:
1517                         settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
1518                         settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
1519                         settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
1520                         memmove(settings->reg_settings,
1521                                         integrated_info->dp1_ext_hdmi_reg_settings,
1522                                         sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
1523                         memmove(settings->reg_settings_6g,
1524                                         integrated_info->dp1_ext_hdmi_6g_reg_settings,
1525                                         sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
1526                         result = true;
1527                         break;
1528                 case ENGINE_ID_DIGC:
1529                         settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
1530                         settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
1531                         settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
1532                         memmove(settings->reg_settings,
1533                                         integrated_info->dp2_ext_hdmi_reg_settings,
1534                                         sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
1535                         memmove(settings->reg_settings_6g,
1536                                         integrated_info->dp2_ext_hdmi_6g_reg_settings,
1537                                         sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
1538                         result = true;
1539                         break;
1540                 case ENGINE_ID_DIGD:
1541                         settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
1542                         settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
1543                         settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
1544                         memmove(settings->reg_settings,
1545                                         integrated_info->dp3_ext_hdmi_reg_settings,
1546                                         sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
1547                         memmove(settings->reg_settings_6g,
1548                                         integrated_info->dp3_ext_hdmi_6g_reg_settings,
1549                                         sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
1550                         result = true;
1551                         break;
1552                 default:
1553                         break;
1554                 }
1555
1556                 if (result == true) {
1557                         // Validate settings from bios integrated info table
1558                         if (settings->slv_addr == 0)
1559                                 return false;
1560                         if (settings->reg_num > 9)
1561                                 return false;
1562                         if (settings->reg_num_6g > 3)
1563                                 return false;
1564
1565                         for (i = 0; i < settings->reg_num; i++) {
1566                                 if (settings->reg_settings[i].i2c_reg_index > 0x20)
1567                                         return false;
1568                         }
1569
1570                         for (i = 0; i < settings->reg_num_6g; i++) {
1571                                 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
1572                                         return false;
1573                         }
1574                 }
1575         }
1576
1577         return result;
1578 }
1579
1580 static bool i2c_write(struct pipe_ctx *pipe_ctx,
1581                 uint8_t address, uint8_t *buffer, uint32_t length)
1582 {
1583         struct i2c_command cmd = {0};
1584         struct i2c_payload payload = {0};
1585
1586         memset(&payload, 0, sizeof(payload));
1587         memset(&cmd, 0, sizeof(cmd));
1588
1589         cmd.number_of_payloads = 1;
1590         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1591         cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
1592
1593         payload.address = address;
1594         payload.data = buffer;
1595         payload.length = length;
1596         payload.write = true;
1597         cmd.payloads = &payload;
1598
1599         if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
1600                         pipe_ctx->stream->sink->link, &cmd))
1601                 return true;
1602
1603         return false;
1604 }
1605
1606 static void write_i2c_retimer_setting(
1607                 struct pipe_ctx *pipe_ctx,
1608                 bool is_vga_mode,
1609                 bool is_over_340mhz,
1610                 struct ext_hdmi_settings *settings)
1611 {
1612         uint8_t slave_address = (settings->slv_addr >> 1);
1613         uint8_t buffer[2];
1614         const uint8_t apply_rx_tx_change = 0x4;
1615         uint8_t offset = 0xA;
1616         uint8_t value = 0;
1617         int i = 0;
1618         bool i2c_success = false;
1619         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1620
1621         memset(&buffer, 0, sizeof(buffer));
1622
1623         /* Start Ext-Hdmi programming*/
1624
1625         for (i = 0; i < settings->reg_num; i++) {
1626                 /* Apply 3G settings */
1627                 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1628
1629                         buffer[0] = settings->reg_settings[i].i2c_reg_index;
1630                         buffer[1] = settings->reg_settings[i].i2c_reg_val;
1631                         i2c_success = i2c_write(pipe_ctx, slave_address,
1632                                                 buffer, sizeof(buffer));
1633                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1634                                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1635                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1636
1637                         if (!i2c_success)
1638                                 /* Write failure */
1639                                 ASSERT(i2c_success);
1640
1641                         /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1642                          * needs to be set to 1 on every 0xA-0xC write.
1643                          */
1644                         if (settings->reg_settings[i].i2c_reg_index == 0xA ||
1645                                 settings->reg_settings[i].i2c_reg_index == 0xB ||
1646                                 settings->reg_settings[i].i2c_reg_index == 0xC) {
1647
1648                                 /* Query current value from offset 0xA */
1649                                 if (settings->reg_settings[i].i2c_reg_index == 0xA)
1650                                         value = settings->reg_settings[i].i2c_reg_val;
1651                                 else {
1652                                         i2c_success =
1653                                                 dal_ddc_service_query_ddc_data(
1654                                                 pipe_ctx->stream->sink->link->ddc,
1655                                                 slave_address, &offset, 1, &value, 1);
1656                                         if (!i2c_success)
1657                                                 /* Write failure */
1658                                                 ASSERT(i2c_success);
1659                                 }
1660
1661                                 buffer[0] = offset;
1662                                 /* Set APPLY_RX_TX_CHANGE bit to 1 */
1663                                 buffer[1] = value | apply_rx_tx_change;
1664                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1665                                                 buffer, sizeof(buffer));
1666                                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1667                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1668                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1669                                 if (!i2c_success)
1670                                         /* Write failure */
1671                                         ASSERT(i2c_success);
1672                         }
1673                 }
1674         }
1675
1676         /* Apply 3G settings */
1677         if (is_over_340mhz) {
1678                 for (i = 0; i < settings->reg_num_6g; i++) {
1679                         /* Apply 3G settings */
1680                         if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1681
1682                                 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
1683                                 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
1684                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1685                                                         buffer, sizeof(buffer));
1686                                 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
1687                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1688                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1689
1690                                 if (!i2c_success)
1691                                         /* Write failure */
1692                                         ASSERT(i2c_success);
1693
1694                                 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1695                                  * needs to be set to 1 on every 0xA-0xC write.
1696                                  */
1697                                 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
1698                                         settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
1699                                         settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
1700
1701                                         /* Query current value from offset 0xA */
1702                                         if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
1703                                                 value = settings->reg_settings_6g[i].i2c_reg_val;
1704                                         else {
1705                                                 i2c_success =
1706                                                                 dal_ddc_service_query_ddc_data(
1707                                                                 pipe_ctx->stream->sink->link->ddc,
1708                                                                 slave_address, &offset, 1, &value, 1);
1709                                                 if (!i2c_success)
1710                                                         /* Write failure */
1711                                                         ASSERT(i2c_success);
1712                                         }
1713
1714                                         buffer[0] = offset;
1715                                         /* Set APPLY_RX_TX_CHANGE bit to 1 */
1716                                         buffer[1] = value | apply_rx_tx_change;
1717                                         i2c_success = i2c_write(pipe_ctx, slave_address,
1718                                                         buffer, sizeof(buffer));
1719                                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1720                                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1721                                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1722                                         if (!i2c_success)
1723                                                 /* Write failure */
1724                                                 ASSERT(i2c_success);
1725                                 }
1726                         }
1727                 }
1728         }
1729
1730         if (is_vga_mode) {
1731                 /* Program additional settings if using 640x480 resolution */
1732
1733                 /* Write offset 0xFF to 0x01 */
1734                 buffer[0] = 0xff;
1735                 buffer[1] = 0x01;
1736                 i2c_success = i2c_write(pipe_ctx, slave_address,
1737                                 buffer, sizeof(buffer));
1738                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1739                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1740                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1741                 if (!i2c_success)
1742                         /* Write failure */
1743                         ASSERT(i2c_success);
1744
1745                 /* Write offset 0x00 to 0x23 */
1746                 buffer[0] = 0x00;
1747                 buffer[1] = 0x23;
1748                 i2c_success = i2c_write(pipe_ctx, slave_address,
1749                                 buffer, sizeof(buffer));
1750                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1751                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1752                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1753                 if (!i2c_success)
1754                         /* Write failure */
1755                         ASSERT(i2c_success);
1756
1757                 /* Write offset 0xff to 0x00 */
1758                 buffer[0] = 0xff;
1759                 buffer[1] = 0x00;
1760                 i2c_success = i2c_write(pipe_ctx, slave_address,
1761                                 buffer, sizeof(buffer));
1762                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1763                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1764                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1765                 if (!i2c_success)
1766                         /* Write failure */
1767                         ASSERT(i2c_success);
1768
1769         }
1770 }
1771
1772 static void write_i2c_default_retimer_setting(
1773                 struct pipe_ctx *pipe_ctx,
1774                 bool is_vga_mode,
1775                 bool is_over_340mhz)
1776 {
1777         uint8_t slave_address = (0xBA >> 1);
1778         uint8_t buffer[2];
1779         bool i2c_success = false;
1780         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1781
1782         memset(&buffer, 0, sizeof(buffer));
1783
1784         /* Program Slave Address for tuning single integrity */
1785         /* Write offset 0x0A to 0x13 */
1786         buffer[0] = 0x0A;
1787         buffer[1] = 0x13;
1788         i2c_success = i2c_write(pipe_ctx, slave_address,
1789                         buffer, sizeof(buffer));
1790         RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
1791                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1792                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1793         if (!i2c_success)
1794                 /* Write failure */
1795                 ASSERT(i2c_success);
1796
1797         /* Write offset 0x0A to 0x17 */
1798         buffer[0] = 0x0A;
1799         buffer[1] = 0x17;
1800         i2c_success = i2c_write(pipe_ctx, slave_address,
1801                         buffer, sizeof(buffer));
1802         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1803                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1804                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1805         if (!i2c_success)
1806                 /* Write failure */
1807                 ASSERT(i2c_success);
1808
1809         /* Write offset 0x0B to 0xDA or 0xD8 */
1810         buffer[0] = 0x0B;
1811         buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
1812         i2c_success = i2c_write(pipe_ctx, slave_address,
1813                         buffer, sizeof(buffer));
1814         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1815                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1816                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1817         if (!i2c_success)
1818                 /* Write failure */
1819                 ASSERT(i2c_success);
1820
1821         /* Write offset 0x0A to 0x17 */
1822         buffer[0] = 0x0A;
1823         buffer[1] = 0x17;
1824         i2c_success = i2c_write(pipe_ctx, slave_address,
1825                         buffer, sizeof(buffer));
1826         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1827                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1828                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1829         if (!i2c_success)
1830                 /* Write failure */
1831                 ASSERT(i2c_success);
1832
1833         /* Write offset 0x0C to 0x1D or 0x91 */
1834         buffer[0] = 0x0C;
1835         buffer[1] = is_over_340mhz ? 0x1D : 0x91;
1836         i2c_success = i2c_write(pipe_ctx, slave_address,
1837                         buffer, sizeof(buffer));
1838         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1839                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1840                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1841         if (!i2c_success)
1842                 /* Write failure */
1843                 ASSERT(i2c_success);
1844
1845         /* Write offset 0x0A to 0x17 */
1846         buffer[0] = 0x0A;
1847         buffer[1] = 0x17;
1848         i2c_success = i2c_write(pipe_ctx, slave_address,
1849                         buffer, sizeof(buffer));
1850         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1851                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1852                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1853         if (!i2c_success)
1854                 /* Write failure */
1855                 ASSERT(i2c_success);
1856
1857
1858         if (is_vga_mode) {
1859                 /* Program additional settings if using 640x480 resolution */
1860
1861                 /* Write offset 0xFF to 0x01 */
1862                 buffer[0] = 0xff;
1863                 buffer[1] = 0x01;
1864                 i2c_success = i2c_write(pipe_ctx, slave_address,
1865                                 buffer, sizeof(buffer));
1866                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1867                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1868                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1869                 if (!i2c_success)
1870                         /* Write failure */
1871                         ASSERT(i2c_success);
1872
1873                 /* Write offset 0x00 to 0x23 */
1874                 buffer[0] = 0x00;
1875                 buffer[1] = 0x23;
1876                 i2c_success = i2c_write(pipe_ctx, slave_address,
1877                                 buffer, sizeof(buffer));
1878                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1879                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1880                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1881                 if (!i2c_success)
1882                         /* Write failure */
1883                         ASSERT(i2c_success);
1884
1885                 /* Write offset 0xff to 0x00 */
1886                 buffer[0] = 0xff;
1887                 buffer[1] = 0x00;
1888                 i2c_success = i2c_write(pipe_ctx, slave_address,
1889                                 buffer, sizeof(buffer));
1890                 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
1891                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
1892                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1893                 if (!i2c_success)
1894                         /* Write failure */
1895                         ASSERT(i2c_success);
1896         }
1897 }
1898
1899 static void write_i2c_redriver_setting(
1900                 struct pipe_ctx *pipe_ctx,
1901                 bool is_over_340mhz)
1902 {
1903         uint8_t slave_address = (0xF0 >> 1);
1904         uint8_t buffer[16];
1905         bool i2c_success = false;
1906         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1907
1908         memset(&buffer, 0, sizeof(buffer));
1909
1910         // Program Slave Address for tuning single integrity
1911         buffer[3] = 0x4E;
1912         buffer[4] = 0x4E;
1913         buffer[5] = 0x4E;
1914         buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
1915
1916         i2c_success = i2c_write(pipe_ctx, slave_address,
1917                                         buffer, sizeof(buffer));
1918         RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
1919                 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
1920                 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
1921                 i2c_success = %d\n",
1922                 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
1923
1924         if (!i2c_success)
1925                 /* Write failure */
1926                 ASSERT(i2c_success);
1927 }
1928
1929 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
1930 {
1931         struct dc_stream_state *stream = pipe_ctx->stream;
1932         struct dc_link *link = stream->sink->link;
1933         enum dc_color_depth display_color_depth;
1934         enum engine_id eng_id;
1935         struct ext_hdmi_settings settings = {0};
1936         bool is_over_340mhz = false;
1937         bool is_vga_mode = (stream->timing.h_addressable == 640)
1938                         && (stream->timing.v_addressable == 480);
1939
1940         if (stream->phy_pix_clk == 0)
1941                 stream->phy_pix_clk = stream->timing.pix_clk_khz;
1942         if (stream->phy_pix_clk > 340000)
1943                 is_over_340mhz = true;
1944
1945         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
1946                 unsigned short masked_chip_caps = pipe_ctx->stream->sink->link->chip_caps &
1947                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
1948                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
1949                         /* DP159, Retimer settings */
1950                         eng_id = pipe_ctx->stream_res.stream_enc->id;
1951
1952                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
1953                                 write_i2c_retimer_setting(pipe_ctx,
1954                                                 is_vga_mode, is_over_340mhz, &settings);
1955                         } else {
1956                                 write_i2c_default_retimer_setting(pipe_ctx,
1957                                                 is_vga_mode, is_over_340mhz);
1958                         }
1959                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
1960                         /* PI3EQX1204, Redriver settings */
1961                         write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
1962                 }
1963         }
1964
1965         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1966                 dal_ddc_service_write_scdc_data(
1967                         stream->sink->link->ddc,
1968                         stream->phy_pix_clk,
1969                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
1970
1971         memset(&stream->sink->link->cur_link_settings, 0,
1972                         sizeof(struct dc_link_settings));
1973
1974         display_color_depth = stream->timing.display_color_depth;
1975         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1976                 display_color_depth = COLOR_DEPTH_888;
1977
1978         link->link_enc->funcs->enable_tmds_output(
1979                         link->link_enc,
1980                         pipe_ctx->clock_source->id,
1981                         display_color_depth,
1982                         pipe_ctx->stream->signal,
1983                         stream->phy_pix_clk);
1984
1985         if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
1986                 dal_ddc_service_read_scdc_data(link->ddc);
1987 }
1988
1989 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
1990 {
1991         struct dc_stream_state *stream = pipe_ctx->stream;
1992         struct dc_link *link = stream->sink->link;
1993
1994         if (stream->phy_pix_clk == 0)
1995                 stream->phy_pix_clk = stream->timing.pix_clk_khz;
1996
1997         memset(&stream->sink->link->cur_link_settings, 0,
1998                         sizeof(struct dc_link_settings));
1999
2000         link->link_enc->funcs->enable_lvds_output(
2001                         link->link_enc,
2002                         pipe_ctx->clock_source->id,
2003                         stream->phy_pix_clk);
2004
2005 }
2006
2007 /****************************enable_link***********************************/
2008 static enum dc_status enable_link(
2009                 struct dc_state *state,
2010                 struct pipe_ctx *pipe_ctx)
2011 {
2012         enum dc_status status = DC_ERROR_UNEXPECTED;
2013         switch (pipe_ctx->stream->signal) {
2014         case SIGNAL_TYPE_DISPLAY_PORT:
2015                 status = enable_link_dp(state, pipe_ctx);
2016                 break;
2017         case SIGNAL_TYPE_EDP:
2018                 status = enable_link_edp(state, pipe_ctx);
2019                 break;
2020         case SIGNAL_TYPE_DISPLAY_PORT_MST:
2021                 status = enable_link_dp_mst(state, pipe_ctx);
2022                 msleep(200);
2023                 break;
2024         case SIGNAL_TYPE_DVI_SINGLE_LINK:
2025         case SIGNAL_TYPE_DVI_DUAL_LINK:
2026         case SIGNAL_TYPE_HDMI_TYPE_A:
2027                 enable_link_hdmi(pipe_ctx);
2028                 status = DC_OK;
2029                 break;
2030         case SIGNAL_TYPE_LVDS:
2031                 enable_link_lvds(pipe_ctx);
2032                 status = DC_OK;
2033                 break;
2034         case SIGNAL_TYPE_VIRTUAL:
2035                 status = DC_OK;
2036                 break;
2037         default:
2038                 break;
2039         }
2040
2041         return status;
2042 }
2043
2044 static void disable_link(struct dc_link *link, enum signal_type signal)
2045 {
2046         /*
2047          * TODO: implement call for dp_set_hw_test_pattern
2048          * it is needed for compliance testing
2049          */
2050
2051         /* here we need to specify that encoder output settings
2052          * need to be calculated as for the set mode,
2053          * it will lead to querying dynamic link capabilities
2054          * which should be done before enable output */
2055
2056         if (dc_is_dp_signal(signal)) {
2057                 /* SST DP, eDP */
2058                 if (dc_is_dp_sst_signal(signal))
2059                         dp_disable_link_phy(link, signal);
2060                 else
2061                         dp_disable_link_phy_mst(link, signal);
2062         } else
2063                 link->link_enc->funcs->disable_output(link->link_enc, signal);
2064 }
2065
2066 static bool dp_active_dongle_validate_timing(
2067                 const struct dc_crtc_timing *timing,
2068                 const struct dpcd_caps *dpcd_caps)
2069 {
2070         unsigned int required_pix_clk = timing->pix_clk_khz;
2071         const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2072
2073         switch (dpcd_caps->dongle_type) {
2074         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2075         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2076         case DISPLAY_DONGLE_DP_DVI_DONGLE:
2077                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2078                         return true;
2079                 else
2080                         return false;
2081         default:
2082                 break;
2083         }
2084
2085         if (dongle_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
2086                 dongle_caps->extendedCapValid == false)
2087                 return true;
2088
2089         /* Check Pixel Encoding */
2090         switch (timing->pixel_encoding) {
2091         case PIXEL_ENCODING_RGB:
2092         case PIXEL_ENCODING_YCBCR444:
2093                 break;
2094         case PIXEL_ENCODING_YCBCR422:
2095                 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2096                         return false;
2097                 break;
2098         case PIXEL_ENCODING_YCBCR420:
2099                 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2100                         return false;
2101                 break;
2102         default:
2103                 /* Invalid Pixel Encoding*/
2104                 return false;
2105         }
2106
2107
2108         /* Check Color Depth and Pixel Clock */
2109         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2110                 required_pix_clk /= 2;
2111         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2112                 required_pix_clk = required_pix_clk * 2 / 3;
2113
2114         switch (timing->display_color_depth) {
2115         case COLOR_DEPTH_666:
2116         case COLOR_DEPTH_888:
2117                 /*888 and 666 should always be supported*/
2118                 break;
2119         case COLOR_DEPTH_101010:
2120                 if (dongle_caps->dp_hdmi_max_bpc < 10)
2121                         return false;
2122                 required_pix_clk = required_pix_clk * 10 / 8;
2123                 break;
2124         case COLOR_DEPTH_121212:
2125                 if (dongle_caps->dp_hdmi_max_bpc < 12)
2126                         return false;
2127                 required_pix_clk = required_pix_clk * 12 / 8;
2128                 break;
2129
2130         case COLOR_DEPTH_141414:
2131         case COLOR_DEPTH_161616:
2132         default:
2133                 /* These color depths are currently not supported */
2134                 return false;
2135         }
2136
2137         if (required_pix_clk > dongle_caps->dp_hdmi_max_pixel_clk)
2138                 return false;
2139
2140         return true;
2141 }
2142
2143 enum dc_status dc_link_validate_mode_timing(
2144                 const struct dc_stream_state *stream,
2145                 struct dc_link *link,
2146                 const struct dc_crtc_timing *timing)
2147 {
2148         uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk;
2149         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2150
2151         /* A hack to avoid failing any modes for EDID override feature on
2152          * topology change such as lower quality cable for DP or different dongle
2153          */
2154         if (link->remote_sinks[0])
2155                 return DC_OK;
2156
2157         /* Passive Dongle */
2158         if (0 != max_pix_clk && timing->pix_clk_khz > max_pix_clk)
2159                 return DC_EXCEED_DONGLE_CAP;
2160
2161         /* Active Dongle*/
2162         if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2163                 return DC_EXCEED_DONGLE_CAP;
2164
2165         switch (stream->signal) {
2166         case SIGNAL_TYPE_EDP:
2167         case SIGNAL_TYPE_DISPLAY_PORT:
2168                 if (!dp_validate_mode_timing(
2169                                 link,
2170                                 timing))
2171                         return DC_NO_DP_LINK_BANDWIDTH;
2172                 break;
2173
2174         default:
2175                 break;
2176         }
2177
2178         return DC_OK;
2179 }
2180
2181 int dc_link_get_backlight_level(const struct dc_link *link)
2182 {
2183         struct abm *abm = link->ctx->dc->res_pool->abm;
2184
2185         if (abm == NULL || abm->funcs->get_current_backlight == NULL)
2186                 return DC_ERROR_UNEXPECTED;
2187
2188         return (int) abm->funcs->get_current_backlight(abm);
2189 }
2190
2191 bool dc_link_set_backlight_level(const struct dc_link *link,
2192                 uint32_t backlight_pwm_u16_16,
2193                 uint32_t frame_ramp)
2194 {
2195         struct dc  *core_dc = link->ctx->dc;
2196         struct abm *abm = core_dc->res_pool->abm;
2197         struct dmcu *dmcu = core_dc->res_pool->dmcu;
2198         unsigned int controller_id = 0;
2199         bool use_smooth_brightness = true;
2200         int i;
2201         DC_LOGGER_INIT(link->ctx->logger);
2202
2203         if ((dmcu == NULL) ||
2204                 (abm == NULL) ||
2205                 (abm->funcs->set_backlight_level_pwm == NULL))
2206                 return false;
2207
2208         use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2209
2210         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
2211                         backlight_pwm_u16_16, backlight_pwm_u16_16);
2212
2213         if (dc_is_embedded_signal(link->connector_signal)) {
2214                 for (i = 0; i < MAX_PIPES; i++) {
2215                         if (core_dc->current_state->res_ctx.pipe_ctx[i].stream) {
2216                                 if (core_dc->current_state->res_ctx.
2217                                                 pipe_ctx[i].stream->sink->link
2218                                                 == link)
2219                                         /* DMCU -1 for all controller id values,
2220                                          * therefore +1 here
2221                                          */
2222                                         controller_id =
2223                                                 core_dc->current_state->
2224                                                 res_ctx.pipe_ctx[i].stream_res.tg->inst +
2225                                                 1;
2226                         }
2227                 }
2228                 abm->funcs->set_backlight_level_pwm(
2229                                 abm,
2230                                 backlight_pwm_u16_16,
2231                                 frame_ramp,
2232                                 controller_id,
2233                                 use_smooth_brightness);
2234         }
2235
2236         return true;
2237 }
2238
2239 bool dc_link_set_abm_disable(const struct dc_link *link)
2240 {
2241         struct dc  *core_dc = link->ctx->dc;
2242         struct abm *abm = core_dc->res_pool->abm;
2243
2244         if ((abm == NULL) || (abm->funcs->set_backlight_level_pwm == NULL))
2245                 return false;
2246
2247         abm->funcs->set_abm_immediate_disable(abm);
2248
2249         return true;
2250 }
2251
2252 bool dc_link_set_psr_enable(const struct dc_link *link, bool enable, bool wait)
2253 {
2254         struct dc  *core_dc = link->ctx->dc;
2255         struct dmcu *dmcu = core_dc->res_pool->dmcu;
2256
2257         if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_enabled)
2258                 dmcu->funcs->set_psr_enable(dmcu, enable, wait);
2259
2260         return true;
2261 }
2262
2263 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
2264 {
2265         return &link->link_status;
2266 }
2267
2268 void core_link_resume(struct dc_link *link)
2269 {
2270         if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
2271                 program_hpd_filter(link);
2272 }
2273
2274 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
2275 {
2276         struct dc_link_settings *link_settings =
2277                         &stream->sink->link->cur_link_settings;
2278         uint32_t link_rate_in_mbps =
2279                         link_settings->link_rate * LINK_RATE_REF_FREQ_IN_MHZ;
2280         struct fixed31_32 mbps = dc_fixpt_from_int(
2281                         link_rate_in_mbps * link_settings->lane_count);
2282
2283         return dc_fixpt_div_int(mbps, 54);
2284 }
2285
2286 static int get_color_depth(enum dc_color_depth color_depth)
2287 {
2288         switch (color_depth) {
2289         case COLOR_DEPTH_666: return 6;
2290         case COLOR_DEPTH_888: return 8;
2291         case COLOR_DEPTH_101010: return 10;
2292         case COLOR_DEPTH_121212: return 12;
2293         case COLOR_DEPTH_141414: return 14;
2294         case COLOR_DEPTH_161616: return 16;
2295         default: return 0;
2296         }
2297 }
2298
2299 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
2300 {
2301         uint32_t bpc;
2302         uint64_t kbps;
2303         struct fixed31_32 peak_kbps;
2304         uint32_t numerator;
2305         uint32_t denominator;
2306
2307         bpc = get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth);
2308         kbps = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk * bpc * 3;
2309
2310         /*
2311          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
2312          * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
2313          * common multiplier to render an integer PBN for all link rate/lane
2314          * counts combinations
2315          * calculate
2316          * peak_kbps *= (1006/1000)
2317          * peak_kbps *= (64/54)
2318          * peak_kbps *= 8    convert to bytes
2319          */
2320
2321         numerator = 64 * PEAK_FACTOR_X1000;
2322         denominator = 54 * 8 * 1000 * 1000;
2323         kbps *= numerator;
2324         peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
2325
2326         return peak_kbps;
2327 }
2328
2329 static void update_mst_stream_alloc_table(
2330         struct dc_link *link,
2331         struct stream_encoder *stream_enc,
2332         const struct dp_mst_stream_allocation_table *proposed_table)
2333 {
2334         struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
2335                         { 0 } };
2336         struct link_mst_stream_allocation *dc_alloc;
2337
2338         int i;
2339         int j;
2340
2341         /* if DRM proposed_table has more than one new payload */
2342         ASSERT(proposed_table->stream_count -
2343                         link->mst_stream_alloc_table.stream_count < 2);
2344
2345         /* copy proposed_table to link, add stream encoder */
2346         for (i = 0; i < proposed_table->stream_count; i++) {
2347
2348                 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
2349                         dc_alloc =
2350                         &link->mst_stream_alloc_table.stream_allocations[j];
2351
2352                         if (dc_alloc->vcp_id ==
2353                                 proposed_table->stream_allocations[i].vcp_id) {
2354
2355                                 work_table[i] = *dc_alloc;
2356                                 break; /* exit j loop */
2357                         }
2358                 }
2359
2360                 /* new vcp_id */
2361                 if (j == link->mst_stream_alloc_table.stream_count) {
2362                         work_table[i].vcp_id =
2363                                 proposed_table->stream_allocations[i].vcp_id;
2364                         work_table[i].slot_count =
2365                                 proposed_table->stream_allocations[i].slot_count;
2366                         work_table[i].stream_enc = stream_enc;
2367                 }
2368         }
2369
2370         /* update link->mst_stream_alloc_table with work_table */
2371         link->mst_stream_alloc_table.stream_count =
2372                         proposed_table->stream_count;
2373         for (i = 0; i < MAX_CONTROLLER_NUM; i++)
2374                 link->mst_stream_alloc_table.stream_allocations[i] =
2375                                 work_table[i];
2376 }
2377
2378 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
2379  * because stream_encoder is not exposed to dm
2380  */
2381 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
2382 {
2383         struct dc_stream_state *stream = pipe_ctx->stream;
2384         struct dc_link *link = stream->sink->link;
2385         struct link_encoder *link_encoder = link->link_enc;
2386         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2387         struct dp_mst_stream_allocation_table proposed_table = {0};
2388         struct fixed31_32 avg_time_slots_per_mtp;
2389         struct fixed31_32 pbn;
2390         struct fixed31_32 pbn_per_slot;
2391         uint8_t i;
2392         DC_LOGGER_INIT(link->ctx->logger);
2393
2394         /* enable_link_dp_mst already check link->enabled_stream_count
2395          * and stream is in link->stream[]. This is called during set mode,
2396          * stream_enc is available.
2397          */
2398
2399         /* get calculate VC payload for stream: stream_alloc */
2400         if (dm_helpers_dp_mst_write_payload_allocation_table(
2401                 stream->ctx,
2402                 stream,
2403                 &proposed_table,
2404                 true)) {
2405                 update_mst_stream_alloc_table(
2406                                         link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2407         }
2408         else
2409                 DC_LOG_WARNING("Failed to update"
2410                                 "MST allocation table for"
2411                                 "pipe idx:%d\n",
2412                                 pipe_ctx->pipe_idx);
2413
2414         DC_LOG_MST("%s  "
2415                         "stream_count: %d: \n ",
2416                         __func__,
2417                         link->mst_stream_alloc_table.stream_count);
2418
2419         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2420                 DC_LOG_MST("stream_enc[%d]: %p      "
2421                 "stream[%d].vcp_id: %d      "
2422                 "stream[%d].slot_count: %d\n",
2423                 i,
2424                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2425                 i,
2426                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2427                 i,
2428                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2429         }
2430
2431         ASSERT(proposed_table.stream_count > 0);
2432
2433         /* program DP source TX for payload */
2434         link_encoder->funcs->update_mst_stream_allocation_table(
2435                 link_encoder,
2436                 &link->mst_stream_alloc_table);
2437
2438         /* send down message */
2439         dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2440                         stream->ctx,
2441                         stream);
2442
2443         dm_helpers_dp_mst_send_payload_allocation(
2444                         stream->ctx,
2445                         stream,
2446                         true);
2447
2448         /* slot X.Y for only current stream */
2449         pbn_per_slot = get_pbn_per_slot(stream);
2450         pbn = get_pbn_from_timing(pipe_ctx);
2451         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
2452
2453         stream_encoder->funcs->set_mst_bandwidth(
2454                 stream_encoder,
2455                 avg_time_slots_per_mtp);
2456
2457         return DC_OK;
2458
2459 }
2460
2461 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
2462 {
2463         struct dc_stream_state *stream = pipe_ctx->stream;
2464         struct dc_link *link = stream->sink->link;
2465         struct link_encoder *link_encoder = link->link_enc;
2466         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2467         struct dp_mst_stream_allocation_table proposed_table = {0};
2468         struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
2469         uint8_t i;
2470         bool mst_mode = (link->type == dc_connection_mst_branch);
2471         DC_LOGGER_INIT(link->ctx->logger);
2472
2473         /* deallocate_mst_payload is called before disable link. When mode or
2474          * disable/enable monitor, new stream is created which is not in link
2475          * stream[] yet. For this, payload is not allocated yet, so de-alloc
2476          * should not done. For new mode set, map_resources will get engine
2477          * for new stream, so stream_enc->id should be validated until here.
2478          */
2479
2480         /* slot X.Y */
2481         stream_encoder->funcs->set_mst_bandwidth(
2482                 stream_encoder,
2483                 avg_time_slots_per_mtp);
2484
2485         /* TODO: which component is responsible for remove payload table? */
2486         if (mst_mode) {
2487                 if (dm_helpers_dp_mst_write_payload_allocation_table(
2488                                 stream->ctx,
2489                                 stream,
2490                                 &proposed_table,
2491                                 false)) {
2492
2493                         update_mst_stream_alloc_table(
2494                                 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2495                 }
2496                 else {
2497                                 DC_LOG_WARNING("Failed to update"
2498                                                 "MST allocation table for"
2499                                                 "pipe idx:%d\n",
2500                                                 pipe_ctx->pipe_idx);
2501                 }
2502         }
2503
2504         DC_LOG_MST("%s"
2505                         "stream_count: %d: ",
2506                         __func__,
2507                         link->mst_stream_alloc_table.stream_count);
2508
2509         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2510                 DC_LOG_MST("stream_enc[%d]: %p      "
2511                 "stream[%d].vcp_id: %d      "
2512                 "stream[%d].slot_count: %d\n",
2513                 i,
2514                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2515                 i,
2516                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2517                 i,
2518                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2519         }
2520
2521         link_encoder->funcs->update_mst_stream_allocation_table(
2522                 link_encoder,
2523                 &link->mst_stream_alloc_table);
2524
2525         if (mst_mode) {
2526                 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2527                         stream->ctx,
2528                         stream);
2529
2530                 dm_helpers_dp_mst_send_payload_allocation(
2531                         stream->ctx,
2532                         stream,
2533                         false);
2534         }
2535
2536         return DC_OK;
2537 }
2538
2539 void core_link_enable_stream(
2540                 struct dc_state *state,
2541                 struct pipe_ctx *pipe_ctx)
2542 {
2543         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2544         struct dc_stream_state *stream = pipe_ctx->stream;
2545         enum dc_status status;
2546         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2547
2548         if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) {
2549                 stream->sink->link->link_enc->funcs->setup(
2550                         stream->sink->link->link_enc,
2551                         pipe_ctx->stream->signal);
2552                 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
2553                         pipe_ctx->stream_res.stream_enc,
2554                         pipe_ctx->stream_res.tg->inst,
2555                         stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
2556         }
2557
2558         if (dc_is_dp_signal(pipe_ctx->stream->signal))
2559                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
2560                         pipe_ctx->stream_res.stream_enc,
2561                         &stream->timing,
2562                         stream->output_color_space);
2563
2564         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2565                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
2566                         pipe_ctx->stream_res.stream_enc,
2567                         &stream->timing,
2568                         stream->phy_pix_clk,
2569                         pipe_ctx->stream_res.audio != NULL);
2570
2571         if (dc_is_dvi_signal(pipe_ctx->stream->signal))
2572                 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
2573                         pipe_ctx->stream_res.stream_enc,
2574                         &stream->timing,
2575                         (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
2576                         true : false);
2577
2578         if (dc_is_lvds_signal(pipe_ctx->stream->signal))
2579                 pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
2580                         pipe_ctx->stream_res.stream_enc,
2581                         &stream->timing);
2582
2583         if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
2584                 resource_build_info_frame(pipe_ctx);
2585                 core_dc->hwss.update_info_frame(pipe_ctx);
2586
2587                 /* eDP lit up by bios already, no need to enable again. */
2588                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
2589                                 pipe_ctx->stream->apply_edp_fast_boot_optimization) {
2590                         pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
2591                         pipe_ctx->stream->dpms_off = false;
2592                         return;
2593                 }
2594
2595                 if (pipe_ctx->stream->dpms_off)
2596                         return;
2597
2598                 status = enable_link(state, pipe_ctx);
2599
2600                 if (status != DC_OK) {
2601                         DC_LOG_WARNING("enabling link %u failed: %d\n",
2602                         pipe_ctx->stream->sink->link->link_index,
2603                         status);
2604
2605                         /* Abort stream enable *unless* the failure was due to
2606                          * DP link training - some DP monitors will recover and
2607                          * show the stream anyway. But MST displays can't proceed
2608                          * without link training.
2609                          */
2610                         if (status != DC_FAIL_DP_LINK_TRAINING ||
2611                                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2612                                 BREAK_TO_DEBUGGER();
2613                                 return;
2614                         }
2615                 }
2616
2617                 core_dc->hwss.enable_audio_stream(pipe_ctx);
2618
2619                 /* turn off otg test pattern if enable */
2620                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
2621                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
2622                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2623                                         COLOR_DEPTH_UNDEFINED);
2624
2625                 core_dc->hwss.enable_stream(pipe_ctx);
2626
2627                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2628                         allocate_mst_payload(pipe_ctx);
2629
2630                 core_dc->hwss.unblank_stream(pipe_ctx,
2631                         &pipe_ctx->stream->sink->link->cur_link_settings);
2632
2633                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2634                         enable_stream_features(pipe_ctx);
2635         }
2636
2637 }
2638
2639 void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
2640 {
2641         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2642
2643         core_dc->hwss.blank_stream(pipe_ctx);
2644
2645         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2646                 deallocate_mst_payload(pipe_ctx);
2647
2648         core_dc->hwss.disable_stream(pipe_ctx, option);
2649
2650         disable_link(pipe_ctx->stream->sink->link, pipe_ctx->stream->signal);
2651 }
2652
2653 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
2654 {
2655         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2656
2657         if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2658                 return;
2659
2660         core_dc->hwss.set_avmute(pipe_ctx, enable);
2661 }
2662
2663 /**
2664  *****************************************************************************
2665  *  Function: dc_link_enable_hpd_filter
2666  *
2667  *  @brief
2668  *     If enable is true, programs HPD filter on associated HPD line using
2669  *     delay_on_disconnect/delay_on_connect values dependent on
2670  *     link->connector_signal
2671  *
2672  *     If enable is false, programs HPD filter on associated HPD line with no
2673  *     delays on connect or disconnect
2674  *
2675  *  @param [in] link: pointer to the dc link
2676  *  @param [in] enable: boolean specifying whether to enable hbd
2677  *****************************************************************************
2678  */
2679 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
2680 {
2681         struct gpio *hpd;
2682
2683         if (enable) {
2684                 link->is_hpd_filter_disabled = false;
2685                 program_hpd_filter(link);
2686         } else {
2687                 link->is_hpd_filter_disabled = true;
2688                 /* Obtain HPD handle */
2689                 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
2690
2691                 if (!hpd)
2692                         return;
2693
2694                 /* Setup HPD filtering */
2695                 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
2696                         struct gpio_hpd_config config;
2697
2698                         config.delay_on_connect = 0;
2699                         config.delay_on_disconnect = 0;
2700
2701                         dal_irq_setup_hpd_filter(hpd, &config);
2702
2703                         dal_gpio_close(hpd);
2704                 } else {
2705                         ASSERT_CRITICAL(false);
2706                 }
2707                 /* Release HPD handle */
2708                 dal_gpio_destroy_irq(&hpd);
2709         }
2710 }
2711