drivers/gpu/drm/amd/display/dc/core/dc_link.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "atom.h"
  28 #include "dm_helpers.h"
  29 #include "dc.h"
  30 #include "grph_object_id.h"
  31 #include "gpio_service_interface.h"
  32 #include "core_status.h"
  33 #include "dc_link_dp.h"
  34 #include "dc_link_ddc.h"
  35 #include "link_hwss.h"
  36 #include "opp.h"
  37
  38 #include "link_encoder.h"
  39 #include "hw_sequencer.h"
  40 #include "resource.h"
  41 #include "abm.h"
  42 #include "fixed31_32.h"
  43 #include "dpcd_defs.h"
  44 #include "dmcu.h"
  45
  46 #include "dce/dce_11_0_d.h"
  47 #include "dce/dce_11_0_enum.h"
  48 #include "dce/dce_11_0_sh_mask.h"
  49
  50 #define DC_LOGGER_INIT(logger)
  51
  52
  53 #define LINK_INFO(...) \
  54         DC_LOG_HW_HOTPLUG(  \
  55                 __VA_ARGS__)
  56
  57 #define RETIMER_REDRIVER_INFO(...) \
  58         DC_LOG_RETIMER_REDRIVER(  \
  59                 __VA_ARGS__)
  60 /*******************************************************************************
  61  * Private structures
  62  ******************************************************************************/
  63
  64 enum {
  65         LINK_RATE_REF_FREQ_IN_MHZ = 27,
  66         PEAK_FACTOR_X1000 = 1006,
  67         /*
  68         * Some receivers fail to train on first try and are good
  69         * on subsequent tries. 2 retries should be plenty. If we
  70         * don't have a successful training then we don't expect to
  71         * ever get one.
  72         */
  73         LINK_TRAINING_MAX_VERIFY_RETRY = 2
  74 };
  75
  76 /*******************************************************************************
  77  * Private functions
  78  ******************************************************************************/
  79 static void destruct(struct dc_link *link)
  80 {
  81         int i;
  82
  83         if (link->ddc)
  84                 dal_ddc_service_destroy(&link->ddc);
  85
  86         if(link->link_enc)
  87                 link->link_enc->funcs->destroy(&link->link_enc);
  88
  89         if (link->local_sink)
  90                 dc_sink_release(link->local_sink);
  91
  92         for (i = 0; i < link->sink_count; ++i)
  93                 dc_sink_release(link->remote_sinks[i]);
  94 }
  95
  96 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
  97                 struct graphics_object_id link_id,
  98                 struct gpio_service *gpio_service)
  99 {
 100         enum bp_result bp_result;
 101         struct graphics_object_hpd_info hpd_info;
 102         struct gpio_pin_info pin_info;
 103
 104         if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
 105                 return NULL;
 106
 107         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
 108                 hpd_info.hpd_int_gpio_uid, &pin_info);
 109
 110         if (bp_result != BP_RESULT_OK) {
 111                 ASSERT(bp_result == BP_RESULT_NORECORD);
 112                 return NULL;
 113         }
 114
 115         return dal_gpio_service_create_irq(
 116                 gpio_service,
 117                 pin_info.offset,
 118                 pin_info.mask);
 119 }
 120
 121 /*
 122  *  Function: program_hpd_filter
 123  *
 124  *  @brief
 125  *     Programs HPD filter on associated HPD line
 126  *
 127  *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 128  *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 129  *
 130  *  @return
 131  *     true on success, false otherwise
 132  */
 133 static bool program_hpd_filter(
 134         const struct dc_link *link)
 135 {
 136         bool result = false;
 137
 138         struct gpio *hpd;
 139
 140         int delay_on_connect_in_ms = 0;
 141         int delay_on_disconnect_in_ms = 0;
 142
 143         if (link->is_hpd_filter_disabled)
 144                 return false;
 145         /* Verify feature is supported */
 146         switch (link->connector_signal) {
 147         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 148         case SIGNAL_TYPE_DVI_DUAL_LINK:
 149         case SIGNAL_TYPE_HDMI_TYPE_A:
 150                 /* Program hpd filter */
 151                 delay_on_connect_in_ms = 500;
 152                 delay_on_disconnect_in_ms = 100;
 153                 break;
 154         case SIGNAL_TYPE_DISPLAY_PORT:
 155         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 156                 /* Program hpd filter to allow DP signal to settle */
 157                 /* 500: not able to detect MST <-> SST switch as HPD is low for
 158                  *      only 100ms on DELL U2413
 159                  * 0:   some passive dongle still show aux mode instead of i2c
 160                  * 20-50:not enough to hide bouncing HPD with passive dongle.
 161                  *      also see intermittent i2c read issues.
 162                  */
 163                 delay_on_connect_in_ms = 80;
 164                 delay_on_disconnect_in_ms = 0;
 165                 break;
 166         case SIGNAL_TYPE_LVDS:
 167         case SIGNAL_TYPE_EDP:
 168         default:
 169                 /* Don't program hpd filter */
 170                 return false;
 171         }
 172
 173         /* Obtain HPD handle */
 174         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 175
 176         if (!hpd)
 177                 return result;
 178
 179         /* Setup HPD filtering */
 180         if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 181                 struct gpio_hpd_config config;
 182
 183                 config.delay_on_connect = delay_on_connect_in_ms;
 184                 config.delay_on_disconnect = delay_on_disconnect_in_ms;
 185
 186                 dal_irq_setup_hpd_filter(hpd, &config);
 187
 188                 dal_gpio_close(hpd);
 189
 190                 result = true;
 191         } else {
 192                 ASSERT_CRITICAL(false);
 193         }
 194
 195         /* Release HPD handle */
 196         dal_gpio_destroy_irq(&hpd);
 197
 198         return result;
 199 }
 200
 201 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 202 {
 203         uint32_t is_hpd_high = 0;
 204         struct gpio *hpd_pin;
 205
 206         if (link->connector_signal == SIGNAL_TYPE_LVDS) {
 207                 *type = dc_connection_single;
 208                 return true;
 209         }
 210
 211         /* todo: may need to lock gpio access */
 212         hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 213         if (hpd_pin == NULL)
 214                 goto hpd_gpio_failure;
 215
 216         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 217         dal_gpio_get_value(hpd_pin, &is_hpd_high);
 218         dal_gpio_close(hpd_pin);
 219         dal_gpio_destroy_irq(&hpd_pin);
 220
 221         if (is_hpd_high) {
 222                 *type = dc_connection_single;
 223                 /* TODO: need to do the actual detection */
 224         } else {
 225                 *type = dc_connection_none;
 226         }
 227
 228         return true;
 229
 230 hpd_gpio_failure:
 231         return false;
 232 }
 233
 234 static enum ddc_transaction_type get_ddc_transaction_type(
 235                 enum signal_type sink_signal)
 236 {
 237         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 238
 239         switch (sink_signal) {
 240         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 241         case SIGNAL_TYPE_DVI_DUAL_LINK:
 242         case SIGNAL_TYPE_HDMI_TYPE_A:
 243         case SIGNAL_TYPE_LVDS:
 244         case SIGNAL_TYPE_RGB:
 245                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
 246                 break;
 247
 248         case SIGNAL_TYPE_DISPLAY_PORT:
 249         case SIGNAL_TYPE_EDP:
 250                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 251                 break;
 252
 253         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 254                 /* MST does not use I2COverAux, but there is the
 255                  * SPECIAL use case for "immediate dwnstrm device
 256                  * access" (EPR#370830). */
 257                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 258                 break;
 259
 260         default:
 261                 break;
 262         }
 263
 264         return transaction_type;
 265 }
 266
 267 static enum signal_type get_basic_signal_type(
 268         struct graphics_object_id encoder,
 269         struct graphics_object_id downstream)
 270 {
 271         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 272                 switch (downstream.id) {
 273                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 274                         switch (encoder.id) {
 275                         case ENCODER_ID_INTERNAL_DAC1:
 276                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 277                         case ENCODER_ID_INTERNAL_DAC2:
 278                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 279                                 return SIGNAL_TYPE_RGB;
 280                         default:
 281                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 282                         }
 283                 break;
 284                 case CONNECTOR_ID_DUAL_LINK_DVII:
 285                 {
 286                         switch (encoder.id) {
 287                         case ENCODER_ID_INTERNAL_DAC1:
 288                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 289                         case ENCODER_ID_INTERNAL_DAC2:
 290                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 291                                 return SIGNAL_TYPE_RGB;
 292                         default:
 293                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 294                         }
 295                 }
 296                 break;
 297                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 298                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 299                 case CONNECTOR_ID_DUAL_LINK_DVID:
 300                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 301                 case CONNECTOR_ID_VGA:
 302                         return SIGNAL_TYPE_RGB;
 303                 case CONNECTOR_ID_HDMI_TYPE_A:
 304                         return SIGNAL_TYPE_HDMI_TYPE_A;
 305                 case CONNECTOR_ID_LVDS:
 306                         return SIGNAL_TYPE_LVDS;
 307                 case CONNECTOR_ID_DISPLAY_PORT:
 308                         return SIGNAL_TYPE_DISPLAY_PORT;
 309                 case CONNECTOR_ID_EDP:
 310                         return SIGNAL_TYPE_EDP;
 311                 default:
 312                         return SIGNAL_TYPE_NONE;
 313                 }
 314         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 315                 switch (downstream.id) {
 316                 case ENCODER_ID_EXTERNAL_NUTMEG:
 317                 case ENCODER_ID_EXTERNAL_TRAVIS:
 318                         return SIGNAL_TYPE_DISPLAY_PORT;
 319                 default:
 320                         return SIGNAL_TYPE_NONE;
 321                 }
 322         }
 323
 324         return SIGNAL_TYPE_NONE;
 325 }
 326
 327 /*
 328  * @brief
 329  * Check whether there is a dongle on DP connector
 330  */
 331 bool dc_link_is_dp_sink_present(struct dc_link *link)
 332 {
 333         enum gpio_result gpio_result;
 334         uint32_t clock_pin = 0;
 335
 336         struct ddc *ddc;
 337
 338         enum connector_id connector_id =
 339                 dal_graphics_object_id_get_connector_id(link->link_id);
 340
 341         bool present =
 342                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 343                 (connector_id == CONNECTOR_ID_EDP));
 344
 345         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 346
 347         if (!ddc) {
 348                 BREAK_TO_DEBUGGER();
 349                 return present;
 350         }
 351
 352         /* Open GPIO and set it to I2C mode */
 353         /* Note: this GpioMode_Input will be converted
 354          * to GpioConfigType_I2cAuxDualMode in GPIO component,
 355          * which indicates we need additional delay */
 356
 357         if (GPIO_RESULT_OK != dal_ddc_open(
 358                 ddc, GPIO_MODE_INPUT, GPIO_DDC_CONFIG_TYPE_MODE_I2C)) {
 359                 dal_gpio_destroy_ddc(&ddc);
 360
 361                 return present;
 362         }
 363
 364         /* Read GPIO: DP sink is present if both clock and data pins are zero */
 365         /* [anaumov] in DAL2, there was no check for GPIO failure */
 366
 367         gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 368         ASSERT(gpio_result == GPIO_RESULT_OK);
 369
 370         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 371
 372         dal_ddc_close(ddc);
 373
 374         return present;
 375 }
 376
 377 /*
 378  * @brief
 379  * Detect output sink type
 380  */
 381 static enum signal_type link_detect_sink(
 382         struct dc_link *link,
 383         enum dc_detect_reason reason)
 384 {
 385         enum signal_type result = get_basic_signal_type(
 386                 link->link_enc->id, link->link_id);
 387
 388         /* Internal digital encoder will detect only dongles
 389          * that require digital signal */
 390
 391         /* Detection mechanism is different
 392          * for different native connectors.
 393          * LVDS connector supports only LVDS signal;
 394          * PCIE is a bus slot, the actual connector needs to be detected first;
 395          * eDP connector supports only eDP signal;
 396          * HDMI should check straps for audio */
 397
 398         /* PCIE detects the actual connector on add-on board */
 399
 400         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 401                 /* ZAZTODO implement PCIE add-on card detection */
 402         }
 403
 404         switch (link->link_id.id) {
 405         case CONNECTOR_ID_HDMI_TYPE_A: {
 406                 /* check audio support:
 407                  * if native HDMI is not supported, switch to DVI */
 408                 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 409
 410                 if (!aud_support->hdmi_audio_native)
 411                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 412                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 413         }
 414         break;
 415         case CONNECTOR_ID_DISPLAY_PORT: {
 416                 /* DP HPD short pulse. Passive DP dongle will not
 417                  * have short pulse
 418                  */
 419                 if (reason != DETECT_REASON_HPDRX) {
 420                         /* Check whether DP signal detected: if not -
 421                          * we assume signal is DVI; it could be corrected
 422                          * to HDMI after dongle detection
 423                          */
 424                         if (!dm_helpers_is_dp_sink_present(link))
 425                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 426                 }
 427         }
 428         break;
 429         default:
 430         break;
 431         }
 432
 433         return result;
 434 }
 435
 436 static enum signal_type decide_signal_from_strap_and_dongle_type(
 437                 enum display_dongle_type dongle_type,
 438                 struct audio_support *audio_support)
 439 {
 440         enum signal_type signal = SIGNAL_TYPE_NONE;
 441
 442         switch (dongle_type) {
 443         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 444                 if (audio_support->hdmi_audio_on_dongle)
 445                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 446                 else
 447                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 448                 break;
 449         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 450                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 451                 break;
 452         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 453                 if (audio_support->hdmi_audio_native)
 454                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 455                 else
 456                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 457                 break;
 458         default:
 459                 signal = SIGNAL_TYPE_NONE;
 460                 break;
 461         }
 462
 463         return signal;
 464 }
 465
 466 static enum signal_type dp_passive_dongle_detection(
 467                 struct ddc_service *ddc,
 468                 struct display_sink_capability *sink_cap,
 469                 struct audio_support *audio_support)
 470 {
 471         dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
 472                                                 ddc, sink_cap);
 473         return decide_signal_from_strap_and_dongle_type(
 474                         sink_cap->dongle_type,
 475                         audio_support);
 476 }
 477
 478 static void link_disconnect_sink(struct dc_link *link)
 479 {
 480         if (link->local_sink) {
 481                 dc_sink_release(link->local_sink);
 482                 link->local_sink = NULL;
 483         }
 484
 485         link->dpcd_sink_count = 0;
 486 }
 487
 488 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 489 {
 490         dc_sink_release(link->local_sink);
 491         link->local_sink = prev_sink;
 492 }
 493
 494
 495 static bool detect_dp(
 496         struct dc_link *link,
 497         struct display_sink_capability *sink_caps,
 498         bool *converter_disable_audio,
 499         struct audio_support *audio_support,
 500         enum dc_detect_reason reason)
 501 {
 502         bool boot = false;
 503         sink_caps->signal = link_detect_sink(link, reason);
 504         sink_caps->transaction_type =
 505                 get_ddc_transaction_type(sink_caps->signal);
 506
 507         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 508                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 509                 if (!detect_dp_sink_caps(link))
 510                         return false;
 511
 512                 if (is_mst_supported(link)) {
 513                         sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
 514                         link->type = dc_connection_mst_branch;
 515
 516                         dal_ddc_service_set_transaction_type(
 517                                                         link->ddc,
 518                                                         sink_caps->transaction_type);
 519
 520                         /*
 521                          * This call will initiate MST topology discovery. Which
 522                          * will detect MST ports and add new DRM connector DRM
 523                          * framework. Then read EDID via remote i2c over aux. In
 524                          * the end, will notify DRM detect result and save EDID
 525                          * into DRM framework.
 526                          *
 527                          * .detect is called by .fill_modes.
 528                          * .fill_modes is called by user mode ioctl
 529                          * DRM_IOCTL_MODE_GETCONNECTOR.
 530                          *
 531                          * .get_modes is called by .fill_modes.
 532                          *
 533                          * call .get_modes, AMDGPU DM implementation will create
 534                          * new dc_sink and add to dc_link. For long HPD plug
 535                          * in/out, MST has its own handle.
 536                          *
 537                          * Therefore, just after dc_create, link->sink is not
 538                          * created for MST until user mode app calls
 539                          * DRM_IOCTL_MODE_GETCONNECTOR.
 540                          *
 541                          * Need check ->sink usages in case ->sink = NULL
 542                          * TODO: s3 resume check
 543                          */
 544                         if (reason == DETECT_REASON_BOOT)
 545                                 boot = true;
 546
 547                         dm_helpers_dp_update_branch_info(
 548                                 link->ctx,
 549                                 link);
 550
 551                         if (!dm_helpers_dp_mst_start_top_mgr(
 552                                 link->ctx,
 553                                 link, boot)) {
 554                                 /* MST not supported */
 555                                 link->type = dc_connection_single;
 556                                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 557                         }
 558                 }
 559
 560                 if (link->type != dc_connection_mst_branch &&
 561                         is_dp_active_dongle(link)) {
 562                         /* DP active dongles */
 563                         link->type = dc_connection_active_dongle;
 564                         if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
 565                                 /*
 566                                  * active dongle unplug processing for short irq
 567                                  */
 568                                 link_disconnect_sink(link);
 569                                 return true;
 570                         }
 571
 572                         if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER)
 573                                 *converter_disable_audio = true;
 574                 }
 575         } else {
 576                 /* DP passive dongles */
 577                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 578                                 sink_caps,
 579                                 audio_support);
 580         }
 581
 582         return true;
 583 }
 584
 585 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 586 {
 587         if (old_edid->length != new_edid->length)
 588                 return false;
 589
 590         if (new_edid->length == 0)
 591                 return false;
 592
 593         return (memcmp(old_edid->raw_edid, new_edid->raw_edid, new_edid->length) == 0);
 594 }
 595
 596 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
 597 {
 598         struct dc_sink_init_data sink_init_data = { 0 };
 599         struct display_sink_capability sink_caps = { 0 };
 600         uint8_t i;
 601         bool converter_disable_audio = false;
 602         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 603         bool same_edid = false;
 604         enum dc_edid_status edid_status;
 605         struct dc_context *dc_ctx = link->ctx;
 606         struct dc_sink *sink = NULL;
 607         struct dc_sink *prev_sink = NULL;
 608         struct dpcd_caps prev_dpcd_caps;
 609         bool same_dpcd = true;
 610         enum dc_connection_type new_connection_type = dc_connection_none;
 611         DC_LOGGER_INIT(link->ctx->logger);
 612         if (link->connector_signal == SIGNAL_TYPE_VIRTUAL)
 613                 return false;
 614
 615         if (false == dc_link_detect_sink(link, &new_connection_type)) {
 616                 BREAK_TO_DEBUGGER();
 617                 return false;
 618         }
 619
 620         if (link->connector_signal == SIGNAL_TYPE_EDP &&
 621                         link->local_sink)
 622                 return true;
 623
 624         if (link->connector_signal == SIGNAL_TYPE_LVDS &&
 625                         link->local_sink)
 626                 return true;
 627
 628         prev_sink = link->local_sink;
 629         if (prev_sink != NULL) {
 630                 dc_sink_retain(prev_sink);
 631                 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
 632         }
 633         link_disconnect_sink(link);
 634
 635         if (new_connection_type != dc_connection_none) {
 636                 link->type = new_connection_type;
 637
 638                 /* From Disconnected-to-Connected. */
 639                 switch (link->connector_signal) {
 640                 case SIGNAL_TYPE_HDMI_TYPE_A: {
 641                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 642                         if (aud_support->hdmi_audio_native)
 643                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 644                         else
 645                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 646                         break;
 647                 }
 648
 649                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
 650                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 651                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 652                         break;
 653                 }
 654
 655                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
 656                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 657                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 658                         break;
 659                 }
 660
 661                 case SIGNAL_TYPE_LVDS: {
 662                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 663                         sink_caps.signal = SIGNAL_TYPE_LVDS;
 664                         break;
 665                 }
 666
 667                 case SIGNAL_TYPE_EDP: {
 668                         detect_edp_sink_caps(link);
 669                         sink_caps.transaction_type =
 670                                 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 671                         sink_caps.signal = SIGNAL_TYPE_EDP;
 672                         break;
 673                 }
 674
 675                 case SIGNAL_TYPE_DISPLAY_PORT: {
 676                         if (!detect_dp(
 677                                 link,
 678                                 &sink_caps,
 679                                 &converter_disable_audio,
 680                                 aud_support, reason)) {
 681                                 if (prev_sink != NULL)
 682                                         dc_sink_release(prev_sink);
 683                                 return false;
 684                         }
 685
 686                         // Check if dpcp block is the same
 687                         if (prev_sink != NULL) {
 688                                 if (memcmp(&link->dpcd_caps, &prev_dpcd_caps, sizeof(struct dpcd_caps)))
 689                                         same_dpcd = false;
 690                         }
 691                         /* Active dongle downstream unplug */
 692                         if (link->type == dc_connection_active_dongle
 693                                         && link->dpcd_caps.sink_count.
 694                                         bits.SINK_COUNT == 0) {
 695                                 if (prev_sink != NULL)
 696                                         dc_sink_release(prev_sink);
 697                                 return true;
 698                         }
 699
 700                         if (link->type == dc_connection_mst_branch) {
 701                                 LINK_INFO("link=%d, mst branch is now Connected\n",
 702                                         link->link_index);
 703                                 /* Need to setup mst link_cap struct here
 704                                  * otherwise dc_link_detect() will leave mst link_cap
 705                                  * empty which leads to allocate_mst_payload() has "0"
 706                                  * pbn_per_slot value leading to exception on dc_fixpt_div()
 707                                  */
 708                                 link->verified_link_cap = link->reported_link_cap;
 709                                 if (prev_sink != NULL)
 710                                         dc_sink_release(prev_sink);
 711                                 return false;
 712                         }
 713
 714                         break;
 715                 }
 716
 717                 default:
 718                         DC_ERROR("Invalid connector type! signal:%d\n",
 719                                 link->connector_signal);
 720                         if (prev_sink != NULL)
 721                                 dc_sink_release(prev_sink);
 722                         return false;
 723                 } /* switch() */
 724
 725                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
 726                         link->dpcd_sink_count = link->dpcd_caps.sink_count.
 727                                         bits.SINK_COUNT;
 728                 else
 729                         link->dpcd_sink_count = 1;
 730
 731                 dal_ddc_service_set_transaction_type(
 732                                                 link->ddc,
 733                                                 sink_caps.transaction_type);
 734
 735                 link->aux_mode = dal_ddc_service_is_in_aux_transaction_mode(
 736                                 link->ddc);
 737
 738                 sink_init_data.link = link;
 739                 sink_init_data.sink_signal = sink_caps.signal;
 740
 741                 sink = dc_sink_create(&sink_init_data);
 742                 if (!sink) {
 743                         DC_ERROR("Failed to create sink!\n");
 744                         if (prev_sink != NULL)
 745                                 dc_sink_release(prev_sink);
 746                         return false;
 747                 }
 748
 749                 sink->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
 750                 sink->converter_disable_audio = converter_disable_audio;
 751
 752                 link->local_sink = sink;
 753
 754                 edid_status = dm_helpers_read_local_edid(
 755                                 link->ctx,
 756                                 link,
 757                                 sink);
 758
 759                 switch (edid_status) {
 760                 case EDID_BAD_CHECKSUM:
 761                         DC_LOG_ERROR("EDID checksum invalid.\n");
 762                         break;
 763                 case EDID_NO_RESPONSE:
 764                         DC_LOG_ERROR("No EDID read.\n");
 765
 766                         /*
 767                          * Abort detection for non-DP connectors if we have
 768                          * no EDID
 769                          *
 770                          * DP needs to report as connected if HDP is high
 771                          * even if we have no EDID in order to go to
 772                          * fail-safe mode
 773                          */
 774                         if (dc_is_hdmi_signal(link->connector_signal) ||
 775                             dc_is_dvi_signal(link->connector_signal)) {
 776                                 if (prev_sink != NULL)
 777                                         dc_sink_release(prev_sink);
 778
 779                                 return false;
 780                         }
 781                 default:
 782                         break;
 783                 }
 784
 785                 // Check if edid is the same
 786                 if ((prev_sink != NULL) && ((edid_status == EDID_THE_SAME) || (edid_status == EDID_OK)))
 787                         same_edid = is_same_edid(&prev_sink->dc_edid, &sink->dc_edid);
 788
 789                 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 790                         sink_caps.transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX &&
 791                         reason != DETECT_REASON_HPDRX) {
 792                         /*
 793                          * TODO debug why Dell 2413 doesn't like
 794                          *  two link trainings
 795                          */
 796
 797                         /* deal with non-mst cases */
 798                         for (i = 0; i < LINK_TRAINING_MAX_VERIFY_RETRY; i++) {
 799                                 int fail_count = 0;
 800
 801                                 dp_verify_link_cap(link,
 802                                                   &link->reported_link_cap,
 803                                                   &fail_count);
 804
 805                                 if (fail_count == 0)
 806                                         break;
 807                         }
 808
 809                 } else {
 810                         // If edid is the same, then discard new sink and revert back to original sink
 811                         if (same_edid) {
 812                                 link_disconnect_remap(prev_sink, link);
 813                                 sink = prev_sink;
 814                                 prev_sink = NULL;
 815
 816                         }
 817                 }
 818
 819                 /* HDMI-DVI Dongle */
 820                 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
 821                                 !sink->edid_caps.edid_hdmi)
 822                         sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 823
 824                 /* Connectivity log: detection */
 825                 for (i = 0; i < sink->dc_edid.length / EDID_BLOCK_SIZE; i++) {
 826                         CONN_DATA_DETECT(link,
 827                                         &sink->dc_edid.raw_edid[i * EDID_BLOCK_SIZE],
 828                                         EDID_BLOCK_SIZE,
 829                                         "%s: [Block %d] ", sink->edid_caps.display_name, i);
 830                 }
 831
 832                 DC_LOG_DETECTION_EDID_PARSER("%s: "
 833                         "manufacturer_id = %X, "
 834                         "product_id = %X, "
 835                         "serial_number = %X, "
 836                         "manufacture_week = %d, "
 837                         "manufacture_year = %d, "
 838                         "display_name = %s, "
 839                         "speaker_flag = %d, "
 840                         "audio_mode_count = %d\n",
 841                         __func__,
 842                         sink->edid_caps.manufacturer_id,
 843                         sink->edid_caps.product_id,
 844                         sink->edid_caps.serial_number,
 845                         sink->edid_caps.manufacture_week,
 846                         sink->edid_caps.manufacture_year,
 847                         sink->edid_caps.display_name,
 848                         sink->edid_caps.speaker_flags,
 849                         sink->edid_caps.audio_mode_count);
 850
 851                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
 852                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
 853                                 "format_code = %d, "
 854                                 "channel_count = %d, "
 855                                 "sample_rate = %d, "
 856                                 "sample_size = %d\n",
 857                                 __func__,
 858                                 i,
 859                                 sink->edid_caps.audio_modes[i].format_code,
 860                                 sink->edid_caps.audio_modes[i].channel_count,
 861                                 sink->edid_caps.audio_modes[i].sample_rate,
 862                                 sink->edid_caps.audio_modes[i].sample_size);
 863                 }
 864
 865         } else {
 866                 /* From Connected-to-Disconnected. */
 867                 if (link->type == dc_connection_mst_branch) {
 868                         LINK_INFO("link=%d, mst branch is now Disconnected\n",
 869                                 link->link_index);
 870
 871                         dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
 872
 873                         link->mst_stream_alloc_table.stream_count = 0;
 874                         memset(link->mst_stream_alloc_table.stream_allocations, 0, sizeof(link->mst_stream_alloc_table.stream_allocations));
 875                 }
 876
 877                 link->type = dc_connection_none;
 878                 sink_caps.signal = SIGNAL_TYPE_NONE;
 879         }
 880
 881         LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n",
 882                 link->link_index, sink,
 883                 (sink_caps.signal == SIGNAL_TYPE_NONE ?
 884                         "Disconnected":"Connected"), prev_sink,
 885                         same_dpcd, same_edid);
 886
 887         if (prev_sink != NULL)
 888                 dc_sink_release(prev_sink);
 889
 890         return true;
 891 }
 892
 893 bool dc_link_get_hpd_state(struct dc_link *dc_link)
 894 {
 895         struct gpio *hpd_pin;
 896         uint32_t state;
 897
 898         hpd_pin = get_hpd_gpio(dc_link->ctx->dc_bios,
 899                                         dc_link->link_id, dc_link->ctx->gpio_service);
 900         if (hpd_pin == NULL)
 901                 ASSERT(false);
 902
 903         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 904         dal_gpio_get_value(hpd_pin, &state);
 905         dal_gpio_close(hpd_pin);
 906         dal_gpio_destroy_irq(&hpd_pin);
 907
 908         return state;
 909 }
 910
 911 static enum hpd_source_id get_hpd_line(
 912                 struct dc_link *link)
 913 {
 914         struct gpio *hpd;
 915         enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
 916
 917         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 918
 919         if (hpd) {
 920                 switch (dal_irq_get_source(hpd)) {
 921                 case DC_IRQ_SOURCE_HPD1:
 922                         hpd_id = HPD_SOURCEID1;
 923                 break;
 924                 case DC_IRQ_SOURCE_HPD2:
 925                         hpd_id = HPD_SOURCEID2;
 926                 break;
 927                 case DC_IRQ_SOURCE_HPD3:
 928                         hpd_id = HPD_SOURCEID3;
 929                 break;
 930                 case DC_IRQ_SOURCE_HPD4:
 931                         hpd_id = HPD_SOURCEID4;
 932                 break;
 933                 case DC_IRQ_SOURCE_HPD5:
 934                         hpd_id = HPD_SOURCEID5;
 935                 break;
 936                 case DC_IRQ_SOURCE_HPD6:
 937                         hpd_id = HPD_SOURCEID6;
 938                 break;
 939                 default:
 940                         BREAK_TO_DEBUGGER();
 941                 break;
 942                 }
 943
 944                 dal_gpio_destroy_irq(&hpd);
 945         }
 946
 947         return hpd_id;
 948 }
 949
 950 static enum channel_id get_ddc_line(struct dc_link *link)
 951 {
 952         struct ddc *ddc;
 953         enum channel_id channel = CHANNEL_ID_UNKNOWN;
 954
 955         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 956
 957         if (ddc) {
 958                 switch (dal_ddc_get_line(ddc)) {
 959                 case GPIO_DDC_LINE_DDC1:
 960                         channel = CHANNEL_ID_DDC1;
 961                         break;
 962                 case GPIO_DDC_LINE_DDC2:
 963                         channel = CHANNEL_ID_DDC2;
 964                         break;
 965                 case GPIO_DDC_LINE_DDC3:
 966                         channel = CHANNEL_ID_DDC3;
 967                         break;
 968                 case GPIO_DDC_LINE_DDC4:
 969                         channel = CHANNEL_ID_DDC4;
 970                         break;
 971                 case GPIO_DDC_LINE_DDC5:
 972                         channel = CHANNEL_ID_DDC5;
 973                         break;
 974                 case GPIO_DDC_LINE_DDC6:
 975                         channel = CHANNEL_ID_DDC6;
 976                         break;
 977                 case GPIO_DDC_LINE_DDC_VGA:
 978                         channel = CHANNEL_ID_DDC_VGA;
 979                         break;
 980                 case GPIO_DDC_LINE_I2C_PAD:
 981                         channel = CHANNEL_ID_I2C_PAD;
 982                         break;
 983                 default:
 984                         BREAK_TO_DEBUGGER();
 985                         break;
 986                 }
 987         }
 988
 989         return channel;
 990 }
 991
 992 static enum transmitter translate_encoder_to_transmitter(
 993         struct graphics_object_id encoder)
 994 {
 995         switch (encoder.id) {
 996         case ENCODER_ID_INTERNAL_UNIPHY:
 997                 switch (encoder.enum_id) {
 998                 case ENUM_ID_1:
 999                         return TRANSMITTER_UNIPHY_A;
1000                 case ENUM_ID_2:
1001                         return TRANSMITTER_UNIPHY_B;
1002                 default:
1003                         return TRANSMITTER_UNKNOWN;
1004                 }
1005         break;
1006         case ENCODER_ID_INTERNAL_UNIPHY1:
1007                 switch (encoder.enum_id) {
1008                 case ENUM_ID_1:
1009                         return TRANSMITTER_UNIPHY_C;
1010                 case ENUM_ID_2:
1011                         return TRANSMITTER_UNIPHY_D;
1012                 default:
1013                         return TRANSMITTER_UNKNOWN;
1014                 }
1015         break;
1016         case ENCODER_ID_INTERNAL_UNIPHY2:
1017                 switch (encoder.enum_id) {
1018                 case ENUM_ID_1:
1019                         return TRANSMITTER_UNIPHY_E;
1020                 case ENUM_ID_2:
1021                         return TRANSMITTER_UNIPHY_F;
1022                 default:
1023                         return TRANSMITTER_UNKNOWN;
1024                 }
1025         break;
1026         case ENCODER_ID_INTERNAL_UNIPHY3:
1027                 switch (encoder.enum_id) {
1028                 case ENUM_ID_1:
1029                         return TRANSMITTER_UNIPHY_G;
1030                 default:
1031                         return TRANSMITTER_UNKNOWN;
1032                 }
1033         break;
1034         case ENCODER_ID_EXTERNAL_NUTMEG:
1035                 switch (encoder.enum_id) {
1036                 case ENUM_ID_1:
1037                         return TRANSMITTER_NUTMEG_CRT;
1038                 default:
1039                         return TRANSMITTER_UNKNOWN;
1040                 }
1041         break;
1042         case ENCODER_ID_EXTERNAL_TRAVIS:
1043                 switch (encoder.enum_id) {
1044                 case ENUM_ID_1:
1045                         return TRANSMITTER_TRAVIS_CRT;
1046                 case ENUM_ID_2:
1047                         return TRANSMITTER_TRAVIS_LCD;
1048                 default:
1049                         return TRANSMITTER_UNKNOWN;
1050                 }
1051         break;
1052         default:
1053                 return TRANSMITTER_UNKNOWN;
1054         }
1055 }
1056
1057 static bool construct(
1058         struct dc_link *link,
1059         const struct link_init_data *init_params)
1060 {
1061         uint8_t i;
1062         struct gpio *hpd_gpio = NULL;
1063         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1064         struct dc_context *dc_ctx = init_params->ctx;
1065         struct encoder_init_data enc_init_data = { 0 };
1066         struct integrated_info info = {{{ 0 }}};
1067         struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1068         const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1069         DC_LOGGER_INIT(dc_ctx->logger);
1070
1071         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1072         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1073
1074         link->link_status.dpcd_caps = &link->dpcd_caps;
1075
1076         link->dc = init_params->dc;
1077         link->ctx = dc_ctx;
1078         link->link_index = init_params->link_index;
1079
1080         link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index);
1081
1082         if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1083                 dm_error("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1084                          __func__, init_params->connector_index,
1085                          link->link_id.type, OBJECT_TYPE_CONNECTOR);
1086                 goto create_fail;
1087         }
1088
1089         if (link->dc->res_pool->funcs->link_init)
1090                 link->dc->res_pool->funcs->link_init(link);
1091
1092         hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
1093
1094         if (hpd_gpio != NULL)
1095                 link->irq_source_hpd = dal_irq_get_source(hpd_gpio);
1096
1097         switch (link->link_id.id) {
1098         case CONNECTOR_ID_HDMI_TYPE_A:
1099                 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1100
1101                 break;
1102         case CONNECTOR_ID_SINGLE_LINK_DVID:
1103         case CONNECTOR_ID_SINGLE_LINK_DVII:
1104                 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1105                 break;
1106         case CONNECTOR_ID_DUAL_LINK_DVID:
1107         case CONNECTOR_ID_DUAL_LINK_DVII:
1108                 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1109                 break;
1110         case CONNECTOR_ID_DISPLAY_PORT:
1111                 link->connector_signal =        SIGNAL_TYPE_DISPLAY_PORT;
1112
1113                 if (hpd_gpio != NULL)
1114                         link->irq_source_hpd_rx =
1115                                         dal_irq_get_rx_source(hpd_gpio);
1116
1117                 break;
1118         case CONNECTOR_ID_EDP:
1119                 link->connector_signal = SIGNAL_TYPE_EDP;
1120
1121                 if (hpd_gpio != NULL) {
1122                         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1123                         link->irq_source_hpd_rx =
1124                                         dal_irq_get_rx_source(hpd_gpio);
1125                 }
1126                 break;
1127         case CONNECTOR_ID_LVDS:
1128                 link->connector_signal = SIGNAL_TYPE_LVDS;
1129                 break;
1130         default:
1131                 DC_LOG_WARNING("Unsupported Connector type:%d!\n", link->link_id.id);
1132                 goto create_fail;
1133         }
1134
1135         if (hpd_gpio != NULL) {
1136                 dal_gpio_destroy_irq(&hpd_gpio);
1137                 hpd_gpio = NULL;
1138         }
1139
1140         /* TODO: #DAL3 Implement id to str function.*/
1141         LINK_INFO("Connector[%d] description:"
1142                         "signal %d\n",
1143                         init_params->connector_index,
1144                         link->connector_signal);
1145
1146         ddc_service_init_data.ctx = link->ctx;
1147         ddc_service_init_data.id = link->link_id;
1148         ddc_service_init_data.link = link;
1149         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1150
1151         if (link->ddc == NULL) {
1152                 DC_ERROR("Failed to create ddc_service!\n");
1153                 goto ddc_create_fail;
1154         }
1155
1156         link->ddc_hw_inst =
1157                 dal_ddc_get_line(
1158                         dal_ddc_service_get_ddc_pin(link->ddc));
1159
1160         enc_init_data.ctx = dc_ctx;
1161         bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0, &enc_init_data.encoder);
1162         enc_init_data.connector = link->link_id;
1163         enc_init_data.channel = get_ddc_line(link);
1164         enc_init_data.hpd_source = get_hpd_line(link);
1165
1166         link->hpd_src = enc_init_data.hpd_source;
1167
1168         enc_init_data.transmitter =
1169                         translate_encoder_to_transmitter(enc_init_data.encoder);
1170         link->link_enc = link->dc->res_pool->funcs->link_enc_create(
1171                                                                 &enc_init_data);
1172
1173         if( link->link_enc == NULL) {
1174                 DC_ERROR("Failed to create link encoder!\n");
1175                 goto link_enc_create_fail;
1176         }
1177
1178         link->link_enc_hw_inst = link->link_enc->transmitter;
1179
1180         for (i = 0; i < 4; i++) {
1181                 if (BP_RESULT_OK !=
1182                                 bp_funcs->get_device_tag(dc_ctx->dc_bios, link->link_id, i, &link->device_tag)) {
1183                         DC_ERROR("Failed to find device tag!\n");
1184                         goto device_tag_fail;
1185                 }
1186
1187                 /* Look for device tag that matches connector signal,
1188                  * CRT for rgb, LCD for other supported signal tyes
1189                  */
1190                 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios, link->device_tag.dev_id))
1191                         continue;
1192                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT
1193                         && link->connector_signal != SIGNAL_TYPE_RGB)
1194                         continue;
1195                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD
1196                         && link->connector_signal == SIGNAL_TYPE_RGB)
1197                         continue;
1198                 break;
1199         }
1200
1201         if (bios->integrated_info)
1202                 info = *bios->integrated_info;
1203
1204         /* Look for channel mapping corresponding to connector and device tag */
1205         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1206                 struct external_display_path *path =
1207                         &info.ext_disp_conn_info.path[i];
1208                 if (path->device_connector_id.enum_id == link->link_id.enum_id
1209                         && path->device_connector_id.id == link->link_id.id
1210                         && path->device_connector_id.type == link->link_id.type) {
1211
1212                         if (link->device_tag.acpi_device != 0
1213                                 && path->device_acpi_enum == link->device_tag.acpi_device) {
1214                                 link->ddi_channel_mapping = path->channel_mapping;
1215                                 link->chip_caps = path->caps;
1216                         } else if (path->device_tag ==
1217                                         link->device_tag.dev_id.raw_device_tag) {
1218                                 link->ddi_channel_mapping = path->channel_mapping;
1219                                 link->chip_caps = path->caps;
1220                         }
1221                         break;
1222                 }
1223         }
1224
1225         /*
1226          * TODO check if GPIO programmed correctly
1227          *
1228          * If GPIO isn't programmed correctly HPD might not rise or drain
1229          * fast enough, leading to bounces.
1230          */
1231         program_hpd_filter(link);
1232
1233         return true;
1234 device_tag_fail:
1235         link->link_enc->funcs->destroy(&link->link_enc);
1236 link_enc_create_fail:
1237         dal_ddc_service_destroy(&link->ddc);
1238 ddc_create_fail:
1239 create_fail:
1240
1241         if (hpd_gpio != NULL) {
1242                 dal_gpio_destroy_irq(&hpd_gpio);
1243         }
1244
1245         return false;
1246 }
1247
1248 /*******************************************************************************
1249  * Public functions
1250  ******************************************************************************/
1251 struct dc_link *link_create(const struct link_init_data *init_params)
1252 {
1253         struct dc_link *link =
1254                         kzalloc(sizeof(*link), GFP_KERNEL);
1255
1256         if (NULL == link)
1257                 goto alloc_fail;
1258
1259         if (false == construct(link, init_params))
1260                 goto construct_fail;
1261
1262         return link;
1263
1264 construct_fail:
1265         kfree(link);
1266
1267 alloc_fail:
1268         return NULL;
1269 }
1270
1271 void link_destroy(struct dc_link **link)
1272 {
1273         destruct(*link);
1274         kfree(*link);
1275         *link = NULL;
1276 }
1277
1278 static void dpcd_configure_panel_mode(
1279         struct dc_link *link,
1280         enum dp_panel_mode panel_mode)
1281 {
1282         union dpcd_edp_config edp_config_set;
1283         bool panel_mode_edp = false;
1284         DC_LOGGER_INIT(link->ctx->logger);
1285
1286         memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
1287
1288         if (DP_PANEL_MODE_DEFAULT != panel_mode) {
1289
1290                 switch (panel_mode) {
1291                 case DP_PANEL_MODE_EDP:
1292                 case DP_PANEL_MODE_SPECIAL:
1293                         panel_mode_edp = true;
1294                         break;
1295
1296                 default:
1297                         break;
1298                 }
1299
1300                 /*set edp panel mode in receiver*/
1301                 core_link_read_dpcd(
1302                         link,
1303                         DP_EDP_CONFIGURATION_SET,
1304                         &edp_config_set.raw,
1305                         sizeof(edp_config_set.raw));
1306
1307                 if (edp_config_set.bits.PANEL_MODE_EDP
1308                         != panel_mode_edp) {
1309                         enum ddc_result result = DDC_RESULT_UNKNOWN;
1310
1311                         edp_config_set.bits.PANEL_MODE_EDP =
1312                         panel_mode_edp;
1313                         result = core_link_write_dpcd(
1314                                 link,
1315                                 DP_EDP_CONFIGURATION_SET,
1316                                 &edp_config_set.raw,
1317                                 sizeof(edp_config_set.raw));
1318
1319                         ASSERT(result == DDC_RESULT_SUCESSFULL);
1320                 }
1321         }
1322         DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
1323                         "eDP panel mode enabled: %d \n",
1324                         link->link_index,
1325                         link->dpcd_caps.panel_mode_edp,
1326                         panel_mode_edp);
1327 }
1328
1329 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1330 {
1331         struct dc_stream_state *stream = pipe_ctx->stream;
1332         struct dc_link *link = stream->sink->link;
1333         union down_spread_ctrl old_downspread;
1334         union down_spread_ctrl new_downspread;
1335
1336         core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1337                         &old_downspread.raw, sizeof(old_downspread));
1338
1339         new_downspread.raw = old_downspread.raw;
1340
1341         new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1342                         (stream->ignore_msa_timing_param) ? 1 : 0;
1343
1344         if (new_downspread.raw != old_downspread.raw) {
1345                 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1346                         &new_downspread.raw, sizeof(new_downspread));
1347         }
1348 }
1349
1350 static enum dc_status enable_link_dp(
1351                 struct dc_state *state,
1352                 struct pipe_ctx *pipe_ctx)
1353 {
1354         struct dc_stream_state *stream = pipe_ctx->stream;
1355         enum dc_status status;
1356         bool skip_video_pattern;
1357         struct dc_link *link = stream->sink->link;
1358         struct dc_link_settings link_settings = {0};
1359         enum dp_panel_mode panel_mode;
1360         enum dc_link_rate max_link_rate = LINK_RATE_HIGH2;
1361
1362         /* get link settings for video mode timing */
1363         decide_link_settings(stream, &link_settings);
1364
1365         /* raise clock state for HBR3 if required. Confirmed with HW DCE/DPCS
1366          * logic for HBR3 still needs Nominal (0.8V) on VDDC rail
1367          */
1368         if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
1369                 max_link_rate = LINK_RATE_HIGH3;
1370
1371         if (link_settings.link_rate == max_link_rate) {
1372                 struct dc_clocks clocks = state->bw.dcn.clk;
1373
1374                 /* dce/dcn compat, do not update dispclk */
1375                 clocks.dispclk_khz = 0;
1376                 /* 27mhz = 27000000hz= 27000khz */
1377                 clocks.phyclk_khz = link_settings.link_rate * 27000;
1378
1379                 state->dis_clk->funcs->update_clocks(
1380                                 state->dis_clk, &clocks, false);
1381         }
1382
1383         dp_enable_link_phy(
1384                 link,
1385                 pipe_ctx->stream->signal,
1386                 pipe_ctx->clock_source->id,
1387                 &link_settings);
1388
1389         if (stream->sink->edid_caps.panel_patch.dppowerup_delay > 0) {
1390                 int delay_dp_power_up_in_ms = stream->sink->edid_caps.panel_patch.dppowerup_delay;
1391
1392                 msleep(delay_dp_power_up_in_ms);
1393         }
1394
1395         panel_mode = dp_get_panel_mode(link);
1396         dpcd_configure_panel_mode(link, panel_mode);
1397
1398         skip_video_pattern = true;
1399
1400         if (link_settings.link_rate == LINK_RATE_LOW)
1401                         skip_video_pattern = false;
1402
1403         if (perform_link_training_with_retries(
1404                         link,
1405                         &link_settings,
1406                         skip_video_pattern,
1407                         LINK_TRAINING_ATTEMPTS)) {
1408                 link->cur_link_settings = link_settings;
1409                 status = DC_OK;
1410         }
1411         else
1412                 status = DC_FAIL_DP_LINK_TRAINING;
1413
1414         enable_stream_features(pipe_ctx);
1415
1416         return status;
1417 }
1418
1419 static enum dc_status enable_link_edp(
1420                 struct dc_state *state,
1421                 struct pipe_ctx *pipe_ctx)
1422 {
1423         enum dc_status status;
1424         struct dc_stream_state *stream = pipe_ctx->stream;
1425         struct dc_link *link = stream->sink->link;
1426         /*in case it is not on*/
1427         link->dc->hwss.edp_power_control(link, true);
1428         link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1429
1430         status = enable_link_dp(state, pipe_ctx);
1431
1432
1433         return status;
1434 }
1435
1436 static enum dc_status enable_link_dp_mst(
1437                 struct dc_state *state,
1438                 struct pipe_ctx *pipe_ctx)
1439 {
1440         struct dc_link *link = pipe_ctx->stream->sink->link;
1441
1442         /* sink signal type after MST branch is MST. Multiple MST sinks
1443          * share one link. Link DP PHY is enable or training only once.
1444          */
1445         if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
1446                 return DC_OK;
1447
1448         /* clear payload table */
1449         dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
1450
1451         /* set the sink to MST mode before enabling the link */
1452         dp_enable_mst_on_sink(link, true);
1453
1454         return enable_link_dp(state, pipe_ctx);
1455 }
1456
1457 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
1458                 enum engine_id eng_id,
1459                 struct ext_hdmi_settings *settings)
1460 {
1461         bool result = false;
1462         int i = 0;
1463         struct integrated_info *integrated_info =
1464                         pipe_ctx->stream->ctx->dc_bios->integrated_info;
1465
1466         if (integrated_info == NULL)
1467                 return false;
1468
1469         /*
1470          * Get retimer settings from sbios for passing SI eye test for DCE11
1471          * The setting values are varied based on board revision and port id
1472          * Therefore the setting values of each ports is passed by sbios.
1473          */
1474
1475         // Check if current bios contains ext Hdmi settings
1476         if (integrated_info->gpu_cap_info & 0x20) {
1477                 switch (eng_id) {
1478                 case ENGINE_ID_DIGA:
1479                         settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
1480                         settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
1481                         settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
1482                         memmove(settings->reg_settings,
1483                                         integrated_info->dp0_ext_hdmi_reg_settings,
1484                                         sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
1485                         memmove(settings->reg_settings_6g,
1486                                         integrated_info->dp0_ext_hdmi_6g_reg_settings,
1487                                         sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
1488                         result = true;
1489                         break;
1490                 case ENGINE_ID_DIGB:
1491                         settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
1492                         settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
1493                         settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
1494                         memmove(settings->reg_settings,
1495                                         integrated_info->dp1_ext_hdmi_reg_settings,
1496                                         sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
1497                         memmove(settings->reg_settings_6g,
1498                                         integrated_info->dp1_ext_hdmi_6g_reg_settings,
1499                                         sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
1500                         result = true;
1501                         break;
1502                 case ENGINE_ID_DIGC:
1503                         settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
1504                         settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
1505                         settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
1506                         memmove(settings->reg_settings,
1507                                         integrated_info->dp2_ext_hdmi_reg_settings,
1508                                         sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
1509                         memmove(settings->reg_settings_6g,
1510                                         integrated_info->dp2_ext_hdmi_6g_reg_settings,
1511                                         sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
1512                         result = true;
1513                         break;
1514                 case ENGINE_ID_DIGD:
1515                         settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
1516                         settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
1517                         settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
1518                         memmove(settings->reg_settings,
1519                                         integrated_info->dp3_ext_hdmi_reg_settings,
1520                                         sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
1521                         memmove(settings->reg_settings_6g,
1522                                         integrated_info->dp3_ext_hdmi_6g_reg_settings,
1523                                         sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
1524                         result = true;
1525                         break;
1526                 default:
1527                         break;
1528                 }
1529
1530                 if (result == true) {
1531                         // Validate settings from bios integrated info table
1532                         if (settings->slv_addr == 0)
1533                                 return false;
1534                         if (settings->reg_num > 9)
1535                                 return false;
1536                         if (settings->reg_num_6g > 3)
1537                                 return false;
1538
1539                         for (i = 0; i < settings->reg_num; i++) {
1540                                 if (settings->reg_settings[i].i2c_reg_index > 0x20)
1541                                         return false;
1542                         }
1543
1544                         for (i = 0; i < settings->reg_num_6g; i++) {
1545                                 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
1546                                         return false;
1547                         }
1548                 }
1549         }
1550
1551         return result;
1552 }
1553
1554 static bool i2c_write(struct pipe_ctx *pipe_ctx,
1555                 uint8_t address, uint8_t *buffer, uint32_t length)
1556 {
1557         struct i2c_command cmd = {0};
1558         struct i2c_payload payload = {0};
1559
1560         memset(&payload, 0, sizeof(payload));
1561         memset(&cmd, 0, sizeof(cmd));
1562
1563         cmd.number_of_payloads = 1;
1564         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1565         cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
1566
1567         payload.address = address;
1568         payload.data = buffer;
1569         payload.length = length;
1570         payload.write = true;
1571         cmd.payloads = &payload;
1572
1573         if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
1574                         pipe_ctx->stream->sink->link, &cmd))
1575                 return true;
1576
1577         return false;
1578 }
1579
1580 static void write_i2c_retimer_setting(
1581                 struct pipe_ctx *pipe_ctx,
1582                 bool is_vga_mode,
1583                 bool is_over_340mhz,
1584                 struct ext_hdmi_settings *settings)
1585 {
1586         uint8_t slave_address = (settings->slv_addr >> 1);
1587         uint8_t buffer[2];
1588         const uint8_t apply_rx_tx_change = 0x4;
1589         uint8_t offset = 0xA;
1590         uint8_t value = 0;
1591         int i = 0;
1592         bool i2c_success = false;
1593         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1594
1595         memset(&buffer, 0, sizeof(buffer));
1596
1597         /* Start Ext-Hdmi programming*/
1598
1599         for (i = 0; i < settings->reg_num; i++) {
1600                 /* Apply 3G settings */
1601                 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1602
1603                         buffer[0] = settings->reg_settings[i].i2c_reg_index;
1604                         buffer[1] = settings->reg_settings[i].i2c_reg_val;
1605                         i2c_success = i2c_write(pipe_ctx, slave_address,
1606                                                 buffer, sizeof(buffer));
1607                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1608                                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1609                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1610
1611                         if (!i2c_success)
1612                                 /* Write failure */
1613                                 ASSERT(i2c_success);
1614
1615                         /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1616                          * needs to be set to 1 on every 0xA-0xC write.
1617                          */
1618                         if (settings->reg_settings[i].i2c_reg_index == 0xA ||
1619                                 settings->reg_settings[i].i2c_reg_index == 0xB ||
1620                                 settings->reg_settings[i].i2c_reg_index == 0xC) {
1621
1622                                 /* Query current value from offset 0xA */
1623                                 if (settings->reg_settings[i].i2c_reg_index == 0xA)
1624                                         value = settings->reg_settings[i].i2c_reg_val;
1625                                 else {
1626                                         i2c_success =
1627                                                 dal_ddc_service_query_ddc_data(
1628                                                 pipe_ctx->stream->sink->link->ddc,
1629                                                 slave_address, &offset, 1, &value, 1);
1630                                         if (!i2c_success)
1631                                                 /* Write failure */
1632                                                 ASSERT(i2c_success);
1633                                 }
1634
1635                                 buffer[0] = offset;
1636                                 /* Set APPLY_RX_TX_CHANGE bit to 1 */
1637                                 buffer[1] = value | apply_rx_tx_change;
1638                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1639                                                 buffer, sizeof(buffer));
1640                                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1641                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1642                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1643                                 if (!i2c_success)
1644                                         /* Write failure */
1645                                         ASSERT(i2c_success);
1646                         }
1647                 }
1648         }
1649
1650         /* Apply 3G settings */
1651         if (is_over_340mhz) {
1652                 for (i = 0; i < settings->reg_num_6g; i++) {
1653                         /* Apply 3G settings */
1654                         if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1655
1656                                 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
1657                                 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
1658                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1659                                                         buffer, sizeof(buffer));
1660                                 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
1661                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1662                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1663
1664                                 if (!i2c_success)
1665                                         /* Write failure */
1666                                         ASSERT(i2c_success);
1667
1668                                 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1669                                  * needs to be set to 1 on every 0xA-0xC write.
1670                                  */
1671                                 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
1672                                         settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
1673                                         settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
1674
1675                                         /* Query current value from offset 0xA */
1676                                         if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
1677                                                 value = settings->reg_settings_6g[i].i2c_reg_val;
1678                                         else {
1679                                                 i2c_success =
1680                                                                 dal_ddc_service_query_ddc_data(
1681                                                                 pipe_ctx->stream->sink->link->ddc,
1682                                                                 slave_address, &offset, 1, &value, 1);
1683                                                 if (!i2c_success)
1684                                                         /* Write failure */
1685                                                         ASSERT(i2c_success);
1686                                         }
1687
1688                                         buffer[0] = offset;
1689                                         /* Set APPLY_RX_TX_CHANGE bit to 1 */
1690                                         buffer[1] = value | apply_rx_tx_change;
1691                                         i2c_success = i2c_write(pipe_ctx, slave_address,
1692                                                         buffer, sizeof(buffer));
1693                                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1694                                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1695                                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1696                                         if (!i2c_success)
1697                                                 /* Write failure */
1698                                                 ASSERT(i2c_success);
1699                                 }
1700                         }
1701                 }
1702         }
1703
1704         if (is_vga_mode) {
1705                 /* Program additional settings if using 640x480 resolution */
1706
1707                 /* Write offset 0xFF to 0x01 */
1708                 buffer[0] = 0xff;
1709                 buffer[1] = 0x01;
1710                 i2c_success = i2c_write(pipe_ctx, slave_address,
1711                                 buffer, sizeof(buffer));
1712                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1713                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1714                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1715                 if (!i2c_success)
1716                         /* Write failure */
1717                         ASSERT(i2c_success);
1718
1719                 /* Write offset 0x00 to 0x23 */
1720                 buffer[0] = 0x00;
1721                 buffer[1] = 0x23;
1722                 i2c_success = i2c_write(pipe_ctx, slave_address,
1723                                 buffer, sizeof(buffer));
1724                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1725                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1726                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1727                 if (!i2c_success)
1728                         /* Write failure */
1729                         ASSERT(i2c_success);
1730
1731                 /* Write offset 0xff to 0x00 */
1732                 buffer[0] = 0xff;
1733                 buffer[1] = 0x00;
1734                 i2c_success = i2c_write(pipe_ctx, slave_address,
1735                                 buffer, sizeof(buffer));
1736                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1737                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1738                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1739                 if (!i2c_success)
1740                         /* Write failure */
1741                         ASSERT(i2c_success);
1742
1743         }
1744 }
1745
1746 static void write_i2c_default_retimer_setting(
1747                 struct pipe_ctx *pipe_ctx,
1748                 bool is_vga_mode,
1749                 bool is_over_340mhz)
1750 {
1751         uint8_t slave_address = (0xBA >> 1);
1752         uint8_t buffer[2];
1753         bool i2c_success = false;
1754         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1755
1756         memset(&buffer, 0, sizeof(buffer));
1757
1758         /* Program Slave Address for tuning single integrity */
1759         /* Write offset 0x0A to 0x13 */
1760         buffer[0] = 0x0A;
1761         buffer[1] = 0x13;
1762         i2c_success = i2c_write(pipe_ctx, slave_address,
1763                         buffer, sizeof(buffer));
1764         RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
1765                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1766                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1767         if (!i2c_success)
1768                 /* Write failure */
1769                 ASSERT(i2c_success);
1770
1771         /* Write offset 0x0A to 0x17 */
1772         buffer[0] = 0x0A;
1773         buffer[1] = 0x17;
1774         i2c_success = i2c_write(pipe_ctx, slave_address,
1775                         buffer, sizeof(buffer));
1776         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1777                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1778                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1779         if (!i2c_success)
1780                 /* Write failure */
1781                 ASSERT(i2c_success);
1782
1783         /* Write offset 0x0B to 0xDA or 0xD8 */
1784         buffer[0] = 0x0B;
1785         buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
1786         i2c_success = i2c_write(pipe_ctx, slave_address,
1787                         buffer, sizeof(buffer));
1788         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1789                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1790                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1791         if (!i2c_success)
1792                 /* Write failure */
1793                 ASSERT(i2c_success);
1794
1795         /* Write offset 0x0A to 0x17 */
1796         buffer[0] = 0x0A;
1797         buffer[1] = 0x17;
1798         i2c_success = i2c_write(pipe_ctx, slave_address,
1799                         buffer, sizeof(buffer));
1800         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1801                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1802                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1803         if (!i2c_success)
1804                 /* Write failure */
1805                 ASSERT(i2c_success);
1806
1807         /* Write offset 0x0C to 0x1D or 0x91 */
1808         buffer[0] = 0x0C;
1809         buffer[1] = is_over_340mhz ? 0x1D : 0x91;
1810         i2c_success = i2c_write(pipe_ctx, slave_address,
1811                         buffer, sizeof(buffer));
1812         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1813                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1814                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1815         if (!i2c_success)
1816                 /* Write failure */
1817                 ASSERT(i2c_success);
1818
1819         /* Write offset 0x0A to 0x17 */
1820         buffer[0] = 0x0A;
1821         buffer[1] = 0x17;
1822         i2c_success = i2c_write(pipe_ctx, slave_address,
1823                         buffer, sizeof(buffer));
1824         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1825                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1826                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1827         if (!i2c_success)
1828                 /* Write failure */
1829                 ASSERT(i2c_success);
1830
1831
1832         if (is_vga_mode) {
1833                 /* Program additional settings if using 640x480 resolution */
1834
1835                 /* Write offset 0xFF to 0x01 */
1836                 buffer[0] = 0xff;
1837                 buffer[1] = 0x01;
1838                 i2c_success = i2c_write(pipe_ctx, slave_address,
1839                                 buffer, sizeof(buffer));
1840                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1841                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1842                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1843                 if (!i2c_success)
1844                         /* Write failure */
1845                         ASSERT(i2c_success);
1846
1847                 /* Write offset 0x00 to 0x23 */
1848                 buffer[0] = 0x00;
1849                 buffer[1] = 0x23;
1850                 i2c_success = i2c_write(pipe_ctx, slave_address,
1851                                 buffer, sizeof(buffer));
1852                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1853                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1854                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1855                 if (!i2c_success)
1856                         /* Write failure */
1857                         ASSERT(i2c_success);
1858
1859                 /* Write offset 0xff to 0x00 */
1860                 buffer[0] = 0xff;
1861                 buffer[1] = 0x00;
1862                 i2c_success = i2c_write(pipe_ctx, slave_address,
1863                                 buffer, sizeof(buffer));
1864                 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
1865                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
1866                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1867                 if (!i2c_success)
1868                         /* Write failure */
1869                         ASSERT(i2c_success);
1870         }
1871 }
1872
1873 static void write_i2c_redriver_setting(
1874                 struct pipe_ctx *pipe_ctx,
1875                 bool is_over_340mhz)
1876 {
1877         uint8_t slave_address = (0xF0 >> 1);
1878         uint8_t buffer[16];
1879         bool i2c_success = false;
1880         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1881
1882         memset(&buffer, 0, sizeof(buffer));
1883
1884         // Program Slave Address for tuning single integrity
1885         buffer[3] = 0x4E;
1886         buffer[4] = 0x4E;
1887         buffer[5] = 0x4E;
1888         buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
1889
1890         i2c_success = i2c_write(pipe_ctx, slave_address,
1891                                         buffer, sizeof(buffer));
1892         RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
1893                 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
1894                 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
1895                 i2c_success = %d\n",
1896                 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
1897
1898         if (!i2c_success)
1899                 /* Write failure */
1900                 ASSERT(i2c_success);
1901 }
1902
1903 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
1904 {
1905         struct dc_stream_state *stream = pipe_ctx->stream;
1906         struct dc_link *link = stream->sink->link;
1907         enum dc_color_depth display_color_depth;
1908         enum engine_id eng_id;
1909         struct ext_hdmi_settings settings = {0};
1910         bool is_over_340mhz = false;
1911         bool is_vga_mode = (stream->timing.h_addressable == 640)
1912                         && (stream->timing.v_addressable == 480);
1913
1914         if (stream->phy_pix_clk == 0)
1915                 stream->phy_pix_clk = stream->timing.pix_clk_khz;
1916         if (stream->phy_pix_clk > 340000)
1917                 is_over_340mhz = true;
1918
1919         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
1920                 unsigned short masked_chip_caps = pipe_ctx->stream->sink->link->chip_caps &
1921                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
1922                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
1923                         /* DP159, Retimer settings */
1924                         eng_id = pipe_ctx->stream_res.stream_enc->id;
1925
1926                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
1927                                 write_i2c_retimer_setting(pipe_ctx,
1928                                                 is_vga_mode, is_over_340mhz, &settings);
1929                         } else {
1930                                 write_i2c_default_retimer_setting(pipe_ctx,
1931                                                 is_vga_mode, is_over_340mhz);
1932                         }
1933                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
1934                         /* PI3EQX1204, Redriver settings */
1935                         write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
1936                 }
1937         }
1938
1939         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1940                 dal_ddc_service_write_scdc_data(
1941                         stream->sink->link->ddc,
1942                         stream->phy_pix_clk,
1943                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
1944
1945         memset(&stream->sink->link->cur_link_settings, 0,
1946                         sizeof(struct dc_link_settings));
1947
1948         display_color_depth = stream->timing.display_color_depth;
1949         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1950                 display_color_depth = COLOR_DEPTH_888;
1951
1952         link->link_enc->funcs->enable_tmds_output(
1953                         link->link_enc,
1954                         pipe_ctx->clock_source->id,
1955                         display_color_depth,
1956                         pipe_ctx->stream->signal,
1957                         stream->phy_pix_clk);
1958
1959         if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
1960                 dal_ddc_service_read_scdc_data(link->ddc);
1961 }
1962
1963 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
1964 {
1965         struct dc_stream_state *stream = pipe_ctx->stream;
1966         struct dc_link *link = stream->sink->link;
1967
1968         if (stream->phy_pix_clk == 0)
1969                 stream->phy_pix_clk = stream->timing.pix_clk_khz;
1970
1971         memset(&stream->sink->link->cur_link_settings, 0,
1972                         sizeof(struct dc_link_settings));
1973
1974         link->link_enc->funcs->enable_lvds_output(
1975                         link->link_enc,
1976                         pipe_ctx->clock_source->id,
1977                         stream->phy_pix_clk);
1978
1979 }
1980
1981 /****************************enable_link***********************************/
1982 static enum dc_status enable_link(
1983                 struct dc_state *state,
1984                 struct pipe_ctx *pipe_ctx)
1985 {
1986         enum dc_status status = DC_ERROR_UNEXPECTED;
1987         switch (pipe_ctx->stream->signal) {
1988         case SIGNAL_TYPE_DISPLAY_PORT:
1989                 status = enable_link_dp(state, pipe_ctx);
1990                 break;
1991         case SIGNAL_TYPE_EDP:
1992                 status = enable_link_edp(state, pipe_ctx);
1993                 break;
1994         case SIGNAL_TYPE_DISPLAY_PORT_MST:
1995                 status = enable_link_dp_mst(state, pipe_ctx);
1996                 msleep(200);
1997                 break;
1998         case SIGNAL_TYPE_DVI_SINGLE_LINK:
1999         case SIGNAL_TYPE_DVI_DUAL_LINK:
2000         case SIGNAL_TYPE_HDMI_TYPE_A:
2001                 enable_link_hdmi(pipe_ctx);
2002                 status = DC_OK;
2003                 break;
2004         case SIGNAL_TYPE_LVDS:
2005                 enable_link_lvds(pipe_ctx);
2006                 status = DC_OK;
2007                 break;
2008         case SIGNAL_TYPE_VIRTUAL:
2009                 status = DC_OK;
2010                 break;
2011         default:
2012                 break;
2013         }
2014
2015         return status;
2016 }
2017
2018 static void disable_link(struct dc_link *link, enum signal_type signal)
2019 {
2020         /*
2021          * TODO: implement call for dp_set_hw_test_pattern
2022          * it is needed for compliance testing
2023          */
2024
2025         /* here we need to specify that encoder output settings
2026          * need to be calculated as for the set mode,
2027          * it will lead to querying dynamic link capabilities
2028          * which should be done before enable output */
2029
2030         if (dc_is_dp_signal(signal)) {
2031                 /* SST DP, eDP */
2032                 if (dc_is_dp_sst_signal(signal))
2033                         dp_disable_link_phy(link, signal);
2034                 else
2035                         dp_disable_link_phy_mst(link, signal);
2036         } else
2037                 link->link_enc->funcs->disable_output(link->link_enc, signal);
2038 }
2039
2040 static bool dp_active_dongle_validate_timing(
2041                 const struct dc_crtc_timing *timing,
2042                 const struct dpcd_caps *dpcd_caps)
2043 {
2044         unsigned int required_pix_clk = timing->pix_clk_khz;
2045         const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2046
2047         switch (dpcd_caps->dongle_type) {
2048         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2049         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2050         case DISPLAY_DONGLE_DP_DVI_DONGLE:
2051                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2052                         return true;
2053                 else
2054                         return false;
2055         default:
2056                 break;
2057         }
2058
2059         if (dongle_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
2060                 dongle_caps->extendedCapValid == false)
2061                 return true;
2062
2063         /* Check Pixel Encoding */
2064         switch (timing->pixel_encoding) {
2065         case PIXEL_ENCODING_RGB:
2066         case PIXEL_ENCODING_YCBCR444:
2067                 break;
2068         case PIXEL_ENCODING_YCBCR422:
2069                 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2070                         return false;
2071                 break;
2072         case PIXEL_ENCODING_YCBCR420:
2073                 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2074                         return false;
2075                 break;
2076         default:
2077                 /* Invalid Pixel Encoding*/
2078                 return false;
2079         }
2080
2081
2082         /* Check Color Depth and Pixel Clock */
2083         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2084                 required_pix_clk /= 2;
2085         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2086                 required_pix_clk = required_pix_clk * 2 / 3;
2087
2088         switch (timing->display_color_depth) {
2089         case COLOR_DEPTH_666:
2090         case COLOR_DEPTH_888:
2091                 /*888 and 666 should always be supported*/
2092                 break;
2093         case COLOR_DEPTH_101010:
2094                 if (dongle_caps->dp_hdmi_max_bpc < 10)
2095                         return false;
2096                 required_pix_clk = required_pix_clk * 10 / 8;
2097                 break;
2098         case COLOR_DEPTH_121212:
2099                 if (dongle_caps->dp_hdmi_max_bpc < 12)
2100                         return false;
2101                 required_pix_clk = required_pix_clk * 12 / 8;
2102                 break;
2103
2104         case COLOR_DEPTH_141414:
2105         case COLOR_DEPTH_161616:
2106         default:
2107                 /* These color depths are currently not supported */
2108                 return false;
2109         }
2110
2111         if (required_pix_clk > dongle_caps->dp_hdmi_max_pixel_clk)
2112                 return false;
2113
2114         return true;
2115 }
2116
2117 enum dc_status dc_link_validate_mode_timing(
2118                 const struct dc_stream_state *stream,
2119                 struct dc_link *link,
2120                 const struct dc_crtc_timing *timing)
2121 {
2122         uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk;
2123         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2124
2125         /* A hack to avoid failing any modes for EDID override feature on
2126          * topology change such as lower quality cable for DP or different dongle
2127          */
2128         if (link->remote_sinks[0])
2129                 return DC_OK;
2130
2131         /* Passive Dongle */
2132         if (0 != max_pix_clk && timing->pix_clk_khz > max_pix_clk)
2133                 return DC_EXCEED_DONGLE_CAP;
2134
2135         /* Active Dongle*/
2136         if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2137                 return DC_EXCEED_DONGLE_CAP;
2138
2139         switch (stream->signal) {
2140         case SIGNAL_TYPE_EDP:
2141         case SIGNAL_TYPE_DISPLAY_PORT:
2142                 if (!dp_validate_mode_timing(
2143                                 link,
2144                                 timing))
2145                         return DC_NO_DP_LINK_BANDWIDTH;
2146                 break;
2147
2148         default:
2149                 break;
2150         }
2151
2152         return DC_OK;
2153 }
2154
2155 int dc_link_get_backlight_level(const struct dc_link *link)
2156 {
2157         struct abm *abm = link->ctx->dc->res_pool->abm;
2158
2159         if (abm == NULL || abm->funcs->get_current_backlight_8_bit == NULL)
2160                 return DC_ERROR_UNEXPECTED;
2161
2162         return (int) abm->funcs->get_current_backlight_8_bit(abm);
2163 }
2164
2165 bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level,
2166                 uint32_t frame_ramp, const struct dc_stream_state *stream)
2167 {
2168         struct dc  *core_dc = link->ctx->dc;
2169         struct abm *abm = core_dc->res_pool->abm;
2170         struct dmcu *dmcu = core_dc->res_pool->dmcu;
2171         unsigned int controller_id = 0;
2172         bool use_smooth_brightness = true;
2173         int i;
2174         DC_LOGGER_INIT(link->ctx->logger);
2175
2176         if ((dmcu == NULL) ||
2177                 (abm == NULL) ||
2178                 (abm->funcs->set_backlight_level == NULL))
2179                 return false;
2180
2181         if (stream) {
2182                 if (stream->bl_pwm_level == EDP_BACKLIGHT_RAMP_DISABLE_LEVEL)
2183                         frame_ramp = 0;
2184
2185                 ((struct dc_stream_state *)stream)->bl_pwm_level = level;
2186         }
2187
2188         use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2189
2190         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n", level, level);
2191
2192         if (dc_is_embedded_signal(link->connector_signal)) {
2193                 if (stream != NULL) {
2194                         for (i = 0; i < MAX_PIPES; i++) {
2195                                 if (core_dc->current_state->res_ctx.
2196                                                 pipe_ctx[i].stream
2197                                                 == stream)
2198                                         /* DMCU -1 for all controller id values,
2199                                          * therefore +1 here
2200                                          */
2201                                         controller_id =
2202                                                 core_dc->current_state->
2203                                                 res_ctx.pipe_ctx[i].stream_res.tg->inst +
2204                                                 1;
2205                         }
2206                 }
2207                 abm->funcs->set_backlight_level(
2208                                 abm,
2209                                 level,
2210                                 frame_ramp,
2211                                 controller_id,
2212                                 use_smooth_brightness);
2213         }
2214
2215         return true;
2216 }
2217
2218 bool dc_link_set_abm_disable(const struct dc_link *link)
2219 {
2220         struct dc  *core_dc = link->ctx->dc;
2221         struct abm *abm = core_dc->res_pool->abm;
2222
2223         if ((abm == NULL) || (abm->funcs->set_backlight_level == NULL))
2224                 return false;
2225
2226         abm->funcs->set_abm_immediate_disable(abm);
2227
2228         return true;
2229 }
2230
2231 bool dc_link_set_psr_enable(const struct dc_link *link, bool enable, bool wait)
2232 {
2233         struct dc  *core_dc = link->ctx->dc;
2234         struct dmcu *dmcu = core_dc->res_pool->dmcu;
2235
2236         if (dmcu != NULL && link->psr_enabled)
2237                 dmcu->funcs->set_psr_enable(dmcu, enable, wait);
2238
2239         return true;
2240 }
2241
2242 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
2243 {
2244         return &link->link_status;
2245 }
2246
2247 void core_link_resume(struct dc_link *link)
2248 {
2249         if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
2250                 program_hpd_filter(link);
2251 }
2252
2253 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
2254 {
2255         struct dc_link_settings *link_settings =
2256                         &stream->sink->link->cur_link_settings;
2257         uint32_t link_rate_in_mbps =
2258                         link_settings->link_rate * LINK_RATE_REF_FREQ_IN_MHZ;
2259         struct fixed31_32 mbps = dc_fixpt_from_int(
2260                         link_rate_in_mbps * link_settings->lane_count);
2261
2262         return dc_fixpt_div_int(mbps, 54);
2263 }
2264
2265 static int get_color_depth(enum dc_color_depth color_depth)
2266 {
2267         switch (color_depth) {
2268         case COLOR_DEPTH_666: return 6;
2269         case COLOR_DEPTH_888: return 8;
2270         case COLOR_DEPTH_101010: return 10;
2271         case COLOR_DEPTH_121212: return 12;
2272         case COLOR_DEPTH_141414: return 14;
2273         case COLOR_DEPTH_161616: return 16;
2274         default: return 0;
2275         }
2276 }
2277
2278 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
2279 {
2280         uint32_t bpc;
2281         uint64_t kbps;
2282         struct fixed31_32 peak_kbps;
2283         uint32_t numerator;
2284         uint32_t denominator;
2285
2286         bpc = get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth);
2287         kbps = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk * bpc * 3;
2288
2289         /*
2290          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
2291          * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
2292          * common multiplier to render an integer PBN for all link rate/lane
2293          * counts combinations
2294          * calculate
2295          * peak_kbps *= (1006/1000)
2296          * peak_kbps *= (64/54)
2297          * peak_kbps *= 8    convert to bytes
2298          */
2299
2300         numerator = 64 * PEAK_FACTOR_X1000;
2301         denominator = 54 * 8 * 1000 * 1000;
2302         kbps *= numerator;
2303         peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
2304
2305         return peak_kbps;
2306 }
2307
2308 static void update_mst_stream_alloc_table(
2309         struct dc_link *link,
2310         struct stream_encoder *stream_enc,
2311         const struct dp_mst_stream_allocation_table *proposed_table)
2312 {
2313         struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
2314                         { 0 } };
2315         struct link_mst_stream_allocation *dc_alloc;
2316
2317         int i;
2318         int j;
2319
2320         /* if DRM proposed_table has more than one new payload */
2321         ASSERT(proposed_table->stream_count -
2322                         link->mst_stream_alloc_table.stream_count < 2);
2323
2324         /* copy proposed_table to link, add stream encoder */
2325         for (i = 0; i < proposed_table->stream_count; i++) {
2326
2327                 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
2328                         dc_alloc =
2329                         &link->mst_stream_alloc_table.stream_allocations[j];
2330
2331                         if (dc_alloc->vcp_id ==
2332                                 proposed_table->stream_allocations[i].vcp_id) {
2333
2334                                 work_table[i] = *dc_alloc;
2335                                 break; /* exit j loop */
2336                         }
2337                 }
2338
2339                 /* new vcp_id */
2340                 if (j == link->mst_stream_alloc_table.stream_count) {
2341                         work_table[i].vcp_id =
2342                                 proposed_table->stream_allocations[i].vcp_id;
2343                         work_table[i].slot_count =
2344                                 proposed_table->stream_allocations[i].slot_count;
2345                         work_table[i].stream_enc = stream_enc;
2346                 }
2347         }
2348
2349         /* update link->mst_stream_alloc_table with work_table */
2350         link->mst_stream_alloc_table.stream_count =
2351                         proposed_table->stream_count;
2352         for (i = 0; i < MAX_CONTROLLER_NUM; i++)
2353                 link->mst_stream_alloc_table.stream_allocations[i] =
2354                                 work_table[i];
2355 }
2356
2357 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
2358  * because stream_encoder is not exposed to dm
2359  */
2360 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
2361 {
2362         struct dc_stream_state *stream = pipe_ctx->stream;
2363         struct dc_link *link = stream->sink->link;
2364         struct link_encoder *link_encoder = link->link_enc;
2365         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2366         struct dp_mst_stream_allocation_table proposed_table = {0};
2367         struct fixed31_32 avg_time_slots_per_mtp;
2368         struct fixed31_32 pbn;
2369         struct fixed31_32 pbn_per_slot;
2370         uint8_t i;
2371         DC_LOGGER_INIT(link->ctx->logger);
2372
2373         /* enable_link_dp_mst already check link->enabled_stream_count
2374          * and stream is in link->stream[]. This is called during set mode,
2375          * stream_enc is available.
2376          */
2377
2378         /* get calculate VC payload for stream: stream_alloc */
2379         if (dm_helpers_dp_mst_write_payload_allocation_table(
2380                 stream->ctx,
2381                 stream,
2382                 &proposed_table,
2383                 true)) {
2384                 update_mst_stream_alloc_table(
2385                                         link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2386         }
2387         else
2388                 DC_LOG_WARNING("Failed to update"
2389                                 "MST allocation table for"
2390                                 "pipe idx:%d\n",
2391                                 pipe_ctx->pipe_idx);
2392
2393         DC_LOG_MST("%s  "
2394                         "stream_count: %d: \n ",
2395                         __func__,
2396                         link->mst_stream_alloc_table.stream_count);
2397
2398         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2399                 DC_LOG_MST("stream_enc[%d]: %p      "
2400                 "stream[%d].vcp_id: %d      "
2401                 "stream[%d].slot_count: %d\n",
2402                 i,
2403                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2404                 i,
2405                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2406                 i,
2407                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2408         }
2409
2410         ASSERT(proposed_table.stream_count > 0);
2411
2412         /* program DP source TX for payload */
2413         link_encoder->funcs->update_mst_stream_allocation_table(
2414                 link_encoder,
2415                 &link->mst_stream_alloc_table);
2416
2417         /* send down message */
2418         dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2419                         stream->ctx,
2420                         stream);
2421
2422         dm_helpers_dp_mst_send_payload_allocation(
2423                         stream->ctx,
2424                         stream,
2425                         true);
2426
2427         /* slot X.Y for only current stream */
2428         pbn_per_slot = get_pbn_per_slot(stream);
2429         pbn = get_pbn_from_timing(pipe_ctx);
2430         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
2431
2432         stream_encoder->funcs->set_mst_bandwidth(
2433                 stream_encoder,
2434                 avg_time_slots_per_mtp);
2435
2436         return DC_OK;
2437
2438 }
2439
2440 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
2441 {
2442         struct dc_stream_state *stream = pipe_ctx->stream;
2443         struct dc_link *link = stream->sink->link;
2444         struct link_encoder *link_encoder = link->link_enc;
2445         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2446         struct dp_mst_stream_allocation_table proposed_table = {0};
2447         struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
2448         uint8_t i;
2449         bool mst_mode = (link->type == dc_connection_mst_branch);
2450         DC_LOGGER_INIT(link->ctx->logger);
2451
2452         /* deallocate_mst_payload is called before disable link. When mode or
2453          * disable/enable monitor, new stream is created which is not in link
2454          * stream[] yet. For this, payload is not allocated yet, so de-alloc
2455          * should not done. For new mode set, map_resources will get engine
2456          * for new stream, so stream_enc->id should be validated until here.
2457          */
2458
2459         /* slot X.Y */
2460         stream_encoder->funcs->set_mst_bandwidth(
2461                 stream_encoder,
2462                 avg_time_slots_per_mtp);
2463
2464         /* TODO: which component is responsible for remove payload table? */
2465         if (mst_mode) {
2466                 if (dm_helpers_dp_mst_write_payload_allocation_table(
2467                                 stream->ctx,
2468                                 stream,
2469                                 &proposed_table,
2470                                 false)) {
2471
2472                         update_mst_stream_alloc_table(
2473                                 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2474                 }
2475                 else {
2476                                 DC_LOG_WARNING("Failed to update"
2477                                                 "MST allocation table for"
2478                                                 "pipe idx:%d\n",
2479                                                 pipe_ctx->pipe_idx);
2480                 }
2481         }
2482
2483         DC_LOG_MST("%s"
2484                         "stream_count: %d: ",
2485                         __func__,
2486                         link->mst_stream_alloc_table.stream_count);
2487
2488         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2489                 DC_LOG_MST("stream_enc[%d]: %p      "
2490                 "stream[%d].vcp_id: %d      "
2491                 "stream[%d].slot_count: %d\n",
2492                 i,
2493                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2494                 i,
2495                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2496                 i,
2497                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2498         }
2499
2500         link_encoder->funcs->update_mst_stream_allocation_table(
2501                 link_encoder,
2502                 &link->mst_stream_alloc_table);
2503
2504         if (mst_mode) {
2505                 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2506                         stream->ctx,
2507                         stream);
2508
2509                 dm_helpers_dp_mst_send_payload_allocation(
2510                         stream->ctx,
2511                         stream,
2512                         false);
2513         }
2514
2515         return DC_OK;
2516 }
2517
2518 void core_link_enable_stream(
2519                 struct dc_state *state,
2520                 struct pipe_ctx *pipe_ctx)
2521 {
2522         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2523         struct dc_stream_state *stream = pipe_ctx->stream;
2524         enum dc_status status;
2525         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2526
2527         if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) {
2528                 stream->sink->link->link_enc->funcs->setup(
2529                         stream->sink->link->link_enc,
2530                         pipe_ctx->stream->signal);
2531                 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
2532                         pipe_ctx->stream_res.stream_enc,
2533                         pipe_ctx->stream_res.tg->inst,
2534                         stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
2535         }
2536
2537         if (dc_is_dp_signal(pipe_ctx->stream->signal))
2538                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
2539                         pipe_ctx->stream_res.stream_enc,
2540                         &stream->timing,
2541                         stream->output_color_space);
2542
2543         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2544                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
2545                         pipe_ctx->stream_res.stream_enc,
2546                         &stream->timing,
2547                         stream->phy_pix_clk,
2548                         pipe_ctx->stream_res.audio != NULL);
2549
2550         if (dc_is_dvi_signal(pipe_ctx->stream->signal))
2551                 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
2552                         pipe_ctx->stream_res.stream_enc,
2553                         &stream->timing,
2554                         (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
2555                         true : false);
2556
2557         if (dc_is_lvds_signal(pipe_ctx->stream->signal))
2558                 pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
2559                         pipe_ctx->stream_res.stream_enc,
2560                         &stream->timing);
2561
2562         if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
2563                 resource_build_info_frame(pipe_ctx);
2564                 core_dc->hwss.update_info_frame(pipe_ctx);
2565
2566                 /* eDP lit up by bios already, no need to enable again. */
2567                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
2568                                 pipe_ctx->stream->apply_edp_fast_boot_optimization) {
2569                         pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
2570                         pipe_ctx->stream->dpms_off = false;
2571                         return;
2572                 }
2573
2574                 if (pipe_ctx->stream->dpms_off)
2575                         return;
2576
2577                 status = enable_link(state, pipe_ctx);
2578
2579                 if (status != DC_OK) {
2580                         DC_LOG_WARNING("enabling link %u failed: %d\n",
2581                         pipe_ctx->stream->sink->link->link_index,
2582                         status);
2583
2584                         /* Abort stream enable *unless* the failure was due to
2585                          * DP link training - some DP monitors will recover and
2586                          * show the stream anyway. But MST displays can't proceed
2587                          * without link training.
2588                          */
2589                         if (status != DC_FAIL_DP_LINK_TRAINING ||
2590                                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2591                                 BREAK_TO_DEBUGGER();
2592                                 return;
2593                         }
2594                 }
2595
2596                 core_dc->hwss.enable_audio_stream(pipe_ctx);
2597
2598                 /* turn off otg test pattern if enable */
2599                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
2600                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
2601                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2602                                         COLOR_DEPTH_UNDEFINED);
2603
2604                 core_dc->hwss.enable_stream(pipe_ctx);
2605
2606                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2607                         allocate_mst_payload(pipe_ctx);
2608
2609                 core_dc->hwss.unblank_stream(pipe_ctx,
2610                         &pipe_ctx->stream->sink->link->cur_link_settings);
2611
2612         }
2613
2614 }
2615
2616 void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
2617 {
2618         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2619
2620         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2621                 deallocate_mst_payload(pipe_ctx);
2622
2623         core_dc->hwss.blank_stream(pipe_ctx);
2624
2625         core_dc->hwss.disable_stream(pipe_ctx, option);
2626
2627         disable_link(pipe_ctx->stream->sink->link, pipe_ctx->stream->signal);
2628 }
2629
2630 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
2631 {
2632         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2633
2634         if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2635                 return;
2636
2637         core_dc->hwss.set_avmute(pipe_ctx, enable);
2638 }
2639
2640 /**
2641  *****************************************************************************
2642  *  Function: dc_link_enable_hpd_filter
2643  *
2644  *  @brief
2645  *     If enable is true, programs HPD filter on associated HPD line using
2646  *     delay_on_disconnect/delay_on_connect values dependent on
2647  *     link->connector_signal
2648  *
2649  *     If enable is false, programs HPD filter on associated HPD line with no
2650  *     delays on connect or disconnect
2651  *
2652  *  @param [in] link: pointer to the dc link
2653  *  @param [in] enable: boolean specifying whether to enable hbd
2654  *****************************************************************************
2655  */
2656 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
2657 {
2658         struct gpio *hpd;
2659
2660         if (enable) {
2661                 link->is_hpd_filter_disabled = false;
2662                 program_hpd_filter(link);
2663         } else {
2664                 link->is_hpd_filter_disabled = true;
2665                 /* Obtain HPD handle */
2666                 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
2667
2668                 if (!hpd)
2669                         return;
2670
2671                 /* Setup HPD filtering */
2672                 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
2673                         struct gpio_hpd_config config;
2674
2675                         config.delay_on_connect = 0;
2676                         config.delay_on_disconnect = 0;
2677
2678                         dal_irq_setup_hpd_filter(hpd, &config);
2679
2680                         dal_gpio_close(hpd);
2681                 } else {
2682                         ASSERT_CRITICAL(false);
2683                 }
2684                 /* Release HPD handle */
2685                 dal_gpio_destroy_irq(&hpd);
2686         }
2687 }
2688