drivers/gpu/drm/amd/display/dc/core/dc.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24
  25 #include "dm_services.h"
  26
  27 #include "dc.h"
  28
  29 #include "core_status.h"
  30 #include "core_types.h"
  31 #include "hw_sequencer.h"
  32 #include "dce/dce_hwseq.h"
  33
  34 #include "resource.h"
  35
  36 #include "clock_source.h"
  37 #include "dc_bios_types.h"
  38
  39 #include "bios_parser_interface.h"
  40 #include "include/irq_service_interface.h"
  41 #include "transform.h"
  42 #include "dmcu.h"
  43 #include "dpp.h"
  44 #include "timing_generator.h"
  45 #include "abm.h"
  46 #include "virtual/virtual_link_encoder.h"
  47
  48 #include "link_hwss.h"
  49 #include "link_encoder.h"
  50
  51 #include "dc_link_ddc.h"
  52 #include "dm_helpers.h"
  53 #include "mem_input.h"
  54 #include "hubp.h"
  55
  56 #include "dc_link_dp.h"
  57
  58 #include "dce/dce_i2c.h"
  59
  60 #define DC_LOGGER \
  61         dc->ctx->logger
  62
  63 const static char DC_BUILD_ID[] = "production-build";
  64
  65 /**
  66  * DOC: Overview
  67  *
  68  * DC is the OS-agnostic component of the amdgpu DC driver.
  69  *
  70  * DC maintains and validates a set of structs representing the state of the
  71  * driver and writes that state to AMD hardware
  72  *
  73  * Main DC HW structs:
  74  *
  75  * struct dc - The central struct.  One per driver.  Created on driver load,
  76  * destroyed on driver unload.
  77  *
  78  * struct dc_context - One per driver.
  79  * Used as a backpointer by most other structs in dc.
  80  *
  81  * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
  82  * plugpoints).  Created on driver load, destroyed on driver unload.
  83  *
  84  * struct dc_sink - One per display.  Created on boot or hotplug.
  85  * Destroyed on shutdown or hotunplug.  A dc_link can have a local sink
  86  * (the display directly attached).  It may also have one or more remote
  87  * sinks (in the Multi-Stream Transport case)
  88  *
  89  * struct resource_pool - One per driver.  Represents the hw blocks not in the
  90  * main pipeline.  Not directly accessible by dm.
  91  *
  92  * Main dc state structs:
  93  *
  94  * These structs can be created and destroyed as needed.  There is a full set of
  95  * these structs in dc->current_state representing the currently programmed state.
  96  *
  97  * struct dc_state - The global DC state to track global state information,
  98  * such as bandwidth values.
  99  *
 100  * struct dc_stream_state - Represents the hw configuration for the pipeline from
 101  * a framebuffer to a display.  Maps one-to-one with dc_sink.
 102  *
 103  * struct dc_plane_state - Represents a framebuffer.  Each stream has at least one,
 104  * and may have more in the Multi-Plane Overlay case.
 105  *
 106  * struct resource_context - Represents the programmable state of everything in
 107  * the resource_pool.  Not directly accessible by dm.
 108  *
 109  * struct pipe_ctx - A member of struct resource_context.  Represents the
 110  * internal hardware pipeline components.  Each dc_plane_state has either
 111  * one or two (in the pipe-split case).
 112  */
 113
 114 /*******************************************************************************
 115  * Private functions
 116  ******************************************************************************/
 117
 118 static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)
 119 {
 120         if (new > *original)
 121                 *original = new;
 122 }
 123
 124 static void destroy_links(struct dc *dc)
 125 {
 126         uint32_t i;
 127
 128         for (i = 0; i < dc->link_count; i++) {
 129                 if (NULL != dc->links[i])
 130                         link_destroy(&dc->links[i]);
 131         }
 132 }
 133
 134 static bool create_links(
 135                 struct dc *dc,
 136                 uint32_t num_virtual_links)
 137 {
 138         int i;
 139         int connectors_num;
 140         struct dc_bios *bios = dc->ctx->dc_bios;
 141
 142         dc->link_count = 0;
 143
 144         connectors_num = bios->funcs->get_connectors_number(bios);
 145
 146         if (connectors_num > ENUM_ID_COUNT) {
 147                 dm_error(
 148                         "DC: Number of connectors %d exceeds maximum of %d!\n",
 149                         connectors_num,
 150                         ENUM_ID_COUNT);
 151                 return false;
 152         }
 153
 154         dm_output_to_console(
 155                 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
 156                 __func__,
 157                 connectors_num,
 158                 num_virtual_links);
 159
 160         for (i = 0; i < connectors_num; i++) {
 161                 struct link_init_data link_init_params = {0};
 162                 struct dc_link *link;
 163
 164                 link_init_params.ctx = dc->ctx;
 165                 /* next BIOS object table connector */
 166                 link_init_params.connector_index = i;
 167                 link_init_params.link_index = dc->link_count;
 168                 link_init_params.dc = dc;
 169                 link = link_create(&link_init_params);
 170
 171                 if (link) {
 172                         dc->links[dc->link_count] = link;
 173                         link->dc = dc;
 174                         ++dc->link_count;
 175                 }
 176         }
 177
 178         for (i = 0; i < num_virtual_links; i++) {
 179                 struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL);
 180                 struct encoder_init_data enc_init = {0};
 181
 182                 if (link == NULL) {
 183                         BREAK_TO_DEBUGGER();
 184                         goto failed_alloc;
 185                 }
 186
 187                 link->link_index = dc->link_count;
 188                 dc->links[dc->link_count] = link;
 189                 dc->link_count++;
 190
 191                 link->ctx = dc->ctx;
 192                 link->dc = dc;
 193                 link->connector_signal = SIGNAL_TYPE_VIRTUAL;
 194                 link->link_id.type = OBJECT_TYPE_CONNECTOR;
 195                 link->link_id.id = CONNECTOR_ID_VIRTUAL;
 196                 link->link_id.enum_id = ENUM_ID_1;
 197                 link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL);
 198
 199                 if (!link->link_enc) {
 200                         BREAK_TO_DEBUGGER();
 201                         goto failed_alloc;
 202                 }
 203
 204                 link->link_status.dpcd_caps = &link->dpcd_caps;
 205
 206                 enc_init.ctx = dc->ctx;
 207                 enc_init.channel = CHANNEL_ID_UNKNOWN;
 208                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
 209                 enc_init.transmitter = TRANSMITTER_UNKNOWN;
 210                 enc_init.connector = link->link_id;
 211                 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
 212                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
 213                 enc_init.encoder.enum_id = ENUM_ID_1;
 214                 virtual_link_encoder_construct(link->link_enc, &enc_init);
 215         }
 216
 217         return true;
 218
 219 failed_alloc:
 220         return false;
 221 }
 222
 223 static struct dc_perf_trace *dc_perf_trace_create(void)
 224 {
 225         return kzalloc(sizeof(struct dc_perf_trace), GFP_KERNEL);
 226 }
 227
 228 static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace)
 229 {
 230         kfree(*perf_trace);
 231         *perf_trace = NULL;
 232 }
 233
 234 /**
 235  *****************************************************************************
 236  *  Function: dc_stream_adjust_vmin_vmax
 237  *
 238  *  @brief
 239  *     Looks up the pipe context of dc_stream_state and updates the
 240  *     vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
 241  *     Rate, which is a power-saving feature that targets reducing panel
 242  *     refresh rate while the screen is static
 243  *
 244  *  @param [in] dc: dc reference
 245  *  @param [in] stream: Initial dc stream state
 246  *  @param [in] adjust: Updated parameters for vertical_total_min and
 247  *  vertical_total_max
 248  *****************************************************************************
 249  */
 250 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 251                 struct dc_stream_state *stream,
 252                 struct dc_crtc_timing_adjust *adjust)
 253 {
 254         int i = 0;
 255         bool ret = false;
 256
 257         for (i = 0; i < MAX_PIPES; i++) {
 258                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 259
 260                 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
 261                         pipe->stream->adjust = *adjust;
 262                         dc->hwss.set_drr(&pipe,
 263                                         1,
 264                                         adjust->v_total_min,
 265                                         adjust->v_total_max);
 266
 267                         ret = true;
 268                 }
 269         }
 270         return ret;
 271 }
 272
 273 bool dc_stream_get_crtc_position(struct dc *dc,
 274                 struct dc_stream_state **streams, int num_streams,
 275                 unsigned int *v_pos, unsigned int *nom_v_pos)
 276 {
 277         /* TODO: Support multiple streams */
 278         const struct dc_stream_state *stream = streams[0];
 279         int i = 0;
 280         bool ret = false;
 281         struct crtc_position position;
 282
 283         for (i = 0; i < MAX_PIPES; i++) {
 284                 struct pipe_ctx *pipe =
 285                                 &dc->current_state->res_ctx.pipe_ctx[i];
 286
 287                 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
 288                         dc->hwss.get_position(&pipe, 1, &position);
 289
 290                         *v_pos = position.vertical_count;
 291                         *nom_v_pos = position.nominal_vcount;
 292                         ret = true;
 293                 }
 294         }
 295         return ret;
 296 }
 297
 298 /**
 299  * dc_stream_configure_crc() - Configure CRC capture for the given stream.
 300  * @dc: DC Object
 301  * @stream: The stream to configure CRC on.
 302  * @enable: Enable CRC if true, disable otherwise.
 303  * @continuous: Capture CRC on every frame if true. Otherwise, only capture
 304  *              once.
 305  *
 306  * By default, only CRC0 is configured, and the entire frame is used to
 307  * calculate the crc.
 308  */
 309 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
 310                              bool enable, bool continuous)
 311 {
 312         int i;
 313         struct pipe_ctx *pipe;
 314         struct crc_params param;
 315         struct timing_generator *tg;
 316
 317         for (i = 0; i < MAX_PIPES; i++) {
 318                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 319                 if (pipe->stream == stream)
 320                         break;
 321         }
 322         /* Stream not found */
 323         if (i == MAX_PIPES)
 324                 return false;
 325
 326         /* Always capture the full frame */
 327         param.windowa_x_start = 0;
 328         param.windowa_y_start = 0;
 329         param.windowa_x_end = pipe->stream->timing.h_addressable;
 330         param.windowa_y_end = pipe->stream->timing.v_addressable;
 331         param.windowb_x_start = 0;
 332         param.windowb_y_start = 0;
 333         param.windowb_x_end = pipe->stream->timing.h_addressable;
 334         param.windowb_y_end = pipe->stream->timing.v_addressable;
 335
 336         /* Default to the union of both windows */
 337         param.selection = UNION_WINDOW_A_B;
 338         param.continuous_mode = continuous;
 339         param.enable = enable;
 340
 341         tg = pipe->stream_res.tg;
 342
 343         /* Only call if supported */
 344         if (tg->funcs->configure_crc)
 345                 return tg->funcs->configure_crc(tg, &param);
 346         DC_LOG_WARNING("CRC capture not supported.");
 347         return false;
 348 }
 349
 350 /**
 351  * dc_stream_get_crc() - Get CRC values for the given stream.
 352  * @dc: DC object
 353  * @stream: The DC stream state of the stream to get CRCs from.
 354  * @r_cr, g_y, b_cb: CRC values for the three channels are stored here.
 355  *
 356  * dc_stream_configure_crc needs to be called beforehand to enable CRCs.
 357  * Return false if stream is not found, or if CRCs are not enabled.
 358  */
 359 bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
 360                        uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
 361 {
 362         int i;
 363         struct pipe_ctx *pipe;
 364         struct timing_generator *tg;
 365
 366         for (i = 0; i < MAX_PIPES; i++) {
 367                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 368                 if (pipe->stream == stream)
 369                         break;
 370         }
 371         /* Stream not found */
 372         if (i == MAX_PIPES)
 373                 return false;
 374
 375         tg = pipe->stream_res.tg;
 376
 377         if (tg->funcs->get_crc)
 378                 return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);
 379         DC_LOG_WARNING("CRC capture not supported.");
 380         return false;
 381 }
 382
 383 void dc_stream_set_dither_option(struct dc_stream_state *stream,
 384                 enum dc_dither_option option)
 385 {
 386         struct bit_depth_reduction_params params;
 387         struct dc_link *link = stream->link;
 388         struct pipe_ctx *pipes = NULL;
 389         int i;
 390
 391         for (i = 0; i < MAX_PIPES; i++) {
 392                 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
 393                                 stream) {
 394                         pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
 395                         break;
 396                 }
 397         }
 398
 399         if (!pipes)
 400                 return;
 401         if (option > DITHER_OPTION_MAX)
 402                 return;
 403
 404         stream->dither_option = option;
 405
 406         memset(&params, 0, sizeof(params));
 407         resource_build_bit_depth_reduction_params(stream, &params);
 408         stream->bit_depth_params = params;
 409
 410         if (pipes->plane_res.xfm &&
 411             pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
 412                 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
 413                         pipes->plane_res.xfm,
 414                         pipes->plane_res.scl_data.lb_params.depth,
 415                         &stream->bit_depth_params);
 416         }
 417
 418         pipes->stream_res.opp->funcs->
 419                 opp_program_bit_depth_reduction(pipes->stream_res.opp, &params);
 420 }
 421
 422 bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
 423 {
 424         int i = 0;
 425         bool ret = false;
 426         struct pipe_ctx *pipes;
 427
 428         for (i = 0; i < MAX_PIPES; i++) {
 429                 if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
 430                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 431                         dc->hwss.program_gamut_remap(pipes);
 432                         ret = true;
 433                 }
 434         }
 435
 436         return ret;
 437 }
 438
 439 bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
 440 {
 441         int i = 0;
 442         bool ret = false;
 443         struct pipe_ctx *pipes;
 444
 445         for (i = 0; i < MAX_PIPES; i++) {
 446                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 447                                 == stream) {
 448
 449                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 450                         dc->hwss.program_output_csc(dc,
 451                                         pipes,
 452                                         stream->output_color_space,
 453                                         stream->csc_color_matrix.matrix,
 454                                         pipes->plane_res.hubp ? pipes->plane_res.hubp->opp_id : 0);
 455                         ret = true;
 456                 }
 457         }
 458
 459         return ret;
 460 }
 461
 462 void dc_stream_set_static_screen_events(struct dc *dc,
 463                 struct dc_stream_state **streams,
 464                 int num_streams,
 465                 const struct dc_static_screen_events *events)
 466 {
 467         int i = 0;
 468         int j = 0;
 469         struct pipe_ctx *pipes_affected[MAX_PIPES];
 470         int num_pipes_affected = 0;
 471
 472         for (i = 0; i < num_streams; i++) {
 473                 struct dc_stream_state *stream = streams[i];
 474
 475                 for (j = 0; j < MAX_PIPES; j++) {
 476                         if (dc->current_state->res_ctx.pipe_ctx[j].stream
 477                                         == stream) {
 478                                 pipes_affected[num_pipes_affected++] =
 479                                                 &dc->current_state->res_ctx.pipe_ctx[j];
 480                         }
 481                 }
 482         }
 483
 484         dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events);
 485 }
 486
 487 void dc_link_set_drive_settings(struct dc *dc,
 488                                 struct link_training_settings *lt_settings,
 489                                 const struct dc_link *link)
 490 {
 491
 492         int i;
 493
 494         for (i = 0; i < dc->link_count; i++) {
 495                 if (dc->links[i] == link)
 496                         break;
 497         }
 498
 499         if (i >= dc->link_count)
 500                 ASSERT_CRITICAL(false);
 501
 502         dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
 503 }
 504
 505 void dc_link_perform_link_training(struct dc *dc,
 506                                    struct dc_link_settings *link_setting,
 507                                    bool skip_video_pattern)
 508 {
 509         int i;
 510
 511         for (i = 0; i < dc->link_count; i++)
 512                 dc_link_dp_perform_link_training(
 513                         dc->links[i],
 514                         link_setting,
 515                         skip_video_pattern);
 516 }
 517
 518 void dc_link_set_preferred_link_settings(struct dc *dc,
 519                                          struct dc_link_settings *link_setting,
 520                                          struct dc_link *link)
 521 {
 522         int i;
 523         struct pipe_ctx *pipe;
 524         struct dc_stream_state *link_stream;
 525         struct dc_link_settings store_settings = *link_setting;
 526
 527         for (i = 0; i < MAX_PIPES; i++) {
 528                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 529                 if (pipe->stream && pipe->stream->link) {
 530                         if (pipe->stream->link == link)
 531                                 break;
 532                 }
 533         }
 534
 535         /* Stream not found */
 536         if (i == MAX_PIPES)
 537                 return;
 538
 539         link_stream = link->dc->current_state->res_ctx.pipe_ctx[i].stream;
 540
 541         link->preferred_link_setting = store_settings;
 542         if (link_stream)
 543                 decide_link_settings(link_stream, &store_settings);
 544
 545         if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
 546                 (store_settings.link_rate != LINK_RATE_UNKNOWN))
 547                 dp_retrain_link_dp_test(link, &store_settings, false);
 548 }
 549
 550 void dc_link_enable_hpd(const struct dc_link *link)
 551 {
 552         dc_link_dp_enable_hpd(link);
 553 }
 554
 555 void dc_link_disable_hpd(const struct dc_link *link)
 556 {
 557         dc_link_dp_disable_hpd(link);
 558 }
 559
 560
 561 void dc_link_set_test_pattern(struct dc_link *link,
 562                               enum dp_test_pattern test_pattern,
 563                               const struct link_training_settings *p_link_settings,
 564                               const unsigned char *p_custom_pattern,
 565                               unsigned int cust_pattern_size)
 566 {
 567         if (link != NULL)
 568                 dc_link_dp_set_test_pattern(
 569                         link,
 570                         test_pattern,
 571                         p_link_settings,
 572                         p_custom_pattern,
 573                         cust_pattern_size);
 574 }
 575
 576 static void destruct(struct dc *dc)
 577 {
 578         dc_release_state(dc->current_state);
 579         dc->current_state = NULL;
 580
 581         destroy_links(dc);
 582
 583         dc_destroy_resource_pool(dc);
 584
 585         if (dc->ctx->gpio_service)
 586                 dal_gpio_service_destroy(&dc->ctx->gpio_service);
 587
 588         if (dc->ctx->created_bios)
 589                 dal_bios_parser_destroy(&dc->ctx->dc_bios);
 590
 591         dc_perf_trace_destroy(&dc->ctx->perf_trace);
 592
 593         kfree(dc->ctx);
 594         dc->ctx = NULL;
 595
 596         kfree(dc->bw_vbios);
 597         dc->bw_vbios = NULL;
 598
 599         kfree(dc->bw_dceip);
 600         dc->bw_dceip = NULL;
 601
 602 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 603         kfree(dc->dcn_soc);
 604         dc->dcn_soc = NULL;
 605
 606         kfree(dc->dcn_ip);
 607         dc->dcn_ip = NULL;
 608
 609 #endif
 610 }
 611
 612 static bool construct(struct dc *dc,
 613                 const struct dc_init_data *init_params)
 614 {
 615         struct dc_context *dc_ctx;
 616         struct bw_calcs_dceip *dc_dceip;
 617         struct bw_calcs_vbios *dc_vbios;
 618 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 619         struct dcn_soc_bounding_box *dcn_soc;
 620         struct dcn_ip_params *dcn_ip;
 621 #endif
 622
 623         enum dce_version dc_version = DCE_VERSION_UNKNOWN;
 624         dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
 625         if (!dc_dceip) {
 626                 dm_error("%s: failed to create dceip\n", __func__);
 627                 goto fail;
 628         }
 629
 630         dc->bw_dceip = dc_dceip;
 631
 632         dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL);
 633         if (!dc_vbios) {
 634                 dm_error("%s: failed to create vbios\n", __func__);
 635                 goto fail;
 636         }
 637
 638         dc->bw_vbios = dc_vbios;
 639 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 640         dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
 641         if (!dcn_soc) {
 642                 dm_error("%s: failed to create dcn_soc\n", __func__);
 643                 goto fail;
 644         }
 645
 646         dc->dcn_soc = dcn_soc;
 647
 648         dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL);
 649         if (!dcn_ip) {
 650                 dm_error("%s: failed to create dcn_ip\n", __func__);
 651                 goto fail;
 652         }
 653
 654         dc->dcn_ip = dcn_ip;
 655 #endif
 656
 657         dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
 658         if (!dc_ctx) {
 659                 dm_error("%s: failed to create ctx\n", __func__);
 660                 goto fail;
 661         }
 662
 663         dc_ctx->cgs_device = init_params->cgs_device;
 664         dc_ctx->driver_context = init_params->driver;
 665         dc_ctx->dc = dc;
 666         dc_ctx->asic_id = init_params->asic_id;
 667         dc_ctx->dc_sink_id_count = 0;
 668         dc_ctx->dc_stream_id_count = 0;
 669         dc->ctx = dc_ctx;
 670
 671         dc->current_state = dc_create_state();
 672
 673         if (!dc->current_state) {
 674                 dm_error("%s: failed to create validate ctx\n", __func__);
 675                 goto fail;
 676         }
 677
 678         /* Create logger */
 679
 680         dc_ctx->dce_environment = init_params->dce_environment;
 681
 682         dc_version = resource_parse_asic_id(init_params->asic_id);
 683         dc_ctx->dce_version = dc_version;
 684
 685         /* Resource should construct all asic specific resources.
 686          * This should be the only place where we need to parse the asic id
 687          */
 688         if (init_params->vbios_override)
 689                 dc_ctx->dc_bios = init_params->vbios_override;
 690         else {
 691                 /* Create BIOS parser */
 692                 struct bp_init_data bp_init_data;
 693
 694                 bp_init_data.ctx = dc_ctx;
 695                 bp_init_data.bios = init_params->asic_id.atombios_base_address;
 696
 697                 dc_ctx->dc_bios = dal_bios_parser_create(
 698                                 &bp_init_data, dc_version);
 699
 700                 if (!dc_ctx->dc_bios) {
 701                         ASSERT_CRITICAL(false);
 702                         goto fail;
 703                 }
 704
 705                 dc_ctx->created_bios = true;
 706                 }
 707
 708         dc_ctx->perf_trace = dc_perf_trace_create();
 709         if (!dc_ctx->perf_trace) {
 710                 ASSERT_CRITICAL(false);
 711                 goto fail;
 712         }
 713
 714         /* Create GPIO service */
 715         dc_ctx->gpio_service = dal_gpio_service_create(
 716                         dc_version,
 717                         dc_ctx->dce_environment,
 718                         dc_ctx);
 719
 720         if (!dc_ctx->gpio_service) {
 721                 ASSERT_CRITICAL(false);
 722                 goto fail;
 723         }
 724
 725         dc->res_pool = dc_create_resource_pool(
 726                         dc,
 727                         init_params->num_virtual_links,
 728                         dc_version,
 729                         init_params->asic_id);
 730         if (!dc->res_pool)
 731                 goto fail;
 732
 733         dc_resource_state_construct(dc, dc->current_state);
 734
 735         if (!create_links(dc, init_params->num_virtual_links))
 736                 goto fail;
 737
 738         return true;
 739
 740 fail:
 741
 742         destruct(dc);
 743         return false;
 744 }
 745
 746 static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
 747 {
 748         int i, j;
 749         struct dc_state *dangling_context = dc_create_state();
 750         struct dc_state *current_ctx;
 751
 752         if (dangling_context == NULL)
 753                 return;
 754
 755         dc_resource_state_copy_construct(dc->current_state, dangling_context);
 756
 757         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 758                 struct dc_stream_state *old_stream =
 759                                 dc->current_state->res_ctx.pipe_ctx[i].stream;
 760                 bool should_disable = true;
 761
 762                 for (j = 0; j < context->stream_count; j++) {
 763                         if (old_stream == context->streams[j]) {
 764                                 should_disable = false;
 765                                 break;
 766                         }
 767                 }
 768                 if (should_disable && old_stream) {
 769                         dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
 770                         dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
 771                 }
 772         }
 773
 774         current_ctx = dc->current_state;
 775         dc->current_state = dangling_context;
 776         dc_release_state(current_ctx);
 777 }
 778
 779 /*******************************************************************************
 780  * Public functions
 781  ******************************************************************************/
 782
 783 struct dc *dc_create(const struct dc_init_data *init_params)
 784 {
 785         struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
 786         unsigned int full_pipe_count;
 787
 788         if (NULL == dc)
 789                 goto alloc_fail;
 790
 791         if (false == construct(dc, init_params))
 792                 goto construct_fail;
 793
 794         /*TODO: separate HW and SW initialization*/
 795         dc->hwss.init_hw(dc);
 796
 797         full_pipe_count = dc->res_pool->pipe_count;
 798         if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
 799                 full_pipe_count--;
 800         dc->caps.max_streams = min(
 801                         full_pipe_count,
 802                         dc->res_pool->stream_enc_count);
 803
 804         dc->caps.max_links = dc->link_count;
 805         dc->caps.max_audios = dc->res_pool->audio_count;
 806         dc->caps.linear_pitch_alignment = 64;
 807
 808         /* Populate versioning information */
 809         dc->versions.dc_ver = DC_VER;
 810
 811         if (dc->res_pool->dmcu != NULL)
 812                 dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
 813
 814         dc->config = init_params->flags;
 815
 816         dc->build_id = DC_BUILD_ID;
 817
 818         DC_LOG_DC("Display Core initialized\n");
 819
 820
 821
 822         return dc;
 823
 824 construct_fail:
 825         kfree(dc);
 826
 827 alloc_fail:
 828         return NULL;
 829 }
 830
 831 void dc_init_callbacks(struct dc *dc,
 832                 const struct dc_callback_init *init_params)
 833 {
 834 }
 835
 836 void dc_destroy(struct dc **dc)
 837 {
 838         destruct(*dc);
 839         kfree(*dc);
 840         *dc = NULL;
 841 }
 842
 843 static void enable_timing_multisync(
 844                 struct dc *dc,
 845                 struct dc_state *ctx)
 846 {
 847         int i = 0, multisync_count = 0;
 848         int pipe_count = dc->res_pool->pipe_count;
 849         struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
 850
 851         for (i = 0; i < pipe_count; i++) {
 852                 if (!ctx->res_ctx.pipe_ctx[i].stream ||
 853                                 !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
 854                         continue;
 855                 if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)
 856                         continue;
 857                 multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
 858                 multisync_count++;
 859         }
 860
 861         if (multisync_count > 0) {
 862                 dc->hwss.enable_per_frame_crtc_position_reset(
 863                         dc, multisync_count, multisync_pipes);
 864         }
 865 }
 866
 867 static void program_timing_sync(
 868                 struct dc *dc,
 869                 struct dc_state *ctx)
 870 {
 871         int i, j, k;
 872         int group_index = 0;
 873         int num_group = 0;
 874         int pipe_count = dc->res_pool->pipe_count;
 875         struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
 876
 877         for (i = 0; i < pipe_count; i++) {
 878                 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
 879                         continue;
 880
 881                 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
 882         }
 883
 884         for (i = 0; i < pipe_count; i++) {
 885                 int group_size = 1;
 886                 struct pipe_ctx *pipe_set[MAX_PIPES];
 887
 888                 if (!unsynced_pipes[i])
 889                         continue;
 890
 891                 pipe_set[0] = unsynced_pipes[i];
 892                 unsynced_pipes[i] = NULL;
 893
 894                 /* Add tg to the set, search rest of the tg's for ones with
 895                  * same timing, add all tgs with same timing to the group
 896                  */
 897                 for (j = i + 1; j < pipe_count; j++) {
 898                         if (!unsynced_pipes[j])
 899                                 continue;
 900
 901                         if (resource_are_streams_timing_synchronizable(
 902                                         unsynced_pipes[j]->stream,
 903                                         pipe_set[0]->stream)) {
 904                                 pipe_set[group_size] = unsynced_pipes[j];
 905                                 unsynced_pipes[j] = NULL;
 906                                 group_size++;
 907                         }
 908                 }
 909
 910                 /* set first pipe with plane as master */
 911                 for (j = 0; j < group_size; j++) {
 912                         struct pipe_ctx *temp;
 913
 914                         if (pipe_set[j]->plane_state) {
 915                                 if (j == 0)
 916                                         break;
 917
 918                                 temp = pipe_set[0];
 919                                 pipe_set[0] = pipe_set[j];
 920                                 pipe_set[j] = temp;
 921                                 break;
 922                         }
 923                 }
 924
 925
 926                 for (k = 0; k < group_size; k++) {
 927                         struct dc_stream_status *status = dc_stream_get_status_from_state(ctx, pipe_set[k]->stream);
 928
 929                         status->timing_sync_info.group_id = num_group;
 930                         status->timing_sync_info.group_size = group_size;
 931                         if (k == 0)
 932                                 status->timing_sync_info.master = true;
 933                         else
 934                                 status->timing_sync_info.master = false;
 935
 936                 }
 937                 /* remove any other pipes with plane as they have already been synced */
 938                 for (j = j + 1; j < group_size; j++) {
 939                         if (pipe_set[j]->plane_state) {
 940                                 group_size--;
 941                                 pipe_set[j] = pipe_set[group_size];
 942                                 j--;
 943                         }
 944                 }
 945
 946                 if (group_size > 1) {
 947                         dc->hwss.enable_timing_synchronization(
 948                                 dc, group_index, group_size, pipe_set);
 949                         group_index++;
 950                 }
 951                 num_group++;
 952         }
 953 }
 954
 955 static bool context_changed(
 956                 struct dc *dc,
 957                 struct dc_state *context)
 958 {
 959         uint8_t i;
 960
 961         if (context->stream_count != dc->current_state->stream_count)
 962                 return true;
 963
 964         for (i = 0; i < dc->current_state->stream_count; i++) {
 965                 if (dc->current_state->streams[i] != context->streams[i])
 966                         return true;
 967         }
 968
 969         return false;
 970 }
 971
 972 bool dc_validate_seamless_boot_timing(struct dc *dc,
 973                                 const struct dc_sink *sink,
 974                                 struct dc_crtc_timing *crtc_timing)
 975 {
 976         struct timing_generator *tg;
 977         struct dc_link *link = sink->link;
 978         unsigned int inst;
 979
 980         /* Check for enabled DIG to identify enabled display */
 981         if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
 982                 return false;
 983
 984         /* Check for which front end is used by this encoder.
 985          * Note the inst is 1 indexed, where 0 is undefined.
 986          * Note that DIG_FE can source from different OTG but our
 987          * current implementation always map 1-to-1, so this code makes
 988          * the same assumption and doesn't check OTG source.
 989          */
 990         inst = link->link_enc->funcs->get_dig_frontend(link->link_enc) - 1;
 991
 992         /* Instance should be within the range of the pool */
 993         if (inst >= dc->res_pool->pipe_count)
 994                 return false;
 995
 996         tg = dc->res_pool->timing_generators[inst];
 997
 998         if (!tg->funcs->is_matching_timing)
 999                 return false;
1000
1001         if (!tg->funcs->is_matching_timing(tg, crtc_timing))
1002                 return false;
1003
1004         if (dc_is_dp_signal(link->connector_signal)) {
1005                 unsigned int pix_clk_100hz;
1006
1007                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1008                         dc->res_pool->dp_clock_source,
1009                         inst, &pix_clk_100hz);
1010
1011                 if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
1012                         return false;
1013         }
1014
1015         return true;
1016 }
1017
1018 bool dc_enable_stereo(
1019         struct dc *dc,
1020         struct dc_state *context,
1021         struct dc_stream_state *streams[],
1022         uint8_t stream_count)
1023 {
1024         bool ret = true;
1025         int i, j;
1026         struct pipe_ctx *pipe;
1027
1028         for (i = 0; i < MAX_PIPES; i++) {
1029                 if (context != NULL)
1030                         pipe = &context->res_ctx.pipe_ctx[i];
1031                 else
1032                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1033                 for (j = 0 ; pipe && j < stream_count; j++)  {
1034                         if (streams[j] && streams[j] == pipe->stream &&
1035                                 dc->hwss.setup_stereo)
1036                                 dc->hwss.setup_stereo(pipe, dc);
1037                 }
1038         }
1039
1040         return ret;
1041 }
1042
1043 /*
1044  * Applies given context to HW and copy it into current context.
1045  * It's up to the user to release the src context afterwards.
1046  */
1047 static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
1048 {
1049         struct dc_bios *dcb = dc->ctx->dc_bios;
1050         enum dc_status result = DC_ERROR_UNEXPECTED;
1051         struct pipe_ctx *pipe;
1052         int i, k, l;
1053         struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
1054
1055         disable_dangling_plane(dc, context);
1056
1057         for (i = 0; i < context->stream_count; i++)
1058                 dc_streams[i] =  context->streams[i];
1059
1060         if (!dcb->funcs->is_accelerated_mode(dcb))
1061                 dc->hwss.enable_accelerated_mode(dc, context);
1062
1063         dc->hwss.prepare_bandwidth(dc, context);
1064
1065         /* re-program planes for existing stream, in case we need to
1066          * free up plane resource for later use
1067          */
1068         for (i = 0; i < context->stream_count; i++) {
1069                 if (context->streams[i]->mode_changed)
1070                         continue;
1071
1072                 dc->hwss.apply_ctx_for_surface(
1073                         dc, context->streams[i],
1074                         context->stream_status[i].plane_count,
1075                         context); /* use new pipe config in new context */
1076         }
1077
1078         /* Program hardware */
1079         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1080                 pipe = &context->res_ctx.pipe_ctx[i];
1081                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
1082         }
1083
1084         result = dc->hwss.apply_ctx_to_hw(dc, context);
1085
1086         if (result != DC_OK)
1087                 return result;
1088
1089         if (context->stream_count > 1) {
1090                 enable_timing_multisync(dc, context);
1091                 program_timing_sync(dc, context);
1092         }
1093
1094         /* Program all planes within new context*/
1095         for (i = 0; i < context->stream_count; i++) {
1096                 const struct dc_link *link = context->streams[i]->link;
1097                 struct dc_stream_status *status;
1098
1099                 if (context->streams[i]->apply_seamless_boot_optimization)
1100                         context->streams[i]->apply_seamless_boot_optimization = false;
1101
1102                 if (!context->streams[i]->mode_changed)
1103                         continue;
1104
1105                 dc->hwss.apply_ctx_for_surface(
1106                                 dc, context->streams[i],
1107                                 context->stream_status[i].plane_count,
1108                                 context);
1109
1110                 /*
1111                  * enable stereo
1112                  * TODO rework dc_enable_stereo call to work with validation sets?
1113                  */
1114                 for (k = 0; k < MAX_PIPES; k++) {
1115                         pipe = &context->res_ctx.pipe_ctx[k];
1116
1117                         for (l = 0 ; pipe && l < context->stream_count; l++)  {
1118                                 if (context->streams[l] &&
1119                                         context->streams[l] == pipe->stream &&
1120                                         dc->hwss.setup_stereo)
1121                                         dc->hwss.setup_stereo(pipe, dc);
1122                         }
1123                 }
1124
1125                 status = dc_stream_get_status_from_state(context, context->streams[i]);
1126                 context->streams[i]->out.otg_offset = status->primary_otg_inst;
1127
1128                 CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",
1129                                 context->streams[i]->timing.h_addressable,
1130                                 context->streams[i]->timing.v_addressable,
1131                                 context->streams[i]->timing.h_total,
1132                                 context->streams[i]->timing.v_total,
1133                                 context->streams[i]->timing.pix_clk_100hz / 10);
1134         }
1135
1136         dc_enable_stereo(dc, context, dc_streams, context->stream_count);
1137
1138         /* pplib is notified if disp_num changed */
1139         dc->hwss.optimize_bandwidth(dc, context);
1140
1141         for (i = 0; i < context->stream_count; i++)
1142                 context->streams[i]->mode_changed = false;
1143
1144         dc_release_state(dc->current_state);
1145
1146         dc->current_state = context;
1147
1148         dc_retain_state(dc->current_state);
1149
1150         return result;
1151 }
1152
1153 bool dc_commit_state(struct dc *dc, struct dc_state *context)
1154 {
1155         enum dc_status result = DC_ERROR_UNEXPECTED;
1156         int i;
1157
1158         if (false == context_changed(dc, context))
1159                 return DC_OK;
1160
1161         DC_LOG_DC("%s: %d streams\n",
1162                                 __func__, context->stream_count);
1163
1164         for (i = 0; i < context->stream_count; i++) {
1165                 struct dc_stream_state *stream = context->streams[i];
1166
1167                 dc_stream_log(dc, stream);
1168         }
1169
1170         result = dc_commit_state_no_check(dc, context);
1171
1172         return (result == DC_OK);
1173 }
1174
1175 bool dc_post_update_surfaces_to_stream(struct dc *dc)
1176 {
1177         int i;
1178         struct dc_state *context = dc->current_state;
1179
1180         if (dc->optimized_required == false)
1181                 return true;
1182
1183         post_surface_trace(dc);
1184
1185         for (i = 0; i < dc->res_pool->pipe_count; i++)
1186                 if (context->res_ctx.pipe_ctx[i].stream == NULL ||
1187                     context->res_ctx.pipe_ctx[i].plane_state == NULL) {
1188                         context->res_ctx.pipe_ctx[i].pipe_idx = i;
1189                         dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
1190                 }
1191
1192         dc->optimized_required = false;
1193
1194         dc->hwss.optimize_bandwidth(dc, context);
1195         return true;
1196 }
1197
1198 struct dc_state *dc_create_state(void)
1199 {
1200         struct dc_state *context = kzalloc(sizeof(struct dc_state),
1201                                            GFP_KERNEL);
1202
1203         if (!context)
1204                 return NULL;
1205
1206         kref_init(&context->refcount);
1207         return context;
1208 }
1209
1210 void dc_retain_state(struct dc_state *context)
1211 {
1212         kref_get(&context->refcount);
1213 }
1214
1215 static void dc_state_free(struct kref *kref)
1216 {
1217         struct dc_state *context = container_of(kref, struct dc_state, refcount);
1218         dc_resource_state_destruct(context);
1219         kfree(context);
1220 }
1221
1222 void dc_release_state(struct dc_state *context)
1223 {
1224         kref_put(&context->refcount, dc_state_free);
1225 }
1226
1227 static bool is_surface_in_context(
1228                 const struct dc_state *context,
1229                 const struct dc_plane_state *plane_state)
1230 {
1231         int j;
1232
1233         for (j = 0; j < MAX_PIPES; j++) {
1234                 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1235
1236                 if (plane_state == pipe_ctx->plane_state) {
1237                         return true;
1238                 }
1239         }
1240
1241         return false;
1242 }
1243
1244 static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
1245 {
1246         union surface_update_flags *update_flags = &u->surface->update_flags;
1247
1248         if (!u->plane_info)
1249                 return UPDATE_TYPE_FAST;
1250
1251         if (u->plane_info->color_space != u->surface->color_space)
1252                 update_flags->bits.color_space_change = 1;
1253
1254         if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror)
1255                 update_flags->bits.horizontal_mirror_change = 1;
1256
1257         if (u->plane_info->rotation != u->surface->rotation)
1258                 update_flags->bits.rotation_change = 1;
1259
1260         if (u->plane_info->format != u->surface->format)
1261                 update_flags->bits.pixel_format_change = 1;
1262
1263         if (u->plane_info->stereo_format != u->surface->stereo_format)
1264                 update_flags->bits.stereo_format_change = 1;
1265
1266         if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha)
1267                 update_flags->bits.per_pixel_alpha_change = 1;
1268
1269         if (u->plane_info->global_alpha_value != u->surface->global_alpha_value)
1270                 update_flags->bits.global_alpha_change = 1;
1271
1272         if (u->plane_info->dcc.enable != u->surface->dcc.enable
1273                         || u->plane_info->dcc.grph.independent_64b_blks != u->surface->dcc.grph.independent_64b_blks
1274                         || u->plane_info->dcc.grph.meta_pitch != u->surface->dcc.grph.meta_pitch)
1275                 update_flags->bits.dcc_change = 1;
1276
1277         if (resource_pixel_format_to_bpp(u->plane_info->format) !=
1278                         resource_pixel_format_to_bpp(u->surface->format))
1279                 /* different bytes per element will require full bandwidth
1280                  * and DML calculation
1281                  */
1282                 update_flags->bits.bpp_change = 1;
1283
1284         if (u->plane_info->plane_size.grph.surface_pitch != u->surface->plane_size.grph.surface_pitch
1285                         || u->plane_info->plane_size.video.luma_pitch != u->surface->plane_size.video.luma_pitch
1286                         || u->plane_info->plane_size.video.chroma_pitch != u->surface->plane_size.video.chroma_pitch)
1287                 update_flags->bits.plane_size_change = 1;
1288
1289
1290         if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
1291                         sizeof(union dc_tiling_info)) != 0) {
1292                 update_flags->bits.swizzle_change = 1;
1293                 /* todo: below are HW dependent, we should add a hook to
1294                  * DCE/N resource and validated there.
1295                  */
1296                 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR)
1297                         /* swizzled mode requires RQ to be setup properly,
1298                          * thus need to run DML to calculate RQ settings
1299                          */
1300                         update_flags->bits.bandwidth_change = 1;
1301         }
1302
1303         if (update_flags->bits.rotation_change
1304                         || update_flags->bits.stereo_format_change
1305                         || update_flags->bits.pixel_format_change
1306                         || update_flags->bits.bpp_change
1307                         || update_flags->bits.bandwidth_change
1308                         || update_flags->bits.output_tf_change)
1309                 return UPDATE_TYPE_FULL;
1310
1311         return update_flags->raw ? UPDATE_TYPE_MED : UPDATE_TYPE_FAST;
1312 }
1313
1314 static enum surface_update_type get_scaling_info_update_type(
1315                 const struct dc_surface_update *u)
1316 {
1317         union surface_update_flags *update_flags = &u->surface->update_flags;
1318
1319         if (!u->scaling_info)
1320                 return UPDATE_TYPE_FAST;
1321
1322         if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
1323                         || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
1324                         || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
1325                         || u->scaling_info->dst_rect.height != u->surface->dst_rect.height) {
1326                 update_flags->bits.scaling_change = 1;
1327
1328                 if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
1329                         || u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
1330                                 && (u->scaling_info->dst_rect.width < u->surface->src_rect.width
1331                                         || u->scaling_info->dst_rect.height < u->surface->src_rect.height))
1332                         /* Making dst rect smaller requires a bandwidth change */
1333                         update_flags->bits.bandwidth_change = 1;
1334         }
1335
1336         if (u->scaling_info->src_rect.width != u->surface->src_rect.width
1337                 || u->scaling_info->src_rect.height != u->surface->src_rect.height) {
1338
1339                 update_flags->bits.scaling_change = 1;
1340                 if (u->scaling_info->src_rect.width > u->surface->src_rect.width
1341                                 && u->scaling_info->src_rect.height > u->surface->src_rect.height)
1342                         /* Making src rect bigger requires a bandwidth change */
1343                         update_flags->bits.clock_change = 1;
1344         }
1345
1346         if (u->scaling_info->src_rect.x != u->surface->src_rect.x
1347                         || u->scaling_info->src_rect.y != u->surface->src_rect.y
1348                         || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
1349                         || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
1350                         || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
1351                         || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
1352                 update_flags->bits.position_change = 1;
1353
1354         if (update_flags->bits.clock_change
1355                         || update_flags->bits.bandwidth_change)
1356                 return UPDATE_TYPE_FULL;
1357
1358         if (update_flags->bits.scaling_change
1359                         || update_flags->bits.position_change)
1360                 return UPDATE_TYPE_MED;
1361
1362         return UPDATE_TYPE_FAST;
1363 }
1364
1365 static enum surface_update_type det_surface_update(const struct dc *dc,
1366                 const struct dc_surface_update *u)
1367 {
1368         const struct dc_state *context = dc->current_state;
1369         enum surface_update_type type;
1370         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1371         union surface_update_flags *update_flags = &u->surface->update_flags;
1372
1373         update_flags->raw = 0; // Reset all flags
1374
1375         if (!is_surface_in_context(context, u->surface)) {
1376                 update_flags->bits.new_plane = 1;
1377                 return UPDATE_TYPE_FULL;
1378         }
1379
1380         if (u->surface->force_full_update) {
1381                 update_flags->bits.full_update = 1;
1382                 return UPDATE_TYPE_FULL;
1383         }
1384
1385         type = get_plane_info_update_type(u);
1386         elevate_update_type(&overall_type, type);
1387
1388         type = get_scaling_info_update_type(u);
1389         elevate_update_type(&overall_type, type);
1390
1391         if (u->in_transfer_func)
1392                 update_flags->bits.in_transfer_func_change = 1;
1393
1394         if (u->input_csc_color_matrix)
1395                 update_flags->bits.input_csc_change = 1;
1396
1397         if (u->coeff_reduction_factor)
1398                 update_flags->bits.coeff_reduction_change = 1;
1399
1400         if (u->gamma) {
1401                 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN;
1402
1403                 if (u->plane_info)
1404                         format = u->plane_info->format;
1405                 else if (u->surface)
1406                         format = u->surface->format;
1407
1408                 if (dce_use_lut(format))
1409                         update_flags->bits.gamma_change = 1;
1410         }
1411
1412         if (update_flags->bits.in_transfer_func_change) {
1413                 type = UPDATE_TYPE_MED;
1414                 elevate_update_type(&overall_type, type);
1415         }
1416
1417         if (update_flags->bits.input_csc_change
1418                         || update_flags->bits.coeff_reduction_change
1419                         || update_flags->bits.gamma_change) {
1420                 type = UPDATE_TYPE_FULL;
1421                 elevate_update_type(&overall_type, type);
1422         }
1423
1424         return overall_type;
1425 }
1426
1427 static enum surface_update_type check_update_surfaces_for_stream(
1428                 struct dc *dc,
1429                 struct dc_surface_update *updates,
1430                 int surface_count,
1431                 struct dc_stream_update *stream_update,
1432                 const struct dc_stream_status *stream_status)
1433 {
1434         int i;
1435         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1436
1437         if (stream_status == NULL || stream_status->plane_count != surface_count)
1438                 return UPDATE_TYPE_FULL;
1439
1440         /* some stream updates require passive update */
1441         if (stream_update) {
1442                 if ((stream_update->src.height != 0) &&
1443                                 (stream_update->src.width != 0))
1444                         return UPDATE_TYPE_FULL;
1445
1446                 if ((stream_update->dst.height != 0) &&
1447                                 (stream_update->dst.width != 0))
1448                         return UPDATE_TYPE_FULL;
1449
1450                 if (stream_update->out_transfer_func)
1451                         return UPDATE_TYPE_FULL;
1452
1453                 if (stream_update->abm_level)
1454                         return UPDATE_TYPE_FULL;
1455
1456                 if (stream_update->dpms_off)
1457                         return UPDATE_TYPE_FULL;
1458         }
1459
1460         for (i = 0 ; i < surface_count; i++) {
1461                 enum surface_update_type type =
1462                                 det_surface_update(dc, &updates[i]);
1463
1464                 if (type == UPDATE_TYPE_FULL)
1465                         return type;
1466
1467                 elevate_update_type(&overall_type, type);
1468         }
1469
1470         return overall_type;
1471 }
1472
1473 /**
1474  * dc_check_update_surfaces_for_stream() - Determine update type (fast, med, or full)
1475  *
1476  * See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types
1477  */
1478 enum surface_update_type dc_check_update_surfaces_for_stream(
1479                 struct dc *dc,
1480                 struct dc_surface_update *updates,
1481                 int surface_count,
1482                 struct dc_stream_update *stream_update,
1483                 const struct dc_stream_status *stream_status)
1484 {
1485         int i;
1486         enum surface_update_type type;
1487
1488         for (i = 0; i < surface_count; i++)
1489                 updates[i].surface->update_flags.raw = 0;
1490
1491         type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
1492         if (type == UPDATE_TYPE_FULL)
1493                 for (i = 0; i < surface_count; i++)
1494                         updates[i].surface->update_flags.raw = 0xFFFFFFFF;
1495
1496         return type;
1497 }
1498
1499 static struct dc_stream_status *stream_get_status(
1500         struct dc_state *ctx,
1501         struct dc_stream_state *stream)
1502 {
1503         uint8_t i;
1504
1505         for (i = 0; i < ctx->stream_count; i++) {
1506                 if (stream == ctx->streams[i]) {
1507                         return &ctx->stream_status[i];
1508                 }
1509         }
1510
1511         return NULL;
1512 }
1513
1514 static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
1515
1516 static void copy_surface_update_to_plane(
1517                 struct dc_plane_state *surface,
1518                 struct dc_surface_update *srf_update)
1519 {
1520         if (srf_update->flip_addr) {
1521                 surface->address = srf_update->flip_addr->address;
1522                 surface->flip_immediate =
1523                         srf_update->flip_addr->flip_immediate;
1524                 surface->time.time_elapsed_in_us[surface->time.index] =
1525                         srf_update->flip_addr->flip_timestamp_in_us -
1526                                 surface->time.prev_update_time_in_us;
1527                 surface->time.prev_update_time_in_us =
1528                         srf_update->flip_addr->flip_timestamp_in_us;
1529                 surface->time.index++;
1530                 if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
1531                         surface->time.index = 0;
1532         }
1533
1534         if (srf_update->scaling_info) {
1535                 surface->scaling_quality =
1536                                 srf_update->scaling_info->scaling_quality;
1537                 surface->dst_rect =
1538                                 srf_update->scaling_info->dst_rect;
1539                 surface->src_rect =
1540                                 srf_update->scaling_info->src_rect;
1541                 surface->clip_rect =
1542                                 srf_update->scaling_info->clip_rect;
1543         }
1544
1545         if (srf_update->plane_info) {
1546                 surface->color_space =
1547                                 srf_update->plane_info->color_space;
1548                 surface->format =
1549                                 srf_update->plane_info->format;
1550                 surface->plane_size =
1551                                 srf_update->plane_info->plane_size;
1552                 surface->rotation =
1553                                 srf_update->plane_info->rotation;
1554                 surface->horizontal_mirror =
1555                                 srf_update->plane_info->horizontal_mirror;
1556                 surface->stereo_format =
1557                                 srf_update->plane_info->stereo_format;
1558                 surface->tiling_info =
1559                                 srf_update->plane_info->tiling_info;
1560                 surface->visible =
1561                                 srf_update->plane_info->visible;
1562                 surface->per_pixel_alpha =
1563                                 srf_update->plane_info->per_pixel_alpha;
1564                 surface->global_alpha =
1565                                 srf_update->plane_info->global_alpha;
1566                 surface->global_alpha_value =
1567                                 srf_update->plane_info->global_alpha_value;
1568                 surface->dcc =
1569                                 srf_update->plane_info->dcc;
1570                 surface->sdr_white_level =
1571                                 srf_update->plane_info->sdr_white_level;
1572         }
1573
1574         if (srf_update->gamma &&
1575                         (surface->gamma_correction !=
1576                                         srf_update->gamma)) {
1577                 memcpy(&surface->gamma_correction->entries,
1578                         &srf_update->gamma->entries,
1579                         sizeof(struct dc_gamma_entries));
1580                 surface->gamma_correction->is_identity =
1581                         srf_update->gamma->is_identity;
1582                 surface->gamma_correction->num_entries =
1583                         srf_update->gamma->num_entries;
1584                 surface->gamma_correction->type =
1585                         srf_update->gamma->type;
1586         }
1587
1588         if (srf_update->in_transfer_func &&
1589                         (surface->in_transfer_func !=
1590                                 srf_update->in_transfer_func)) {
1591                 surface->in_transfer_func->sdr_ref_white_level =
1592                         srf_update->in_transfer_func->sdr_ref_white_level;
1593                 surface->in_transfer_func->tf =
1594                         srf_update->in_transfer_func->tf;
1595                 surface->in_transfer_func->type =
1596                         srf_update->in_transfer_func->type;
1597                 memcpy(&surface->in_transfer_func->tf_pts,
1598                         &srf_update->in_transfer_func->tf_pts,
1599                         sizeof(struct dc_transfer_func_distributed_points));
1600         }
1601
1602         if (srf_update->input_csc_color_matrix)
1603                 surface->input_csc_color_matrix =
1604                         *srf_update->input_csc_color_matrix;
1605
1606         if (srf_update->coeff_reduction_factor)
1607                 surface->coeff_reduction_factor =
1608                         *srf_update->coeff_reduction_factor;
1609 }
1610
1611 static void commit_planes_do_stream_update(struct dc *dc,
1612                 struct dc_stream_state *stream,
1613                 struct dc_stream_update *stream_update,
1614                 enum surface_update_type update_type,
1615                 struct dc_state *context)
1616 {
1617         int j;
1618
1619         // Stream updates
1620         for (j = 0; j < dc->res_pool->pipe_count; j++) {
1621                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1622
1623                 if (!pipe_ctx->top_pipe &&
1624                         pipe_ctx->stream &&
1625                         pipe_ctx->stream == stream) {
1626
1627                         /* Fast update*/
1628                         // VRR program can be done as part of FAST UPDATE
1629                         if (stream_update->adjust)
1630                                 dc->hwss.set_drr(&pipe_ctx, 1,
1631                                         stream_update->adjust->v_total_min,
1632                                         stream_update->adjust->v_total_max);
1633
1634                         if (stream_update->periodic_interrupt0 &&
1635                                         dc->hwss.setup_periodic_interrupt)
1636                                 dc->hwss.setup_periodic_interrupt(pipe_ctx, VLINE0);
1637
1638                         if (stream_update->periodic_interrupt1 &&
1639                                         dc->hwss.setup_periodic_interrupt)
1640                                 dc->hwss.setup_periodic_interrupt(pipe_ctx, VLINE1);
1641
1642                         if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
1643                                         stream_update->vrr_infopacket ||
1644                                         stream_update->vsc_infopacket ||
1645                                         stream_update->vsp_infopacket) {
1646                                 resource_build_info_frame(pipe_ctx);
1647                                 dc->hwss.update_info_frame(pipe_ctx);
1648                         }
1649
1650                         if (stream_update->gamut_remap)
1651                                 dc_stream_set_gamut_remap(dc, stream);
1652
1653                         if (stream_update->output_csc_transform)
1654                                 dc_stream_program_csc_matrix(dc, stream);
1655
1656                         if (stream_update->dither_option) {
1657                                 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1658                                                                         &pipe_ctx->stream->bit_depth_params);
1659                                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
1660                                                 &stream->bit_depth_params,
1661                                                 &stream->clamping);
1662                         }
1663
1664                         /* Full fe update*/
1665                         if (update_type == UPDATE_TYPE_FAST)
1666                                 continue;
1667
1668                         if (stream_update->dpms_off) {
1669                                 if (*stream_update->dpms_off) {
1670                                         core_link_disable_stream(pipe_ctx, KEEP_ACQUIRED_RESOURCE);
1671                                         dc->hwss.optimize_bandwidth(dc, dc->current_state);
1672                                 } else {
1673                                         dc->hwss.prepare_bandwidth(dc, dc->current_state);
1674                                         core_link_enable_stream(dc->current_state, pipe_ctx);
1675                                 }
1676                         }
1677
1678                         if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
1679                                 if (pipe_ctx->stream_res.tg->funcs->is_blanked) {
1680                                         // if otg funcs defined check if blanked before programming
1681                                         if (!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
1682                                                 pipe_ctx->stream_res.abm->funcs->set_abm_level(
1683                                                         pipe_ctx->stream_res.abm, stream->abm_level);
1684                                 } else
1685                                         pipe_ctx->stream_res.abm->funcs->set_abm_level(
1686                                                 pipe_ctx->stream_res.abm, stream->abm_level);
1687                         }
1688                 }
1689         }
1690 }
1691
1692 static void commit_planes_for_stream(struct dc *dc,
1693                 struct dc_surface_update *srf_updates,
1694                 int surface_count,
1695                 struct dc_stream_state *stream,
1696                 struct dc_stream_update *stream_update,
1697                 enum surface_update_type update_type,
1698                 struct dc_state *context)
1699 {
1700         int i, j;
1701         struct pipe_ctx *top_pipe_to_program = NULL;
1702
1703         if (update_type == UPDATE_TYPE_FULL) {
1704                 dc->hwss.prepare_bandwidth(dc, context);
1705                 context_clock_trace(dc, context);
1706         }
1707
1708         // Stream updates
1709         if (stream_update)
1710                 commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
1711
1712         if (surface_count == 0) {
1713                 /*
1714                  * In case of turning off screen, no need to program front end a second time.
1715                  * just return after program blank.
1716                  */
1717                 dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
1718                 return;
1719         }
1720
1721         // Update Type FULL, Surface updates
1722         for (j = 0; j < dc->res_pool->pipe_count; j++) {
1723                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1724
1725                 if (!pipe_ctx->top_pipe &&
1726                         pipe_ctx->stream &&
1727                         pipe_ctx->stream == stream) {
1728                         struct dc_stream_status *stream_status = NULL;
1729
1730                         top_pipe_to_program = pipe_ctx;
1731
1732                         if (!pipe_ctx->plane_state)
1733                                 continue;
1734
1735                         /* Full fe update*/
1736                         if (update_type == UPDATE_TYPE_FAST)
1737                                 continue;
1738
1739                         stream_status =
1740                                 stream_get_status(context, pipe_ctx->stream);
1741
1742                         dc->hwss.apply_ctx_for_surface(
1743                                         dc, pipe_ctx->stream, stream_status->plane_count, context);
1744                 }
1745         }
1746
1747         // Update Type FAST, Surface updates
1748         if (update_type == UPDATE_TYPE_FAST) {
1749                 /* Lock the top pipe while updating plane addrs, since freesync requires
1750                  *  plane addr update event triggers to be synchronized.
1751                  *  top_pipe_to_program is expected to never be NULL
1752                  */
1753                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
1754
1755                 /* Perform requested Updates */
1756                 for (i = 0; i < surface_count; i++) {
1757                         struct dc_plane_state *plane_state = srf_updates[i].surface;
1758
1759                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
1760                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1761
1762                                 if (pipe_ctx->stream != stream)
1763                                         continue;
1764
1765                                 if (pipe_ctx->plane_state != plane_state)
1766                                         continue;
1767
1768                                 if (srf_updates[i].flip_addr)
1769                                         dc->hwss.update_plane_addr(dc, pipe_ctx);
1770                         }
1771                 }
1772
1773                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
1774         }
1775 }
1776
1777 void dc_commit_updates_for_stream(struct dc *dc,
1778                 struct dc_surface_update *srf_updates,
1779                 int surface_count,
1780                 struct dc_stream_state *stream,
1781                 struct dc_stream_update *stream_update,
1782                 struct dc_state *state)
1783 {
1784         const struct dc_stream_status *stream_status;
1785         enum surface_update_type update_type;
1786         struct dc_state *context;
1787         struct dc_context *dc_ctx = dc->ctx;
1788         int i, j;
1789
1790         stream_status = dc_stream_get_status(stream);
1791         context = dc->current_state;
1792
1793         update_type = dc_check_update_surfaces_for_stream(
1794                                 dc, srf_updates, surface_count, stream_update, stream_status);
1795
1796         if (update_type >= update_surface_trace_level)
1797                 update_surface_trace(dc, srf_updates, surface_count);
1798
1799
1800         if (update_type >= UPDATE_TYPE_FULL) {
1801
1802                 /* initialize scratch memory for building context */
1803                 context = dc_create_state();
1804                 if (context == NULL) {
1805                         DC_ERROR("Failed to allocate new validate context!\n");
1806                         return;
1807                 }
1808
1809                 dc_resource_state_copy_construct(state, context);
1810
1811                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1812                         struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
1813                         struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1814
1815                         if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
1816                                 new_pipe->plane_state->force_full_update = true;
1817                 }
1818         }
1819
1820
1821         for (i = 0; i < surface_count; i++) {
1822                 struct dc_plane_state *surface = srf_updates[i].surface;
1823
1824                 copy_surface_update_to_plane(surface, &srf_updates[i]);
1825
1826                 if (update_type >= UPDATE_TYPE_MED) {
1827                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
1828                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1829
1830                                 if (pipe_ctx->plane_state != surface)
1831                                         continue;
1832
1833                                 resource_build_scaling_params(pipe_ctx);
1834                         }
1835                 }
1836         }
1837
1838         commit_planes_for_stream(
1839                                 dc,
1840                                 srf_updates,
1841                                 surface_count,
1842                                 stream,
1843                                 stream_update,
1844                                 update_type,
1845                                 context);
1846         /*update current_State*/
1847         if (dc->current_state != context) {
1848
1849                 struct dc_state *old = dc->current_state;
1850
1851                 dc->current_state = context;
1852                 dc_release_state(old);
1853
1854                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1855                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1856
1857                         if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
1858                                 pipe_ctx->plane_state->force_full_update = false;
1859                 }
1860         }
1861         /*let's use current_state to update watermark etc*/
1862         if (update_type >= UPDATE_TYPE_FULL)
1863                 dc_post_update_surfaces_to_stream(dc);
1864
1865         return;
1866
1867 }
1868
1869 uint8_t dc_get_current_stream_count(struct dc *dc)
1870 {
1871         return dc->current_state->stream_count;
1872 }
1873
1874 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
1875 {
1876         if (i < dc->current_state->stream_count)
1877                 return dc->current_state->streams[i];
1878         return NULL;
1879 }
1880
1881 enum dc_irq_source dc_interrupt_to_irq_source(
1882                 struct dc *dc,
1883                 uint32_t src_id,
1884                 uint32_t ext_id)
1885 {
1886         return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
1887 }
1888
1889 /**
1890  * dc_interrupt_set() - Enable/disable an AMD hw interrupt source
1891  */
1892 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
1893 {
1894
1895         if (dc == NULL)
1896                 return false;
1897
1898         return dal_irq_service_set(dc->res_pool->irqs, src, enable);
1899 }
1900
1901 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
1902 {
1903         dal_irq_service_ack(dc->res_pool->irqs, src);
1904 }
1905
1906 void dc_set_power_state(
1907         struct dc *dc,
1908         enum dc_acpi_cm_power_state power_state)
1909 {
1910         struct kref refcount;
1911
1912         switch (power_state) {
1913         case DC_ACPI_CM_POWER_STATE_D0:
1914                 dc_resource_state_construct(dc, dc->current_state);
1915
1916                 dc->hwss.init_hw(dc);
1917                 break;
1918         default:
1919                 ASSERT(dc->current_state->stream_count == 0);
1920                 /* Zero out the current context so that on resume we start with
1921                  * clean state, and dc hw programming optimizations will not
1922                  * cause any trouble.
1923                  */
1924
1925                 /* Preserve refcount */
1926                 refcount = dc->current_state->refcount;
1927                 dc_resource_state_destruct(dc->current_state);
1928                 memset(dc->current_state, 0,
1929                                 sizeof(*dc->current_state));
1930
1931                 dc->current_state->refcount = refcount;
1932
1933                 break;
1934         }
1935
1936 }
1937
1938 void dc_resume(struct dc *dc)
1939 {
1940
1941         uint32_t i;
1942
1943         for (i = 0; i < dc->link_count; i++)
1944                 core_link_resume(dc->links[i]);
1945 }
1946
1947 unsigned int dc_get_current_backlight_pwm(struct dc *dc)
1948 {
1949         struct abm *abm = dc->res_pool->abm;
1950
1951         if (abm)
1952                 return abm->funcs->get_current_backlight(abm);
1953
1954         return 0;
1955 }
1956
1957 unsigned int dc_get_target_backlight_pwm(struct dc *dc)
1958 {
1959         struct abm *abm = dc->res_pool->abm;
1960
1961         if (abm)
1962                 return abm->funcs->get_target_backlight(abm);
1963
1964         return 0;
1965 }
1966
1967 bool dc_is_dmcu_initialized(struct dc *dc)
1968 {
1969         struct dmcu *dmcu = dc->res_pool->dmcu;
1970
1971         if (dmcu)
1972                 return dmcu->funcs->is_dmcu_initialized(dmcu);
1973         return false;
1974 }
1975
1976 bool dc_submit_i2c(
1977                 struct dc *dc,
1978                 uint32_t link_index,
1979                 struct i2c_command *cmd)
1980 {
1981
1982         struct dc_link *link = dc->links[link_index];
1983         struct ddc_service *ddc = link->ddc;
1984         return dce_i2c_submit_command(
1985                 dc->res_pool,
1986                 ddc->ddc_pin,
1987                 cmd);
1988 }
1989
1990 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
1991 {
1992         if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
1993                 BREAK_TO_DEBUGGER();
1994                 return false;
1995         }
1996
1997         dc_sink_retain(sink);
1998
1999         dc_link->remote_sinks[dc_link->sink_count] = sink;
2000         dc_link->sink_count++;
2001
2002         return true;
2003 }
2004
2005 /**
2006  * dc_link_add_remote_sink() - Create a sink and attach it to an existing link
2007  *
2008  * EDID length is in bytes
2009  */
2010 struct dc_sink *dc_link_add_remote_sink(
2011                 struct dc_link *link,
2012                 const uint8_t *edid,
2013                 int len,
2014                 struct dc_sink_init_data *init_data)
2015 {
2016         struct dc_sink *dc_sink;
2017         enum dc_edid_status edid_status;
2018
2019         if (len > DC_MAX_EDID_BUFFER_SIZE) {
2020                 dm_error("Max EDID buffer size breached!\n");
2021                 return NULL;
2022         }
2023
2024         if (!init_data) {
2025                 BREAK_TO_DEBUGGER();
2026                 return NULL;
2027         }
2028
2029         if (!init_data->link) {
2030                 BREAK_TO_DEBUGGER();
2031                 return NULL;
2032         }
2033
2034         dc_sink = dc_sink_create(init_data);
2035
2036         if (!dc_sink)
2037                 return NULL;
2038
2039         memmove(dc_sink->dc_edid.raw_edid, edid, len);
2040         dc_sink->dc_edid.length = len;
2041
2042         if (!link_add_remote_sink_helper(
2043                         link,
2044                         dc_sink))
2045                 goto fail_add_sink;
2046
2047         edid_status = dm_helpers_parse_edid_caps(
2048                         link->ctx,
2049                         &dc_sink->dc_edid,
2050                         &dc_sink->edid_caps);
2051
2052         /*
2053          * Treat device as no EDID device if EDID
2054          * parsing fails
2055          */
2056         if (edid_status != EDID_OK) {
2057                 dc_sink->dc_edid.length = 0;
2058                 dm_error("Bad EDID, status%d!\n", edid_status);
2059         }
2060
2061         return dc_sink;
2062
2063 fail_add_sink:
2064         dc_sink_release(dc_sink);
2065         return NULL;
2066 }
2067
2068 /**
2069  * dc_link_remove_remote_sink() - Remove a remote sink from a dc_link
2070  *
2071  * Note that this just removes the struct dc_sink - it doesn't
2072  * program hardware or alter other members of dc_link
2073  */
2074 void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
2075 {
2076         int i;
2077
2078         if (!link->sink_count) {
2079                 BREAK_TO_DEBUGGER();
2080                 return;
2081         }
2082
2083         for (i = 0; i < link->sink_count; i++) {
2084                 if (link->remote_sinks[i] == sink) {
2085                         dc_sink_release(sink);
2086                         link->remote_sinks[i] = NULL;
2087
2088                         /* shrink array to remove empty place */
2089                         while (i < link->sink_count - 1) {
2090                                 link->remote_sinks[i] = link->remote_sinks[i+1];
2091                                 i++;
2092                         }
2093                         link->remote_sinks[i] = NULL;
2094                         link->sink_count--;
2095                         return;
2096                 }
2097         }
2098 }
2099
2100 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
2101 {
2102         info->displayClock                              = (unsigned int)state->bw.dcn.clk.dispclk_khz;
2103         info->engineClock                               = (unsigned int)state->bw.dcn.clk.dcfclk_khz;
2104         info->memoryClock                               = (unsigned int)state->bw.dcn.clk.dramclk_khz;
2105         info->maxSupportedDppClock              = (unsigned int)state->bw.dcn.clk.max_supported_dppclk_khz;
2106         info->dppClock                                  = (unsigned int)state->bw.dcn.clk.dppclk_khz;
2107         info->socClock                                  = (unsigned int)state->bw.dcn.clk.socclk_khz;
2108         info->dcfClockDeepSleep                 = (unsigned int)state->bw.dcn.clk.dcfclk_deep_sleep_khz;
2109         info->fClock                                    = (unsigned int)state->bw.dcn.clk.fclk_khz;
2110         info->phyClock                                  = (unsigned int)state->bw.dcn.clk.phyclk_khz;
2111 }