drivers/gpu/drm/amd/display/dc/core/dc.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24
  25 #include "dm_services.h"
  26
  27 #include "dc.h"
  28
  29 #include "core_status.h"
  30 #include "core_types.h"
  31 #include "hw_sequencer.h"
  32 #include "dce/dce_hwseq.h"
  33
  34 #include "resource.h"
  35
  36 #include "clock_source.h"
  37 #include "dc_bios_types.h"
  38
  39 #include "bios_parser_interface.h"
  40 #include "include/irq_service_interface.h"
  41 #include "transform.h"
  42 #include "dmcu.h"
  43 #include "dpp.h"
  44 #include "timing_generator.h"
  45 #include "abm.h"
  46 #include "virtual/virtual_link_encoder.h"
  47
  48 #include "link_hwss.h"
  49 #include "link_encoder.h"
  50
  51 #include "dc_link_ddc.h"
  52 #include "dm_helpers.h"
  53 #include "mem_input.h"
  54 #include "hubp.h"
  55
  56 #include "dc_link_dp.h"
  57
  58 #include "dce/dce_i2c.h"
  59
  60 #define DC_LOGGER \
  61         dc->ctx->logger
  62
  63 const static char DC_BUILD_ID[] = "production-build";
  64
  65 /**
  66  * DOC: Overview
  67  *
  68  * DC is the OS-agnostic component of the amdgpu DC driver.
  69  *
  70  * DC maintains and validates a set of structs representing the state of the
  71  * driver and writes that state to AMD hardware
  72  *
  73  * Main DC HW structs:
  74  *
  75  * struct dc - The central struct.  One per driver.  Created on driver load,
  76  * destroyed on driver unload.
  77  *
  78  * struct dc_context - One per driver.
  79  * Used as a backpointer by most other structs in dc.
  80  *
  81  * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
  82  * plugpoints).  Created on driver load, destroyed on driver unload.
  83  *
  84  * struct dc_sink - One per display.  Created on boot or hotplug.
  85  * Destroyed on shutdown or hotunplug.  A dc_link can have a local sink
  86  * (the display directly attached).  It may also have one or more remote
  87  * sinks (in the Multi-Stream Transport case)
  88  *
  89  * struct resource_pool - One per driver.  Represents the hw blocks not in the
  90  * main pipeline.  Not directly accessible by dm.
  91  *
  92  * Main dc state structs:
  93  *
  94  * These structs can be created and destroyed as needed.  There is a full set of
  95  * these structs in dc->current_state representing the currently programmed state.
  96  *
  97  * struct dc_state - The global DC state to track global state information,
  98  * such as bandwidth values.
  99  *
 100  * struct dc_stream_state - Represents the hw configuration for the pipeline from
 101  * a framebuffer to a display.  Maps one-to-one with dc_sink.
 102  *
 103  * struct dc_plane_state - Represents a framebuffer.  Each stream has at least one,
 104  * and may have more in the Multi-Plane Overlay case.
 105  *
 106  * struct resource_context - Represents the programmable state of everything in
 107  * the resource_pool.  Not directly accessible by dm.
 108  *
 109  * struct pipe_ctx - A member of struct resource_context.  Represents the
 110  * internal hardware pipeline components.  Each dc_plane_state has either
 111  * one or two (in the pipe-split case).
 112  */
 113
 114 /*******************************************************************************
 115  * Private functions
 116  ******************************************************************************/
 117
 118 static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)
 119 {
 120         if (new > *original)
 121                 *original = new;
 122 }
 123
 124 static void destroy_links(struct dc *dc)
 125 {
 126         uint32_t i;
 127
 128         for (i = 0; i < dc->link_count; i++) {
 129                 if (NULL != dc->links[i])
 130                         link_destroy(&dc->links[i]);
 131         }
 132 }
 133
 134 static bool create_links(
 135                 struct dc *dc,
 136                 uint32_t num_virtual_links)
 137 {
 138         int i;
 139         int connectors_num;
 140         struct dc_bios *bios = dc->ctx->dc_bios;
 141
 142         dc->link_count = 0;
 143
 144         connectors_num = bios->funcs->get_connectors_number(bios);
 145
 146         if (connectors_num > ENUM_ID_COUNT) {
 147                 dm_error(
 148                         "DC: Number of connectors %d exceeds maximum of %d!\n",
 149                         connectors_num,
 150                         ENUM_ID_COUNT);
 151                 return false;
 152         }
 153
 154         dm_output_to_console(
 155                 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
 156                 __func__,
 157                 connectors_num,
 158                 num_virtual_links);
 159
 160         for (i = 0; i < connectors_num; i++) {
 161                 struct link_init_data link_init_params = {0};
 162                 struct dc_link *link;
 163
 164                 link_init_params.ctx = dc->ctx;
 165                 /* next BIOS object table connector */
 166                 link_init_params.connector_index = i;
 167                 link_init_params.link_index = dc->link_count;
 168                 link_init_params.dc = dc;
 169                 link = link_create(&link_init_params);
 170
 171                 if (link) {
 172                         dc->links[dc->link_count] = link;
 173                         link->dc = dc;
 174                         ++dc->link_count;
 175                 }
 176         }
 177
 178         for (i = 0; i < num_virtual_links; i++) {
 179                 struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL);
 180                 struct encoder_init_data enc_init = {0};
 181
 182                 if (link == NULL) {
 183                         BREAK_TO_DEBUGGER();
 184                         goto failed_alloc;
 185                 }
 186
 187                 link->link_index = dc->link_count;
 188                 dc->links[dc->link_count] = link;
 189                 dc->link_count++;
 190
 191                 link->ctx = dc->ctx;
 192                 link->dc = dc;
 193                 link->connector_signal = SIGNAL_TYPE_VIRTUAL;
 194                 link->link_id.type = OBJECT_TYPE_CONNECTOR;
 195                 link->link_id.id = CONNECTOR_ID_VIRTUAL;
 196                 link->link_id.enum_id = ENUM_ID_1;
 197                 link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL);
 198
 199                 if (!link->link_enc) {
 200                         BREAK_TO_DEBUGGER();
 201                         goto failed_alloc;
 202                 }
 203
 204                 link->link_status.dpcd_caps = &link->dpcd_caps;
 205
 206                 enc_init.ctx = dc->ctx;
 207                 enc_init.channel = CHANNEL_ID_UNKNOWN;
 208                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
 209                 enc_init.transmitter = TRANSMITTER_UNKNOWN;
 210                 enc_init.connector = link->link_id;
 211                 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
 212                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
 213                 enc_init.encoder.enum_id = ENUM_ID_1;
 214                 virtual_link_encoder_construct(link->link_enc, &enc_init);
 215         }
 216
 217         return true;
 218
 219 failed_alloc:
 220         return false;
 221 }
 222
 223 static struct dc_perf_trace *dc_perf_trace_create(void)
 224 {
 225         return kzalloc(sizeof(struct dc_perf_trace), GFP_KERNEL);
 226 }
 227
 228 static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace)
 229 {
 230         kfree(*perf_trace);
 231         *perf_trace = NULL;
 232 }
 233
 234 /**
 235  *****************************************************************************
 236  *  Function: dc_stream_adjust_vmin_vmax
 237  *
 238  *  @brief
 239  *     Looks up the pipe context of dc_stream_state and updates the
 240  *     vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
 241  *     Rate, which is a power-saving feature that targets reducing panel
 242  *     refresh rate while the screen is static
 243  *
 244  *  @param [in] dc: dc reference
 245  *  @param [in] stream: Initial dc stream state
 246  *  @param [in] adjust: Updated parameters for vertical_total_min and
 247  *  vertical_total_max
 248  *****************************************************************************
 249  */
 250 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 251                 struct dc_stream_state *stream,
 252                 struct dc_crtc_timing_adjust *adjust)
 253 {
 254         int i = 0;
 255         bool ret = false;
 256
 257         for (i = 0; i < MAX_PIPES; i++) {
 258                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 259
 260                 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
 261                         pipe->stream->adjust = *adjust;
 262                         dc->hwss.set_drr(&pipe,
 263                                         1,
 264                                         adjust->v_total_min,
 265                                         adjust->v_total_max);
 266
 267                         ret = true;
 268                 }
 269         }
 270         return ret;
 271 }
 272
 273 bool dc_stream_get_crtc_position(struct dc *dc,
 274                 struct dc_stream_state **streams, int num_streams,
 275                 unsigned int *v_pos, unsigned int *nom_v_pos)
 276 {
 277         /* TODO: Support multiple streams */
 278         const struct dc_stream_state *stream = streams[0];
 279         int i = 0;
 280         bool ret = false;
 281         struct crtc_position position;
 282
 283         for (i = 0; i < MAX_PIPES; i++) {
 284                 struct pipe_ctx *pipe =
 285                                 &dc->current_state->res_ctx.pipe_ctx[i];
 286
 287                 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
 288                         dc->hwss.get_position(&pipe, 1, &position);
 289
 290                         *v_pos = position.vertical_count;
 291                         *nom_v_pos = position.nominal_vcount;
 292                         ret = true;
 293                 }
 294         }
 295         return ret;
 296 }
 297
 298 /**
 299  * dc_stream_configure_crc() - Configure CRC capture for the given stream.
 300  * @dc: DC Object
 301  * @stream: The stream to configure CRC on.
 302  * @enable: Enable CRC if true, disable otherwise.
 303  * @continuous: Capture CRC on every frame if true. Otherwise, only capture
 304  *              once.
 305  *
 306  * By default, only CRC0 is configured, and the entire frame is used to
 307  * calculate the crc.
 308  */
 309 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
 310                              bool enable, bool continuous)
 311 {
 312         int i;
 313         struct pipe_ctx *pipe;
 314         struct crc_params param;
 315         struct timing_generator *tg;
 316
 317         for (i = 0; i < MAX_PIPES; i++) {
 318                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 319                 if (pipe->stream == stream)
 320                         break;
 321         }
 322         /* Stream not found */
 323         if (i == MAX_PIPES)
 324                 return false;
 325
 326         /* Always capture the full frame */
 327         param.windowa_x_start = 0;
 328         param.windowa_y_start = 0;
 329         param.windowa_x_end = pipe->stream->timing.h_addressable;
 330         param.windowa_y_end = pipe->stream->timing.v_addressable;
 331         param.windowb_x_start = 0;
 332         param.windowb_y_start = 0;
 333         param.windowb_x_end = pipe->stream->timing.h_addressable;
 334         param.windowb_y_end = pipe->stream->timing.v_addressable;
 335
 336         /* Default to the union of both windows */
 337         param.selection = UNION_WINDOW_A_B;
 338         param.continuous_mode = continuous;
 339         param.enable = enable;
 340
 341         tg = pipe->stream_res.tg;
 342
 343         /* Only call if supported */
 344         if (tg->funcs->configure_crc)
 345                 return tg->funcs->configure_crc(tg, &param);
 346         DC_LOG_WARNING("CRC capture not supported.");
 347         return false;
 348 }
 349
 350 /**
 351  * dc_stream_get_crc() - Get CRC values for the given stream.
 352  * @dc: DC object
 353  * @stream: The DC stream state of the stream to get CRCs from.
 354  * @r_cr, g_y, b_cb: CRC values for the three channels are stored here.
 355  *
 356  * dc_stream_configure_crc needs to be called beforehand to enable CRCs.
 357  * Return false if stream is not found, or if CRCs are not enabled.
 358  */
 359 bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
 360                        uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
 361 {
 362         int i;
 363         struct pipe_ctx *pipe;
 364         struct timing_generator *tg;
 365
 366         for (i = 0; i < MAX_PIPES; i++) {
 367                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 368                 if (pipe->stream == stream)
 369                         break;
 370         }
 371         /* Stream not found */
 372         if (i == MAX_PIPES)
 373                 return false;
 374
 375         tg = pipe->stream_res.tg;
 376
 377         if (tg->funcs->get_crc)
 378                 return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);
 379         DC_LOG_WARNING("CRC capture not supported.");
 380         return false;
 381 }
 382
 383 void dc_stream_set_dither_option(struct dc_stream_state *stream,
 384                 enum dc_dither_option option)
 385 {
 386         struct bit_depth_reduction_params params;
 387         struct dc_link *link = stream->sink->link;
 388         struct pipe_ctx *pipes = NULL;
 389         int i;
 390
 391         for (i = 0; i < MAX_PIPES; i++) {
 392                 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
 393                                 stream) {
 394                         pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
 395                         break;
 396                 }
 397         }
 398
 399         if (!pipes)
 400                 return;
 401         if (option > DITHER_OPTION_MAX)
 402                 return;
 403
 404         stream->dither_option = option;
 405
 406         memset(&params, 0, sizeof(params));
 407         resource_build_bit_depth_reduction_params(stream, &params);
 408         stream->bit_depth_params = params;
 409
 410         if (pipes->plane_res.xfm &&
 411             pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
 412                 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
 413                         pipes->plane_res.xfm,
 414                         pipes->plane_res.scl_data.lb_params.depth,
 415                         &stream->bit_depth_params);
 416         }
 417
 418         pipes->stream_res.opp->funcs->
 419                 opp_program_bit_depth_reduction(pipes->stream_res.opp, &params);
 420 }
 421
 422 bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
 423 {
 424         int i = 0;
 425         bool ret = false;
 426         struct pipe_ctx *pipes;
 427
 428         for (i = 0; i < MAX_PIPES; i++) {
 429                 if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
 430                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 431                         dc->hwss.program_gamut_remap(pipes);
 432                         ret = true;
 433                 }
 434         }
 435
 436         return ret;
 437 }
 438
 439 bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
 440 {
 441         int i = 0;
 442         bool ret = false;
 443         struct pipe_ctx *pipes;
 444
 445         for (i = 0; i < MAX_PIPES; i++) {
 446                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 447                                 == stream) {
 448
 449                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 450                         dc->hwss.program_output_csc(dc,
 451                                         pipes,
 452                                         stream->output_color_space,
 453                                         stream->csc_color_matrix.matrix,
 454                                         pipes->plane_res.hubp->opp_id);
 455                         ret = true;
 456                 }
 457         }
 458
 459         return ret;
 460 }
 461
 462 void dc_stream_set_static_screen_events(struct dc *dc,
 463                 struct dc_stream_state **streams,
 464                 int num_streams,
 465                 const struct dc_static_screen_events *events)
 466 {
 467         int i = 0;
 468         int j = 0;
 469         struct pipe_ctx *pipes_affected[MAX_PIPES];
 470         int num_pipes_affected = 0;
 471
 472         for (i = 0; i < num_streams; i++) {
 473                 struct dc_stream_state *stream = streams[i];
 474
 475                 for (j = 0; j < MAX_PIPES; j++) {
 476                         if (dc->current_state->res_ctx.pipe_ctx[j].stream
 477                                         == stream) {
 478                                 pipes_affected[num_pipes_affected++] =
 479                                                 &dc->current_state->res_ctx.pipe_ctx[j];
 480                         }
 481                 }
 482         }
 483
 484         dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events);
 485 }
 486
 487 void dc_link_set_drive_settings(struct dc *dc,
 488                                 struct link_training_settings *lt_settings,
 489                                 const struct dc_link *link)
 490 {
 491
 492         int i;
 493
 494         for (i = 0; i < dc->link_count; i++) {
 495                 if (dc->links[i] == link)
 496                         break;
 497         }
 498
 499         if (i >= dc->link_count)
 500                 ASSERT_CRITICAL(false);
 501
 502         dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
 503 }
 504
 505 void dc_link_perform_link_training(struct dc *dc,
 506                                    struct dc_link_settings *link_setting,
 507                                    bool skip_video_pattern)
 508 {
 509         int i;
 510
 511         for (i = 0; i < dc->link_count; i++)
 512                 dc_link_dp_perform_link_training(
 513                         dc->links[i],
 514                         link_setting,
 515                         skip_video_pattern);
 516 }
 517
 518 void dc_link_set_preferred_link_settings(struct dc *dc,
 519                                          struct dc_link_settings *link_setting,
 520                                          struct dc_link *link)
 521 {
 522         int i;
 523         struct pipe_ctx *pipe;
 524         struct dc_stream_state *link_stream;
 525         struct dc_link_settings store_settings = *link_setting;
 526
 527         for (i = 0; i < MAX_PIPES; i++) {
 528                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 529                 if (pipe->stream && pipe->stream->sink
 530                         && pipe->stream->sink->link) {
 531                         if (pipe->stream->sink->link == link)
 532                                 break;
 533                 }
 534         }
 535
 536         /* Stream not found */
 537         if (i == MAX_PIPES)
 538                 return;
 539
 540         link_stream = link->dc->current_state->res_ctx.pipe_ctx[i].stream;
 541
 542         link->preferred_link_setting = store_settings;
 543         if (link_stream)
 544                 decide_link_settings(link_stream, &store_settings);
 545
 546         if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
 547                 (store_settings.link_rate != LINK_RATE_UNKNOWN))
 548                 dp_retrain_link_dp_test(link, &store_settings, false);
 549 }
 550
 551 void dc_link_enable_hpd(const struct dc_link *link)
 552 {
 553         dc_link_dp_enable_hpd(link);
 554 }
 555
 556 void dc_link_disable_hpd(const struct dc_link *link)
 557 {
 558         dc_link_dp_disable_hpd(link);
 559 }
 560
 561
 562 void dc_link_set_test_pattern(struct dc_link *link,
 563                               enum dp_test_pattern test_pattern,
 564                               const struct link_training_settings *p_link_settings,
 565                               const unsigned char *p_custom_pattern,
 566                               unsigned int cust_pattern_size)
 567 {
 568         if (link != NULL)
 569                 dc_link_dp_set_test_pattern(
 570                         link,
 571                         test_pattern,
 572                         p_link_settings,
 573                         p_custom_pattern,
 574                         cust_pattern_size);
 575 }
 576
 577 static void destruct(struct dc *dc)
 578 {
 579         dc_release_state(dc->current_state);
 580         dc->current_state = NULL;
 581
 582         destroy_links(dc);
 583
 584         dc_destroy_resource_pool(dc);
 585
 586         if (dc->ctx->gpio_service)
 587                 dal_gpio_service_destroy(&dc->ctx->gpio_service);
 588
 589         if (dc->ctx->i2caux)
 590                 dal_i2caux_destroy(&dc->ctx->i2caux);
 591
 592         if (dc->ctx->created_bios)
 593                 dal_bios_parser_destroy(&dc->ctx->dc_bios);
 594
 595         dc_perf_trace_destroy(&dc->ctx->perf_trace);
 596
 597         kfree(dc->ctx);
 598         dc->ctx = NULL;
 599
 600         kfree(dc->bw_vbios);
 601         dc->bw_vbios = NULL;
 602
 603         kfree(dc->bw_dceip);
 604         dc->bw_dceip = NULL;
 605
 606 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 607         kfree(dc->dcn_soc);
 608         dc->dcn_soc = NULL;
 609
 610         kfree(dc->dcn_ip);
 611         dc->dcn_ip = NULL;
 612
 613 #endif
 614 }
 615
 616 static bool construct(struct dc *dc,
 617                 const struct dc_init_data *init_params)
 618 {
 619         struct dc_context *dc_ctx;
 620         struct bw_calcs_dceip *dc_dceip;
 621         struct bw_calcs_vbios *dc_vbios;
 622 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 623         struct dcn_soc_bounding_box *dcn_soc;
 624         struct dcn_ip_params *dcn_ip;
 625 #endif
 626
 627         enum dce_version dc_version = DCE_VERSION_UNKNOWN;
 628
 629         dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
 630         if (!dc_dceip) {
 631                 dm_error("%s: failed to create dceip\n", __func__);
 632                 goto fail;
 633         }
 634
 635         dc->bw_dceip = dc_dceip;
 636
 637         dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL);
 638         if (!dc_vbios) {
 639                 dm_error("%s: failed to create vbios\n", __func__);
 640                 goto fail;
 641         }
 642
 643         dc->bw_vbios = dc_vbios;
 644 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 645         dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
 646         if (!dcn_soc) {
 647                 dm_error("%s: failed to create dcn_soc\n", __func__);
 648                 goto fail;
 649         }
 650
 651         dc->dcn_soc = dcn_soc;
 652
 653         dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL);
 654         if (!dcn_ip) {
 655                 dm_error("%s: failed to create dcn_ip\n", __func__);
 656                 goto fail;
 657         }
 658
 659         dc->dcn_ip = dcn_ip;
 660 #endif
 661
 662         dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
 663         if (!dc_ctx) {
 664                 dm_error("%s: failed to create ctx\n", __func__);
 665                 goto fail;
 666         }
 667
 668         dc_ctx->cgs_device = init_params->cgs_device;
 669         dc_ctx->driver_context = init_params->driver;
 670         dc_ctx->dc = dc;
 671         dc_ctx->asic_id = init_params->asic_id;
 672         dc_ctx->dc_sink_id_count = 0;
 673         dc->ctx = dc_ctx;
 674
 675         dc->current_state = dc_create_state();
 676
 677         if (!dc->current_state) {
 678                 dm_error("%s: failed to create validate ctx\n", __func__);
 679                 goto fail;
 680         }
 681
 682         /* Create logger */
 683
 684         dc_ctx->dce_environment = init_params->dce_environment;
 685
 686         dc_version = resource_parse_asic_id(init_params->asic_id);
 687         dc_ctx->dce_version = dc_version;
 688
 689         /* Resource should construct all asic specific resources.
 690          * This should be the only place where we need to parse the asic id
 691          */
 692         if (init_params->vbios_override)
 693                 dc_ctx->dc_bios = init_params->vbios_override;
 694         else {
 695                 /* Create BIOS parser */
 696                 struct bp_init_data bp_init_data;
 697
 698                 bp_init_data.ctx = dc_ctx;
 699                 bp_init_data.bios = init_params->asic_id.atombios_base_address;
 700
 701                 dc_ctx->dc_bios = dal_bios_parser_create(
 702                                 &bp_init_data, dc_version);
 703
 704                 if (!dc_ctx->dc_bios) {
 705                         ASSERT_CRITICAL(false);
 706                         goto fail;
 707                 }
 708
 709                 dc_ctx->created_bios = true;
 710                 }
 711
 712         /* Create I2C AUX */
 713         dc_ctx->i2caux = dal_i2caux_create(dc_ctx);
 714
 715         if (!dc_ctx->i2caux) {
 716                 ASSERT_CRITICAL(false);
 717                 goto fail;
 718         }
 719
 720         dc_ctx->perf_trace = dc_perf_trace_create();
 721         if (!dc_ctx->perf_trace) {
 722                 ASSERT_CRITICAL(false);
 723                 goto fail;
 724         }
 725
 726         /* Create GPIO service */
 727         dc_ctx->gpio_service = dal_gpio_service_create(
 728                         dc_version,
 729                         dc_ctx->dce_environment,
 730                         dc_ctx);
 731
 732         if (!dc_ctx->gpio_service) {
 733                 ASSERT_CRITICAL(false);
 734                 goto fail;
 735         }
 736
 737         dc->res_pool = dc_create_resource_pool(
 738                         dc,
 739                         init_params->num_virtual_links,
 740                         dc_version,
 741                         init_params->asic_id);
 742         if (!dc->res_pool)
 743                 goto fail;
 744
 745         dc_resource_state_construct(dc, dc->current_state);
 746
 747         if (!create_links(dc, init_params->num_virtual_links))
 748                 goto fail;
 749
 750         return true;
 751
 752 fail:
 753
 754         destruct(dc);
 755         return false;
 756 }
 757
 758 static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
 759 {
 760         int i, j;
 761         struct dc_state *dangling_context = dc_create_state();
 762         struct dc_state *current_ctx;
 763
 764         if (dangling_context == NULL)
 765                 return;
 766
 767         dc_resource_state_copy_construct(dc->current_state, dangling_context);
 768
 769         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 770                 struct dc_stream_state *old_stream =
 771                                 dc->current_state->res_ctx.pipe_ctx[i].stream;
 772                 bool should_disable = true;
 773
 774                 for (j = 0; j < context->stream_count; j++) {
 775                         if (old_stream == context->streams[j]) {
 776                                 should_disable = false;
 777                                 break;
 778                         }
 779                 }
 780                 if (should_disable && old_stream) {
 781                         dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
 782                         dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
 783                 }
 784         }
 785
 786         current_ctx = dc->current_state;
 787         dc->current_state = dangling_context;
 788         dc_release_state(current_ctx);
 789 }
 790
 791 /*******************************************************************************
 792  * Public functions
 793  ******************************************************************************/
 794
 795 struct dc *dc_create(const struct dc_init_data *init_params)
 796 {
 797         struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
 798         unsigned int full_pipe_count;
 799
 800         if (NULL == dc)
 801                 goto alloc_fail;
 802
 803         if (false == construct(dc, init_params))
 804                 goto construct_fail;
 805
 806         /*TODO: separate HW and SW initialization*/
 807         dc->hwss.init_hw(dc);
 808
 809         full_pipe_count = dc->res_pool->pipe_count;
 810         if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
 811                 full_pipe_count--;
 812         dc->caps.max_streams = min(
 813                         full_pipe_count,
 814                         dc->res_pool->stream_enc_count);
 815
 816         dc->caps.max_links = dc->link_count;
 817         dc->caps.max_audios = dc->res_pool->audio_count;
 818         dc->caps.linear_pitch_alignment = 64;
 819
 820         /* Populate versioning information */
 821         dc->versions.dc_ver = DC_VER;
 822
 823         if (dc->res_pool->dmcu != NULL)
 824                 dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
 825
 826         dc->config = init_params->flags;
 827
 828         dc->build_id = DC_BUILD_ID;
 829
 830         DC_LOG_DC("Display Core initialized\n");
 831
 832
 833
 834         return dc;
 835
 836 construct_fail:
 837         kfree(dc);
 838
 839 alloc_fail:
 840         return NULL;
 841 }
 842
 843 void dc_destroy(struct dc **dc)
 844 {
 845         destruct(*dc);
 846         kfree(*dc);
 847         *dc = NULL;
 848 }
 849
 850 static void enable_timing_multisync(
 851                 struct dc *dc,
 852                 struct dc_state *ctx)
 853 {
 854         int i = 0, multisync_count = 0;
 855         int pipe_count = dc->res_pool->pipe_count;
 856         struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
 857
 858         for (i = 0; i < pipe_count; i++) {
 859                 if (!ctx->res_ctx.pipe_ctx[i].stream ||
 860                                 !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
 861                         continue;
 862                 if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)
 863                         continue;
 864                 multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
 865                 multisync_count++;
 866         }
 867
 868         if (multisync_count > 0) {
 869                 dc->hwss.enable_per_frame_crtc_position_reset(
 870                         dc, multisync_count, multisync_pipes);
 871         }
 872 }
 873
 874 static void program_timing_sync(
 875                 struct dc *dc,
 876                 struct dc_state *ctx)
 877 {
 878         int i, j;
 879         int group_index = 0;
 880         int pipe_count = dc->res_pool->pipe_count;
 881         struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
 882
 883         for (i = 0; i < pipe_count; i++) {
 884                 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
 885                         continue;
 886
 887                 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
 888         }
 889
 890         for (i = 0; i < pipe_count; i++) {
 891                 int group_size = 1;
 892                 struct pipe_ctx *pipe_set[MAX_PIPES];
 893
 894                 if (!unsynced_pipes[i])
 895                         continue;
 896
 897                 pipe_set[0] = unsynced_pipes[i];
 898                 unsynced_pipes[i] = NULL;
 899
 900                 /* Add tg to the set, search rest of the tg's for ones with
 901                  * same timing, add all tgs with same timing to the group
 902                  */
 903                 for (j = i + 1; j < pipe_count; j++) {
 904                         if (!unsynced_pipes[j])
 905                                 continue;
 906
 907                         if (resource_are_streams_timing_synchronizable(
 908                                         unsynced_pipes[j]->stream,
 909                                         pipe_set[0]->stream)) {
 910                                 pipe_set[group_size] = unsynced_pipes[j];
 911                                 unsynced_pipes[j] = NULL;
 912                                 group_size++;
 913                         }
 914                 }
 915
 916                 /* set first unblanked pipe as master */
 917                 for (j = 0; j < group_size; j++) {
 918                         struct pipe_ctx *temp;
 919
 920                         if (pipe_set[j]->stream_res.tg->funcs->is_blanked && !pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg)) {
 921                                 if (j == 0)
 922                                         break;
 923
 924                                 temp = pipe_set[0];
 925                                 pipe_set[0] = pipe_set[j];
 926                                 pipe_set[j] = temp;
 927                                 break;
 928                         }
 929                 }
 930
 931                 /* remove any other unblanked pipes as they have already been synced */
 932                 for (j = j + 1; j < group_size; j++) {
 933                         if (pipe_set[j]->stream_res.tg->funcs->is_blanked && !pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg)) {
 934                                 group_size--;
 935                                 pipe_set[j] = pipe_set[group_size];
 936                                 j--;
 937                         }
 938                 }
 939
 940                 if (group_size > 1) {
 941                         dc->hwss.enable_timing_synchronization(
 942                                 dc, group_index, group_size, pipe_set);
 943                         group_index++;
 944                 }
 945         }
 946 }
 947
 948 static bool context_changed(
 949                 struct dc *dc,
 950                 struct dc_state *context)
 951 {
 952         uint8_t i;
 953
 954         if (context->stream_count != dc->current_state->stream_count)
 955                 return true;
 956
 957         for (i = 0; i < dc->current_state->stream_count; i++) {
 958                 if (dc->current_state->streams[i] != context->streams[i])
 959                         return true;
 960         }
 961
 962         return false;
 963 }
 964
 965 bool dc_enable_stereo(
 966         struct dc *dc,
 967         struct dc_state *context,
 968         struct dc_stream_state *streams[],
 969         uint8_t stream_count)
 970 {
 971         bool ret = true;
 972         int i, j;
 973         struct pipe_ctx *pipe;
 974
 975         for (i = 0; i < MAX_PIPES; i++) {
 976                 if (context != NULL)
 977                         pipe = &context->res_ctx.pipe_ctx[i];
 978                 else
 979                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 980                 for (j = 0 ; pipe && j < stream_count; j++)  {
 981                         if (streams[j] && streams[j] == pipe->stream &&
 982                                 dc->hwss.setup_stereo)
 983                                 dc->hwss.setup_stereo(pipe, dc);
 984                 }
 985         }
 986
 987         return ret;
 988 }
 989
 990 /*
 991  * Applies given context to HW and copy it into current context.
 992  * It's up to the user to release the src context afterwards.
 993  */
 994 static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
 995 {
 996         struct dc_bios *dcb = dc->ctx->dc_bios;
 997         enum dc_status result = DC_ERROR_UNEXPECTED;
 998         struct pipe_ctx *pipe;
 999         int i, k, l;
1000         struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
1001
1002         disable_dangling_plane(dc, context);
1003
1004         for (i = 0; i < context->stream_count; i++)
1005                 dc_streams[i] =  context->streams[i];
1006
1007         if (!dcb->funcs->is_accelerated_mode(dcb))
1008                 dc->hwss.enable_accelerated_mode(dc, context);
1009
1010         dc->hwss.prepare_bandwidth(dc, context);
1011
1012         /* re-program planes for existing stream, in case we need to
1013          * free up plane resource for later use
1014          */
1015         for (i = 0; i < context->stream_count; i++) {
1016                 if (context->streams[i]->mode_changed)
1017                         continue;
1018
1019                 dc->hwss.apply_ctx_for_surface(
1020                         dc, context->streams[i],
1021                         context->stream_status[i].plane_count,
1022                         context); /* use new pipe config in new context */
1023         }
1024
1025         /* Program hardware */
1026         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1027                 pipe = &context->res_ctx.pipe_ctx[i];
1028                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
1029         }
1030
1031         result = dc->hwss.apply_ctx_to_hw(dc, context);
1032
1033         if (result != DC_OK)
1034                 return result;
1035
1036         if (context->stream_count > 1) {
1037                 enable_timing_multisync(dc, context);
1038                 program_timing_sync(dc, context);
1039         }
1040
1041         /* Program all planes within new context*/
1042         for (i = 0; i < context->stream_count; i++) {
1043                 const struct dc_sink *sink = context->streams[i]->sink;
1044
1045                 if (!context->streams[i]->mode_changed)
1046                         continue;
1047
1048                 dc->hwss.apply_ctx_for_surface(
1049                                 dc, context->streams[i],
1050                                 context->stream_status[i].plane_count,
1051                                 context);
1052
1053                 /*
1054                  * enable stereo
1055                  * TODO rework dc_enable_stereo call to work with validation sets?
1056                  */
1057                 for (k = 0; k < MAX_PIPES; k++) {
1058                         pipe = &context->res_ctx.pipe_ctx[k];
1059
1060                         for (l = 0 ; pipe && l < context->stream_count; l++)  {
1061                                 if (context->streams[l] &&
1062                                         context->streams[l] == pipe->stream &&
1063                                         dc->hwss.setup_stereo)
1064                                         dc->hwss.setup_stereo(pipe, dc);
1065                         }
1066                 }
1067
1068                 CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}",
1069                                 context->streams[i]->timing.h_addressable,
1070                                 context->streams[i]->timing.v_addressable,
1071                                 context->streams[i]->timing.h_total,
1072                                 context->streams[i]->timing.v_total,
1073                                 context->streams[i]->timing.pix_clk_khz);
1074         }
1075
1076         dc_enable_stereo(dc, context, dc_streams, context->stream_count);
1077
1078         /* pplib is notified if disp_num changed */
1079         dc->hwss.optimize_bandwidth(dc, context);
1080
1081         dc_release_state(dc->current_state);
1082
1083         dc->current_state = context;
1084
1085         dc_retain_state(dc->current_state);
1086
1087         return result;
1088 }
1089
1090 bool dc_commit_state(struct dc *dc, struct dc_state *context)
1091 {
1092         enum dc_status result = DC_ERROR_UNEXPECTED;
1093         int i;
1094
1095         if (false == context_changed(dc, context))
1096                 return DC_OK;
1097
1098         DC_LOG_DC("%s: %d streams\n",
1099                                 __func__, context->stream_count);
1100
1101         for (i = 0; i < context->stream_count; i++) {
1102                 struct dc_stream_state *stream = context->streams[i];
1103
1104                 dc_stream_log(dc, stream);
1105         }
1106
1107         result = dc_commit_state_no_check(dc, context);
1108
1109         return (result == DC_OK);
1110 }
1111
1112 bool dc_post_update_surfaces_to_stream(struct dc *dc)
1113 {
1114         int i;
1115         struct dc_state *context = dc->current_state;
1116
1117         post_surface_trace(dc);
1118
1119         for (i = 0; i < dc->res_pool->pipe_count; i++)
1120                 if (context->res_ctx.pipe_ctx[i].stream == NULL ||
1121                     context->res_ctx.pipe_ctx[i].plane_state == NULL) {
1122                         context->res_ctx.pipe_ctx[i].pipe_idx = i;
1123                         dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
1124                 }
1125
1126         dc->optimized_required = false;
1127
1128         dc->hwss.optimize_bandwidth(dc, context);
1129         return true;
1130 }
1131
1132 struct dc_state *dc_create_state(void)
1133 {
1134         struct dc_state *context = kzalloc(sizeof(struct dc_state),
1135                                            GFP_KERNEL);
1136
1137         if (!context)
1138                 return NULL;
1139
1140         kref_init(&context->refcount);
1141         return context;
1142 }
1143
1144 void dc_retain_state(struct dc_state *context)
1145 {
1146         kref_get(&context->refcount);
1147 }
1148
1149 static void dc_state_free(struct kref *kref)
1150 {
1151         struct dc_state *context = container_of(kref, struct dc_state, refcount);
1152         dc_resource_state_destruct(context);
1153         kfree(context);
1154 }
1155
1156 void dc_release_state(struct dc_state *context)
1157 {
1158         kref_put(&context->refcount, dc_state_free);
1159 }
1160
1161 static bool is_surface_in_context(
1162                 const struct dc_state *context,
1163                 const struct dc_plane_state *plane_state)
1164 {
1165         int j;
1166
1167         for (j = 0; j < MAX_PIPES; j++) {
1168                 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1169
1170                 if (plane_state == pipe_ctx->plane_state) {
1171                         return true;
1172                 }
1173         }
1174
1175         return false;
1176 }
1177
1178 static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
1179 {
1180         union surface_update_flags *update_flags = &u->surface->update_flags;
1181
1182         if (!u->plane_info)
1183                 return UPDATE_TYPE_FAST;
1184
1185         if (u->plane_info->color_space != u->surface->color_space)
1186                 update_flags->bits.color_space_change = 1;
1187
1188         if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror)
1189                 update_flags->bits.horizontal_mirror_change = 1;
1190
1191         if (u->plane_info->rotation != u->surface->rotation)
1192                 update_flags->bits.rotation_change = 1;
1193
1194         if (u->plane_info->format != u->surface->format)
1195                 update_flags->bits.pixel_format_change = 1;
1196
1197         if (u->plane_info->stereo_format != u->surface->stereo_format)
1198                 update_flags->bits.stereo_format_change = 1;
1199
1200         if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha)
1201                 update_flags->bits.per_pixel_alpha_change = 1;
1202
1203         if (u->plane_info->global_alpha_value != u->surface->global_alpha_value)
1204                 update_flags->bits.global_alpha_change = 1;
1205
1206         if (u->plane_info->dcc.enable != u->surface->dcc.enable
1207                         || u->plane_info->dcc.grph.independent_64b_blks != u->surface->dcc.grph.independent_64b_blks
1208                         || u->plane_info->dcc.grph.meta_pitch != u->surface->dcc.grph.meta_pitch)
1209                 update_flags->bits.dcc_change = 1;
1210
1211         if (resource_pixel_format_to_bpp(u->plane_info->format) !=
1212                         resource_pixel_format_to_bpp(u->surface->format))
1213                 /* different bytes per element will require full bandwidth
1214                  * and DML calculation
1215                  */
1216                 update_flags->bits.bpp_change = 1;
1217
1218         if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
1219                         sizeof(union dc_tiling_info)) != 0) {
1220                 update_flags->bits.swizzle_change = 1;
1221                 /* todo: below are HW dependent, we should add a hook to
1222                  * DCE/N resource and validated there.
1223                  */
1224                 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR)
1225                         /* swizzled mode requires RQ to be setup properly,
1226                          * thus need to run DML to calculate RQ settings
1227                          */
1228                         update_flags->bits.bandwidth_change = 1;
1229         }
1230
1231         if (update_flags->bits.rotation_change
1232                         || update_flags->bits.stereo_format_change
1233                         || update_flags->bits.pixel_format_change
1234                         || update_flags->bits.bpp_change
1235                         || update_flags->bits.bandwidth_change
1236                         || update_flags->bits.output_tf_change)
1237                 return UPDATE_TYPE_FULL;
1238
1239         return UPDATE_TYPE_MED;
1240 }
1241
1242 static enum surface_update_type get_scaling_info_update_type(
1243                 const struct dc_surface_update *u)
1244 {
1245         union surface_update_flags *update_flags = &u->surface->update_flags;
1246
1247         if (!u->scaling_info)
1248                 return UPDATE_TYPE_FAST;
1249
1250         if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
1251                         || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
1252                         || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
1253                         || u->scaling_info->dst_rect.height != u->surface->dst_rect.height) {
1254                 update_flags->bits.scaling_change = 1;
1255
1256                 if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
1257                         || u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
1258                                 && (u->scaling_info->dst_rect.width < u->surface->src_rect.width
1259                                         || u->scaling_info->dst_rect.height < u->surface->src_rect.height))
1260                         /* Making dst rect smaller requires a bandwidth change */
1261                         update_flags->bits.bandwidth_change = 1;
1262         }
1263
1264         if (u->scaling_info->src_rect.width != u->surface->src_rect.width
1265                 || u->scaling_info->src_rect.height != u->surface->src_rect.height) {
1266
1267                 update_flags->bits.scaling_change = 1;
1268                 if (u->scaling_info->src_rect.width > u->surface->src_rect.width
1269                                 && u->scaling_info->src_rect.height > u->surface->src_rect.height)
1270                         /* Making src rect bigger requires a bandwidth change */
1271                         update_flags->bits.clock_change = 1;
1272         }
1273
1274         if (u->scaling_info->src_rect.x != u->surface->src_rect.x
1275                         || u->scaling_info->src_rect.y != u->surface->src_rect.y
1276                         || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
1277                         || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
1278                         || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
1279                         || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
1280                 update_flags->bits.position_change = 1;
1281
1282         if (update_flags->bits.clock_change
1283                         || update_flags->bits.bandwidth_change)
1284                 return UPDATE_TYPE_FULL;
1285
1286         if (update_flags->bits.scaling_change
1287                         || update_flags->bits.position_change)
1288                 return UPDATE_TYPE_MED;
1289
1290         return UPDATE_TYPE_FAST;
1291 }
1292
1293 static enum surface_update_type det_surface_update(const struct dc *dc,
1294                 const struct dc_surface_update *u)
1295 {
1296         const struct dc_state *context = dc->current_state;
1297         enum surface_update_type type;
1298         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1299         union surface_update_flags *update_flags = &u->surface->update_flags;
1300
1301         update_flags->raw = 0; // Reset all flags
1302
1303         if (!is_surface_in_context(context, u->surface)) {
1304                 update_flags->bits.new_plane = 1;
1305                 return UPDATE_TYPE_FULL;
1306         }
1307
1308         type = get_plane_info_update_type(u);
1309         elevate_update_type(&overall_type, type);
1310
1311         type = get_scaling_info_update_type(u);
1312         elevate_update_type(&overall_type, type);
1313
1314         if (u->in_transfer_func)
1315                 update_flags->bits.in_transfer_func_change = 1;
1316
1317         if (u->input_csc_color_matrix)
1318                 update_flags->bits.input_csc_change = 1;
1319
1320         if (u->coeff_reduction_factor)
1321                 update_flags->bits.coeff_reduction_change = 1;
1322
1323         if (u->gamma) {
1324                 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN;
1325
1326                 if (u->plane_info)
1327                         format = u->plane_info->format;
1328                 else if (u->surface)
1329                         format = u->surface->format;
1330
1331                 if (dce_use_lut(format))
1332                         update_flags->bits.gamma_change = 1;
1333         }
1334
1335         if (update_flags->bits.in_transfer_func_change) {
1336                 type = UPDATE_TYPE_MED;
1337                 elevate_update_type(&overall_type, type);
1338         }
1339
1340         if (update_flags->bits.input_csc_change
1341                         || update_flags->bits.coeff_reduction_change
1342                         || update_flags->bits.gamma_change) {
1343                 type = UPDATE_TYPE_FULL;
1344                 elevate_update_type(&overall_type, type);
1345         }
1346
1347         return overall_type;
1348 }
1349
1350 static enum surface_update_type check_update_surfaces_for_stream(
1351                 struct dc *dc,
1352                 struct dc_surface_update *updates,
1353                 int surface_count,
1354                 struct dc_stream_update *stream_update,
1355                 const struct dc_stream_status *stream_status)
1356 {
1357         int i;
1358         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1359
1360         if (stream_status == NULL || stream_status->plane_count != surface_count)
1361                 return UPDATE_TYPE_FULL;
1362
1363         /* some stream updates require passive update */
1364         if (stream_update) {
1365                 if ((stream_update->src.height != 0) &&
1366                                 (stream_update->src.width != 0))
1367                         return UPDATE_TYPE_FULL;
1368
1369                 if ((stream_update->dst.height != 0) &&
1370                                 (stream_update->dst.width != 0))
1371                         return UPDATE_TYPE_FULL;
1372
1373                 if (stream_update->out_transfer_func)
1374                         return UPDATE_TYPE_FULL;
1375
1376                 if (stream_update->abm_level)
1377                         return UPDATE_TYPE_FULL;
1378
1379                 if (stream_update->dpms_off)
1380                         return UPDATE_TYPE_FULL;
1381         }
1382
1383         for (i = 0 ; i < surface_count; i++) {
1384                 enum surface_update_type type =
1385                                 det_surface_update(dc, &updates[i]);
1386
1387                 if (type == UPDATE_TYPE_FULL)
1388                         return type;
1389
1390                 elevate_update_type(&overall_type, type);
1391         }
1392
1393         return overall_type;
1394 }
1395
1396 /**
1397  * dc_check_update_surfaces_for_stream() - Determine update type (fast, med, or full)
1398  *
1399  * See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types
1400  */
1401 enum surface_update_type dc_check_update_surfaces_for_stream(
1402                 struct dc *dc,
1403                 struct dc_surface_update *updates,
1404                 int surface_count,
1405                 struct dc_stream_update *stream_update,
1406                 const struct dc_stream_status *stream_status)
1407 {
1408         int i;
1409         enum surface_update_type type;
1410
1411         for (i = 0; i < surface_count; i++)
1412                 updates[i].surface->update_flags.raw = 0;
1413
1414         type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
1415         if (type == UPDATE_TYPE_FULL)
1416                 for (i = 0; i < surface_count; i++)
1417                         updates[i].surface->update_flags.raw = 0xFFFFFFFF;
1418
1419         return type;
1420 }
1421
1422 static struct dc_stream_status *stream_get_status(
1423         struct dc_state *ctx,
1424         struct dc_stream_state *stream)
1425 {
1426         uint8_t i;
1427
1428         for (i = 0; i < ctx->stream_count; i++) {
1429                 if (stream == ctx->streams[i]) {
1430                         return &ctx->stream_status[i];
1431                 }
1432         }
1433
1434         return NULL;
1435 }
1436
1437 static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
1438
1439 static void commit_planes_do_stream_update(struct dc *dc,
1440                 struct dc_stream_state *stream,
1441                 struct dc_stream_update *stream_update,
1442                 enum surface_update_type update_type,
1443                 struct dc_state *context)
1444 {
1445         int j;
1446
1447         // Stream updates
1448         for (j = 0; j < dc->res_pool->pipe_count; j++) {
1449                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1450
1451                 if (!pipe_ctx->top_pipe &&
1452                         pipe_ctx->stream &&
1453                         pipe_ctx->stream == stream) {
1454
1455                         /* Fast update*/
1456                         // VRR program can be done as part of FAST UPDATE
1457                         if (stream_update->adjust)
1458                                 dc->hwss.set_drr(&pipe_ctx, 1,
1459                                         stream_update->adjust->v_total_min,
1460                                         stream_update->adjust->v_total_max);
1461
1462                         if (stream_update->periodic_fn_vsync_delta &&
1463                                         pipe_ctx->stream_res.tg->funcs->program_vline_interrupt)
1464                                 pipe_ctx->stream_res.tg->funcs->program_vline_interrupt(
1465                                         pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing,
1466                                         pipe_ctx->stream->periodic_fn_vsync_delta);
1467
1468                         if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
1469                                         stream_update->vrr_infopacket ||
1470                                         stream_update->vsc_infopacket ||
1471                                         stream_update->vsp_infopacket) {
1472                                 resource_build_info_frame(pipe_ctx);
1473                                 dc->hwss.update_info_frame(pipe_ctx);
1474                         }
1475
1476                         if (stream_update->gamut_remap)
1477                                 dc_stream_set_gamut_remap(dc, stream);
1478
1479                         if (stream_update->output_csc_transform)
1480                                 dc_stream_program_csc_matrix(dc, stream);
1481
1482                         if (stream_update->dither_option) {
1483                                 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1484                                                                         &pipe_ctx->stream->bit_depth_params);
1485                                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
1486                                                 &stream->bit_depth_params,
1487                                                 &stream->clamping);
1488                         }
1489
1490                         /* Full fe update*/
1491                         if (update_type == UPDATE_TYPE_FAST)
1492                                 continue;
1493
1494                         if (stream_update->dpms_off) {
1495                                 if (*stream_update->dpms_off) {
1496                                         core_link_disable_stream(pipe_ctx, KEEP_ACQUIRED_RESOURCE);
1497                                         dc->hwss.optimize_bandwidth(dc, dc->current_state);
1498                                 } else {
1499                                         dc->hwss.prepare_bandwidth(dc, dc->current_state);
1500                                         core_link_enable_stream(dc->current_state, pipe_ctx);
1501                                 }
1502                         }
1503
1504                         if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
1505                                 if (pipe_ctx->stream_res.tg->funcs->is_blanked) {
1506                                         // if otg funcs defined check if blanked before programming
1507                                         if (!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
1508                                                 pipe_ctx->stream_res.abm->funcs->set_abm_level(
1509                                                         pipe_ctx->stream_res.abm, stream->abm_level);
1510                                 } else
1511                                         pipe_ctx->stream_res.abm->funcs->set_abm_level(
1512                                                 pipe_ctx->stream_res.abm, stream->abm_level);
1513                         }
1514                 }
1515         }
1516 }
1517
1518 static void commit_planes_for_stream(struct dc *dc,
1519                 struct dc_surface_update *srf_updates,
1520                 int surface_count,
1521                 struct dc_stream_state *stream,
1522                 struct dc_stream_update *stream_update,
1523                 enum surface_update_type update_type,
1524                 struct dc_state *context)
1525 {
1526         int i, j;
1527         struct pipe_ctx *top_pipe_to_program = NULL;
1528
1529         if (update_type == UPDATE_TYPE_FULL) {
1530                 dc->hwss.prepare_bandwidth(dc, context);
1531                 context_clock_trace(dc, context);
1532         }
1533
1534         // Stream updates
1535         if (stream_update)
1536                 commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
1537
1538         if (surface_count == 0) {
1539                 /*
1540                  * In case of turning off screen, no need to program front end a second time.
1541                  * just return after program blank.
1542                  */
1543                 dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
1544                 return;
1545         }
1546
1547         // Update Type FULL, Surface updates
1548         for (j = 0; j < dc->res_pool->pipe_count; j++) {
1549                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1550
1551                 if (!pipe_ctx->top_pipe &&
1552                         pipe_ctx->stream &&
1553                         pipe_ctx->stream == stream) {
1554                         struct dc_stream_status *stream_status = NULL;
1555
1556                         top_pipe_to_program = pipe_ctx;
1557
1558                         if (!pipe_ctx->plane_state)
1559                                 continue;
1560
1561                         /* Full fe update*/
1562                         if (update_type == UPDATE_TYPE_FAST)
1563                                 continue;
1564
1565                         stream_status =
1566                                 stream_get_status(context, pipe_ctx->stream);
1567
1568                         dc->hwss.apply_ctx_for_surface(
1569                                         dc, pipe_ctx->stream, stream_status->plane_count, context);
1570                 }
1571         }
1572
1573         // Update Type FAST, Surface updates
1574         if (update_type == UPDATE_TYPE_FAST) {
1575                 /* Lock the top pipe while updating plane addrs, since freesync requires
1576                  *  plane addr update event triggers to be synchronized.
1577                  *  top_pipe_to_program is expected to never be NULL
1578                  */
1579                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
1580
1581                 /* Perform requested Updates */
1582                 for (i = 0; i < surface_count; i++) {
1583                         struct dc_plane_state *plane_state = srf_updates[i].surface;
1584
1585                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
1586                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1587
1588                                 if (pipe_ctx->stream != stream)
1589                                         continue;
1590
1591                                 if (pipe_ctx->plane_state != plane_state)
1592                                         continue;
1593
1594                                 if (srf_updates[i].flip_addr)
1595                                         dc->hwss.update_plane_addr(dc, pipe_ctx);
1596                         }
1597                 }
1598
1599                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
1600         }
1601 }
1602
1603 void dc_commit_updates_for_stream(struct dc *dc,
1604                 struct dc_surface_update *srf_updates,
1605                 int surface_count,
1606                 struct dc_stream_state *stream,
1607                 struct dc_stream_update *stream_update,
1608                 struct dc_plane_state **plane_states,
1609                 struct dc_state *state)
1610 {
1611         const struct dc_stream_status *stream_status;
1612         enum surface_update_type update_type;
1613         struct dc_state *context;
1614         struct dc_context *dc_ctx = dc->ctx;
1615         int i, j;
1616
1617         stream_status = dc_stream_get_status(stream);
1618         context = dc->current_state;
1619
1620         update_type = dc_check_update_surfaces_for_stream(
1621                                 dc, srf_updates, surface_count, stream_update, stream_status);
1622
1623         if (update_type >= update_surface_trace_level)
1624                 update_surface_trace(dc, srf_updates, surface_count);
1625
1626
1627         if (update_type >= UPDATE_TYPE_FULL) {
1628
1629                 /* initialize scratch memory for building context */
1630                 context = dc_create_state();
1631                 if (context == NULL) {
1632                         DC_ERROR("Failed to allocate new validate context!\n");
1633                         return;
1634                 }
1635
1636                 dc_resource_state_copy_construct(state, context);
1637         }
1638
1639
1640         for (i = 0; i < surface_count; i++) {
1641                 struct dc_plane_state *surface = srf_updates[i].surface;
1642
1643                 /* TODO: On flip we don't build the state, so it still has the
1644                  * old address. Which is why we are updating the address here
1645                  */
1646                 if (srf_updates[i].flip_addr) {
1647                         surface->address = srf_updates[i].flip_addr->address;
1648                         surface->flip_immediate = srf_updates[i].flip_addr->flip_immediate;
1649
1650                 }
1651
1652                 if (update_type >= UPDATE_TYPE_MED) {
1653                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
1654                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1655
1656                                 if (pipe_ctx->plane_state != surface)
1657                                         continue;
1658
1659                                 resource_build_scaling_params(pipe_ctx);
1660                         }
1661                 }
1662         }
1663
1664         commit_planes_for_stream(
1665                                 dc,
1666                                 srf_updates,
1667                                 surface_count,
1668                                 stream,
1669                                 stream_update,
1670                                 update_type,
1671                                 context);
1672         /*update current_State*/
1673         if (dc->current_state != context) {
1674
1675                 struct dc_state *old = dc->current_state;
1676
1677                 dc->current_state = context;
1678                 dc_release_state(old);
1679
1680         }
1681         /*let's use current_state to update watermark etc*/
1682         if (update_type >= UPDATE_TYPE_FULL)
1683                 dc_post_update_surfaces_to_stream(dc);
1684
1685         return;
1686
1687 }
1688
1689 uint8_t dc_get_current_stream_count(struct dc *dc)
1690 {
1691         return dc->current_state->stream_count;
1692 }
1693
1694 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
1695 {
1696         if (i < dc->current_state->stream_count)
1697                 return dc->current_state->streams[i];
1698         return NULL;
1699 }
1700
1701 enum dc_irq_source dc_interrupt_to_irq_source(
1702                 struct dc *dc,
1703                 uint32_t src_id,
1704                 uint32_t ext_id)
1705 {
1706         return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
1707 }
1708
1709 /**
1710  * dc_interrupt_set() - Enable/disable an AMD hw interrupt source
1711  */
1712 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
1713 {
1714
1715         if (dc == NULL)
1716                 return false;
1717
1718         return dal_irq_service_set(dc->res_pool->irqs, src, enable);
1719 }
1720
1721 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
1722 {
1723         dal_irq_service_ack(dc->res_pool->irqs, src);
1724 }
1725
1726 void dc_set_power_state(
1727         struct dc *dc,
1728         enum dc_acpi_cm_power_state power_state)
1729 {
1730         struct kref refcount;
1731
1732         switch (power_state) {
1733         case DC_ACPI_CM_POWER_STATE_D0:
1734                 dc_resource_state_construct(dc, dc->current_state);
1735
1736                 dc->hwss.init_hw(dc);
1737                 break;
1738         default:
1739                 ASSERT(dc->current_state->stream_count == 0);
1740                 /* Zero out the current context so that on resume we start with
1741                  * clean state, and dc hw programming optimizations will not
1742                  * cause any trouble.
1743                  */
1744
1745                 /* Preserve refcount */
1746                 refcount = dc->current_state->refcount;
1747                 dc_resource_state_destruct(dc->current_state);
1748                 memset(dc->current_state, 0,
1749                                 sizeof(*dc->current_state));
1750
1751                 dc->current_state->refcount = refcount;
1752
1753                 break;
1754         }
1755
1756 }
1757
1758 void dc_resume(struct dc *dc)
1759 {
1760
1761         uint32_t i;
1762
1763         for (i = 0; i < dc->link_count; i++)
1764                 core_link_resume(dc->links[i]);
1765 }
1766
1767 bool dc_is_dmcu_initialized(struct dc *dc)
1768 {
1769         struct dmcu *dmcu = dc->res_pool->dmcu;
1770
1771         if (dmcu)
1772                 return dmcu->funcs->is_dmcu_initialized(dmcu);
1773         return false;
1774 }
1775
1776 bool dc_submit_i2c(
1777                 struct dc *dc,
1778                 uint32_t link_index,
1779                 struct i2c_command *cmd)
1780 {
1781
1782         struct dc_link *link = dc->links[link_index];
1783         struct ddc_service *ddc = link->ddc;
1784         return dce_i2c_submit_command(
1785                 dc->res_pool,
1786                 ddc->ddc_pin,
1787                 cmd);
1788 }
1789
1790 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
1791 {
1792         if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
1793                 BREAK_TO_DEBUGGER();
1794                 return false;
1795         }
1796
1797         dc_sink_retain(sink);
1798
1799         dc_link->remote_sinks[dc_link->sink_count] = sink;
1800         dc_link->sink_count++;
1801
1802         return true;
1803 }
1804
1805 /**
1806  * dc_link_add_remote_sink() - Create a sink and attach it to an existing link
1807  *
1808  * EDID length is in bytes
1809  */
1810 struct dc_sink *dc_link_add_remote_sink(
1811                 struct dc_link *link,
1812                 const uint8_t *edid,
1813                 int len,
1814                 struct dc_sink_init_data *init_data)
1815 {
1816         struct dc_sink *dc_sink;
1817         enum dc_edid_status edid_status;
1818
1819         if (len > DC_MAX_EDID_BUFFER_SIZE) {
1820                 dm_error("Max EDID buffer size breached!\n");
1821                 return NULL;
1822         }
1823
1824         if (!init_data) {
1825                 BREAK_TO_DEBUGGER();
1826                 return NULL;
1827         }
1828
1829         if (!init_data->link) {
1830                 BREAK_TO_DEBUGGER();
1831                 return NULL;
1832         }
1833
1834         dc_sink = dc_sink_create(init_data);
1835
1836         if (!dc_sink)
1837                 return NULL;
1838
1839         memmove(dc_sink->dc_edid.raw_edid, edid, len);
1840         dc_sink->dc_edid.length = len;
1841
1842         if (!link_add_remote_sink_helper(
1843                         link,
1844                         dc_sink))
1845                 goto fail_add_sink;
1846
1847         edid_status = dm_helpers_parse_edid_caps(
1848                         link->ctx,
1849                         &dc_sink->dc_edid,
1850                         &dc_sink->edid_caps);
1851
1852         /*
1853          * Treat device as no EDID device if EDID
1854          * parsing fails
1855          */
1856         if (edid_status != EDID_OK) {
1857                 dc_sink->dc_edid.length = 0;
1858                 dm_error("Bad EDID, status%d!\n", edid_status);
1859         }
1860
1861         return dc_sink;
1862
1863 fail_add_sink:
1864         dc_sink_release(dc_sink);
1865         return NULL;
1866 }
1867
1868 /**
1869  * dc_link_remove_remote_sink() - Remove a remote sink from a dc_link
1870  *
1871  * Note that this just removes the struct dc_sink - it doesn't
1872  * program hardware or alter other members of dc_link
1873  */
1874 void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
1875 {
1876         int i;
1877
1878         if (!link->sink_count) {
1879                 BREAK_TO_DEBUGGER();
1880                 return;
1881         }
1882
1883         for (i = 0; i < link->sink_count; i++) {
1884                 if (link->remote_sinks[i] == sink) {
1885                         dc_sink_release(sink);
1886                         link->remote_sinks[i] = NULL;
1887
1888                         /* shrink array to remove empty place */
1889                         while (i < link->sink_count - 1) {
1890                                 link->remote_sinks[i] = link->remote_sinks[i+1];
1891                                 i++;
1892                         }
1893                         link->remote_sinks[i] = NULL;
1894                         link->sink_count--;
1895                         return;
1896                 }
1897         }
1898 }
1899
1900 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
1901 {
1902         info->displayClock                              = (unsigned int)state->bw.dcn.clk.dispclk_khz;
1903         info->engineClock                               = (unsigned int)state->bw.dcn.clk.dcfclk_khz;
1904         info->memoryClock                               = (unsigned int)state->bw.dcn.clk.dramclk_khz;
1905         info->maxSupportedDppClock              = (unsigned int)state->bw.dcn.clk.max_supported_dppclk_khz;
1906         info->dppClock                                  = (unsigned int)state->bw.dcn.clk.dppclk_khz;
1907         info->socClock                                  = (unsigned int)state->bw.dcn.clk.socclk_khz;
1908         info->dcfClockDeepSleep                 = (unsigned int)state->bw.dcn.clk.dcfclk_deep_sleep_khz;
1909         info->fClock                                    = (unsigned int)state->bw.dcn.clk.fclk_khz;
1910         info->phyClock                                  = (unsigned int)state->bw.dcn.clk.phyclk_khz;
1911 }