drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "dcn_calcs.h"
  28 #include "dcn_calc_auto.h"
  29 #include "dc.h"
  30 #include "dal_asic_id.h"
  31
  32 #include "resource.h"
  33 #include "dcn10/dcn10_resource.h"
  34 #include "dcn10/dcn10_hubbub.h"
  35
  36 #include "dcn_calc_math.h"
  37
  38 #define DC_LOGGER \
  39         dc->ctx->logger
  40
  41 #define WM_SET_COUNT 4
  42 #define WM_A 0
  43 #define WM_B 1
  44 #define WM_C 2
  45 #define WM_D 3
  46
  47 /*
  48  * NOTE:
  49  *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
  50  *
  51  * It doesn't adhere to Linux kernel style and sometimes will do things in odd
  52  * ways. Unless there is something clearly wrong with it the code should
  53  * remain as-is as it provides us with a guarantee from HW that it is correct.
  54  */
  55
  56 /* Defaults from spreadsheet rev#247 */
  57 const struct dcn_soc_bounding_box dcn10_soc_defaults = {
  58                 /* latencies */
  59                 .sr_exit_time = 17, /*us*/
  60                 .sr_enter_plus_exit_time = 19, /*us*/
  61                 .urgent_latency = 4, /*us*/
  62                 .dram_clock_change_latency = 17, /*us*/
  63                 .write_back_latency = 12, /*us*/
  64                 .percent_of_ideal_drambw_received_after_urg_latency = 80, /*%*/
  65
  66                 /* below default clocks derived from STA target base on
  67                  * slow-slow corner + 10% margin with voltages aligned to FCLK.
  68                  *
  69                  * Use these value if fused value doesn't make sense as earlier
  70                  * part don't have correct value fused */
  71                 /* default DCF CLK DPM on RV*/
  72                 .dcfclkv_max0p9 = 655,  /* MHz, = 3600/5.5 */
  73                 .dcfclkv_nom0p8 = 626,  /* MHz, = 3600/5.75 */
  74                 .dcfclkv_mid0p72 = 600, /* MHz, = 3600/6, bypass */
  75                 .dcfclkv_min0p65 = 300, /* MHz, = 3600/12, bypass */
  76
  77                 /* default DISP CLK voltage state on RV */
  78                 .max_dispclk_vmax0p9 = 1108,    /* MHz, = 3600/3.25 */
  79                 .max_dispclk_vnom0p8 = 1029,    /* MHz, = 3600/3.5 */
  80                 .max_dispclk_vmid0p72 = 960,    /* MHz, = 3600/3.75 */
  81                 .max_dispclk_vmin0p65 = 626,    /* MHz, = 3600/5.75 */
  82
  83                 /* default DPP CLK voltage state on RV */
  84                 .max_dppclk_vmax0p9 = 720,      /* MHz, = 3600/5 */
  85                 .max_dppclk_vnom0p8 = 686,      /* MHz, = 3600/5.25 */
  86                 .max_dppclk_vmid0p72 = 626,     /* MHz, = 3600/5.75 */
  87                 .max_dppclk_vmin0p65 = 400,     /* MHz, = 3600/9 */
  88
  89                 /* default PHY CLK voltage state on RV */
  90                 .phyclkv_max0p9 = 900, /*MHz*/
  91                 .phyclkv_nom0p8 = 847, /*MHz*/
  92                 .phyclkv_mid0p72 = 800, /*MHz*/
  93                 .phyclkv_min0p65 = 600, /*MHz*/
  94
  95                 /* BW depend on FCLK, MCLK, # of channels */
  96                 /* dual channel BW */
  97                 .fabric_and_dram_bandwidth_vmax0p9 = 38.4f, /*GB/s*/
  98                 .fabric_and_dram_bandwidth_vnom0p8 = 34.133f, /*GB/s*/
  99                 .fabric_and_dram_bandwidth_vmid0p72 = 29.866f, /*GB/s*/
 100                 .fabric_and_dram_bandwidth_vmin0p65 = 12.8f, /*GB/s*/
 101                 /* single channel BW
 102                 .fabric_and_dram_bandwidth_vmax0p9 = 19.2f,
 103                 .fabric_and_dram_bandwidth_vnom0p8 = 17.066f,
 104                 .fabric_and_dram_bandwidth_vmid0p72 = 14.933f,
 105                 .fabric_and_dram_bandwidth_vmin0p65 = 12.8f,
 106                 */
 107
 108                 .number_of_channels = 2,
 109
 110                 .socclk = 208, /*MHz*/
 111                 .downspreading = 0.5f, /*%*/
 112                 .round_trip_ping_latency_cycles = 128, /*DCFCLK Cycles*/
 113                 .urgent_out_of_order_return_per_channel = 256, /*bytes*/
 114                 .vmm_page_size = 4096, /*bytes*/
 115                 .return_bus_width = 64, /*bytes*/
 116                 .max_request_size = 256, /*bytes*/
 117
 118                 /* Depends on user class (client vs embedded, workstation, etc) */
 119                 .percent_disp_bw_limit = 0.3f /*%*/
 120 };
 121
 122 const struct dcn_ip_params dcn10_ip_defaults = {
 123                 .rob_buffer_size_in_kbyte = 64,
 124                 .det_buffer_size_in_kbyte = 164,
 125                 .dpp_output_buffer_pixels = 2560,
 126                 .opp_output_buffer_lines = 1,
 127                 .pixel_chunk_size_in_kbyte = 8,
 128                 .pte_enable = dcn_bw_yes,
 129                 .pte_chunk_size = 2, /*kbytes*/
 130                 .meta_chunk_size = 2, /*kbytes*/
 131                 .writeback_chunk_size = 2, /*kbytes*/
 132                 .odm_capability = dcn_bw_no,
 133                 .dsc_capability = dcn_bw_no,
 134                 .line_buffer_size = 589824, /*bit*/
 135                 .max_line_buffer_lines = 12,
 136                 .is_line_buffer_bpp_fixed = dcn_bw_no,
 137                 .line_buffer_fixed_bpp = dcn_bw_na,
 138                 .writeback_luma_buffer_size = 12, /*kbytes*/
 139                 .writeback_chroma_buffer_size = 8, /*kbytes*/
 140                 .max_num_dpp = 4,
 141                 .max_num_writeback = 2,
 142                 .max_dchub_topscl_throughput = 4, /*pixels/dppclk*/
 143                 .max_pscl_tolb_throughput = 2, /*pixels/dppclk*/
 144                 .max_lb_tovscl_throughput = 4, /*pixels/dppclk*/
 145                 .max_vscl_tohscl_throughput = 4, /*pixels/dppclk*/
 146                 .max_hscl_ratio = 4,
 147                 .max_vscl_ratio = 4,
 148                 .max_hscl_taps = 8,
 149                 .max_vscl_taps = 8,
 150                 .pte_buffer_size_in_requests = 42,
 151                 .dispclk_ramping_margin = 1, /*%*/
 152                 .under_scan_factor = 1.11f,
 153                 .max_inter_dcn_tile_repeaters = 8,
 154                 .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = dcn_bw_no,
 155                 .bug_forcing_luma_and_chroma_request_to_same_size_fixed = dcn_bw_no,
 156                 .dcfclk_cstate_latency = 10 /*TODO clone of something else? sr_enter_plus_exit_time?*/
 157 };
 158
 159 static enum dcn_bw_defs tl_sw_mode_to_bw_defs(enum swizzle_mode_values sw_mode)
 160 {
 161         switch (sw_mode) {
 162         case DC_SW_LINEAR:
 163                 return dcn_bw_sw_linear;
 164         case DC_SW_4KB_S:
 165                 return dcn_bw_sw_4_kb_s;
 166         case DC_SW_4KB_D:
 167                 return dcn_bw_sw_4_kb_d;
 168         case DC_SW_64KB_S:
 169                 return dcn_bw_sw_64_kb_s;
 170         case DC_SW_64KB_D:
 171                 return dcn_bw_sw_64_kb_d;
 172         case DC_SW_VAR_S:
 173                 return dcn_bw_sw_var_s;
 174         case DC_SW_VAR_D:
 175                 return dcn_bw_sw_var_d;
 176         case DC_SW_64KB_S_T:
 177                 return dcn_bw_sw_64_kb_s_t;
 178         case DC_SW_64KB_D_T:
 179                 return dcn_bw_sw_64_kb_d_t;
 180         case DC_SW_4KB_S_X:
 181                 return dcn_bw_sw_4_kb_s_x;
 182         case DC_SW_4KB_D_X:
 183                 return dcn_bw_sw_4_kb_d_x;
 184         case DC_SW_64KB_S_X:
 185                 return dcn_bw_sw_64_kb_s_x;
 186         case DC_SW_64KB_D_X:
 187                 return dcn_bw_sw_64_kb_d_x;
 188         case DC_SW_VAR_S_X:
 189                 return dcn_bw_sw_var_s_x;
 190         case DC_SW_VAR_D_X:
 191                 return dcn_bw_sw_var_d_x;
 192         case DC_SW_256B_S:
 193         case DC_SW_256_D:
 194         case DC_SW_256_R:
 195         case DC_SW_4KB_R:
 196         case DC_SW_64KB_R:
 197         case DC_SW_VAR_R:
 198         case DC_SW_4KB_R_X:
 199         case DC_SW_64KB_R_X:
 200         case DC_SW_VAR_R_X:
 201         default:
 202                 BREAK_TO_DEBUGGER(); /*not in formula*/
 203                 return dcn_bw_sw_4_kb_s;
 204         }
 205 }
 206
 207 static int tl_lb_bpp_to_int(enum lb_pixel_depth depth)
 208 {
 209         switch (depth) {
 210         case LB_PIXEL_DEPTH_18BPP:
 211                 return 18;
 212         case LB_PIXEL_DEPTH_24BPP:
 213                 return 24;
 214         case LB_PIXEL_DEPTH_30BPP:
 215                 return 30;
 216         case LB_PIXEL_DEPTH_36BPP:
 217                 return 36;
 218         default:
 219                 return 30;
 220         }
 221 }
 222
 223 static enum dcn_bw_defs tl_pixel_format_to_bw_defs(enum surface_pixel_format format)
 224 {
 225         switch (format) {
 226         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
 227         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 228                 return dcn_bw_rgb_sub_16;
 229         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 230         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 231         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 232         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 233         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
 234                 return dcn_bw_rgb_sub_32;
 235         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 236         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 237         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 238                 return dcn_bw_rgb_sub_64;
 239         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
 240         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
 241                 return dcn_bw_yuv420_sub_8;
 242         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
 243         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
 244                 return dcn_bw_yuv420_sub_10;
 245         default:
 246                 return dcn_bw_rgb_sub_32;
 247         }
 248 }
 249
 250 static void pipe_ctx_to_e2e_pipe_params (
 251                 const struct pipe_ctx *pipe,
 252                 struct _vcs_dpi_display_pipe_params_st *input)
 253 {
 254         input->src.is_hsplit = false;
 255         if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state)
 256                 input->src.is_hsplit = true;
 257         else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state)
 258                 input->src.is_hsplit = true;
 259
 260         if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) {
 261                 /*
 262                  * this method requires us to always re-calculate watermark when dcc change
 263                  * between flip.
 264                  */
 265                 input->src.dcc = pipe->plane_state->dcc.enable ? 1 : 0;
 266         } else {
 267                 /*
 268                  * allow us to disable dcc on the fly without re-calculating WM
 269                  *
 270                  * extra overhead for DCC is quite small.  for 1080p WM without
 271                  * DCC is only 0.417us lower (urgent goes from 6.979us to 6.562us)
 272                  */
 273                 unsigned int bpe;
 274
 275                 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs->
 276                         dcc_support_pixel_format(pipe->plane_state->format, &bpe) ? 1 : 0;
 277         }
 278         input->src.dcc_rate            = 1;
 279         input->src.meta_pitch          = pipe->plane_state->dcc.grph.meta_pitch;
 280         input->src.source_scan         = dm_horz;
 281         input->src.sw_mode             = pipe->plane_state->tiling_info.gfx9.swizzle;
 282
 283         input->src.viewport_width      = pipe->plane_res.scl_data.viewport.width;
 284         input->src.viewport_height     = pipe->plane_res.scl_data.viewport.height;
 285         input->src.data_pitch          = pipe->plane_res.scl_data.viewport.width;
 286         input->src.data_pitch_c        = pipe->plane_res.scl_data.viewport.width;
 287         input->src.cur0_src_width      = 128; /* TODO: Cursor calcs, not curently stored */
 288         input->src.cur0_bpp            = 32;
 289
 290         switch (pipe->plane_state->tiling_info.gfx9.swizzle) {
 291         /* for 4/8/16 high tiles */
 292         case DC_SW_LINEAR:
 293                 input->src.macro_tile_size = dm_4k_tile;
 294                 break;
 295         case DC_SW_4KB_S:
 296         case DC_SW_4KB_S_X:
 297                 input->src.macro_tile_size = dm_4k_tile;
 298                 break;
 299         case DC_SW_64KB_S:
 300         case DC_SW_64KB_S_X:
 301         case DC_SW_64KB_S_T:
 302                 input->src.macro_tile_size = dm_64k_tile;
 303                 break;
 304         case DC_SW_VAR_S:
 305         case DC_SW_VAR_S_X:
 306                 input->src.macro_tile_size = dm_256k_tile;
 307                 break;
 308
 309         /* For 64bpp 2 high tiles */
 310         case DC_SW_4KB_D:
 311         case DC_SW_4KB_D_X:
 312                 input->src.macro_tile_size = dm_4k_tile;
 313                 break;
 314         case DC_SW_64KB_D:
 315         case DC_SW_64KB_D_X:
 316         case DC_SW_64KB_D_T:
 317                 input->src.macro_tile_size = dm_64k_tile;
 318                 break;
 319         case DC_SW_VAR_D:
 320         case DC_SW_VAR_D_X:
 321                 input->src.macro_tile_size = dm_256k_tile;
 322                 break;
 323
 324         /* Unsupported swizzle modes for dcn */
 325         case DC_SW_256B_S:
 326         default:
 327                 ASSERT(0); /* Not supported */
 328                 break;
 329         }
 330
 331         switch (pipe->plane_state->rotation) {
 332         case ROTATION_ANGLE_0:
 333         case ROTATION_ANGLE_180:
 334                 input->src.source_scan = dm_horz;
 335                 break;
 336         case ROTATION_ANGLE_90:
 337         case ROTATION_ANGLE_270:
 338                 input->src.source_scan = dm_vert;
 339                 break;
 340         default:
 341                 ASSERT(0); /* Not supported */
 342                 break;
 343         }
 344
 345         /* TODO: Fix pixel format mappings */
 346         switch (pipe->plane_state->format) {
 347         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
 348         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
 349                 input->src.source_format = dm_420_8;
 350                 input->src.viewport_width_c    = input->src.viewport_width / 2;
 351                 input->src.viewport_height_c   = input->src.viewport_height / 2;
 352                 break;
 353         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
 354         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
 355                 input->src.source_format = dm_420_10;
 356                 input->src.viewport_width_c    = input->src.viewport_width / 2;
 357                 input->src.viewport_height_c   = input->src.viewport_height / 2;
 358                 break;
 359         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 360         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 361         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 362                 input->src.source_format = dm_444_64;
 363                 input->src.viewport_width_c    = input->src.viewport_width;
 364                 input->src.viewport_height_c   = input->src.viewport_height;
 365                 break;
 366         default:
 367                 input->src.source_format = dm_444_32;
 368                 input->src.viewport_width_c    = input->src.viewport_width;
 369                 input->src.viewport_height_c   = input->src.viewport_height;
 370                 break;
 371         }
 372
 373         input->scale_taps.htaps                = pipe->plane_res.scl_data.taps.h_taps;
 374         input->scale_ratio_depth.hscl_ratio    = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0;
 375         input->scale_ratio_depth.vscl_ratio    = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0;
 376         input->scale_ratio_depth.vinit =  pipe->plane_res.scl_data.inits.v.value/4294967296.0;
 377         if (input->scale_ratio_depth.vinit < 1.0)
 378                         input->scale_ratio_depth.vinit = 1;
 379         input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps;
 380         input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c;
 381         input->scale_taps.htaps_c              = pipe->plane_res.scl_data.taps.h_taps_c;
 382         input->scale_ratio_depth.hscl_ratio_c  = pipe->plane_res.scl_data.ratios.horz_c.value/4294967296.0;
 383         input->scale_ratio_depth.vscl_ratio_c  = pipe->plane_res.scl_data.ratios.vert_c.value/4294967296.0;
 384         input->scale_ratio_depth.vinit_c       = pipe->plane_res.scl_data.inits.v_c.value/4294967296.0;
 385         if (input->scale_ratio_depth.vinit_c < 1.0)
 386                         input->scale_ratio_depth.vinit_c = 1;
 387         switch (pipe->plane_res.scl_data.lb_params.depth) {
 388         case LB_PIXEL_DEPTH_30BPP:
 389                 input->scale_ratio_depth.lb_depth = 30; break;
 390         case LB_PIXEL_DEPTH_36BPP:
 391                 input->scale_ratio_depth.lb_depth = 36; break;
 392         default:
 393                 input->scale_ratio_depth.lb_depth = 24; break;
 394         }
 395
 396
 397         input->dest.vactive        = pipe->stream->timing.v_addressable + pipe->stream->timing.v_border_top
 398                         + pipe->stream->timing.v_border_bottom;
 399
 400         input->dest.recout_width   = pipe->plane_res.scl_data.recout.width;
 401         input->dest.recout_height  = pipe->plane_res.scl_data.recout.height;
 402
 403         input->dest.full_recout_width   = pipe->plane_res.scl_data.recout.width;
 404         input->dest.full_recout_height  = pipe->plane_res.scl_data.recout.height;
 405
 406         input->dest.htotal         = pipe->stream->timing.h_total;
 407         input->dest.hblank_start   = input->dest.htotal - pipe->stream->timing.h_front_porch;
 408         input->dest.hblank_end     = input->dest.hblank_start
 409                         - pipe->stream->timing.h_addressable
 410                         - pipe->stream->timing.h_border_left
 411                         - pipe->stream->timing.h_border_right;
 412
 413         input->dest.vtotal         = pipe->stream->timing.v_total;
 414         input->dest.vblank_start   = input->dest.vtotal - pipe->stream->timing.v_front_porch;
 415         input->dest.vblank_end     = input->dest.vblank_start
 416                         - pipe->stream->timing.v_addressable
 417                         - pipe->stream->timing.v_border_bottom
 418                         - pipe->stream->timing.v_border_top;
 419         input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_100hz/10000.0;
 420         input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start;
 421         input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
 422         input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
 423         input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width;
 424
 425 }
 426
 427 static void dcn_bw_calc_rq_dlg_ttu(
 428                 const struct dc *dc,
 429                 const struct dcn_bw_internal_vars *v,
 430                 struct pipe_ctx *pipe,
 431                 int in_idx)
 432 {
 433         struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml);
 434         struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &pipe->dlg_regs;
 435         struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &pipe->ttu_regs;
 436         struct _vcs_dpi_display_rq_regs_st *rq_regs = &pipe->rq_regs;
 437         struct _vcs_dpi_display_rq_params_st rq_param = {0};
 438         struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param = {0};
 439         struct _vcs_dpi_display_e2e_pipe_params_st input = { { { 0 } } };
 440         float total_active_bw = 0;
 441         float total_prefetch_bw = 0;
 442         int total_flip_bytes = 0;
 443         int i;
 444
 445         memset(dlg_regs, 0, sizeof(*dlg_regs));
 446         memset(ttu_regs, 0, sizeof(*ttu_regs));
 447         memset(rq_regs, 0, sizeof(*rq_regs));
 448
 449         for (i = 0; i < number_of_planes; i++) {
 450                 total_active_bw += v->read_bandwidth[i];
 451                 total_prefetch_bw += v->prefetch_bandwidth[i];
 452                 total_flip_bytes += v->total_immediate_flip_bytes[i];
 453         }
 454         dlg_sys_param.total_flip_bw = v->return_bw - dcn_bw_max2(total_active_bw, total_prefetch_bw);
 455         if (dlg_sys_param.total_flip_bw < 0.0)
 456                 dlg_sys_param.total_flip_bw = 0;
 457
 458         dlg_sys_param.t_mclk_wm_us = v->dram_clock_change_watermark;
 459         dlg_sys_param.t_sr_wm_us = v->stutter_enter_plus_exit_watermark;
 460         dlg_sys_param.t_urg_wm_us = v->urgent_watermark;
 461         dlg_sys_param.t_extra_us = v->urgent_extra_latency;
 462         dlg_sys_param.deepsleep_dcfclk_mhz = v->dcf_clk_deep_sleep;
 463         dlg_sys_param.total_flip_bytes = total_flip_bytes;
 464
 465         pipe_ctx_to_e2e_pipe_params(pipe, &input.pipe);
 466         input.clks_cfg.dcfclk_mhz = v->dcfclk;
 467         input.clks_cfg.dispclk_mhz = v->dispclk;
 468         input.clks_cfg.dppclk_mhz = v->dppclk;
 469         input.clks_cfg.refclk_mhz = dc->res_pool->ref_clock_inKhz / 1000.0;
 470         input.clks_cfg.socclk_mhz = v->socclk;
 471         input.clks_cfg.voltage = v->voltage_level;
 472 //      dc->dml.logger = pool->base.logger;
 473         input.dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444;
 474         input.dout.output_type  = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp;
 475         //input[in_idx].dout.output_standard;
 476
 477         /*todo: soc->sr_enter_plus_exit_time??*/
 478         dlg_sys_param.t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep;
 479
 480         dml1_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src);
 481         dml1_extract_rq_regs(dml, rq_regs, rq_param);
 482         dml1_rq_dlg_get_dlg_params(
 483                         dml,
 484                         dlg_regs,
 485                         ttu_regs,
 486                         rq_param.dlg,
 487                         dlg_sys_param,
 488                         input,
 489                         true,
 490                         true,
 491                         v->pte_enable == dcn_bw_yes,
 492                         pipe->plane_state->flip_immediate);
 493 }
 494
 495 static void split_stream_across_pipes(
 496                 struct resource_context *res_ctx,
 497                 const struct resource_pool *pool,
 498                 struct pipe_ctx *primary_pipe,
 499                 struct pipe_ctx *secondary_pipe)
 500 {
 501         int pipe_idx = secondary_pipe->pipe_idx;
 502
 503         if (!primary_pipe->plane_state)
 504                 return;
 505
 506         *secondary_pipe = *primary_pipe;
 507
 508         secondary_pipe->pipe_idx = pipe_idx;
 509         secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
 510         secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
 511         secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
 512         secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
 513         secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
 514         secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
 515         if (primary_pipe->bottom_pipe) {
 516                 ASSERT(primary_pipe->bottom_pipe != secondary_pipe);
 517                 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
 518                 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
 519         }
 520         primary_pipe->bottom_pipe = secondary_pipe;
 521         secondary_pipe->top_pipe = primary_pipe;
 522
 523         resource_build_scaling_params(primary_pipe);
 524         resource_build_scaling_params(secondary_pipe);
 525 }
 526
 527 #if 0
 528 static void calc_wm_sets_and_perf_params(
 529                 struct dc_state *context,
 530                 struct dcn_bw_internal_vars *v)
 531 {
 532         /* Calculate set A last to keep internal var state consistent for required config */
 533         if (v->voltage_level < 2) {
 534                 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vnom0p8;
 535                 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vnom0p8;
 536                 v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vnom0p8;
 537                 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
 538
 539                 context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =
 540                         v->stutter_exit_watermark * 1000;
 541                 context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
 542                                 v->stutter_enter_plus_exit_watermark * 1000;
 543                 context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =
 544                                 v->dram_clock_change_watermark * 1000;
 545                 context->bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
 546                 context->bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;
 547
 548                 v->dcfclk_per_state[1] = v->dcfclkv_nom0p8;
 549                 v->dcfclk_per_state[0] = v->dcfclkv_nom0p8;
 550                 v->dcfclk = v->dcfclkv_nom0p8;
 551                 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
 552
 553                 context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
 554                         v->stutter_exit_watermark * 1000;
 555                 context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
 556                                 v->stutter_enter_plus_exit_watermark * 1000;
 557                 context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =
 558                                 v->dram_clock_change_watermark * 1000;
 559                 context->bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
 560                 context->bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000;
 561         }
 562
 563         if (v->voltage_level < 3) {
 564                 v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vmax0p9;
 565                 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmax0p9;
 566                 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmax0p9;
 567                 v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vmax0p9;
 568                 v->dcfclk_per_state[2] = v->dcfclkv_max0p9;
 569                 v->dcfclk_per_state[1] = v->dcfclkv_max0p9;
 570                 v->dcfclk_per_state[0] = v->dcfclkv_max0p9;
 571                 v->dcfclk = v->dcfclkv_max0p9;
 572                 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
 573
 574                 context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns =
 575                         v->stutter_exit_watermark * 1000;
 576                 context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
 577                                 v->stutter_enter_plus_exit_watermark * 1000;
 578                 context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns =
 579                                 v->dram_clock_change_watermark * 1000;
 580                 context->bw.dcn.watermarks.d.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
 581                 context->bw.dcn.watermarks.d.urgent_ns = v->urgent_watermark * 1000;
 582         }
 583
 584         v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
 585         v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72;
 586         v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65;
 587         v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_per_state[v->voltage_level];
 588         v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
 589         v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
 590         v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
 591         v->dcfclk = v->dcfclk_per_state[v->voltage_level];
 592         dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
 593
 594         context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
 595                 v->stutter_exit_watermark * 1000;
 596         context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
 597                         v->stutter_enter_plus_exit_watermark * 1000;
 598         context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
 599                         v->dram_clock_change_watermark * 1000;
 600         context->bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
 601         context->bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;
 602         if (v->voltage_level >= 2) {
 603                 context->bw.dcn.watermarks.b = context->bw.dcn.watermarks.a;
 604                 context->bw.dcn.watermarks.c = context->bw.dcn.watermarks.a;
 605         }
 606         if (v->voltage_level >= 3)
 607                 context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a;
 608 }
 609 #endif
 610
 611 static bool dcn_bw_apply_registry_override(struct dc *dc)
 612 {
 613         bool updated = false;
 614
 615         kernel_fpu_begin();
 616         if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns
 617                         && dc->debug.sr_exit_time_ns) {
 618                 updated = true;
 619                 dc->dcn_soc->sr_exit_time = dc->debug.sr_exit_time_ns / 1000.0;
 620         }
 621
 622         if ((int)(dc->dcn_soc->sr_enter_plus_exit_time * 1000)
 623                                 != dc->debug.sr_enter_plus_exit_time_ns
 624                         && dc->debug.sr_enter_plus_exit_time_ns) {
 625                 updated = true;
 626                 dc->dcn_soc->sr_enter_plus_exit_time =
 627                                 dc->debug.sr_enter_plus_exit_time_ns / 1000.0;
 628         }
 629
 630         if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->debug.urgent_latency_ns
 631                         && dc->debug.urgent_latency_ns) {
 632                 updated = true;
 633                 dc->dcn_soc->urgent_latency = dc->debug.urgent_latency_ns / 1000.0;
 634         }
 635
 636         if ((int)(dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency * 1000)
 637                                 != dc->debug.percent_of_ideal_drambw
 638                         && dc->debug.percent_of_ideal_drambw) {
 639                 updated = true;
 640                 dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency =
 641                                 dc->debug.percent_of_ideal_drambw;
 642         }
 643
 644         if ((int)(dc->dcn_soc->dram_clock_change_latency * 1000)
 645                                 != dc->debug.dram_clock_change_latency_ns
 646                         && dc->debug.dram_clock_change_latency_ns) {
 647                 updated = true;
 648                 dc->dcn_soc->dram_clock_change_latency =
 649                                 dc->debug.dram_clock_change_latency_ns / 1000.0;
 650         }
 651         kernel_fpu_end();
 652
 653         return updated;
 654 }
 655
 656 static void hack_disable_optional_pipe_split(struct dcn_bw_internal_vars *v)
 657 {
 658         /*
 659          * disable optional pipe split by lower dispclk bounding box
 660          * at DPM0
 661          */
 662         v->max_dispclk[0] = v->max_dppclk_vmin0p65;
 663 }
 664
 665 static void hack_force_pipe_split(struct dcn_bw_internal_vars *v,
 666                 unsigned int pixel_rate_100hz)
 667 {
 668         float pixel_rate_mhz = pixel_rate_100hz / 10000;
 669
 670         /*
 671          * force enabling pipe split by lower dpp clock for DPM0 to just
 672          * below the specify pixel_rate, so bw calc would split pipe.
 673          */
 674         if (pixel_rate_mhz < v->max_dppclk[0])
 675                 v->max_dppclk[0] = pixel_rate_mhz;
 676 }
 677
 678 static void hack_bounding_box(struct dcn_bw_internal_vars *v,
 679                 struct dc_debug_options *dbg,
 680                 struct dc_state *context)
 681 {
 682         if (dbg->pipe_split_policy == MPC_SPLIT_AVOID)
 683                 hack_disable_optional_pipe_split(v);
 684
 685         if (dbg->pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP &&
 686                 context->stream_count >= 2)
 687                 hack_disable_optional_pipe_split(v);
 688
 689         if (context->stream_count == 1 &&
 690                         dbg->force_single_disp_pipe_split)
 691                 hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz);
 692 }
 693
 694 bool dcn_validate_bandwidth(
 695                 struct dc *dc,
 696                 struct dc_state *context)
 697 {
 698         const struct resource_pool *pool = dc->res_pool;
 699         struct dcn_bw_internal_vars *v = &context->dcn_bw_vars;
 700         int i, input_idx;
 701         int vesa_sync_start, asic_blank_end, asic_blank_start;
 702         bool bw_limit_pass;
 703         float bw_limit;
 704
 705         PERFORMANCE_TRACE_START();
 706         if (dcn_bw_apply_registry_override(dc))
 707                 dcn_bw_sync_calcs_and_dml(dc);
 708
 709         memset(v, 0, sizeof(*v));
 710         kernel_fpu_begin();
 711         v->sr_exit_time = dc->dcn_soc->sr_exit_time;
 712         v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
 713         v->urgent_latency = dc->dcn_soc->urgent_latency;
 714         v->write_back_latency = dc->dcn_soc->write_back_latency;
 715         v->percent_of_ideal_drambw_received_after_urg_latency =
 716                         dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency;
 717
 718         v->dcfclkv_min0p65 = dc->dcn_soc->dcfclkv_min0p65;
 719         v->dcfclkv_mid0p72 = dc->dcn_soc->dcfclkv_mid0p72;
 720         v->dcfclkv_nom0p8 = dc->dcn_soc->dcfclkv_nom0p8;
 721         v->dcfclkv_max0p9 = dc->dcn_soc->dcfclkv_max0p9;
 722
 723         v->max_dispclk_vmin0p65 = dc->dcn_soc->max_dispclk_vmin0p65;
 724         v->max_dispclk_vmid0p72 = dc->dcn_soc->max_dispclk_vmid0p72;
 725         v->max_dispclk_vnom0p8 = dc->dcn_soc->max_dispclk_vnom0p8;
 726         v->max_dispclk_vmax0p9 = dc->dcn_soc->max_dispclk_vmax0p9;
 727
 728         v->max_dppclk_vmin0p65 = dc->dcn_soc->max_dppclk_vmin0p65;
 729         v->max_dppclk_vmid0p72 = dc->dcn_soc->max_dppclk_vmid0p72;
 730         v->max_dppclk_vnom0p8 = dc->dcn_soc->max_dppclk_vnom0p8;
 731         v->max_dppclk_vmax0p9 = dc->dcn_soc->max_dppclk_vmax0p9;
 732
 733         v->socclk = dc->dcn_soc->socclk;
 734
 735         v->fabric_and_dram_bandwidth_vmin0p65 = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65;
 736         v->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72;
 737         v->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8;
 738         v->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9;
 739
 740         v->phyclkv_min0p65 = dc->dcn_soc->phyclkv_min0p65;
 741         v->phyclkv_mid0p72 = dc->dcn_soc->phyclkv_mid0p72;
 742         v->phyclkv_nom0p8 = dc->dcn_soc->phyclkv_nom0p8;
 743         v->phyclkv_max0p9 = dc->dcn_soc->phyclkv_max0p9;
 744
 745         v->downspreading = dc->dcn_soc->downspreading;
 746         v->round_trip_ping_latency_cycles = dc->dcn_soc->round_trip_ping_latency_cycles;
 747         v->urgent_out_of_order_return_per_channel = dc->dcn_soc->urgent_out_of_order_return_per_channel;
 748         v->number_of_channels = dc->dcn_soc->number_of_channels;
 749         v->vmm_page_size = dc->dcn_soc->vmm_page_size;
 750         v->dram_clock_change_latency = dc->dcn_soc->dram_clock_change_latency;
 751         v->return_bus_width = dc->dcn_soc->return_bus_width;
 752
 753         v->rob_buffer_size_in_kbyte = dc->dcn_ip->rob_buffer_size_in_kbyte;
 754         v->det_buffer_size_in_kbyte = dc->dcn_ip->det_buffer_size_in_kbyte;
 755         v->dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels;
 756         v->opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines;
 757         v->pixel_chunk_size_in_kbyte = dc->dcn_ip->pixel_chunk_size_in_kbyte;
 758         v->pte_enable = dc->dcn_ip->pte_enable;
 759         v->pte_chunk_size = dc->dcn_ip->pte_chunk_size;
 760         v->meta_chunk_size = dc->dcn_ip->meta_chunk_size;
 761         v->writeback_chunk_size = dc->dcn_ip->writeback_chunk_size;
 762         v->odm_capability = dc->dcn_ip->odm_capability;
 763         v->dsc_capability = dc->dcn_ip->dsc_capability;
 764         v->line_buffer_size = dc->dcn_ip->line_buffer_size;
 765         v->is_line_buffer_bpp_fixed = dc->dcn_ip->is_line_buffer_bpp_fixed;
 766         v->line_buffer_fixed_bpp = dc->dcn_ip->line_buffer_fixed_bpp;
 767         v->max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines;
 768         v->writeback_luma_buffer_size = dc->dcn_ip->writeback_luma_buffer_size;
 769         v->writeback_chroma_buffer_size = dc->dcn_ip->writeback_chroma_buffer_size;
 770         v->max_num_dpp = dc->dcn_ip->max_num_dpp;
 771         v->max_num_writeback = dc->dcn_ip->max_num_writeback;
 772         v->max_dchub_topscl_throughput = dc->dcn_ip->max_dchub_topscl_throughput;
 773         v->max_pscl_tolb_throughput = dc->dcn_ip->max_pscl_tolb_throughput;
 774         v->max_lb_tovscl_throughput = dc->dcn_ip->max_lb_tovscl_throughput;
 775         v->max_vscl_tohscl_throughput = dc->dcn_ip->max_vscl_tohscl_throughput;
 776         v->max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;
 777         v->max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;
 778         v->max_hscl_taps = dc->dcn_ip->max_hscl_taps;
 779         v->max_vscl_taps = dc->dcn_ip->max_vscl_taps;
 780         v->under_scan_factor = dc->dcn_ip->under_scan_factor;
 781         v->pte_buffer_size_in_requests = dc->dcn_ip->pte_buffer_size_in_requests;
 782         v->dispclk_ramping_margin = dc->dcn_ip->dispclk_ramping_margin;
 783         v->max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters;
 784         v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =
 785                         dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
 786         v->bug_forcing_luma_and_chroma_request_to_same_size_fixed =
 787                         dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed;
 788
 789         v->voltage[5] = dcn_bw_no_support;
 790         v->voltage[4] = dcn_bw_v_max0p9;
 791         v->voltage[3] = dcn_bw_v_max0p9;
 792         v->voltage[2] = dcn_bw_v_nom0p8;
 793         v->voltage[1] = dcn_bw_v_mid0p72;
 794         v->voltage[0] = dcn_bw_v_min0p65;
 795         v->fabric_and_dram_bandwidth_per_state[5] = v->fabric_and_dram_bandwidth_vmax0p9;
 796         v->fabric_and_dram_bandwidth_per_state[4] = v->fabric_and_dram_bandwidth_vmax0p9;
 797         v->fabric_and_dram_bandwidth_per_state[3] = v->fabric_and_dram_bandwidth_vmax0p9;
 798         v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
 799         v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72;
 800         v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65;
 801         v->dcfclk_per_state[5] = v->dcfclkv_max0p9;
 802         v->dcfclk_per_state[4] = v->dcfclkv_max0p9;
 803         v->dcfclk_per_state[3] = v->dcfclkv_max0p9;
 804         v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
 805         v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
 806         v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
 807         v->max_dispclk[5] = v->max_dispclk_vmax0p9;
 808         v->max_dispclk[4] = v->max_dispclk_vmax0p9;
 809         v->max_dispclk[3] = v->max_dispclk_vmax0p9;
 810         v->max_dispclk[2] = v->max_dispclk_vnom0p8;
 811         v->max_dispclk[1] = v->max_dispclk_vmid0p72;
 812         v->max_dispclk[0] = v->max_dispclk_vmin0p65;
 813         v->max_dppclk[5] = v->max_dppclk_vmax0p9;
 814         v->max_dppclk[4] = v->max_dppclk_vmax0p9;
 815         v->max_dppclk[3] = v->max_dppclk_vmax0p9;
 816         v->max_dppclk[2] = v->max_dppclk_vnom0p8;
 817         v->max_dppclk[1] = v->max_dppclk_vmid0p72;
 818         v->max_dppclk[0] = v->max_dppclk_vmin0p65;
 819         v->phyclk_per_state[5] = v->phyclkv_max0p9;
 820         v->phyclk_per_state[4] = v->phyclkv_max0p9;
 821         v->phyclk_per_state[3] = v->phyclkv_max0p9;
 822         v->phyclk_per_state[2] = v->phyclkv_nom0p8;
 823         v->phyclk_per_state[1] = v->phyclkv_mid0p72;
 824         v->phyclk_per_state[0] = v->phyclkv_min0p65;
 825         v->synchronized_vblank = dcn_bw_no;
 826         v->ta_pscalculation = dcn_bw_override;
 827         v->allow_different_hratio_vratio = dcn_bw_yes;
 828
 829         for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
 830                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 831
 832                 if (!pipe->stream)
 833                         continue;
 834                 /* skip all but first of split pipes */
 835                 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
 836                         continue;
 837
 838                 v->underscan_output[input_idx] = false; /* taken care of in recout already*/
 839                 v->interlace_output[input_idx] = false;
 840
 841                 v->htotal[input_idx] = pipe->stream->timing.h_total;
 842                 v->vtotal[input_idx] = pipe->stream->timing.v_total;
 843                 v->vactive[input_idx] = pipe->stream->timing.v_addressable +
 844                                 pipe->stream->timing.v_border_top + pipe->stream->timing.v_border_bottom;
 845                 v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total
 846                                 - v->vactive[input_idx]
 847                                 - pipe->stream->timing.v_front_porch;
 848                 v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_100hz/10000.0;
 849                 if (pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
 850                         v->pixel_clock[input_idx] *= 2;
 851                 if (!pipe->plane_state) {
 852                         v->dcc_enable[input_idx] = dcn_bw_yes;
 853                         v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32;
 854                         v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s;
 855                         v->lb_bit_per_pixel[input_idx] = 30;
 856                         v->viewport_width[input_idx] = pipe->stream->timing.h_addressable;
 857                         v->viewport_height[input_idx] = pipe->stream->timing.v_addressable;
 858                         v->scaler_rec_out_width[input_idx] = pipe->stream->timing.h_addressable;
 859                         v->scaler_recout_height[input_idx] = pipe->stream->timing.v_addressable;
 860                         v->override_hta_ps[input_idx] = 1;
 861                         v->override_vta_ps[input_idx] = 1;
 862                         v->override_hta_pschroma[input_idx] = 1;
 863                         v->override_vta_pschroma[input_idx] = 1;
 864                         v->source_scan[input_idx] = dcn_bw_hor;
 865
 866                 } else {
 867                         v->viewport_height[input_idx] =  pipe->plane_res.scl_data.viewport.height;
 868                         v->viewport_width[input_idx] = pipe->plane_res.scl_data.viewport.width;
 869                         v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width;
 870                         v->scaler_recout_height[input_idx] = pipe->plane_res.scl_data.recout.height;
 871                         if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) {
 872                                 if (pipe->plane_state->rotation % 2 == 0) {
 873                                         int viewport_end = pipe->plane_res.scl_data.viewport.width
 874                                                         + pipe->plane_res.scl_data.viewport.x;
 875                                         int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.width
 876                                                         + pipe->bottom_pipe->plane_res.scl_data.viewport.x;
 877
 878                                         if (viewport_end > viewport_b_end)
 879                                                 v->viewport_width[input_idx] = viewport_end
 880                                                         - pipe->bottom_pipe->plane_res.scl_data.viewport.x;
 881                                         else
 882                                                 v->viewport_width[input_idx] = viewport_b_end
 883                                                                         - pipe->plane_res.scl_data.viewport.x;
 884                                 } else  {
 885                                         int viewport_end = pipe->plane_res.scl_data.viewport.height
 886                                                 + pipe->plane_res.scl_data.viewport.y;
 887                                         int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.height
 888                                                 + pipe->bottom_pipe->plane_res.scl_data.viewport.y;
 889
 890                                         if (viewport_end > viewport_b_end)
 891                                                 v->viewport_height[input_idx] = viewport_end
 892                                                         - pipe->bottom_pipe->plane_res.scl_data.viewport.y;
 893                                         else
 894                                                 v->viewport_height[input_idx] = viewport_b_end
 895                                                                         - pipe->plane_res.scl_data.viewport.y;
 896                                 }
 897                                 v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width
 898                                                 + pipe->bottom_pipe->plane_res.scl_data.recout.width;
 899                         }
 900
 901                         if (pipe->plane_state->rotation % 2 == 0) {
 902                                 ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value
 903                                         || v->scaler_rec_out_width[input_idx] == v->viewport_width[input_idx]);
 904                                 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value
 905                                         || v->scaler_recout_height[input_idx] == v->viewport_height[input_idx]);
 906                         } else {
 907                                 ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value
 908                                         || v->scaler_recout_height[input_idx] == v->viewport_width[input_idx]);
 909                                 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value
 910                                         || v->scaler_rec_out_width[input_idx] == v->viewport_height[input_idx]);
 911                         }
 912
 913                         if (dc->debug.optimized_watermark) {
 914                                 /*
 915                                  * this method requires us to always re-calculate watermark when dcc change
 916                                  * between flip.
 917                                  */
 918                                 v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;
 919                         } else {
 920                                 /*
 921                                  * allow us to disable dcc on the fly without re-calculating WM
 922                                  *
 923                                  * extra overhead for DCC is quite small.  for 1080p WM without
 924                                  * DCC is only 0.417us lower (urgent goes from 6.979us to 6.562us)
 925                                  */
 926                                 unsigned int bpe;
 927
 928                                 v->dcc_enable[input_idx] = dc->res_pool->hubbub->funcs->dcc_support_pixel_format(
 929                                                 pipe->plane_state->format, &bpe) ? dcn_bw_yes : dcn_bw_no;
 930                         }
 931
 932                         v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs(
 933                                         pipe->plane_state->format);
 934                         v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs(
 935                                         pipe->plane_state->tiling_info.gfx9.swizzle);
 936                         v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth);
 937                         v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps;
 938                         v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps;
 939                         v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c;
 940                         v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c;
 941                         /*
 942                          * Spreadsheet doesn't handle taps_c is one properly,
 943                          * need to force Chroma to always be scaled to pass
 944                          * bandwidth validation.
 945                          */
 946                         if (v->override_hta_pschroma[input_idx] == 1)
 947                                 v->override_hta_pschroma[input_idx] = 2;
 948                         if (v->override_vta_pschroma[input_idx] == 1)
 949                                 v->override_vta_pschroma[input_idx] = 2;
 950                         v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor;
 951                 }
 952                 if (v->is_line_buffer_bpp_fixed == dcn_bw_yes)
 953                         v->lb_bit_per_pixel[input_idx] = v->line_buffer_fixed_bpp;
 954                 v->dcc_rate[input_idx] = 1; /*TODO: Worst case? does this change?*/
 955                 v->output_format[input_idx] = pipe->stream->timing.pixel_encoding ==
 956                                 PIXEL_ENCODING_YCBCR420 ? dcn_bw_420 : dcn_bw_444;
 957                 v->output[input_idx] = pipe->stream->signal ==
 958                                 SIGNAL_TYPE_HDMI_TYPE_A ? dcn_bw_hdmi : dcn_bw_dp;
 959                 v->output_deep_color[input_idx] = dcn_bw_encoder_8bpc;
 960                 if (v->output[input_idx] == dcn_bw_hdmi) {
 961                         switch (pipe->stream->timing.display_color_depth) {
 962                         case COLOR_DEPTH_101010:
 963                                 v->output_deep_color[input_idx] = dcn_bw_encoder_10bpc;
 964                                 break;
 965                         case COLOR_DEPTH_121212:
 966                                 v->output_deep_color[input_idx]  = dcn_bw_encoder_12bpc;
 967                                 break;
 968                         case COLOR_DEPTH_161616:
 969                                 v->output_deep_color[input_idx]  = dcn_bw_encoder_16bpc;
 970                                 break;
 971                         default:
 972                                 break;
 973                         }
 974                 }
 975
 976                 input_idx++;
 977         }
 978         v->number_of_active_planes = input_idx;
 979
 980         scaler_settings_calculation(v);
 981
 982         hack_bounding_box(v, &dc->debug, context);
 983
 984         mode_support_and_system_configuration(v);
 985
 986         /* Unhack dppclk: dont bother with trying to pipe split if we cannot maintain dpm0 */
 987         if (v->voltage_level != 0
 988                         && context->stream_count == 1
 989                         && dc->debug.force_single_disp_pipe_split) {
 990                 v->max_dppclk[0] = v->max_dppclk_vmin0p65;
 991                 mode_support_and_system_configuration(v);
 992         }
 993
 994         if (v->voltage_level == 0 &&
 995                         (dc->debug.sr_exit_time_dpm0_ns
 996                                 || dc->debug.sr_enter_plus_exit_time_dpm0_ns)) {
 997
 998                 if (dc->debug.sr_enter_plus_exit_time_dpm0_ns)
 999                         v->sr_enter_plus_exit_time =
1000                                 dc->debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f;
1001                 if (dc->debug.sr_exit_time_dpm0_ns)
1002                         v->sr_exit_time =  dc->debug.sr_exit_time_dpm0_ns / 1000.0f;
1003                 dc->dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time;
1004                 dc->dml.soc.sr_exit_time_us = v->sr_exit_time;
1005                 mode_support_and_system_configuration(v);
1006         }
1007
1008         if (v->voltage_level != 5) {
1009                 float bw_consumed = v->total_bandwidth_consumed_gbyte_per_second;
1010                 if (bw_consumed < v->fabric_and_dram_bandwidth_vmin0p65)
1011                         bw_consumed = v->fabric_and_dram_bandwidth_vmin0p65;
1012                 else if (bw_consumed < v->fabric_and_dram_bandwidth_vmid0p72)
1013                         bw_consumed = v->fabric_and_dram_bandwidth_vmid0p72;
1014                 else if (bw_consumed < v->fabric_and_dram_bandwidth_vnom0p8)
1015                         bw_consumed = v->fabric_and_dram_bandwidth_vnom0p8;
1016                 else
1017                         bw_consumed = v->fabric_and_dram_bandwidth_vmax0p9;
1018
1019                 if (bw_consumed < v->fabric_and_dram_bandwidth)
1020                         if (dc->debug.voltage_align_fclk)
1021                                 bw_consumed = v->fabric_and_dram_bandwidth;
1022
1023                 display_pipe_configuration(v);
1024                 /*calc_wm_sets_and_perf_params(context, v);*/
1025                 /* Only 1 set is used by dcn since no noticeable
1026                  * performance improvement was measured and due to hw bug DEGVIDCN10-254
1027                  */
1028                 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
1029
1030                 context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
1031                         v->stutter_exit_watermark * 1000;
1032                 context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
1033                                 v->stutter_enter_plus_exit_watermark * 1000;
1034                 context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
1035                                 v->dram_clock_change_watermark * 1000;
1036                 context->bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
1037                 context->bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;
1038                 context->bw.dcn.watermarks.b = context->bw.dcn.watermarks.a;
1039                 context->bw.dcn.watermarks.c = context->bw.dcn.watermarks.a;
1040                 context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a;
1041
1042                 context->bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 /
1043                                 (ddr4_dram_factor_single_Channel * v->number_of_channels));
1044                 if (bw_consumed == v->fabric_and_dram_bandwidth_vmin0p65) {
1045                         context->bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 / 32);
1046                 }
1047
1048                 context->bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);
1049                 context->bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000);
1050
1051                 context->bw.dcn.clk.dispclk_khz = (int)(v->dispclk * 1000);
1052                 if (dc->debug.max_disp_clk == true)
1053                         context->bw.dcn.clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000);
1054
1055                 if (context->bw.dcn.clk.dispclk_khz <
1056                                 dc->debug.min_disp_clk_khz) {
1057                         context->bw.dcn.clk.dispclk_khz =
1058                                         dc->debug.min_disp_clk_khz;
1059                 }
1060
1061                 context->bw.dcn.clk.dppclk_khz = context->bw.dcn.clk.dispclk_khz / v->dispclk_dppclk_ratio;
1062                 context->bw.dcn.clk.phyclk_khz = v->phyclk_per_state[v->voltage_level];
1063                 switch (v->voltage_level) {
1064                 case 0:
1065                         context->bw.dcn.clk.max_supported_dppclk_khz =
1066                                         (int)(dc->dcn_soc->max_dppclk_vmin0p65 * 1000);
1067                         break;
1068                 case 1:
1069                         context->bw.dcn.clk.max_supported_dppclk_khz =
1070                                         (int)(dc->dcn_soc->max_dppclk_vmid0p72 * 1000);
1071                         break;
1072                 case 2:
1073                         context->bw.dcn.clk.max_supported_dppclk_khz =
1074                                         (int)(dc->dcn_soc->max_dppclk_vnom0p8 * 1000);
1075                         break;
1076                 default:
1077                         context->bw.dcn.clk.max_supported_dppclk_khz =
1078                                         (int)(dc->dcn_soc->max_dppclk_vmax0p9 * 1000);
1079                         break;
1080                 }
1081
1082                 for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
1083                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1084
1085                         /* skip inactive pipe */
1086                         if (!pipe->stream)
1087                                 continue;
1088                         /* skip all but first of split pipes */
1089                         if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
1090                                 continue;
1091
1092                         pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];
1093                         pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];
1094                         pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];
1095                         pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
1096
1097                         pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
1098                         pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;
1099                         vesa_sync_start = pipe->stream->timing.v_addressable +
1100                                                 pipe->stream->timing.v_border_bottom +
1101                                                 pipe->stream->timing.v_front_porch;
1102
1103                         asic_blank_end = (pipe->stream->timing.v_total -
1104                                                 vesa_sync_start -
1105                                                 pipe->stream->timing.v_border_top)
1106                         * (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
1107
1108                         asic_blank_start = asic_blank_end +
1109                                                 (pipe->stream->timing.v_border_top +
1110                                                 pipe->stream->timing.v_addressable +
1111                                                 pipe->stream->timing.v_border_bottom)
1112                         * (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
1113
1114                         pipe->pipe_dlg_param.vblank_start = asic_blank_start;
1115                         pipe->pipe_dlg_param.vblank_end = asic_blank_end;
1116
1117                         if (pipe->plane_state) {
1118                                 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
1119
1120                                 pipe->plane_state->update_flags.bits.full_update = 1;
1121
1122                                 if (v->dpp_per_plane[input_idx] == 2 ||
1123                                         ((pipe->stream->view_format ==
1124                                           VIEW_3D_FORMAT_SIDE_BY_SIDE ||
1125                                           pipe->stream->view_format ==
1126                                           VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
1127                                         (pipe->stream->timing.timing_3d_format ==
1128                                          TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
1129                                          pipe->stream->timing.timing_3d_format ==
1130                                          TIMING_3D_FORMAT_SIDE_BY_SIDE))) {
1131                                         if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
1132                                                 /* update previously split pipe */
1133                                                 hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];
1134                                                 hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];
1135                                                 hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];
1136                                                 hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
1137
1138                                                 hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
1139                                                 hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;
1140                                                 hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start;
1141                                                 hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end;
1142                                         } else {
1143                                                 /* pipe not split previously needs split */
1144                                                 hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, pool);
1145                                                 ASSERT(hsplit_pipe);
1146                                                 split_stream_across_pipes(
1147                                                         &context->res_ctx, pool,
1148                                                         pipe, hsplit_pipe);
1149                                         }
1150
1151                                         dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe, input_idx);
1152                                 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
1153                                         /* merge previously split pipe */
1154                                         pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
1155                                         if (hsplit_pipe->bottom_pipe)
1156                                                 hsplit_pipe->bottom_pipe->top_pipe = pipe;
1157                                         hsplit_pipe->plane_state = NULL;
1158                                         hsplit_pipe->stream = NULL;
1159                                         hsplit_pipe->top_pipe = NULL;
1160                                         hsplit_pipe->bottom_pipe = NULL;
1161                                         /* Clear plane_res and stream_res */
1162                                         memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
1163                                         memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
1164                                         resource_build_scaling_params(pipe);
1165                                 }
1166                                 /* for now important to do this after pipe split for building e2e params */
1167                                 dcn_bw_calc_rq_dlg_ttu(dc, v, pipe, input_idx);
1168                         }
1169
1170                         input_idx++;
1171                 }
1172         }
1173
1174         if (v->voltage_level == 0) {
1175
1176                 dc->dml.soc.sr_enter_plus_exit_time_us =
1177                                 dc->dcn_soc->sr_enter_plus_exit_time;
1178                 dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;
1179         }
1180
1181         /*
1182          * BW limit is set to prevent display from impacting other system functions
1183          */
1184
1185         bw_limit = dc->dcn_soc->percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9;
1186         bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit;
1187
1188         kernel_fpu_end();
1189
1190         PERFORMANCE_TRACE_END();
1191
1192         if (bw_limit_pass && v->voltage_level != 5)
1193                 return true;
1194         else
1195                 return false;
1196 }
1197
1198 static unsigned int dcn_find_normalized_clock_vdd_Level(
1199         const struct dc *dc,
1200         enum dm_pp_clock_type clocks_type,
1201         int clocks_in_khz)
1202 {
1203         int vdd_level = dcn_bw_v_min0p65;
1204
1205         if (clocks_in_khz == 0)/*todo some clock not in the considerations*/
1206                 return vdd_level;
1207
1208         switch (clocks_type) {
1209         case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
1210                 if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmax0p9*1000) {
1211                         vdd_level = dcn_bw_v_max0p91;
1212                         BREAK_TO_DEBUGGER();
1213                 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vnom0p8*1000) {
1214                         vdd_level = dcn_bw_v_max0p9;
1215                 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmid0p72*1000) {
1216                         vdd_level = dcn_bw_v_nom0p8;
1217                 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmin0p65*1000) {
1218                         vdd_level = dcn_bw_v_mid0p72;
1219                 } else
1220                         vdd_level = dcn_bw_v_min0p65;
1221                 break;
1222         case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
1223                 if (clocks_in_khz > dc->dcn_soc->phyclkv_max0p9*1000) {
1224                         vdd_level = dcn_bw_v_max0p91;
1225                         BREAK_TO_DEBUGGER();
1226                 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_nom0p8*1000) {
1227                         vdd_level = dcn_bw_v_max0p9;
1228                 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_mid0p72*1000) {
1229                         vdd_level = dcn_bw_v_nom0p8;
1230                 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_min0p65*1000) {
1231                         vdd_level = dcn_bw_v_mid0p72;
1232                 } else
1233                         vdd_level = dcn_bw_v_min0p65;
1234                 break;
1235
1236         case DM_PP_CLOCK_TYPE_DPPCLK:
1237                 if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmax0p9*1000) {
1238                         vdd_level = dcn_bw_v_max0p91;
1239                         BREAK_TO_DEBUGGER();
1240                 } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vnom0p8*1000) {
1241                         vdd_level = dcn_bw_v_max0p9;
1242                 } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmid0p72*1000) {
1243                         vdd_level = dcn_bw_v_nom0p8;
1244                 } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmin0p65*1000) {
1245                         vdd_level = dcn_bw_v_mid0p72;
1246                 } else
1247                         vdd_level = dcn_bw_v_min0p65;
1248                 break;
1249
1250         case DM_PP_CLOCK_TYPE_MEMORY_CLK:
1251                 {
1252                         unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels);
1253
1254                         if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9*1000000/factor) {
1255                                 vdd_level = dcn_bw_v_max0p91;
1256                                 BREAK_TO_DEBUGGER();
1257                         } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8*1000000/factor) {
1258                                 vdd_level = dcn_bw_v_max0p9;
1259                         } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72*1000000/factor) {
1260                                 vdd_level = dcn_bw_v_nom0p8;
1261                         } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65*1000000/factor) {
1262                                 vdd_level = dcn_bw_v_mid0p72;
1263                         } else
1264                                 vdd_level = dcn_bw_v_min0p65;
1265                 }
1266                 break;
1267
1268         case DM_PP_CLOCK_TYPE_DCFCLK:
1269                 if (clocks_in_khz > dc->dcn_soc->dcfclkv_max0p9*1000) {
1270                         vdd_level = dcn_bw_v_max0p91;
1271                         BREAK_TO_DEBUGGER();
1272                 } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_nom0p8*1000) {
1273                         vdd_level = dcn_bw_v_max0p9;
1274                 } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_mid0p72*1000) {
1275                         vdd_level = dcn_bw_v_nom0p8;
1276                 } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_min0p65*1000) {
1277                         vdd_level = dcn_bw_v_mid0p72;
1278                 } else
1279                         vdd_level = dcn_bw_v_min0p65;
1280                 break;
1281
1282         default:
1283                  break;
1284         }
1285         return vdd_level;
1286 }
1287
1288 unsigned int dcn_find_dcfclk_suits_all(
1289         const struct dc *dc,
1290         struct dc_clocks *clocks)
1291 {
1292         unsigned vdd_level, vdd_level_temp;
1293         unsigned dcf_clk;
1294
1295         /*find a common supported voltage level*/
1296         vdd_level = dcn_find_normalized_clock_vdd_Level(
1297                 dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks->dispclk_khz);
1298         vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1299                 dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks->phyclk_khz);
1300
1301         vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1302         vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1303                 dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_khz);
1304         vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1305
1306         vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1307                 dc, DM_PP_CLOCK_TYPE_MEMORY_CLK, clocks->fclk_khz);
1308         vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1309         vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1310                 dc, DM_PP_CLOCK_TYPE_DCFCLK, clocks->dcfclk_khz);
1311
1312         /*find that level conresponding dcfclk*/
1313         vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1314         if (vdd_level == dcn_bw_v_max0p91) {
1315                 BREAK_TO_DEBUGGER();
1316                 dcf_clk = dc->dcn_soc->dcfclkv_max0p9*1000;
1317         } else if (vdd_level == dcn_bw_v_max0p9)
1318                 dcf_clk =  dc->dcn_soc->dcfclkv_max0p9*1000;
1319         else if (vdd_level == dcn_bw_v_nom0p8)
1320                 dcf_clk =  dc->dcn_soc->dcfclkv_nom0p8*1000;
1321         else if (vdd_level == dcn_bw_v_mid0p72)
1322                 dcf_clk =  dc->dcn_soc->dcfclkv_mid0p72*1000;
1323         else
1324                 dcf_clk =  dc->dcn_soc->dcfclkv_min0p65*1000;
1325
1326         DC_LOG_BANDWIDTH_CALCS("\tdcf_clk for voltage = %d\n", dcf_clk);
1327         return dcf_clk;
1328 }
1329
1330 static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks)
1331 {
1332         int i;
1333
1334         if (clks->num_levels == 0)
1335                 return false;
1336
1337         for (i = 0; i < clks->num_levels; i++)
1338                 /* Ensure that the result is sane */
1339                 if (clks->data[i].clocks_in_khz == 0)
1340                         return false;
1341
1342         return true;
1343 }
1344
1345 void dcn_bw_update_from_pplib(struct dc *dc)
1346 {
1347         struct dc_context *ctx = dc->ctx;
1348         struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0};
1349         bool res;
1350
1351         kernel_fpu_begin();
1352
1353         /* TODO: This is not the proper way to obtain fabric_and_dram_bandwidth, should be min(fclk, memclk) */
1354         res = dm_pp_get_clock_levels_by_type_with_voltage(
1355                         ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);
1356
1357         if (res)
1358                 res = verify_clock_values(&fclks);
1359
1360         if (res) {
1361                 ASSERT(fclks.num_levels >= 3);
1362                 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 32 * (fclks.data[0].clocks_in_khz / 1000.0) / 1000.0;
1363                 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->number_of_channels *
1364                                 (fclks.data[fclks.num_levels - (fclks.num_levels > 2 ? 3 : 2)].clocks_in_khz / 1000.0)
1365                                 * ddr4_dram_factor_single_Channel / 1000.0;
1366                 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->number_of_channels *
1367                                 (fclks.data[fclks.num_levels - 2].clocks_in_khz / 1000.0)
1368                                 * ddr4_dram_factor_single_Channel / 1000.0;
1369                 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->number_of_channels *
1370                                 (fclks.data[fclks.num_levels - 1].clocks_in_khz / 1000.0)
1371                                 * ddr4_dram_factor_single_Channel / 1000.0;
1372         } else
1373                 BREAK_TO_DEBUGGER();
1374
1375         res = dm_pp_get_clock_levels_by_type_with_voltage(
1376                         ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks);
1377
1378         if (res)
1379                 res = verify_clock_values(&dcfclks);
1380
1381         if (res && dcfclks.num_levels >= 3) {
1382                 dc->dcn_soc->dcfclkv_min0p65 = dcfclks.data[0].clocks_in_khz / 1000.0;
1383                 dc->dcn_soc->dcfclkv_mid0p72 = dcfclks.data[dcfclks.num_levels - 3].clocks_in_khz / 1000.0;
1384                 dc->dcn_soc->dcfclkv_nom0p8 = dcfclks.data[dcfclks.num_levels - 2].clocks_in_khz / 1000.0;
1385                 dc->dcn_soc->dcfclkv_max0p9 = dcfclks.data[dcfclks.num_levels - 1].clocks_in_khz / 1000.0;
1386         } else
1387                 BREAK_TO_DEBUGGER();
1388
1389         kernel_fpu_end();
1390 }
1391
1392 void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
1393 {
1394         struct pp_smu_funcs_rv *pp = dc->res_pool->pp_smu;
1395         struct pp_smu_wm_range_sets ranges = {0};
1396         int min_fclk_khz, min_dcfclk_khz, socclk_khz;
1397         const int overdrive = 5000000; /* 5 GHz to cover Overdrive */
1398
1399         if (!pp->set_wm_ranges)
1400                 return;
1401
1402         kernel_fpu_begin();
1403         min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32;
1404         min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000;
1405         socclk_khz = dc->dcn_soc->socclk * 1000;
1406         kernel_fpu_end();
1407
1408         /* Now notify PPLib/SMU about which Watermarks sets they should select
1409          * depending on DPM state they are in. And update BW MGR GFX Engine and
1410          * Memory clock member variables for Watermarks calculations for each
1411          * Watermark Set. Only one watermark set for dcn1 due to hw bug DEGVIDCN10-254.
1412          */
1413         /* SOCCLK does not affect anytihng but writeback for DCN so for now we dont
1414          * care what the value is, hence min to overdrive level
1415          */
1416         ranges.num_reader_wm_sets = WM_SET_COUNT;
1417         ranges.num_writer_wm_sets = WM_SET_COUNT;
1418         ranges.reader_wm_sets[0].wm_inst = WM_A;
1419         ranges.reader_wm_sets[0].min_drain_clk_mhz = min_dcfclk_khz / 1000;
1420         ranges.reader_wm_sets[0].max_drain_clk_mhz = overdrive / 1000;
1421         ranges.reader_wm_sets[0].min_fill_clk_mhz = min_fclk_khz / 1000;
1422         ranges.reader_wm_sets[0].max_fill_clk_mhz = overdrive / 1000;
1423         ranges.writer_wm_sets[0].wm_inst = WM_A;
1424         ranges.writer_wm_sets[0].min_fill_clk_mhz = socclk_khz / 1000;
1425         ranges.writer_wm_sets[0].max_fill_clk_mhz = overdrive / 1000;
1426         ranges.writer_wm_sets[0].min_drain_clk_mhz = min_fclk_khz / 1000;
1427         ranges.writer_wm_sets[0].max_drain_clk_mhz = overdrive / 1000;
1428
1429         if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) {
1430                 ranges.reader_wm_sets[0].wm_inst = WM_A;
1431                 ranges.reader_wm_sets[0].min_drain_clk_mhz = 300;
1432                 ranges.reader_wm_sets[0].max_drain_clk_mhz = 5000;
1433                 ranges.reader_wm_sets[0].min_fill_clk_mhz = 800;
1434                 ranges.reader_wm_sets[0].max_fill_clk_mhz = 5000;
1435                 ranges.writer_wm_sets[0].wm_inst = WM_A;
1436                 ranges.writer_wm_sets[0].min_fill_clk_mhz = 200;
1437                 ranges.writer_wm_sets[0].max_fill_clk_mhz = 5000;
1438                 ranges.writer_wm_sets[0].min_drain_clk_mhz = 800;
1439                 ranges.writer_wm_sets[0].max_drain_clk_mhz = 5000;
1440         }
1441
1442         ranges.reader_wm_sets[1] = ranges.writer_wm_sets[0];
1443         ranges.reader_wm_sets[1].wm_inst = WM_B;
1444
1445         ranges.reader_wm_sets[2] = ranges.writer_wm_sets[0];
1446         ranges.reader_wm_sets[2].wm_inst = WM_C;
1447
1448         ranges.reader_wm_sets[3] = ranges.writer_wm_sets[0];
1449         ranges.reader_wm_sets[3].wm_inst = WM_D;
1450
1451         /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1452         pp->set_wm_ranges(&pp->pp_smu, &ranges);
1453 }
1454
1455 void dcn_bw_sync_calcs_and_dml(struct dc *dc)
1456 {
1457         kernel_fpu_begin();
1458         DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %f ns\n"
1459                         "sr_enter_plus_exit_time: %f ns\n"
1460                         "urgent_latency: %f ns\n"
1461                         "write_back_latency: %f ns\n"
1462                         "percent_of_ideal_drambw_received_after_urg_latency: %f %%\n"
1463                         "max_request_size: %d bytes\n"
1464                         "dcfclkv_max0p9: %f kHz\n"
1465                         "dcfclkv_nom0p8: %f kHz\n"
1466                         "dcfclkv_mid0p72: %f kHz\n"
1467                         "dcfclkv_min0p65: %f kHz\n"
1468                         "max_dispclk_vmax0p9: %f kHz\n"
1469                         "max_dispclk_vnom0p8: %f kHz\n"
1470                         "max_dispclk_vmid0p72: %f kHz\n"
1471                         "max_dispclk_vmin0p65: %f kHz\n"
1472                         "max_dppclk_vmax0p9: %f kHz\n"
1473                         "max_dppclk_vnom0p8: %f kHz\n"
1474                         "max_dppclk_vmid0p72: %f kHz\n"
1475                         "max_dppclk_vmin0p65: %f kHz\n"
1476                         "socclk: %f kHz\n"
1477                         "fabric_and_dram_bandwidth_vmax0p9: %f MB/s\n"
1478                         "fabric_and_dram_bandwidth_vnom0p8: %f MB/s\n"
1479                         "fabric_and_dram_bandwidth_vmid0p72: %f MB/s\n"
1480                         "fabric_and_dram_bandwidth_vmin0p65: %f MB/s\n"
1481                         "phyclkv_max0p9: %f kHz\n"
1482                         "phyclkv_nom0p8: %f kHz\n"
1483                         "phyclkv_mid0p72: %f kHz\n"
1484                         "phyclkv_min0p65: %f kHz\n"
1485                         "downspreading: %f %%\n"
1486                         "round_trip_ping_latency_cycles: %d DCFCLK Cycles\n"
1487                         "urgent_out_of_order_return_per_channel: %d Bytes\n"
1488                         "number_of_channels: %d\n"
1489                         "vmm_page_size: %d Bytes\n"
1490                         "dram_clock_change_latency: %f ns\n"
1491                         "return_bus_width: %d Bytes\n",
1492                         dc->dcn_soc->sr_exit_time * 1000,
1493                         dc->dcn_soc->sr_enter_plus_exit_time * 1000,
1494                         dc->dcn_soc->urgent_latency * 1000,
1495                         dc->dcn_soc->write_back_latency * 1000,
1496                         dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency,
1497                         dc->dcn_soc->max_request_size,
1498                         dc->dcn_soc->dcfclkv_max0p9 * 1000,
1499                         dc->dcn_soc->dcfclkv_nom0p8 * 1000,
1500                         dc->dcn_soc->dcfclkv_mid0p72 * 1000,
1501                         dc->dcn_soc->dcfclkv_min0p65 * 1000,
1502                         dc->dcn_soc->max_dispclk_vmax0p9 * 1000,
1503                         dc->dcn_soc->max_dispclk_vnom0p8 * 1000,
1504                         dc->dcn_soc->max_dispclk_vmid0p72 * 1000,
1505                         dc->dcn_soc->max_dispclk_vmin0p65 * 1000,
1506                         dc->dcn_soc->max_dppclk_vmax0p9 * 1000,
1507                         dc->dcn_soc->max_dppclk_vnom0p8 * 1000,
1508                         dc->dcn_soc->max_dppclk_vmid0p72 * 1000,
1509                         dc->dcn_soc->max_dppclk_vmin0p65 * 1000,
1510                         dc->dcn_soc->socclk * 1000,
1511                         dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 * 1000,
1512                         dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 * 1000,
1513                         dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 * 1000,
1514                         dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000,
1515                         dc->dcn_soc->phyclkv_max0p9 * 1000,
1516                         dc->dcn_soc->phyclkv_nom0p8 * 1000,
1517                         dc->dcn_soc->phyclkv_mid0p72 * 1000,
1518                         dc->dcn_soc->phyclkv_min0p65 * 1000,
1519                         dc->dcn_soc->downspreading * 100,
1520                         dc->dcn_soc->round_trip_ping_latency_cycles,
1521                         dc->dcn_soc->urgent_out_of_order_return_per_channel,
1522                         dc->dcn_soc->number_of_channels,
1523                         dc->dcn_soc->vmm_page_size,
1524                         dc->dcn_soc->dram_clock_change_latency * 1000,
1525                         dc->dcn_soc->return_bus_width);
1526         DC_LOG_BANDWIDTH_CALCS("rob_buffer_size_in_kbyte: %f\n"
1527                         "det_buffer_size_in_kbyte: %f\n"
1528                         "dpp_output_buffer_pixels: %f\n"
1529                         "opp_output_buffer_lines: %f\n"
1530                         "pixel_chunk_size_in_kbyte: %f\n"
1531                         "pte_enable: %d\n"
1532                         "pte_chunk_size: %d kbytes\n"
1533                         "meta_chunk_size: %d kbytes\n"
1534                         "writeback_chunk_size: %d kbytes\n"
1535                         "odm_capability: %d\n"
1536                         "dsc_capability: %d\n"
1537                         "line_buffer_size: %d bits\n"
1538                         "max_line_buffer_lines: %d\n"
1539                         "is_line_buffer_bpp_fixed: %d\n"
1540                         "line_buffer_fixed_bpp: %d\n"
1541                         "writeback_luma_buffer_size: %d kbytes\n"
1542                         "writeback_chroma_buffer_size: %d kbytes\n"
1543                         "max_num_dpp: %d\n"
1544                         "max_num_writeback: %d\n"
1545                         "max_dchub_topscl_throughput: %d pixels/dppclk\n"
1546                         "max_pscl_tolb_throughput: %d pixels/dppclk\n"
1547                         "max_lb_tovscl_throughput: %d pixels/dppclk\n"
1548                         "max_vscl_tohscl_throughput: %d pixels/dppclk\n"
1549                         "max_hscl_ratio: %f\n"
1550                         "max_vscl_ratio: %f\n"
1551                         "max_hscl_taps: %d\n"
1552                         "max_vscl_taps: %d\n"
1553                         "pte_buffer_size_in_requests: %d\n"
1554                         "dispclk_ramping_margin: %f %%\n"
1555                         "under_scan_factor: %f %%\n"
1556                         "max_inter_dcn_tile_repeaters: %d\n"
1557                         "can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one: %d\n"
1558                         "bug_forcing_luma_and_chroma_request_to_same_size_fixed: %d\n"
1559                         "dcfclk_cstate_latency: %d\n",
1560                         dc->dcn_ip->rob_buffer_size_in_kbyte,
1561                         dc->dcn_ip->det_buffer_size_in_kbyte,
1562                         dc->dcn_ip->dpp_output_buffer_pixels,
1563                         dc->dcn_ip->opp_output_buffer_lines,
1564                         dc->dcn_ip->pixel_chunk_size_in_kbyte,
1565                         dc->dcn_ip->pte_enable,
1566                         dc->dcn_ip->pte_chunk_size,
1567                         dc->dcn_ip->meta_chunk_size,
1568                         dc->dcn_ip->writeback_chunk_size,
1569                         dc->dcn_ip->odm_capability,
1570                         dc->dcn_ip->dsc_capability,
1571                         dc->dcn_ip->line_buffer_size,
1572                         dc->dcn_ip->max_line_buffer_lines,
1573                         dc->dcn_ip->is_line_buffer_bpp_fixed,
1574                         dc->dcn_ip->line_buffer_fixed_bpp,
1575                         dc->dcn_ip->writeback_luma_buffer_size,
1576                         dc->dcn_ip->writeback_chroma_buffer_size,
1577                         dc->dcn_ip->max_num_dpp,
1578                         dc->dcn_ip->max_num_writeback,
1579                         dc->dcn_ip->max_dchub_topscl_throughput,
1580                         dc->dcn_ip->max_pscl_tolb_throughput,
1581                         dc->dcn_ip->max_lb_tovscl_throughput,
1582                         dc->dcn_ip->max_vscl_tohscl_throughput,
1583                         dc->dcn_ip->max_hscl_ratio,
1584                         dc->dcn_ip->max_vscl_ratio,
1585                         dc->dcn_ip->max_hscl_taps,
1586                         dc->dcn_ip->max_vscl_taps,
1587                         dc->dcn_ip->pte_buffer_size_in_requests,
1588                         dc->dcn_ip->dispclk_ramping_margin,
1589                         dc->dcn_ip->under_scan_factor * 100,
1590                         dc->dcn_ip->max_inter_dcn_tile_repeaters,
1591                         dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one,
1592                         dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed,
1593                         dc->dcn_ip->dcfclk_cstate_latency);
1594
1595         dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;
1596         dc->dml.soc.sr_enter_plus_exit_time_us = dc->dcn_soc->sr_enter_plus_exit_time;
1597         dc->dml.soc.urgent_latency_us = dc->dcn_soc->urgent_latency;
1598         dc->dml.soc.writeback_latency_us = dc->dcn_soc->write_back_latency;
1599         dc->dml.soc.ideal_dram_bw_after_urgent_percent =
1600                         dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency;
1601         dc->dml.soc.max_request_size_bytes = dc->dcn_soc->max_request_size;
1602         dc->dml.soc.downspread_percent = dc->dcn_soc->downspreading;
1603         dc->dml.soc.round_trip_ping_latency_dcfclk_cycles =
1604                         dc->dcn_soc->round_trip_ping_latency_cycles;
1605         dc->dml.soc.urgent_out_of_order_return_per_channel_bytes =
1606                         dc->dcn_soc->urgent_out_of_order_return_per_channel;
1607         dc->dml.soc.num_chans = dc->dcn_soc->number_of_channels;
1608         dc->dml.soc.vmm_page_size_bytes = dc->dcn_soc->vmm_page_size;
1609         dc->dml.soc.dram_clock_change_latency_us = dc->dcn_soc->dram_clock_change_latency;
1610         dc->dml.soc.return_bus_width_bytes = dc->dcn_soc->return_bus_width;
1611
1612         dc->dml.ip.rob_buffer_size_kbytes = dc->dcn_ip->rob_buffer_size_in_kbyte;
1613         dc->dml.ip.det_buffer_size_kbytes = dc->dcn_ip->det_buffer_size_in_kbyte;
1614         dc->dml.ip.dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels;
1615         dc->dml.ip.opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines;
1616         dc->dml.ip.pixel_chunk_size_kbytes = dc->dcn_ip->pixel_chunk_size_in_kbyte;
1617         dc->dml.ip.pte_enable = dc->dcn_ip->pte_enable == dcn_bw_yes;
1618         dc->dml.ip.pte_chunk_size_kbytes = dc->dcn_ip->pte_chunk_size;
1619         dc->dml.ip.meta_chunk_size_kbytes = dc->dcn_ip->meta_chunk_size;
1620         dc->dml.ip.writeback_chunk_size_kbytes = dc->dcn_ip->writeback_chunk_size;
1621         dc->dml.ip.line_buffer_size_bits = dc->dcn_ip->line_buffer_size;
1622         dc->dml.ip.max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines;
1623         dc->dml.ip.IsLineBufferBppFixed = dc->dcn_ip->is_line_buffer_bpp_fixed == dcn_bw_yes;
1624         dc->dml.ip.LineBufferFixedBpp = dc->dcn_ip->line_buffer_fixed_bpp;
1625         dc->dml.ip.writeback_luma_buffer_size_kbytes = dc->dcn_ip->writeback_luma_buffer_size;
1626         dc->dml.ip.writeback_chroma_buffer_size_kbytes = dc->dcn_ip->writeback_chroma_buffer_size;
1627         dc->dml.ip.max_num_dpp = dc->dcn_ip->max_num_dpp;
1628         dc->dml.ip.max_num_wb = dc->dcn_ip->max_num_writeback;
1629         dc->dml.ip.max_dchub_pscl_bw_pix_per_clk = dc->dcn_ip->max_dchub_topscl_throughput;
1630         dc->dml.ip.max_pscl_lb_bw_pix_per_clk = dc->dcn_ip->max_pscl_tolb_throughput;
1631         dc->dml.ip.max_lb_vscl_bw_pix_per_clk = dc->dcn_ip->max_lb_tovscl_throughput;
1632         dc->dml.ip.max_vscl_hscl_bw_pix_per_clk = dc->dcn_ip->max_vscl_tohscl_throughput;
1633         dc->dml.ip.max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;
1634         dc->dml.ip.max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;
1635         dc->dml.ip.max_hscl_taps = dc->dcn_ip->max_hscl_taps;
1636         dc->dml.ip.max_vscl_taps = dc->dcn_ip->max_vscl_taps;
1637         /*pte_buffer_size_in_requests missing in dml*/
1638         dc->dml.ip.dispclk_ramp_margin_percent = dc->dcn_ip->dispclk_ramping_margin;
1639         dc->dml.ip.underscan_factor = dc->dcn_ip->under_scan_factor;
1640         dc->dml.ip.max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters;
1641         dc->dml.ip.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =
1642                 dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes;
1643         dc->dml.ip.bug_forcing_LC_req_same_size_fixed =
1644                 dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes;
1645         dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip->dcfclk_cstate_latency;
1646         kernel_fpu_end();
1647 }