2 * Copyright 2015 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
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26 #ifndef __AMDGPU_DM_H__
27 #define __AMDGPU_DM_H__
29 #include <drm/drm_atomic.h>
30 #include <drm/drm_connector.h>
31 #include <drm/drm_crtc.h>
32 #include <drm/drm_dp_mst_helper.h>
33 #include <drm/drm_plane.h>
36 * This file contains the definition for amdgpu_display_manager
37 * and its API for amdgpu driver's use.
38 * This component provides all the display related functionality
39 * and this is the only component that calls DAL API.
40 * The API contained here intended for amdgpu driver use.
41 * The API that is called directly from KMS framework is located
42 * in amdgpu_dm_kms.h file
45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31
47 #include "include/amdgpu_dal_power_if.h"
48 #include "amdgpu_dm_irq.h"
51 #include "irq_types.h"
52 #include "signal_types.h"
53 #include "amdgpu_dm_crc.h"
55 /* Forward declarations */
58 struct amdgpu_dm_irq_handler_data;
61 struct common_irq_params {
62 struct amdgpu_device *adev;
63 enum dc_irq_source irq_src;
67 * struct irq_list_head - Linked-list for low context IRQ handlers.
69 * @head: The list_head within &struct handler_data
70 * @work: A work_struct containing the deferred handler work
72 struct irq_list_head {
73 struct list_head head;
74 /* In case this interrupt needs post-processing, 'work' will be queued*/
75 struct work_struct work;
79 * struct dm_compressor_info - Buffer info used by frame buffer compression
80 * @cpu_addr: MMIO cpu addr
81 * @bo_ptr: Pointer to the buffer object
82 * @gpu_addr: MMIO gpu addr
84 struct dm_comressor_info {
86 struct amdgpu_bo *bo_ptr;
91 * struct amdgpu_dm_backlight_caps - Usable range of backlight values from ACPI
92 * @min_input_signal: minimum possible input in range 0-255
93 * @max_input_signal: maximum possible input in range 0-255
94 * @caps_valid: true if these values are from the ACPI interface
96 struct amdgpu_dm_backlight_caps {
103 * struct amdgpu_display_manager - Central amdgpu display manager device
105 * @dc: Display Core control structure
106 * @adev: AMDGPU base driver structure
107 * @ddev: DRM base driver structure
108 * @display_indexes_num: Max number of display streams supported
109 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables
110 * @backlight_dev: Backlight control device
111 * @cached_state: Caches device atomic state for suspend/resume
112 * @compressor: Frame buffer compression buffer. See &struct dm_comressor_info
114 struct amdgpu_display_manager {
121 * The Common Graphics Services device. It provides an interface for
122 * accessing registers.
124 struct cgs_device *cgs_device;
126 struct amdgpu_device *adev;
127 struct drm_device *ddev;
128 u16 display_indexes_num;
133 * In combination with &dm_atomic_state it helps manage
134 * global atomic state that doesn't map cleanly into existing
135 * drm resources, like &dc_context.
137 struct drm_private_obj atomic_obj;
142 * Guards access to DC functions that can issue register write
145 struct mutex dc_lock;
150 * Guards access to audio instance changes.
152 struct mutex audio_lock;
157 * Used to notify ELD changes to sound driver.
159 struct drm_audio_component *audio_component;
164 * True if the audio component has been registered
165 * successfully, false otherwise.
167 bool audio_registered;
170 * @irq_handler_list_low_tab:
172 * Low priority IRQ handler table.
174 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ
175 * source. Low priority IRQ handlers are deferred to a workqueue to be
176 * processed. Hence, they can sleep.
178 * Note that handlers are called in the same order as they were
181 struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
184 * @irq_handler_list_high_tab:
186 * High priority IRQ handler table.
188 * It is a n*m table, same as &irq_handler_list_low_tab. However,
189 * handlers in this table are not deferred and are called immediately.
191 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
196 * Page flip IRQ parameters, passed to registered handlers when
199 struct common_irq_params
200 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
205 * Vertical blanking IRQ parameters, passed to registered handlers when
208 struct common_irq_params
209 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
214 * Vertical update IRQ parameters, passed to registered handlers when
217 struct common_irq_params
218 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1];
220 spinlock_t irq_handler_list_table_lock;
222 struct backlight_device *backlight_dev;
224 const struct dc_link *backlight_link;
225 struct amdgpu_dm_backlight_caps backlight_caps;
227 struct mod_freesync *freesync_module;
229 struct drm_atomic_state *cached_state;
231 struct dm_comressor_info compressor;
233 const struct firmware *fw_dmcu;
234 uint32_t dmcu_fw_version;
235 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
237 * gpu_info FW provided soc bounding box struct or 0 if not
240 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
244 struct amdgpu_dm_connector {
246 struct drm_connector base;
247 uint32_t connector_id;
249 /* we need to mind the EDID between detect
250 and get modes due to analog/digital/tvencoder */
253 /* shared with amdgpu */
254 struct amdgpu_hpd hpd;
256 /* number of modes generated from EDID at 'dc_sink' */
259 /* The 'old' sink - before an HPD.
260 * The 'current' sink is in dc_link->sink. */
261 struct dc_sink *dc_sink;
262 struct dc_link *dc_link;
263 struct dc_sink *dc_em_sink;
266 struct drm_dp_mst_topology_mgr mst_mgr;
267 struct amdgpu_dm_dp_aux dm_dp_aux;
268 struct drm_dp_mst_port *port;
269 struct amdgpu_dm_connector *mst_port;
270 struct amdgpu_encoder *mst_encoder;
272 /* TODO see if we can merge with ddc_bus or make a dm_connector */
273 struct amdgpu_i2c_adapter *i2c;
275 /* Monitor range limits */
280 /* Audio instance - protected by audio_lock. */
283 struct mutex hpd_lock;
286 #ifdef CONFIG_DEBUG_FS
287 uint32_t debugfs_dpcd_address;
288 uint32_t debugfs_dpcd_size;
292 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
294 extern const struct amdgpu_ip_block_version dm_ip_block;
296 struct amdgpu_framebuffer;
297 struct amdgpu_display_manager;
298 struct dc_validation_set;
299 struct dc_plane_state;
301 struct dm_plane_state {
302 struct drm_plane_state base;
303 struct dc_plane_state *dc_state;
306 struct dm_crtc_state {
307 struct drm_crtc_state base;
308 struct dc_stream_state *stream;
311 bool cm_is_degamma_srgb;
315 bool interrupts_enabled;
318 enum amdgpu_dm_pipe_crc_source crc_src;
320 bool freesync_timing_changed;
321 bool freesync_vrr_info_changed;
324 struct mod_freesync_config freesync_config;
325 struct mod_vrr_params vrr_params;
326 struct dc_info_packet vrr_infopacket;
331 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
333 struct dm_atomic_state {
334 struct drm_private_state base;
336 struct dc_state *context;
339 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
341 struct dm_connector_state {
342 struct drm_connector_state base;
344 enum amdgpu_rmx_type scaling;
345 uint8_t underscan_vborder;
346 uint8_t underscan_hborder;
347 bool underscan_enable;
348 bool freesync_capable;
352 #define to_dm_connector_state(x)\
353 container_of((x), struct dm_connector_state, base)
355 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
356 struct drm_connector_state *
357 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector);
358 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
359 struct drm_connector_state *state,
360 struct drm_property *property,
363 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
364 const struct drm_connector_state *state,
365 struct drm_property *property,
368 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);
370 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
371 struct amdgpu_dm_connector *aconnector,
373 struct dc_link *link,
376 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
377 struct drm_display_mode *mode);
379 void dm_restore_drm_connector_state(struct drm_device *dev,
380 struct drm_connector *connector);
382 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
385 #define MAX_COLOR_LUT_ENTRIES 4096
386 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */
387 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256
389 void amdgpu_dm_init_color_mod(void);
390 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);
391 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
392 struct dc_plane_state *dc_plane_state);
394 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
396 #endif /* __AMDGPU_DM_H__ */