2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 /* The caprices of the preprocessor require that this be declared right here */
27 #define CREATE_TRACE_POINTS
29 #include "dm_services_types.h"
31 #include "dc/inc/core_types.h"
32 #include "dal_asic_id.h"
36 #include "amdgpu_display.h"
37 #include "amdgpu_ucode.h"
39 #include "amdgpu_dm.h"
40 #include "amdgpu_pm.h"
42 #include "amd_shared.h"
43 #include "amdgpu_dm_irq.h"
44 #include "dm_helpers.h"
45 #include "amdgpu_dm_mst_types.h"
46 #if defined(CONFIG_DEBUG_FS)
47 #include "amdgpu_dm_debugfs.h"
50 #include "ivsrcid/ivsrcid_vislands30.h"
52 #include <linux/module.h>
53 #include <linux/moduleparam.h>
54 #include <linux/version.h>
55 #include <linux/types.h>
56 #include <linux/pm_runtime.h>
57 #include <linux/firmware.h>
60 #include <drm/drm_atomic.h>
61 #include <drm/drm_atomic_uapi.h>
62 #include <drm/drm_atomic_helper.h>
63 #include <drm/drm_dp_mst_helper.h>
64 #include <drm/drm_fb_helper.h>
65 #include <drm/drm_edid.h>
67 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
68 #include "ivsrcid/irqsrcs_dcn_1_0.h"
70 #include "dcn/dcn_1_0_offset.h"
71 #include "dcn/dcn_1_0_sh_mask.h"
72 #include "soc15_hw_ip.h"
73 #include "vega10_ip_offset.h"
75 #include "soc15_common.h"
78 #include "modules/inc/mod_freesync.h"
79 #include "modules/power/power_helpers.h"
80 #include "modules/inc/mod_info_packet.h"
82 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
83 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
88 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
89 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM
90 * requests into DC requests, and DC responses into DRM responses.
92 * The root control structure is &struct amdgpu_display_manager.
95 /* basic init/fini API */
96 static int amdgpu_dm_init(struct amdgpu_device *adev);
97 static void amdgpu_dm_fini(struct amdgpu_device *adev);
100 * initializes drm_device display related structures, based on the information
101 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
102 * drm_encoder, drm_mode_config
104 * Returns 0 on success
106 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
107 /* removes and deallocates the drm structures, created by the above function */
108 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
111 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
113 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
114 struct drm_plane *plane,
115 unsigned long possible_crtcs,
116 const struct dc_plane_cap *plane_cap);
117 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
118 struct drm_plane *plane,
119 uint32_t link_index);
120 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
121 struct amdgpu_dm_connector *amdgpu_dm_connector,
123 struct amdgpu_encoder *amdgpu_encoder);
124 static int amdgpu_dm_encoder_init(struct drm_device *dev,
125 struct amdgpu_encoder *aencoder,
126 uint32_t link_index);
128 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
130 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
131 struct drm_atomic_state *state,
134 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
136 static int amdgpu_dm_atomic_check(struct drm_device *dev,
137 struct drm_atomic_state *state);
139 static void handle_cursor_update(struct drm_plane *plane,
140 struct drm_plane_state *old_plane_state);
143 * dm_vblank_get_counter
146 * Get counter for number of vertical blanks
149 * struct amdgpu_device *adev - [in] desired amdgpu device
150 * int disp_idx - [in] which CRTC to get the counter from
153 * Counter for vertical blanks
155 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
157 if (crtc >= adev->mode_info.num_crtc)
160 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
161 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
165 if (acrtc_state->stream == NULL) {
166 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
171 return dc_stream_get_vblank_counter(acrtc_state->stream);
175 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
176 u32 *vbl, u32 *position)
178 uint32_t v_blank_start, v_blank_end, h_position, v_position;
180 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
183 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
184 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
187 if (acrtc_state->stream == NULL) {
188 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
194 * TODO rework base driver to use values directly.
195 * for now parse it back into reg-format
197 dc_stream_get_scanoutpos(acrtc_state->stream,
203 *position = v_position | (h_position << 16);
204 *vbl = v_blank_start | (v_blank_end << 16);
210 static bool dm_is_idle(void *handle)
216 static int dm_wait_for_idle(void *handle)
222 static bool dm_check_soft_reset(void *handle)
227 static int dm_soft_reset(void *handle)
233 static struct amdgpu_crtc *
234 get_crtc_by_otg_inst(struct amdgpu_device *adev,
237 struct drm_device *dev = adev->ddev;
238 struct drm_crtc *crtc;
239 struct amdgpu_crtc *amdgpu_crtc;
241 if (otg_inst == -1) {
243 return adev->mode_info.crtcs[0];
246 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
247 amdgpu_crtc = to_amdgpu_crtc(crtc);
249 if (amdgpu_crtc->otg_inst == otg_inst)
256 static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
258 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
259 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
262 static void dm_pflip_high_irq(void *interrupt_params)
264 struct amdgpu_crtc *amdgpu_crtc;
265 struct common_irq_params *irq_params = interrupt_params;
266 struct amdgpu_device *adev = irq_params->adev;
268 struct drm_pending_vblank_event *e;
269 struct dm_crtc_state *acrtc_state;
270 uint32_t vpos, hpos, v_blank_start, v_blank_end;
273 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
275 /* IRQ could occur when in initial stage */
276 /* TODO work and BO cleanup */
277 if (amdgpu_crtc == NULL) {
278 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
282 spin_lock_irqsave(&adev->ddev->event_lock, flags);
284 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
285 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
286 amdgpu_crtc->pflip_status,
287 AMDGPU_FLIP_SUBMITTED,
288 amdgpu_crtc->crtc_id,
290 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
294 /* page flip completed. */
295 e = amdgpu_crtc->event;
296 amdgpu_crtc->event = NULL;
301 acrtc_state = to_dm_crtc_state(amdgpu_crtc->base.state);
302 vrr_active = amdgpu_dm_vrr_active(acrtc_state);
304 /* Fixed refresh rate, or VRR scanout position outside front-porch? */
306 !dc_stream_get_scanoutpos(acrtc_state->stream, &v_blank_start,
307 &v_blank_end, &hpos, &vpos) ||
308 (vpos < v_blank_start)) {
309 /* Update to correct count and vblank timestamp if racing with
310 * vblank irq. This also updates to the correct vblank timestamp
311 * even in VRR mode, as scanout is past the front-porch atm.
313 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
315 /* Wake up userspace by sending the pageflip event with proper
316 * count and timestamp of vblank of flip completion.
319 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
321 /* Event sent, so done with vblank for this flip */
322 drm_crtc_vblank_put(&amdgpu_crtc->base);
325 /* VRR active and inside front-porch: vblank count and
326 * timestamp for pageflip event will only be up to date after
327 * drm_crtc_handle_vblank() has been executed from late vblank
328 * irq handler after start of back-porch (vline 0). We queue the
329 * pageflip event for send-out by drm_crtc_handle_vblank() with
330 * updated timestamp and count, once it runs after us.
332 * We need to open-code this instead of using the helper
333 * drm_crtc_arm_vblank_event(), as that helper would
334 * call drm_crtc_accurate_vblank_count(), which we must
335 * not call in VRR mode while we are in front-porch!
338 /* sequence will be replaced by real count during send-out. */
339 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
340 e->pipe = amdgpu_crtc->crtc_id;
342 list_add_tail(&e->base.link, &adev->ddev->vblank_event_list);
346 /* Keep track of vblank of this flip for flip throttling. We use the
347 * cooked hw counter, as that one incremented at start of this vblank
348 * of pageflip completion, so last_flip_vblank is the forbidden count
349 * for queueing new pageflips if vsync + VRR is enabled.
351 amdgpu_crtc->last_flip_vblank = amdgpu_get_vblank_counter_kms(adev->ddev,
352 amdgpu_crtc->crtc_id);
354 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
355 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
357 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
358 amdgpu_crtc->crtc_id, amdgpu_crtc,
359 vrr_active, (int) !e);
362 static void dm_vupdate_high_irq(void *interrupt_params)
364 struct common_irq_params *irq_params = interrupt_params;
365 struct amdgpu_device *adev = irq_params->adev;
366 struct amdgpu_crtc *acrtc;
367 struct dm_crtc_state *acrtc_state;
370 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
373 acrtc_state = to_dm_crtc_state(acrtc->base.state);
375 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
376 amdgpu_dm_vrr_active(acrtc_state));
378 /* Core vblank handling is done here after end of front-porch in
379 * vrr mode, as vblank timestamping will give valid results
380 * while now done after front-porch. This will also deliver
381 * page-flip completion events that have been queued to us
382 * if a pageflip happened inside front-porch.
384 if (amdgpu_dm_vrr_active(acrtc_state)) {
385 drm_crtc_handle_vblank(&acrtc->base);
387 /* BTR processing for pre-DCE12 ASICs */
388 if (acrtc_state->stream &&
389 adev->family < AMDGPU_FAMILY_AI) {
390 spin_lock_irqsave(&adev->ddev->event_lock, flags);
391 mod_freesync_handle_v_update(
392 adev->dm.freesync_module,
394 &acrtc_state->vrr_params);
396 dc_stream_adjust_vmin_vmax(
399 &acrtc_state->vrr_params.adjust);
400 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
406 static void dm_crtc_high_irq(void *interrupt_params)
408 struct common_irq_params *irq_params = interrupt_params;
409 struct amdgpu_device *adev = irq_params->adev;
410 struct amdgpu_crtc *acrtc;
411 struct dm_crtc_state *acrtc_state;
414 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
417 acrtc_state = to_dm_crtc_state(acrtc->base.state);
419 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
420 amdgpu_dm_vrr_active(acrtc_state));
422 /* Core vblank handling at start of front-porch is only possible
423 * in non-vrr mode, as only there vblank timestamping will give
424 * valid results while done in front-porch. Otherwise defer it
425 * to dm_vupdate_high_irq after end of front-porch.
427 if (!amdgpu_dm_vrr_active(acrtc_state))
428 drm_crtc_handle_vblank(&acrtc->base);
430 /* Following stuff must happen at start of vblank, for crc
431 * computation and below-the-range btr support in vrr mode.
433 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
435 if (acrtc_state->stream && adev->family >= AMDGPU_FAMILY_AI &&
436 acrtc_state->vrr_params.supported &&
437 acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
438 spin_lock_irqsave(&adev->ddev->event_lock, flags);
439 mod_freesync_handle_v_update(
440 adev->dm.freesync_module,
442 &acrtc_state->vrr_params);
444 dc_stream_adjust_vmin_vmax(
447 &acrtc_state->vrr_params.adjust);
448 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
453 static int dm_set_clockgating_state(void *handle,
454 enum amd_clockgating_state state)
459 static int dm_set_powergating_state(void *handle,
460 enum amd_powergating_state state)
465 /* Prototypes of private functions */
466 static int dm_early_init(void* handle);
468 /* Allocate memory for FBC compressed data */
469 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
471 struct drm_device *dev = connector->dev;
472 struct amdgpu_device *adev = dev->dev_private;
473 struct dm_comressor_info *compressor = &adev->dm.compressor;
474 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
475 struct drm_display_mode *mode;
476 unsigned long max_size = 0;
478 if (adev->dm.dc->fbc_compressor == NULL)
481 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
484 if (compressor->bo_ptr)
488 list_for_each_entry(mode, &connector->modes, head) {
489 if (max_size < mode->htotal * mode->vtotal)
490 max_size = mode->htotal * mode->vtotal;
494 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
495 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
496 &compressor->gpu_addr, &compressor->cpu_addr);
499 DRM_ERROR("DM: Failed to initialize FBC\n");
501 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
502 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
509 static int amdgpu_dm_init(struct amdgpu_device *adev)
511 struct dc_init_data init_data;
512 adev->dm.ddev = adev->ddev;
513 adev->dm.adev = adev;
515 /* Zero all the fields */
516 memset(&init_data, 0, sizeof(init_data));
518 mutex_init(&adev->dm.dc_lock);
520 if(amdgpu_dm_irq_init(adev)) {
521 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
525 init_data.asic_id.chip_family = adev->family;
527 init_data.asic_id.pci_revision_id = adev->rev_id;
528 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
530 init_data.asic_id.vram_width = adev->gmc.vram_width;
531 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
532 init_data.asic_id.atombios_base_address =
533 adev->mode_info.atom_context->bios;
535 init_data.driver = adev;
537 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
539 if (!adev->dm.cgs_device) {
540 DRM_ERROR("amdgpu: failed to create cgs device.\n");
544 init_data.cgs_device = adev->dm.cgs_device;
546 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
549 * TODO debug why this doesn't work on Raven
551 if (adev->flags & AMD_IS_APU &&
552 adev->asic_type >= CHIP_CARRIZO &&
553 adev->asic_type < CHIP_RAVEN)
554 init_data.flags.gpu_vm_support = true;
556 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
557 init_data.flags.fbc_support = true;
559 init_data.flags.power_down_display_on_boot = true;
561 /* Display Core create. */
562 adev->dm.dc = dc_create(&init_data);
565 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
567 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
571 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
572 if (!adev->dm.freesync_module) {
574 "amdgpu: failed to initialize freesync_module.\n");
576 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
577 adev->dm.freesync_module);
579 amdgpu_dm_init_color_mod();
581 if (amdgpu_dm_initialize_drm_device(adev)) {
583 "amdgpu: failed to initialize sw for display support.\n");
587 /* Update the actual used number of crtc */
588 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
590 /* TODO: Add_display_info? */
592 /* TODO use dynamic cursor width */
593 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
594 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
596 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
598 "amdgpu: failed to initialize sw for display support.\n");
602 #if defined(CONFIG_DEBUG_FS)
603 if (dtn_debugfs_init(adev))
604 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
607 DRM_DEBUG_DRIVER("KMS initialized.\n");
611 amdgpu_dm_fini(adev);
616 static void amdgpu_dm_fini(struct amdgpu_device *adev)
618 amdgpu_dm_destroy_drm_device(&adev->dm);
620 * TODO: pageflip, vlank interrupt
622 * amdgpu_dm_irq_fini(adev);
625 if (adev->dm.cgs_device) {
626 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
627 adev->dm.cgs_device = NULL;
629 if (adev->dm.freesync_module) {
630 mod_freesync_destroy(adev->dm.freesync_module);
631 adev->dm.freesync_module = NULL;
633 /* DC Destroy TODO: Replace destroy DAL */
635 dc_destroy(&adev->dm.dc);
637 mutex_destroy(&adev->dm.dc_lock);
642 static int load_dmcu_fw(struct amdgpu_device *adev)
644 const char *fw_name_dmcu = NULL;
646 const struct dmcu_firmware_header_v1_0 *hdr;
648 switch(adev->asic_type) {
667 #if defined(CONFIG_DRM_AMD_DC_DCN1_01)
668 if (ASICREV_IS_PICASSO(adev->external_rev_id))
669 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
670 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
671 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
677 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
681 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
682 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
686 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
688 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
689 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
690 adev->dm.fw_dmcu = NULL;
694 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
699 r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
701 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
703 release_firmware(adev->dm.fw_dmcu);
704 adev->dm.fw_dmcu = NULL;
708 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
709 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
710 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
711 adev->firmware.fw_size +=
712 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
714 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
715 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
716 adev->firmware.fw_size +=
717 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
719 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
721 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
726 static int dm_sw_init(void *handle)
728 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
730 return load_dmcu_fw(adev);
733 static int dm_sw_fini(void *handle)
735 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
737 if(adev->dm.fw_dmcu) {
738 release_firmware(adev->dm.fw_dmcu);
739 adev->dm.fw_dmcu = NULL;
745 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
747 struct amdgpu_dm_connector *aconnector;
748 struct drm_connector *connector;
751 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
753 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
754 aconnector = to_amdgpu_dm_connector(connector);
755 if (aconnector->dc_link->type == dc_connection_mst_branch &&
756 aconnector->mst_mgr.aux) {
757 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
758 aconnector, aconnector->base.base.id);
760 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
762 DRM_ERROR("DM_MST: Failed to start MST\n");
763 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
769 drm_modeset_unlock(&dev->mode_config.connection_mutex);
773 static int dm_late_init(void *handle)
775 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
777 struct dmcu_iram_parameters params;
778 unsigned int linear_lut[16];
780 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
783 for (i = 0; i < 16; i++)
784 linear_lut[i] = 0xFFFF * i / 15;
787 params.backlight_ramping_start = 0xCCCC;
788 params.backlight_ramping_reduction = 0xCCCCCCCC;
789 params.backlight_lut_array_size = 16;
790 params.backlight_lut_array = linear_lut;
792 ret = dmcu_load_iram(dmcu, params);
797 return detect_mst_link_for_all_connectors(adev->ddev);
800 static void s3_handle_mst(struct drm_device *dev, bool suspend)
802 struct amdgpu_dm_connector *aconnector;
803 struct drm_connector *connector;
804 struct drm_dp_mst_topology_mgr *mgr;
806 bool need_hotplug = false;
808 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
810 list_for_each_entry(connector, &dev->mode_config.connector_list,
812 aconnector = to_amdgpu_dm_connector(connector);
813 if (aconnector->dc_link->type != dc_connection_mst_branch ||
814 aconnector->mst_port)
817 mgr = &aconnector->mst_mgr;
820 drm_dp_mst_topology_mgr_suspend(mgr);
822 ret = drm_dp_mst_topology_mgr_resume(mgr);
824 drm_dp_mst_topology_mgr_set_mst(mgr, false);
830 drm_modeset_unlock(&dev->mode_config.connection_mutex);
833 drm_kms_helper_hotplug_event(dev);
837 * dm_hw_init() - Initialize DC device
838 * @handle: The base driver device containing the amdpgu_dm device.
840 * Initialize the &struct amdgpu_display_manager device. This involves calling
841 * the initializers of each DM component, then populating the struct with them.
843 * Although the function implies hardware initialization, both hardware and
844 * software are initialized here. Splitting them out to their relevant init
845 * hooks is a future TODO item.
847 * Some notable things that are initialized here:
849 * - Display Core, both software and hardware
850 * - DC modules that we need (freesync and color management)
851 * - DRM software states
852 * - Interrupt sources and handlers
854 * - Debug FS entries, if enabled
856 static int dm_hw_init(void *handle)
858 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
859 /* Create DAL display manager */
860 amdgpu_dm_init(adev);
861 amdgpu_dm_hpd_init(adev);
867 * dm_hw_fini() - Teardown DC device
868 * @handle: The base driver device containing the amdpgu_dm device.
870 * Teardown components within &struct amdgpu_display_manager that require
871 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
872 * were loaded. Also flush IRQ workqueues and disable them.
874 static int dm_hw_fini(void *handle)
876 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
878 amdgpu_dm_hpd_fini(adev);
880 amdgpu_dm_irq_fini(adev);
881 amdgpu_dm_fini(adev);
885 static int dm_suspend(void *handle)
887 struct amdgpu_device *adev = handle;
888 struct amdgpu_display_manager *dm = &adev->dm;
891 WARN_ON(adev->dm.cached_state);
892 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
894 s3_handle_mst(adev->ddev, true);
896 amdgpu_dm_irq_suspend(adev);
899 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
904 static struct amdgpu_dm_connector *
905 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
906 struct drm_crtc *crtc)
909 struct drm_connector_state *new_con_state;
910 struct drm_connector *connector;
911 struct drm_crtc *crtc_from_state;
913 for_each_new_connector_in_state(state, connector, new_con_state, i) {
914 crtc_from_state = new_con_state->crtc;
916 if (crtc_from_state == crtc)
917 return to_amdgpu_dm_connector(connector);
923 static void emulated_link_detect(struct dc_link *link)
925 struct dc_sink_init_data sink_init_data = { 0 };
926 struct display_sink_capability sink_caps = { 0 };
927 enum dc_edid_status edid_status;
928 struct dc_context *dc_ctx = link->ctx;
929 struct dc_sink *sink = NULL;
930 struct dc_sink *prev_sink = NULL;
932 link->type = dc_connection_none;
933 prev_sink = link->local_sink;
935 if (prev_sink != NULL)
936 dc_sink_retain(prev_sink);
938 switch (link->connector_signal) {
939 case SIGNAL_TYPE_HDMI_TYPE_A: {
940 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
941 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
945 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
946 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
947 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
951 case SIGNAL_TYPE_DVI_DUAL_LINK: {
952 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
953 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
957 case SIGNAL_TYPE_LVDS: {
958 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
959 sink_caps.signal = SIGNAL_TYPE_LVDS;
963 case SIGNAL_TYPE_EDP: {
964 sink_caps.transaction_type =
965 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
966 sink_caps.signal = SIGNAL_TYPE_EDP;
970 case SIGNAL_TYPE_DISPLAY_PORT: {
971 sink_caps.transaction_type =
972 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
973 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
978 DC_ERROR("Invalid connector type! signal:%d\n",
979 link->connector_signal);
983 sink_init_data.link = link;
984 sink_init_data.sink_signal = sink_caps.signal;
986 sink = dc_sink_create(&sink_init_data);
988 DC_ERROR("Failed to create sink!\n");
992 /* dc_sink_create returns a new reference */
993 link->local_sink = sink;
995 edid_status = dm_helpers_read_local_edid(
1000 if (edid_status != EDID_OK)
1001 DC_ERROR("Failed to read EDID");
1005 static int dm_resume(void *handle)
1007 struct amdgpu_device *adev = handle;
1008 struct drm_device *ddev = adev->ddev;
1009 struct amdgpu_display_manager *dm = &adev->dm;
1010 struct amdgpu_dm_connector *aconnector;
1011 struct drm_connector *connector;
1012 struct drm_crtc *crtc;
1013 struct drm_crtc_state *new_crtc_state;
1014 struct dm_crtc_state *dm_new_crtc_state;
1015 struct drm_plane *plane;
1016 struct drm_plane_state *new_plane_state;
1017 struct dm_plane_state *dm_new_plane_state;
1018 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
1019 enum dc_connection_type new_connection_type = dc_connection_none;
1022 /* Recreate dc_state - DC invalidates it when setting power state to S3. */
1023 dc_release_state(dm_state->context);
1024 dm_state->context = dc_create_state(dm->dc);
1025 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
1026 dc_resource_state_construct(dm->dc, dm_state->context);
1028 /* power on hardware */
1029 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
1031 /* program HPD filter */
1034 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
1035 s3_handle_mst(ddev, false);
1038 * early enable HPD Rx IRQ, should be done before set mode as short
1039 * pulse interrupts are used for MST
1041 amdgpu_dm_irq_resume_early(adev);
1044 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
1045 aconnector = to_amdgpu_dm_connector(connector);
1048 * this is the case when traversing through already created
1049 * MST connectors, should be skipped
1051 if (aconnector->mst_port)
1054 mutex_lock(&aconnector->hpd_lock);
1055 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1056 DRM_ERROR("KMS: Failed to detect connector\n");
1058 if (aconnector->base.force && new_connection_type == dc_connection_none)
1059 emulated_link_detect(aconnector->dc_link);
1061 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
1063 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
1064 aconnector->fake_enable = false;
1066 if (aconnector->dc_sink)
1067 dc_sink_release(aconnector->dc_sink);
1068 aconnector->dc_sink = NULL;
1069 amdgpu_dm_update_connector_after_detect(aconnector);
1070 mutex_unlock(&aconnector->hpd_lock);
1073 /* Force mode set in atomic commit */
1074 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
1075 new_crtc_state->active_changed = true;
1078 * atomic_check is expected to create the dc states. We need to release
1079 * them here, since they were duplicated as part of the suspend
1082 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
1083 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1084 if (dm_new_crtc_state->stream) {
1085 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
1086 dc_stream_release(dm_new_crtc_state->stream);
1087 dm_new_crtc_state->stream = NULL;
1091 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
1092 dm_new_plane_state = to_dm_plane_state(new_plane_state);
1093 if (dm_new_plane_state->dc_state) {
1094 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
1095 dc_plane_state_release(dm_new_plane_state->dc_state);
1096 dm_new_plane_state->dc_state = NULL;
1100 drm_atomic_helper_resume(ddev, dm->cached_state);
1102 dm->cached_state = NULL;
1104 amdgpu_dm_irq_resume_late(adev);
1112 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
1113 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
1114 * the base driver's device list to be initialized and torn down accordingly.
1116 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
1119 static const struct amd_ip_funcs amdgpu_dm_funcs = {
1121 .early_init = dm_early_init,
1122 .late_init = dm_late_init,
1123 .sw_init = dm_sw_init,
1124 .sw_fini = dm_sw_fini,
1125 .hw_init = dm_hw_init,
1126 .hw_fini = dm_hw_fini,
1127 .suspend = dm_suspend,
1128 .resume = dm_resume,
1129 .is_idle = dm_is_idle,
1130 .wait_for_idle = dm_wait_for_idle,
1131 .check_soft_reset = dm_check_soft_reset,
1132 .soft_reset = dm_soft_reset,
1133 .set_clockgating_state = dm_set_clockgating_state,
1134 .set_powergating_state = dm_set_powergating_state,
1137 const struct amdgpu_ip_block_version dm_ip_block =
1139 .type = AMD_IP_BLOCK_TYPE_DCE,
1143 .funcs = &amdgpu_dm_funcs,
1153 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
1154 .fb_create = amdgpu_display_user_framebuffer_create,
1155 .output_poll_changed = drm_fb_helper_output_poll_changed,
1156 .atomic_check = amdgpu_dm_atomic_check,
1157 .atomic_commit = amdgpu_dm_atomic_commit,
1160 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
1161 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
1165 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
1167 struct drm_connector *connector = &aconnector->base;
1168 struct drm_device *dev = connector->dev;
1169 struct dc_sink *sink;
1171 /* MST handled by drm_mst framework */
1172 if (aconnector->mst_mgr.mst_state == true)
1176 sink = aconnector->dc_link->local_sink;
1178 dc_sink_retain(sink);
1181 * Edid mgmt connector gets first update only in mode_valid hook and then
1182 * the connector sink is set to either fake or physical sink depends on link status.
1183 * Skip if already done during boot.
1185 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
1186 && aconnector->dc_em_sink) {
1189 * For S3 resume with headless use eml_sink to fake stream
1190 * because on resume connector->sink is set to NULL
1192 mutex_lock(&dev->mode_config.mutex);
1195 if (aconnector->dc_sink) {
1196 amdgpu_dm_update_freesync_caps(connector, NULL);
1198 * retain and release below are used to
1199 * bump up refcount for sink because the link doesn't point
1200 * to it anymore after disconnect, so on next crtc to connector
1201 * reshuffle by UMD we will get into unwanted dc_sink release
1203 dc_sink_release(aconnector->dc_sink);
1205 aconnector->dc_sink = sink;
1206 dc_sink_retain(aconnector->dc_sink);
1207 amdgpu_dm_update_freesync_caps(connector,
1210 amdgpu_dm_update_freesync_caps(connector, NULL);
1211 if (!aconnector->dc_sink) {
1212 aconnector->dc_sink = aconnector->dc_em_sink;
1213 dc_sink_retain(aconnector->dc_sink);
1217 mutex_unlock(&dev->mode_config.mutex);
1220 dc_sink_release(sink);
1225 * TODO: temporary guard to look for proper fix
1226 * if this sink is MST sink, we should not do anything
1228 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1229 dc_sink_release(sink);
1233 if (aconnector->dc_sink == sink) {
1235 * We got a DP short pulse (Link Loss, DP CTS, etc...).
1238 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
1239 aconnector->connector_id);
1241 dc_sink_release(sink);
1245 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
1246 aconnector->connector_id, aconnector->dc_sink, sink);
1248 mutex_lock(&dev->mode_config.mutex);
1251 * 1. Update status of the drm connector
1252 * 2. Send an event and let userspace tell us what to do
1256 * TODO: check if we still need the S3 mode update workaround.
1257 * If yes, put it here.
1259 if (aconnector->dc_sink)
1260 amdgpu_dm_update_freesync_caps(connector, NULL);
1262 aconnector->dc_sink = sink;
1263 dc_sink_retain(aconnector->dc_sink);
1264 if (sink->dc_edid.length == 0) {
1265 aconnector->edid = NULL;
1266 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
1269 (struct edid *) sink->dc_edid.raw_edid;
1272 drm_connector_update_edid_property(connector,
1274 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
1277 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
1280 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
1281 amdgpu_dm_update_freesync_caps(connector, NULL);
1282 drm_connector_update_edid_property(connector, NULL);
1283 aconnector->num_modes = 0;
1284 dc_sink_release(aconnector->dc_sink);
1285 aconnector->dc_sink = NULL;
1286 aconnector->edid = NULL;
1289 mutex_unlock(&dev->mode_config.mutex);
1292 dc_sink_release(sink);
1295 static void handle_hpd_irq(void *param)
1297 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1298 struct drm_connector *connector = &aconnector->base;
1299 struct drm_device *dev = connector->dev;
1300 enum dc_connection_type new_connection_type = dc_connection_none;
1303 * In case of failure or MST no need to update connector status or notify the OS
1304 * since (for MST case) MST does this in its own context.
1306 mutex_lock(&aconnector->hpd_lock);
1308 if (aconnector->fake_enable)
1309 aconnector->fake_enable = false;
1311 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1312 DRM_ERROR("KMS: Failed to detect connector\n");
1314 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1315 emulated_link_detect(aconnector->dc_link);
1318 drm_modeset_lock_all(dev);
1319 dm_restore_drm_connector_state(dev, connector);
1320 drm_modeset_unlock_all(dev);
1322 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1323 drm_kms_helper_hotplug_event(dev);
1325 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
1326 amdgpu_dm_update_connector_after_detect(aconnector);
1329 drm_modeset_lock_all(dev);
1330 dm_restore_drm_connector_state(dev, connector);
1331 drm_modeset_unlock_all(dev);
1333 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1334 drm_kms_helper_hotplug_event(dev);
1336 mutex_unlock(&aconnector->hpd_lock);
1340 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
1342 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
1344 bool new_irq_handled = false;
1346 int dpcd_bytes_to_read;
1348 const int max_process_count = 30;
1349 int process_count = 0;
1351 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
1353 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
1354 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
1355 /* DPCD 0x200 - 0x201 for downstream IRQ */
1356 dpcd_addr = DP_SINK_COUNT;
1358 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
1359 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
1360 dpcd_addr = DP_SINK_COUNT_ESI;
1363 dret = drm_dp_dpcd_read(
1364 &aconnector->dm_dp_aux.aux,
1367 dpcd_bytes_to_read);
1369 while (dret == dpcd_bytes_to_read &&
1370 process_count < max_process_count) {
1376 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
1377 /* handle HPD short pulse irq */
1378 if (aconnector->mst_mgr.mst_state)
1380 &aconnector->mst_mgr,
1384 if (new_irq_handled) {
1385 /* ACK at DPCD to notify down stream */
1386 const int ack_dpcd_bytes_to_write =
1387 dpcd_bytes_to_read - 1;
1389 for (retry = 0; retry < 3; retry++) {
1392 wret = drm_dp_dpcd_write(
1393 &aconnector->dm_dp_aux.aux,
1396 ack_dpcd_bytes_to_write);
1397 if (wret == ack_dpcd_bytes_to_write)
1401 /* check if there is new irq to be handled */
1402 dret = drm_dp_dpcd_read(
1403 &aconnector->dm_dp_aux.aux,
1406 dpcd_bytes_to_read);
1408 new_irq_handled = false;
1414 if (process_count == max_process_count)
1415 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
1418 static void handle_hpd_rx_irq(void *param)
1420 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1421 struct drm_connector *connector = &aconnector->base;
1422 struct drm_device *dev = connector->dev;
1423 struct dc_link *dc_link = aconnector->dc_link;
1424 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
1425 enum dc_connection_type new_connection_type = dc_connection_none;
1428 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1429 * conflict, after implement i2c helper, this mutex should be
1432 if (dc_link->type != dc_connection_mst_branch)
1433 mutex_lock(&aconnector->hpd_lock);
1435 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
1436 !is_mst_root_connector) {
1437 /* Downstream Port status changed. */
1438 if (!dc_link_detect_sink(dc_link, &new_connection_type))
1439 DRM_ERROR("KMS: Failed to detect connector\n");
1441 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1442 emulated_link_detect(dc_link);
1444 if (aconnector->fake_enable)
1445 aconnector->fake_enable = false;
1447 amdgpu_dm_update_connector_after_detect(aconnector);
1450 drm_modeset_lock_all(dev);
1451 dm_restore_drm_connector_state(dev, connector);
1452 drm_modeset_unlock_all(dev);
1454 drm_kms_helper_hotplug_event(dev);
1455 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
1457 if (aconnector->fake_enable)
1458 aconnector->fake_enable = false;
1460 amdgpu_dm_update_connector_after_detect(aconnector);
1463 drm_modeset_lock_all(dev);
1464 dm_restore_drm_connector_state(dev, connector);
1465 drm_modeset_unlock_all(dev);
1467 drm_kms_helper_hotplug_event(dev);
1470 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1471 (dc_link->type == dc_connection_mst_branch))
1472 dm_handle_hpd_rx_irq(aconnector);
1474 if (dc_link->type != dc_connection_mst_branch) {
1475 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
1476 mutex_unlock(&aconnector->hpd_lock);
1480 static void register_hpd_handlers(struct amdgpu_device *adev)
1482 struct drm_device *dev = adev->ddev;
1483 struct drm_connector *connector;
1484 struct amdgpu_dm_connector *aconnector;
1485 const struct dc_link *dc_link;
1486 struct dc_interrupt_params int_params = {0};
1488 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1489 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1491 list_for_each_entry(connector,
1492 &dev->mode_config.connector_list, head) {
1494 aconnector = to_amdgpu_dm_connector(connector);
1495 dc_link = aconnector->dc_link;
1497 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1498 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1499 int_params.irq_source = dc_link->irq_source_hpd;
1501 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1503 (void *) aconnector);
1506 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1508 /* Also register for DP short pulse (hpd_rx). */
1509 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1510 int_params.irq_source = dc_link->irq_source_hpd_rx;
1512 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1514 (void *) aconnector);
1519 /* Register IRQ sources and initialize IRQ callbacks */
1520 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1522 struct dc *dc = adev->dm.dc;
1523 struct common_irq_params *c_irq_params;
1524 struct dc_interrupt_params int_params = {0};
1527 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
1529 if (adev->asic_type == CHIP_VEGA10 ||
1530 adev->asic_type == CHIP_VEGA12 ||
1531 adev->asic_type == CHIP_VEGA20 ||
1532 adev->asic_type == CHIP_RAVEN)
1533 client_id = SOC15_IH_CLIENTID_DCE;
1535 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1536 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1539 * Actions of amdgpu_irq_add_id():
1540 * 1. Register a set() function with base driver.
1541 * Base driver will call set() function to enable/disable an
1542 * interrupt in DC hardware.
1543 * 2. Register amdgpu_dm_irq_handler().
1544 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1545 * coming from DC hardware.
1546 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1547 * for acknowledging and handling. */
1549 /* Use VBLANK interrupt */
1550 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
1551 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
1553 DRM_ERROR("Failed to add crtc irq id!\n");
1557 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1558 int_params.irq_source =
1559 dc_interrupt_to_irq_source(dc, i, 0);
1561 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1563 c_irq_params->adev = adev;
1564 c_irq_params->irq_src = int_params.irq_source;
1566 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1567 dm_crtc_high_irq, c_irq_params);
1570 /* Use VUPDATE interrupt */
1571 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
1572 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
1574 DRM_ERROR("Failed to add vupdate irq id!\n");
1578 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1579 int_params.irq_source =
1580 dc_interrupt_to_irq_source(dc, i, 0);
1582 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
1584 c_irq_params->adev = adev;
1585 c_irq_params->irq_src = int_params.irq_source;
1587 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1588 dm_vupdate_high_irq, c_irq_params);
1591 /* Use GRPH_PFLIP interrupt */
1592 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1593 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
1594 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
1596 DRM_ERROR("Failed to add page flip irq id!\n");
1600 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1601 int_params.irq_source =
1602 dc_interrupt_to_irq_source(dc, i, 0);
1604 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1606 c_irq_params->adev = adev;
1607 c_irq_params->irq_src = int_params.irq_source;
1609 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1610 dm_pflip_high_irq, c_irq_params);
1615 r = amdgpu_irq_add_id(adev, client_id,
1616 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
1618 DRM_ERROR("Failed to add hpd irq id!\n");
1622 register_hpd_handlers(adev);
1627 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1628 /* Register IRQ sources and initialize IRQ callbacks */
1629 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1631 struct dc *dc = adev->dm.dc;
1632 struct common_irq_params *c_irq_params;
1633 struct dc_interrupt_params int_params = {0};
1637 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1638 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1641 * Actions of amdgpu_irq_add_id():
1642 * 1. Register a set() function with base driver.
1643 * Base driver will call set() function to enable/disable an
1644 * interrupt in DC hardware.
1645 * 2. Register amdgpu_dm_irq_handler().
1646 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1647 * coming from DC hardware.
1648 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1649 * for acknowledging and handling.
1652 /* Use VSTARTUP interrupt */
1653 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1654 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1656 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1659 DRM_ERROR("Failed to add crtc irq id!\n");
1663 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1664 int_params.irq_source =
1665 dc_interrupt_to_irq_source(dc, i, 0);
1667 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1669 c_irq_params->adev = adev;
1670 c_irq_params->irq_src = int_params.irq_source;
1672 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1673 dm_crtc_high_irq, c_irq_params);
1676 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
1677 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
1678 * to trigger at end of each vblank, regardless of state of the lock,
1679 * matching DCE behaviour.
1681 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
1682 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
1684 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
1687 DRM_ERROR("Failed to add vupdate irq id!\n");
1691 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1692 int_params.irq_source =
1693 dc_interrupt_to_irq_source(dc, i, 0);
1695 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
1697 c_irq_params->adev = adev;
1698 c_irq_params->irq_src = int_params.irq_source;
1700 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1701 dm_vupdate_high_irq, c_irq_params);
1704 /* Use GRPH_PFLIP interrupt */
1705 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1706 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1708 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1710 DRM_ERROR("Failed to add page flip irq id!\n");
1714 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1715 int_params.irq_source =
1716 dc_interrupt_to_irq_source(dc, i, 0);
1718 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1720 c_irq_params->adev = adev;
1721 c_irq_params->irq_src = int_params.irq_source;
1723 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1724 dm_pflip_high_irq, c_irq_params);
1729 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1732 DRM_ERROR("Failed to add hpd irq id!\n");
1736 register_hpd_handlers(adev);
1743 * Acquires the lock for the atomic state object and returns
1744 * the new atomic state.
1746 * This should only be called during atomic check.
1748 static int dm_atomic_get_state(struct drm_atomic_state *state,
1749 struct dm_atomic_state **dm_state)
1751 struct drm_device *dev = state->dev;
1752 struct amdgpu_device *adev = dev->dev_private;
1753 struct amdgpu_display_manager *dm = &adev->dm;
1754 struct drm_private_state *priv_state;
1759 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
1760 if (IS_ERR(priv_state))
1761 return PTR_ERR(priv_state);
1763 *dm_state = to_dm_atomic_state(priv_state);
1768 struct dm_atomic_state *
1769 dm_atomic_get_new_state(struct drm_atomic_state *state)
1771 struct drm_device *dev = state->dev;
1772 struct amdgpu_device *adev = dev->dev_private;
1773 struct amdgpu_display_manager *dm = &adev->dm;
1774 struct drm_private_obj *obj;
1775 struct drm_private_state *new_obj_state;
1778 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
1779 if (obj->funcs == dm->atomic_obj.funcs)
1780 return to_dm_atomic_state(new_obj_state);
1786 struct dm_atomic_state *
1787 dm_atomic_get_old_state(struct drm_atomic_state *state)
1789 struct drm_device *dev = state->dev;
1790 struct amdgpu_device *adev = dev->dev_private;
1791 struct amdgpu_display_manager *dm = &adev->dm;
1792 struct drm_private_obj *obj;
1793 struct drm_private_state *old_obj_state;
1796 for_each_old_private_obj_in_state(state, obj, old_obj_state, i) {
1797 if (obj->funcs == dm->atomic_obj.funcs)
1798 return to_dm_atomic_state(old_obj_state);
1804 static struct drm_private_state *
1805 dm_atomic_duplicate_state(struct drm_private_obj *obj)
1807 struct dm_atomic_state *old_state, *new_state;
1809 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
1813 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
1815 old_state = to_dm_atomic_state(obj->state);
1817 if (old_state && old_state->context)
1818 new_state->context = dc_copy_state(old_state->context);
1820 if (!new_state->context) {
1825 return &new_state->base;
1828 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
1829 struct drm_private_state *state)
1831 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
1833 if (dm_state && dm_state->context)
1834 dc_release_state(dm_state->context);
1839 static struct drm_private_state_funcs dm_atomic_state_funcs = {
1840 .atomic_duplicate_state = dm_atomic_duplicate_state,
1841 .atomic_destroy_state = dm_atomic_destroy_state,
1844 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1846 struct dm_atomic_state *state;
1849 adev->mode_info.mode_config_initialized = true;
1851 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
1852 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
1854 adev->ddev->mode_config.max_width = 16384;
1855 adev->ddev->mode_config.max_height = 16384;
1857 adev->ddev->mode_config.preferred_depth = 24;
1858 adev->ddev->mode_config.prefer_shadow = 1;
1859 /* indicates support for immediate flip */
1860 adev->ddev->mode_config.async_page_flip = true;
1862 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
1864 state = kzalloc(sizeof(*state), GFP_KERNEL);
1868 state->context = dc_create_state(adev->dm.dc);
1869 if (!state->context) {
1874 dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
1876 drm_atomic_private_obj_init(adev->ddev,
1877 &adev->dm.atomic_obj,
1879 &dm_atomic_state_funcs);
1881 r = amdgpu_display_modeset_create_props(adev);
1888 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
1889 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
1891 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1892 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1894 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
1896 #if defined(CONFIG_ACPI)
1897 struct amdgpu_dm_backlight_caps caps;
1899 if (dm->backlight_caps.caps_valid)
1902 amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
1903 if (caps.caps_valid) {
1904 dm->backlight_caps.min_input_signal = caps.min_input_signal;
1905 dm->backlight_caps.max_input_signal = caps.max_input_signal;
1906 dm->backlight_caps.caps_valid = true;
1908 dm->backlight_caps.min_input_signal =
1909 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
1910 dm->backlight_caps.max_input_signal =
1911 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
1914 dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
1915 dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
1919 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1921 struct amdgpu_display_manager *dm = bl_get_data(bd);
1922 struct amdgpu_dm_backlight_caps caps;
1923 uint32_t brightness = bd->props.brightness;
1925 amdgpu_dm_update_backlight_caps(dm);
1926 caps = dm->backlight_caps;
1928 * The brightness input is in the range 0-255
1929 * It needs to be rescaled to be between the
1930 * requested min and max input signal
1932 * It also needs to be scaled up by 0x101 to
1933 * match the DC interface which has a range of
1939 * (caps.max_input_signal - caps.min_input_signal)
1940 / AMDGPU_MAX_BL_LEVEL
1941 + caps.min_input_signal * 0x101;
1943 if (dc_link_set_backlight_level(dm->backlight_link,
1950 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1952 struct amdgpu_display_manager *dm = bl_get_data(bd);
1953 int ret = dc_link_get_backlight_level(dm->backlight_link);
1955 if (ret == DC_ERROR_UNEXPECTED)
1956 return bd->props.brightness;
1960 static const struct backlight_ops amdgpu_dm_backlight_ops = {
1961 .get_brightness = amdgpu_dm_backlight_get_brightness,
1962 .update_status = amdgpu_dm_backlight_update_status,
1966 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
1969 struct backlight_properties props = { 0 };
1971 amdgpu_dm_update_backlight_caps(dm);
1973 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
1974 props.brightness = AMDGPU_MAX_BL_LEVEL;
1975 props.type = BACKLIGHT_RAW;
1977 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1978 dm->adev->ddev->primary->index);
1980 dm->backlight_dev = backlight_device_register(bl_name,
1981 dm->adev->ddev->dev,
1983 &amdgpu_dm_backlight_ops,
1986 if (IS_ERR(dm->backlight_dev))
1987 DRM_ERROR("DM: Backlight registration failed!\n");
1989 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
1994 static int initialize_plane(struct amdgpu_display_manager *dm,
1995 struct amdgpu_mode_info *mode_info, int plane_id,
1996 enum drm_plane_type plane_type,
1997 const struct dc_plane_cap *plane_cap)
1999 struct drm_plane *plane;
2000 unsigned long possible_crtcs;
2003 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
2005 DRM_ERROR("KMS: Failed to allocate plane\n");
2008 plane->type = plane_type;
2011 * HACK: IGT tests expect that the primary plane for a CRTC
2012 * can only have one possible CRTC. Only expose support for
2013 * any CRTC if they're not going to be used as a primary plane
2014 * for a CRTC - like overlay or underlay planes.
2016 possible_crtcs = 1 << plane_id;
2017 if (plane_id >= dm->dc->caps.max_streams)
2018 possible_crtcs = 0xff;
2020 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
2023 DRM_ERROR("KMS: Failed to initialize plane\n");
2029 mode_info->planes[plane_id] = plane;
2035 static void register_backlight_device(struct amdgpu_display_manager *dm,
2036 struct dc_link *link)
2038 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2039 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2041 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
2042 link->type != dc_connection_none) {
2044 * Event if registration failed, we should continue with
2045 * DM initialization because not having a backlight control
2046 * is better then a black screen.
2048 amdgpu_dm_register_backlight_device(dm);
2050 if (dm->backlight_dev)
2051 dm->backlight_link = link;
2058 * In this architecture, the association
2059 * connector -> encoder -> crtc
2060 * id not really requried. The crtc and connector will hold the
2061 * display_index as an abstraction to use with DAL component
2063 * Returns 0 on success
2065 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
2067 struct amdgpu_display_manager *dm = &adev->dm;
2069 struct amdgpu_dm_connector *aconnector = NULL;
2070 struct amdgpu_encoder *aencoder = NULL;
2071 struct amdgpu_mode_info *mode_info = &adev->mode_info;
2073 int32_t primary_planes;
2074 enum dc_connection_type new_connection_type = dc_connection_none;
2075 const struct dc_plane_cap *plane;
2077 link_cnt = dm->dc->caps.max_links;
2078 if (amdgpu_dm_mode_config_init(dm->adev)) {
2079 DRM_ERROR("DM: Failed to initialize mode config\n");
2083 /* There is one primary plane per CRTC */
2084 primary_planes = dm->dc->caps.max_streams;
2085 ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
2088 * Initialize primary planes, implicit planes for legacy IOCTLS.
2089 * Order is reversed to match iteration order in atomic check.
2091 for (i = (primary_planes - 1); i >= 0; i--) {
2092 plane = &dm->dc->caps.planes[i];
2094 if (initialize_plane(dm, mode_info, i,
2095 DRM_PLANE_TYPE_PRIMARY, plane)) {
2096 DRM_ERROR("KMS: Failed to initialize primary plane\n");
2102 * Initialize overlay planes, index starting after primary planes.
2103 * These planes have a higher DRM index than the primary planes since
2104 * they should be considered as having a higher z-order.
2105 * Order is reversed to match iteration order in atomic check.
2107 * Only support DCN for now, and only expose one so we don't encourage
2108 * userspace to use up all the pipes.
2110 for (i = 0; i < dm->dc->caps.max_planes; ++i) {
2111 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
2113 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
2116 if (!plane->blends_with_above || !plane->blends_with_below)
2119 if (!plane->pixel_format_support.argb8888)
2122 if (initialize_plane(dm, NULL, primary_planes + i,
2123 DRM_PLANE_TYPE_OVERLAY, plane)) {
2124 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
2128 /* Only create one overlay plane. */
2132 for (i = 0; i < dm->dc->caps.max_streams; i++)
2133 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
2134 DRM_ERROR("KMS: Failed to initialize crtc\n");
2138 dm->display_indexes_num = dm->dc->caps.max_streams;
2140 /* loops over all connectors on the board */
2141 for (i = 0; i < link_cnt; i++) {
2142 struct dc_link *link = NULL;
2144 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
2146 "KMS: Cannot support more than %d display indexes\n",
2147 AMDGPU_DM_MAX_DISPLAY_INDEX);
2151 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
2155 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
2159 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
2160 DRM_ERROR("KMS: Failed to initialize encoder\n");
2164 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
2165 DRM_ERROR("KMS: Failed to initialize connector\n");
2169 link = dc_get_link_at_index(dm->dc, i);
2171 if (!dc_link_detect_sink(link, &new_connection_type))
2172 DRM_ERROR("KMS: Failed to detect connector\n");
2174 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2175 emulated_link_detect(link);
2176 amdgpu_dm_update_connector_after_detect(aconnector);
2178 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
2179 amdgpu_dm_update_connector_after_detect(aconnector);
2180 register_backlight_device(dm, link);
2186 /* Software is initialized. Now we can register interrupt handlers. */
2187 switch (adev->asic_type) {
2197 case CHIP_POLARIS11:
2198 case CHIP_POLARIS10:
2199 case CHIP_POLARIS12:
2204 if (dce110_register_irq_handlers(dm->adev)) {
2205 DRM_ERROR("DM: Failed to initialize IRQ\n");
2209 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2211 if (dcn10_register_irq_handlers(dm->adev)) {
2212 DRM_ERROR("DM: Failed to initialize IRQ\n");
2218 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2222 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
2223 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
2233 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
2235 drm_mode_config_cleanup(dm->ddev);
2236 drm_atomic_private_obj_fini(&dm->atomic_obj);
2240 /******************************************************************************
2241 * amdgpu_display_funcs functions
2242 *****************************************************************************/
2245 * dm_bandwidth_update - program display watermarks
2247 * @adev: amdgpu_device pointer
2249 * Calculate and program the display watermarks and line buffer allocation.
2251 static void dm_bandwidth_update(struct amdgpu_device *adev)
2253 /* TODO: implement later */
2256 static const struct amdgpu_display_funcs dm_display_funcs = {
2257 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
2258 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
2259 .backlight_set_level = NULL, /* never called for DC */
2260 .backlight_get_level = NULL, /* never called for DC */
2261 .hpd_sense = NULL,/* called unconditionally */
2262 .hpd_set_polarity = NULL, /* called unconditionally */
2263 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
2264 .page_flip_get_scanoutpos =
2265 dm_crtc_get_scanoutpos,/* called unconditionally */
2266 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
2267 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
2270 #if defined(CONFIG_DEBUG_KERNEL_DC)
2272 static ssize_t s3_debug_store(struct device *device,
2273 struct device_attribute *attr,
2279 struct pci_dev *pdev = to_pci_dev(device);
2280 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2281 struct amdgpu_device *adev = drm_dev->dev_private;
2283 ret = kstrtoint(buf, 0, &s3_state);
2288 drm_kms_helper_hotplug_event(adev->ddev);
2293 return ret == 0 ? count : 0;
2296 DEVICE_ATTR_WO(s3_debug);
2300 static int dm_early_init(void *handle)
2302 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2304 switch (adev->asic_type) {
2307 adev->mode_info.num_crtc = 6;
2308 adev->mode_info.num_hpd = 6;
2309 adev->mode_info.num_dig = 6;
2312 adev->mode_info.num_crtc = 4;
2313 adev->mode_info.num_hpd = 6;
2314 adev->mode_info.num_dig = 7;
2318 adev->mode_info.num_crtc = 2;
2319 adev->mode_info.num_hpd = 6;
2320 adev->mode_info.num_dig = 6;
2324 adev->mode_info.num_crtc = 6;
2325 adev->mode_info.num_hpd = 6;
2326 adev->mode_info.num_dig = 7;
2329 adev->mode_info.num_crtc = 3;
2330 adev->mode_info.num_hpd = 6;
2331 adev->mode_info.num_dig = 9;
2334 adev->mode_info.num_crtc = 2;
2335 adev->mode_info.num_hpd = 6;
2336 adev->mode_info.num_dig = 9;
2338 case CHIP_POLARIS11:
2339 case CHIP_POLARIS12:
2340 adev->mode_info.num_crtc = 5;
2341 adev->mode_info.num_hpd = 5;
2342 adev->mode_info.num_dig = 5;
2344 case CHIP_POLARIS10:
2346 adev->mode_info.num_crtc = 6;
2347 adev->mode_info.num_hpd = 6;
2348 adev->mode_info.num_dig = 6;
2353 adev->mode_info.num_crtc = 6;
2354 adev->mode_info.num_hpd = 6;
2355 adev->mode_info.num_dig = 6;
2357 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2359 adev->mode_info.num_crtc = 4;
2360 adev->mode_info.num_hpd = 4;
2361 adev->mode_info.num_dig = 4;
2365 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2369 amdgpu_dm_set_irq_funcs(adev);
2371 if (adev->mode_info.funcs == NULL)
2372 adev->mode_info.funcs = &dm_display_funcs;
2375 * Note: Do NOT change adev->audio_endpt_rreg and
2376 * adev->audio_endpt_wreg because they are initialised in
2377 * amdgpu_device_init()
2379 #if defined(CONFIG_DEBUG_KERNEL_DC)
2382 &dev_attr_s3_debug);
2388 static bool modeset_required(struct drm_crtc_state *crtc_state,
2389 struct dc_stream_state *new_stream,
2390 struct dc_stream_state *old_stream)
2392 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2395 if (!crtc_state->enable)
2398 return crtc_state->active;
2401 static bool modereset_required(struct drm_crtc_state *crtc_state)
2403 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2406 return !crtc_state->enable || !crtc_state->active;
2409 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
2411 drm_encoder_cleanup(encoder);
2415 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
2416 .destroy = amdgpu_dm_encoder_destroy,
2420 static int fill_dc_scaling_info(const struct drm_plane_state *state,
2421 struct dc_scaling_info *scaling_info)
2423 int scale_w, scale_h;
2425 memset(scaling_info, 0, sizeof(*scaling_info));
2427 /* Source is fixed 16.16 but we ignore mantissa for now... */
2428 scaling_info->src_rect.x = state->src_x >> 16;
2429 scaling_info->src_rect.y = state->src_y >> 16;
2431 scaling_info->src_rect.width = state->src_w >> 16;
2432 if (scaling_info->src_rect.width == 0)
2435 scaling_info->src_rect.height = state->src_h >> 16;
2436 if (scaling_info->src_rect.height == 0)
2439 scaling_info->dst_rect.x = state->crtc_x;
2440 scaling_info->dst_rect.y = state->crtc_y;
2442 if (state->crtc_w == 0)
2445 scaling_info->dst_rect.width = state->crtc_w;
2447 if (state->crtc_h == 0)
2450 scaling_info->dst_rect.height = state->crtc_h;
2452 /* DRM doesn't specify clipping on destination output. */
2453 scaling_info->clip_rect = scaling_info->dst_rect;
2455 /* TODO: Validate scaling per-format with DC plane caps */
2456 scale_w = scaling_info->dst_rect.width * 1000 /
2457 scaling_info->src_rect.width;
2459 if (scale_w < 250 || scale_w > 16000)
2462 scale_h = scaling_info->dst_rect.height * 1000 /
2463 scaling_info->src_rect.height;
2465 if (scale_h < 250 || scale_h > 16000)
2469 * The "scaling_quality" can be ignored for now, quality = 0 has DC
2470 * assume reasonable defaults based on the format.
2476 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
2477 uint64_t *tiling_flags)
2479 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
2480 int r = amdgpu_bo_reserve(rbo, false);
2483 /* Don't show error message when returning -ERESTARTSYS */
2484 if (r != -ERESTARTSYS)
2485 DRM_ERROR("Unable to reserve buffer: %d\n", r);
2490 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
2492 amdgpu_bo_unreserve(rbo);
2497 static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags)
2499 uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
2501 return offset ? (address + offset * 256) : 0;
2505 fill_plane_dcc_attributes(struct amdgpu_device *adev,
2506 const struct amdgpu_framebuffer *afb,
2507 const enum surface_pixel_format format,
2508 const enum dc_rotation_angle rotation,
2509 const union plane_size *plane_size,
2510 const union dc_tiling_info *tiling_info,
2511 const uint64_t info,
2512 struct dc_plane_dcc_param *dcc,
2513 struct dc_plane_address *address)
2515 struct dc *dc = adev->dm.dc;
2516 struct dc_dcc_surface_param input;
2517 struct dc_surface_dcc_cap output;
2518 uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
2519 uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
2520 uint64_t dcc_address;
2522 memset(&input, 0, sizeof(input));
2523 memset(&output, 0, sizeof(output));
2528 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
2531 if (!dc->cap_funcs.get_dcc_compression_cap)
2534 input.format = format;
2535 input.surface_size.width = plane_size->grph.surface_size.width;
2536 input.surface_size.height = plane_size->grph.surface_size.height;
2537 input.swizzle_mode = tiling_info->gfx9.swizzle;
2539 if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180)
2540 input.scan = SCAN_DIRECTION_HORIZONTAL;
2541 else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270)
2542 input.scan = SCAN_DIRECTION_VERTICAL;
2544 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
2547 if (!output.capable)
2550 if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0)
2554 dcc->grph.meta_pitch =
2555 AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
2556 dcc->grph.independent_64b_blks = i64b;
2558 dcc_address = get_dcc_address(afb->address, info);
2559 address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
2560 address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
2566 fill_plane_buffer_attributes(struct amdgpu_device *adev,
2567 const struct amdgpu_framebuffer *afb,
2568 const enum surface_pixel_format format,
2569 const enum dc_rotation_angle rotation,
2570 const uint64_t tiling_flags,
2571 union dc_tiling_info *tiling_info,
2572 union plane_size *plane_size,
2573 struct dc_plane_dcc_param *dcc,
2574 struct dc_plane_address *address)
2576 const struct drm_framebuffer *fb = &afb->base;
2579 memset(tiling_info, 0, sizeof(*tiling_info));
2580 memset(plane_size, 0, sizeof(*plane_size));
2581 memset(dcc, 0, sizeof(*dcc));
2582 memset(address, 0, sizeof(*address));
2584 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2585 plane_size->grph.surface_size.x = 0;
2586 plane_size->grph.surface_size.y = 0;
2587 plane_size->grph.surface_size.width = fb->width;
2588 plane_size->grph.surface_size.height = fb->height;
2589 plane_size->grph.surface_pitch =
2590 fb->pitches[0] / fb->format->cpp[0];
2592 address->type = PLN_ADDR_TYPE_GRAPHICS;
2593 address->grph.addr.low_part = lower_32_bits(afb->address);
2594 address->grph.addr.high_part = upper_32_bits(afb->address);
2596 uint64_t chroma_addr = afb->address + fb->offsets[1];
2598 plane_size->video.luma_size.x = 0;
2599 plane_size->video.luma_size.y = 0;
2600 plane_size->video.luma_size.width = fb->width;
2601 plane_size->video.luma_size.height = fb->height;
2602 plane_size->video.luma_pitch =
2603 fb->pitches[0] / fb->format->cpp[0];
2605 plane_size->video.chroma_size.x = 0;
2606 plane_size->video.chroma_size.y = 0;
2607 /* TODO: set these based on surface format */
2608 plane_size->video.chroma_size.width = fb->width / 2;
2609 plane_size->video.chroma_size.height = fb->height / 2;
2611 plane_size->video.chroma_pitch =
2612 fb->pitches[1] / fb->format->cpp[1];
2614 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
2615 address->video_progressive.luma_addr.low_part =
2616 lower_32_bits(afb->address);
2617 address->video_progressive.luma_addr.high_part =
2618 upper_32_bits(afb->address);
2619 address->video_progressive.chroma_addr.low_part =
2620 lower_32_bits(chroma_addr);
2621 address->video_progressive.chroma_addr.high_part =
2622 upper_32_bits(chroma_addr);
2625 /* Fill GFX8 params */
2626 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
2627 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
2629 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2630 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2631 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2632 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2633 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2635 /* XXX fix me for VI */
2636 tiling_info->gfx8.num_banks = num_banks;
2637 tiling_info->gfx8.array_mode =
2638 DC_ARRAY_2D_TILED_THIN1;
2639 tiling_info->gfx8.tile_split = tile_split;
2640 tiling_info->gfx8.bank_width = bankw;
2641 tiling_info->gfx8.bank_height = bankh;
2642 tiling_info->gfx8.tile_aspect = mtaspect;
2643 tiling_info->gfx8.tile_mode =
2644 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
2645 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
2646 == DC_ARRAY_1D_TILED_THIN1) {
2647 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
2650 tiling_info->gfx8.pipe_config =
2651 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2653 if (adev->asic_type == CHIP_VEGA10 ||
2654 adev->asic_type == CHIP_VEGA12 ||
2655 adev->asic_type == CHIP_VEGA20 ||
2656 adev->asic_type == CHIP_RAVEN) {
2657 /* Fill GFX9 params */
2658 tiling_info->gfx9.num_pipes =
2659 adev->gfx.config.gb_addr_config_fields.num_pipes;
2660 tiling_info->gfx9.num_banks =
2661 adev->gfx.config.gb_addr_config_fields.num_banks;
2662 tiling_info->gfx9.pipe_interleave =
2663 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
2664 tiling_info->gfx9.num_shader_engines =
2665 adev->gfx.config.gb_addr_config_fields.num_se;
2666 tiling_info->gfx9.max_compressed_frags =
2667 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
2668 tiling_info->gfx9.num_rb_per_se =
2669 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
2670 tiling_info->gfx9.swizzle =
2671 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
2672 tiling_info->gfx9.shaderEnable = 1;
2674 ret = fill_plane_dcc_attributes(adev, afb, format, rotation,
2675 plane_size, tiling_info,
2676 tiling_flags, dcc, address);
2685 fill_blending_from_plane_state(const struct drm_plane_state *plane_state,
2686 bool *per_pixel_alpha, bool *global_alpha,
2687 int *global_alpha_value)
2689 *per_pixel_alpha = false;
2690 *global_alpha = false;
2691 *global_alpha_value = 0xff;
2693 if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY)
2696 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
2697 static const uint32_t alpha_formats[] = {
2698 DRM_FORMAT_ARGB8888,
2699 DRM_FORMAT_RGBA8888,
2700 DRM_FORMAT_ABGR8888,
2702 uint32_t format = plane_state->fb->format->format;
2705 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) {
2706 if (format == alpha_formats[i]) {
2707 *per_pixel_alpha = true;
2713 if (plane_state->alpha < 0xffff) {
2714 *global_alpha = true;
2715 *global_alpha_value = plane_state->alpha >> 8;
2720 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
2721 const enum surface_pixel_format format,
2722 enum dc_color_space *color_space)
2726 *color_space = COLOR_SPACE_SRGB;
2728 /* DRM color properties only affect non-RGB formats. */
2729 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
2732 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
2734 switch (plane_state->color_encoding) {
2735 case DRM_COLOR_YCBCR_BT601:
2737 *color_space = COLOR_SPACE_YCBCR601;
2739 *color_space = COLOR_SPACE_YCBCR601_LIMITED;
2742 case DRM_COLOR_YCBCR_BT709:
2744 *color_space = COLOR_SPACE_YCBCR709;
2746 *color_space = COLOR_SPACE_YCBCR709_LIMITED;
2749 case DRM_COLOR_YCBCR_BT2020:
2751 *color_space = COLOR_SPACE_2020_YCBCR;
2764 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
2765 const struct drm_plane_state *plane_state,
2766 const uint64_t tiling_flags,
2767 struct dc_plane_info *plane_info,
2768 struct dc_plane_address *address)
2770 const struct drm_framebuffer *fb = plane_state->fb;
2771 const struct amdgpu_framebuffer *afb =
2772 to_amdgpu_framebuffer(plane_state->fb);
2773 struct drm_format_name_buf format_name;
2776 memset(plane_info, 0, sizeof(*plane_info));
2778 switch (fb->format->format) {
2780 plane_info->format =
2781 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
2783 case DRM_FORMAT_RGB565:
2784 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
2786 case DRM_FORMAT_XRGB8888:
2787 case DRM_FORMAT_ARGB8888:
2788 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
2790 case DRM_FORMAT_XRGB2101010:
2791 case DRM_FORMAT_ARGB2101010:
2792 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
2794 case DRM_FORMAT_XBGR2101010:
2795 case DRM_FORMAT_ABGR2101010:
2796 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
2798 case DRM_FORMAT_XBGR8888:
2799 case DRM_FORMAT_ABGR8888:
2800 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
2802 case DRM_FORMAT_NV21:
2803 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
2805 case DRM_FORMAT_NV12:
2806 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
2810 "Unsupported screen format %s\n",
2811 drm_get_format_name(fb->format->format, &format_name));
2815 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
2816 case DRM_MODE_ROTATE_0:
2817 plane_info->rotation = ROTATION_ANGLE_0;
2819 case DRM_MODE_ROTATE_90:
2820 plane_info->rotation = ROTATION_ANGLE_90;
2822 case DRM_MODE_ROTATE_180:
2823 plane_info->rotation = ROTATION_ANGLE_180;
2825 case DRM_MODE_ROTATE_270:
2826 plane_info->rotation = ROTATION_ANGLE_270;
2829 plane_info->rotation = ROTATION_ANGLE_0;
2833 plane_info->visible = true;
2834 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
2836 ret = fill_plane_color_attributes(plane_state, plane_info->format,
2837 &plane_info->color_space);
2841 ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
2842 plane_info->rotation, tiling_flags,
2843 &plane_info->tiling_info,
2844 &plane_info->plane_size,
2845 &plane_info->dcc, address);
2849 fill_blending_from_plane_state(
2850 plane_state, &plane_info->per_pixel_alpha,
2851 &plane_info->global_alpha, &plane_info->global_alpha_value);
2856 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
2857 struct dc_plane_state *dc_plane_state,
2858 struct drm_plane_state *plane_state,
2859 struct drm_crtc_state *crtc_state)
2861 const struct amdgpu_framebuffer *amdgpu_fb =
2862 to_amdgpu_framebuffer(plane_state->fb);
2863 struct dc_scaling_info scaling_info;
2864 struct dc_plane_info plane_info;
2865 uint64_t tiling_flags;
2868 ret = fill_dc_scaling_info(plane_state, &scaling_info);
2872 dc_plane_state->src_rect = scaling_info.src_rect;
2873 dc_plane_state->dst_rect = scaling_info.dst_rect;
2874 dc_plane_state->clip_rect = scaling_info.clip_rect;
2875 dc_plane_state->scaling_quality = scaling_info.scaling_quality;
2877 ret = get_fb_info(amdgpu_fb, &tiling_flags);
2881 ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags,
2883 &dc_plane_state->address);
2887 dc_plane_state->format = plane_info.format;
2888 dc_plane_state->color_space = plane_info.color_space;
2889 dc_plane_state->format = plane_info.format;
2890 dc_plane_state->plane_size = plane_info.plane_size;
2891 dc_plane_state->rotation = plane_info.rotation;
2892 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
2893 dc_plane_state->stereo_format = plane_info.stereo_format;
2894 dc_plane_state->tiling_info = plane_info.tiling_info;
2895 dc_plane_state->visible = plane_info.visible;
2896 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
2897 dc_plane_state->global_alpha = plane_info.global_alpha;
2898 dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
2899 dc_plane_state->dcc = plane_info.dcc;
2902 * Always set input transfer function, since plane state is refreshed
2905 ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
2907 dc_transfer_func_release(dc_plane_state->in_transfer_func);
2908 dc_plane_state->in_transfer_func = NULL;
2914 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2915 const struct dm_connector_state *dm_state,
2916 struct dc_stream_state *stream)
2918 enum amdgpu_rmx_type rmx_type;
2920 struct rect src = { 0 }; /* viewport in composition space*/
2921 struct rect dst = { 0 }; /* stream addressable area */
2923 /* no mode. nothing to be done */
2927 /* Full screen scaling by default */
2928 src.width = mode->hdisplay;
2929 src.height = mode->vdisplay;
2930 dst.width = stream->timing.h_addressable;
2931 dst.height = stream->timing.v_addressable;
2934 rmx_type = dm_state->scaling;
2935 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2936 if (src.width * dst.height <
2937 src.height * dst.width) {
2938 /* height needs less upscaling/more downscaling */
2939 dst.width = src.width *
2940 dst.height / src.height;
2942 /* width needs less upscaling/more downscaling */
2943 dst.height = src.height *
2944 dst.width / src.width;
2946 } else if (rmx_type == RMX_CENTER) {
2950 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2951 dst.y = (stream->timing.v_addressable - dst.height) / 2;
2953 if (dm_state->underscan_enable) {
2954 dst.x += dm_state->underscan_hborder / 2;
2955 dst.y += dm_state->underscan_vborder / 2;
2956 dst.width -= dm_state->underscan_hborder;
2957 dst.height -= dm_state->underscan_vborder;
2964 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
2965 dst.x, dst.y, dst.width, dst.height);
2969 static enum dc_color_depth
2970 convert_color_depth_from_display_info(const struct drm_connector *connector)
2972 struct dm_connector_state *dm_conn_state =
2973 to_dm_connector_state(connector->state);
2974 uint32_t bpc = connector->display_info.bpc;
2976 /* TODO: Remove this when there's support for max_bpc in drm */
2977 if (dm_conn_state && bpc > dm_conn_state->max_bpc)
2978 /* Round down to nearest even number. */
2979 bpc = dm_conn_state->max_bpc - (dm_conn_state->max_bpc & 1);
2984 * Temporary Work around, DRM doesn't parse color depth for
2985 * EDID revision before 1.4
2986 * TODO: Fix edid parsing
2988 return COLOR_DEPTH_888;
2990 return COLOR_DEPTH_666;
2992 return COLOR_DEPTH_888;
2994 return COLOR_DEPTH_101010;
2996 return COLOR_DEPTH_121212;
2998 return COLOR_DEPTH_141414;
3000 return COLOR_DEPTH_161616;
3002 return COLOR_DEPTH_UNDEFINED;
3006 static enum dc_aspect_ratio
3007 get_aspect_ratio(const struct drm_display_mode *mode_in)
3009 /* 1-1 mapping, since both enums follow the HDMI spec. */
3010 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
3013 static enum dc_color_space
3014 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
3016 enum dc_color_space color_space = COLOR_SPACE_SRGB;
3018 switch (dc_crtc_timing->pixel_encoding) {
3019 case PIXEL_ENCODING_YCBCR422:
3020 case PIXEL_ENCODING_YCBCR444:
3021 case PIXEL_ENCODING_YCBCR420:
3024 * 27030khz is the separation point between HDTV and SDTV
3025 * according to HDMI spec, we use YCbCr709 and YCbCr601
3028 if (dc_crtc_timing->pix_clk_100hz > 270300) {
3029 if (dc_crtc_timing->flags.Y_ONLY)
3031 COLOR_SPACE_YCBCR709_LIMITED;
3033 color_space = COLOR_SPACE_YCBCR709;
3035 if (dc_crtc_timing->flags.Y_ONLY)
3037 COLOR_SPACE_YCBCR601_LIMITED;
3039 color_space = COLOR_SPACE_YCBCR601;
3044 case PIXEL_ENCODING_RGB:
3045 color_space = COLOR_SPACE_SRGB;
3056 static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
3058 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
3061 timing_out->display_color_depth--;
3064 static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,
3065 const struct drm_display_info *info)
3068 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
3071 normalized_clk = timing_out->pix_clk_100hz / 10;
3072 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
3073 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3074 normalized_clk /= 2;
3075 /* Adjusting pix clock following on HDMI spec based on colour depth */
3076 switch (timing_out->display_color_depth) {
3077 case COLOR_DEPTH_101010:
3078 normalized_clk = (normalized_clk * 30) / 24;
3080 case COLOR_DEPTH_121212:
3081 normalized_clk = (normalized_clk * 36) / 24;
3083 case COLOR_DEPTH_161616:
3084 normalized_clk = (normalized_clk * 48) / 24;
3089 if (normalized_clk <= info->max_tmds_clock)
3091 reduce_mode_colour_depth(timing_out);
3093 } while (timing_out->display_color_depth > COLOR_DEPTH_888);
3098 fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
3099 const struct drm_display_mode *mode_in,
3100 const struct drm_connector *connector,
3101 const struct dc_stream_state *old_stream)
3103 struct dc_crtc_timing *timing_out = &stream->timing;
3104 const struct drm_display_info *info = &connector->display_info;
3106 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
3108 timing_out->h_border_left = 0;
3109 timing_out->h_border_right = 0;
3110 timing_out->v_border_top = 0;
3111 timing_out->v_border_bottom = 0;
3112 /* TODO: un-hardcode */
3113 if (drm_mode_is_420_only(info, mode_in)
3114 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
3115 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
3116 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
3117 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
3118 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
3120 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
3122 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
3123 timing_out->display_color_depth = convert_color_depth_from_display_info(
3125 timing_out->scan_type = SCANNING_TYPE_NODATA;
3126 timing_out->hdmi_vic = 0;
3129 timing_out->vic = old_stream->timing.vic;
3130 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
3131 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
3133 timing_out->vic = drm_match_cea_mode(mode_in);
3134 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
3135 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
3136 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
3137 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
3140 timing_out->h_addressable = mode_in->crtc_hdisplay;
3141 timing_out->h_total = mode_in->crtc_htotal;
3142 timing_out->h_sync_width =
3143 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
3144 timing_out->h_front_porch =
3145 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
3146 timing_out->v_total = mode_in->crtc_vtotal;
3147 timing_out->v_addressable = mode_in->crtc_vdisplay;
3148 timing_out->v_front_porch =
3149 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
3150 timing_out->v_sync_width =
3151 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
3152 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
3153 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
3155 stream->output_color_space = get_output_color_space(timing_out);
3157 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
3158 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
3159 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
3160 adjust_colour_depth_from_display_info(timing_out, info);
3163 static void fill_audio_info(struct audio_info *audio_info,
3164 const struct drm_connector *drm_connector,
3165 const struct dc_sink *dc_sink)
3168 int cea_revision = 0;
3169 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
3171 audio_info->manufacture_id = edid_caps->manufacturer_id;
3172 audio_info->product_id = edid_caps->product_id;
3174 cea_revision = drm_connector->display_info.cea_rev;
3176 strscpy(audio_info->display_name,
3177 edid_caps->display_name,
3178 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
3180 if (cea_revision >= 3) {
3181 audio_info->mode_count = edid_caps->audio_mode_count;
3183 for (i = 0; i < audio_info->mode_count; ++i) {
3184 audio_info->modes[i].format_code =
3185 (enum audio_format_code)
3186 (edid_caps->audio_modes[i].format_code);
3187 audio_info->modes[i].channel_count =
3188 edid_caps->audio_modes[i].channel_count;
3189 audio_info->modes[i].sample_rates.all =
3190 edid_caps->audio_modes[i].sample_rate;
3191 audio_info->modes[i].sample_size =
3192 edid_caps->audio_modes[i].sample_size;
3196 audio_info->flags.all = edid_caps->speaker_flags;
3198 /* TODO: We only check for the progressive mode, check for interlace mode too */
3199 if (drm_connector->latency_present[0]) {
3200 audio_info->video_latency = drm_connector->video_latency[0];
3201 audio_info->audio_latency = drm_connector->audio_latency[0];
3204 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
3209 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
3210 struct drm_display_mode *dst_mode)
3212 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
3213 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
3214 dst_mode->crtc_clock = src_mode->crtc_clock;
3215 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
3216 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
3217 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
3218 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
3219 dst_mode->crtc_htotal = src_mode->crtc_htotal;
3220 dst_mode->crtc_hskew = src_mode->crtc_hskew;
3221 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
3222 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
3223 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
3224 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
3225 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
3229 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
3230 const struct drm_display_mode *native_mode,
3233 if (scale_enabled) {
3234 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
3235 } else if (native_mode->clock == drm_mode->clock &&
3236 native_mode->htotal == drm_mode->htotal &&
3237 native_mode->vtotal == drm_mode->vtotal) {
3238 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
3240 /* no scaling nor amdgpu inserted, no need to patch */
3244 static struct dc_sink *
3245 create_fake_sink(struct amdgpu_dm_connector *aconnector)
3247 struct dc_sink_init_data sink_init_data = { 0 };
3248 struct dc_sink *sink = NULL;
3249 sink_init_data.link = aconnector->dc_link;
3250 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
3252 sink = dc_sink_create(&sink_init_data);
3254 DRM_ERROR("Failed to create sink!\n");
3257 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
3262 static void set_multisync_trigger_params(
3263 struct dc_stream_state *stream)
3265 if (stream->triggered_crtc_reset.enabled) {
3266 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
3267 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
3271 static void set_master_stream(struct dc_stream_state *stream_set[],
3274 int j, highest_rfr = 0, master_stream = 0;
3276 for (j = 0; j < stream_count; j++) {
3277 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
3278 int refresh_rate = 0;
3280 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
3281 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
3282 if (refresh_rate > highest_rfr) {
3283 highest_rfr = refresh_rate;
3288 for (j = 0; j < stream_count; j++) {
3290 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
3294 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
3298 if (context->stream_count < 2)
3300 for (i = 0; i < context->stream_count ; i++) {
3301 if (!context->streams[i])
3304 * TODO: add a function to read AMD VSDB bits and set
3305 * crtc_sync_master.multi_sync_enabled flag
3306 * For now it's set to false
3308 set_multisync_trigger_params(context->streams[i]);
3310 set_master_stream(context->streams, context->stream_count);
3313 static struct dc_stream_state *
3314 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
3315 const struct drm_display_mode *drm_mode,
3316 const struct dm_connector_state *dm_state,
3317 const struct dc_stream_state *old_stream)
3319 struct drm_display_mode *preferred_mode = NULL;
3320 struct drm_connector *drm_connector;
3321 struct dc_stream_state *stream = NULL;
3322 struct drm_display_mode mode = *drm_mode;
3323 bool native_mode_found = false;
3324 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
3326 int preferred_refresh = 0;
3328 struct dc_sink *sink = NULL;
3329 if (aconnector == NULL) {
3330 DRM_ERROR("aconnector is NULL!\n");
3334 drm_connector = &aconnector->base;
3336 if (!aconnector->dc_sink) {
3337 sink = create_fake_sink(aconnector);
3341 sink = aconnector->dc_sink;
3342 dc_sink_retain(sink);
3345 stream = dc_create_stream_for_sink(sink);
3347 if (stream == NULL) {
3348 DRM_ERROR("Failed to create stream for sink!\n");
3352 stream->dm_stream_context = aconnector;
3354 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
3355 /* Search for preferred mode */
3356 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
3357 native_mode_found = true;
3361 if (!native_mode_found)
3362 preferred_mode = list_first_entry_or_null(
3363 &aconnector->base.modes,
3364 struct drm_display_mode,
3367 mode_refresh = drm_mode_vrefresh(&mode);
3369 if (preferred_mode == NULL) {
3371 * This may not be an error, the use case is when we have no
3372 * usermode calls to reset and set mode upon hotplug. In this
3373 * case, we call set mode ourselves to restore the previous mode
3374 * and the modelist may not be filled in in time.
3376 DRM_DEBUG_DRIVER("No preferred mode found\n");
3378 decide_crtc_timing_for_drm_display_mode(
3379 &mode, preferred_mode,
3380 dm_state ? (dm_state->scaling != RMX_OFF) : false);
3381 preferred_refresh = drm_mode_vrefresh(preferred_mode);
3385 drm_mode_set_crtcinfo(&mode, 0);
3388 * If scaling is enabled and refresh rate didn't change
3389 * we copy the vic and polarities of the old timings
3391 if (!scale || mode_refresh != preferred_refresh)
3392 fill_stream_properties_from_drm_display_mode(stream,
3393 &mode, &aconnector->base, NULL);
3395 fill_stream_properties_from_drm_display_mode(stream,
3396 &mode, &aconnector->base, old_stream);
3398 update_stream_scaling_settings(&mode, dm_state, stream);
3401 &stream->audio_info,
3405 update_stream_signal(stream, sink);
3408 dc_sink_release(sink);
3413 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
3415 drm_crtc_cleanup(crtc);
3419 static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3420 struct drm_crtc_state *state)
3422 struct dm_crtc_state *cur = to_dm_crtc_state(state);
3424 /* TODO Destroy dc_stream objects are stream object is flattened */
3426 dc_stream_release(cur->stream);
3429 __drm_atomic_helper_crtc_destroy_state(state);
3435 static void dm_crtc_reset_state(struct drm_crtc *crtc)
3437 struct dm_crtc_state *state;
3440 dm_crtc_destroy_state(crtc, crtc->state);
3442 state = kzalloc(sizeof(*state), GFP_KERNEL);
3443 if (WARN_ON(!state))
3446 crtc->state = &state->base;
3447 crtc->state->crtc = crtc;
3451 static struct drm_crtc_state *
3452 dm_crtc_duplicate_state(struct drm_crtc *crtc)
3454 struct dm_crtc_state *state, *cur;
3456 cur = to_dm_crtc_state(crtc->state);
3458 if (WARN_ON(!crtc->state))
3461 state = kzalloc(sizeof(*state), GFP_KERNEL);
3465 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
3468 state->stream = cur->stream;
3469 dc_stream_retain(state->stream);
3472 state->active_planes = cur->active_planes;
3473 state->interrupts_enabled = cur->interrupts_enabled;
3474 state->vrr_params = cur->vrr_params;
3475 state->vrr_infopacket = cur->vrr_infopacket;
3476 state->abm_level = cur->abm_level;
3477 state->vrr_supported = cur->vrr_supported;
3478 state->freesync_config = cur->freesync_config;
3479 state->crc_enabled = cur->crc_enabled;
3481 /* TODO Duplicate dc_stream after objects are stream object is flattened */
3483 return &state->base;
3486 static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
3488 enum dc_irq_source irq_source;
3489 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3490 struct amdgpu_device *adev = crtc->dev->dev_private;
3493 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
3495 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
3497 DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n",
3498 acrtc->crtc_id, enable ? "en" : "dis", rc);
3502 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
3504 enum dc_irq_source irq_source;
3505 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3506 struct amdgpu_device *adev = crtc->dev->dev_private;
3507 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3511 /* vblank irq on -> Only need vupdate irq in vrr mode */
3512 if (amdgpu_dm_vrr_active(acrtc_state))
3513 rc = dm_set_vupdate_irq(crtc, true);
3515 /* vblank irq off -> vupdate irq off */
3516 rc = dm_set_vupdate_irq(crtc, false);
3522 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
3523 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
3526 static int dm_enable_vblank(struct drm_crtc *crtc)
3528 return dm_set_vblank(crtc, true);
3531 static void dm_disable_vblank(struct drm_crtc *crtc)
3533 dm_set_vblank(crtc, false);
3536 /* Implemented only the options currently availible for the driver */
3537 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
3538 .reset = dm_crtc_reset_state,
3539 .destroy = amdgpu_dm_crtc_destroy,
3540 .gamma_set = drm_atomic_helper_legacy_gamma_set,
3541 .set_config = drm_atomic_helper_set_config,
3542 .page_flip = drm_atomic_helper_page_flip,
3543 .atomic_duplicate_state = dm_crtc_duplicate_state,
3544 .atomic_destroy_state = dm_crtc_destroy_state,
3545 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
3546 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
3547 .enable_vblank = dm_enable_vblank,
3548 .disable_vblank = dm_disable_vblank,
3551 static enum drm_connector_status
3552 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
3555 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3559 * 1. This interface is NOT called in context of HPD irq.
3560 * 2. This interface *is called* in context of user-mode ioctl. Which
3561 * makes it a bad place for *any* MST-related activity.
3564 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
3565 !aconnector->fake_enable)
3566 connected = (aconnector->dc_sink != NULL);
3568 connected = (aconnector->base.force == DRM_FORCE_ON);
3570 return (connected ? connector_status_connected :
3571 connector_status_disconnected);
3574 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
3575 struct drm_connector_state *connector_state,
3576 struct drm_property *property,
3579 struct drm_device *dev = connector->dev;
3580 struct amdgpu_device *adev = dev->dev_private;
3581 struct dm_connector_state *dm_old_state =
3582 to_dm_connector_state(connector->state);
3583 struct dm_connector_state *dm_new_state =
3584 to_dm_connector_state(connector_state);
3588 if (property == dev->mode_config.scaling_mode_property) {
3589 enum amdgpu_rmx_type rmx_type;
3592 case DRM_MODE_SCALE_CENTER:
3593 rmx_type = RMX_CENTER;
3595 case DRM_MODE_SCALE_ASPECT:
3596 rmx_type = RMX_ASPECT;
3598 case DRM_MODE_SCALE_FULLSCREEN:
3599 rmx_type = RMX_FULL;
3601 case DRM_MODE_SCALE_NONE:
3607 if (dm_old_state->scaling == rmx_type)
3610 dm_new_state->scaling = rmx_type;
3612 } else if (property == adev->mode_info.underscan_hborder_property) {
3613 dm_new_state->underscan_hborder = val;
3615 } else if (property == adev->mode_info.underscan_vborder_property) {
3616 dm_new_state->underscan_vborder = val;
3618 } else if (property == adev->mode_info.underscan_property) {
3619 dm_new_state->underscan_enable = val;
3621 } else if (property == adev->mode_info.max_bpc_property) {
3622 dm_new_state->max_bpc = val;
3624 } else if (property == adev->mode_info.abm_level_property) {
3625 dm_new_state->abm_level = val;
3632 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
3633 const struct drm_connector_state *state,
3634 struct drm_property *property,
3637 struct drm_device *dev = connector->dev;
3638 struct amdgpu_device *adev = dev->dev_private;
3639 struct dm_connector_state *dm_state =
3640 to_dm_connector_state(state);
3643 if (property == dev->mode_config.scaling_mode_property) {
3644 switch (dm_state->scaling) {
3646 *val = DRM_MODE_SCALE_CENTER;
3649 *val = DRM_MODE_SCALE_ASPECT;
3652 *val = DRM_MODE_SCALE_FULLSCREEN;
3656 *val = DRM_MODE_SCALE_NONE;
3660 } else if (property == adev->mode_info.underscan_hborder_property) {
3661 *val = dm_state->underscan_hborder;
3663 } else if (property == adev->mode_info.underscan_vborder_property) {
3664 *val = dm_state->underscan_vborder;
3666 } else if (property == adev->mode_info.underscan_property) {
3667 *val = dm_state->underscan_enable;
3669 } else if (property == adev->mode_info.max_bpc_property) {
3670 *val = dm_state->max_bpc;
3672 } else if (property == adev->mode_info.abm_level_property) {
3673 *val = dm_state->abm_level;
3680 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
3682 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3683 const struct dc_link *link = aconnector->dc_link;
3684 struct amdgpu_device *adev = connector->dev->dev_private;
3685 struct amdgpu_display_manager *dm = &adev->dm;
3687 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3688 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3690 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
3691 link->type != dc_connection_none &&
3692 dm->backlight_dev) {
3693 backlight_device_unregister(dm->backlight_dev);
3694 dm->backlight_dev = NULL;
3698 if (aconnector->dc_em_sink)
3699 dc_sink_release(aconnector->dc_em_sink);
3700 aconnector->dc_em_sink = NULL;
3701 if (aconnector->dc_sink)
3702 dc_sink_release(aconnector->dc_sink);
3703 aconnector->dc_sink = NULL;
3705 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
3706 drm_connector_unregister(connector);
3707 drm_connector_cleanup(connector);
3711 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
3713 struct dm_connector_state *state =
3714 to_dm_connector_state(connector->state);
3716 if (connector->state)
3717 __drm_atomic_helper_connector_destroy_state(connector->state);
3721 state = kzalloc(sizeof(*state), GFP_KERNEL);
3724 state->scaling = RMX_OFF;
3725 state->underscan_enable = false;
3726 state->underscan_hborder = 0;
3727 state->underscan_vborder = 0;
3730 __drm_atomic_helper_connector_reset(connector, &state->base);
3734 struct drm_connector_state *
3735 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
3737 struct dm_connector_state *state =
3738 to_dm_connector_state(connector->state);
3740 struct dm_connector_state *new_state =
3741 kmemdup(state, sizeof(*state), GFP_KERNEL);
3746 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
3748 new_state->freesync_capable = state->freesync_capable;
3749 new_state->abm_level = state->abm_level;
3750 new_state->scaling = state->scaling;
3751 new_state->underscan_enable = state->underscan_enable;
3752 new_state->underscan_hborder = state->underscan_hborder;
3753 new_state->underscan_vborder = state->underscan_vborder;
3754 new_state->max_bpc = state->max_bpc;
3756 return &new_state->base;
3759 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
3760 .reset = amdgpu_dm_connector_funcs_reset,
3761 .detect = amdgpu_dm_connector_detect,
3762 .fill_modes = drm_helper_probe_single_connector_modes,
3763 .destroy = amdgpu_dm_connector_destroy,
3764 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
3765 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
3766 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
3767 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
3770 static int get_modes(struct drm_connector *connector)
3772 return amdgpu_dm_connector_get_modes(connector);
3775 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
3777 struct dc_sink_init_data init_params = {
3778 .link = aconnector->dc_link,
3779 .sink_signal = SIGNAL_TYPE_VIRTUAL
3783 if (!aconnector->base.edid_blob_ptr) {
3784 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
3785 aconnector->base.name);
3787 aconnector->base.force = DRM_FORCE_OFF;
3788 aconnector->base.override_edid = false;
3792 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
3794 aconnector->edid = edid;
3796 aconnector->dc_em_sink = dc_link_add_remote_sink(
3797 aconnector->dc_link,
3799 (edid->extensions + 1) * EDID_LENGTH,
3802 if (aconnector->base.force == DRM_FORCE_ON) {
3803 aconnector->dc_sink = aconnector->dc_link->local_sink ?
3804 aconnector->dc_link->local_sink :
3805 aconnector->dc_em_sink;
3806 dc_sink_retain(aconnector->dc_sink);
3810 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
3812 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
3815 * In case of headless boot with force on for DP managed connector
3816 * Those settings have to be != 0 to get initial modeset
3818 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
3819 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
3820 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
3824 aconnector->base.override_edid = true;
3825 create_eml_sink(aconnector);
3828 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
3829 struct drm_display_mode *mode)
3831 int result = MODE_ERROR;
3832 struct dc_sink *dc_sink;
3833 struct amdgpu_device *adev = connector->dev->dev_private;
3834 /* TODO: Unhardcode stream count */
3835 struct dc_stream_state *stream;
3836 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3837 enum dc_status dc_result = DC_OK;
3839 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
3840 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
3844 * Only run this the first time mode_valid is called to initilialize
3847 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
3848 !aconnector->dc_em_sink)
3849 handle_edid_mgmt(aconnector);
3851 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
3853 if (dc_sink == NULL) {
3854 DRM_ERROR("dc_sink is NULL!\n");
3858 stream = create_stream_for_sink(aconnector, mode, NULL, NULL);
3859 if (stream == NULL) {
3860 DRM_ERROR("Failed to create stream for sink!\n");
3864 dc_result = dc_validate_stream(adev->dm.dc, stream);
3866 if (dc_result == DC_OK)
3869 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
3875 dc_stream_release(stream);
3878 /* TODO: error handling*/
3882 static const struct drm_connector_helper_funcs
3883 amdgpu_dm_connector_helper_funcs = {
3885 * If hotplugging a second bigger display in FB Con mode, bigger resolution
3886 * modes will be filtered by drm_mode_validate_size(), and those modes
3887 * are missing after user start lightdm. So we need to renew modes list.
3888 * in get_modes call back, not just return the modes count
3890 .get_modes = get_modes,
3891 .mode_valid = amdgpu_dm_connector_mode_valid,
3894 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
3898 static bool does_crtc_have_active_cursor(struct drm_crtc_state *new_crtc_state)
3900 struct drm_device *dev = new_crtc_state->crtc->dev;
3901 struct drm_plane *plane;
3903 drm_for_each_plane_mask(plane, dev, new_crtc_state->plane_mask) {
3904 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3911 static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
3913 struct drm_atomic_state *state = new_crtc_state->state;
3914 struct drm_plane *plane;
3917 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
3918 struct drm_plane_state *new_plane_state;
3920 /* Cursor planes are "fake". */
3921 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3924 new_plane_state = drm_atomic_get_new_plane_state(state, plane);
3926 if (!new_plane_state) {
3928 * The plane is enable on the CRTC and hasn't changed
3929 * state. This means that it previously passed
3930 * validation and is therefore enabled.
3936 /* We need a framebuffer to be considered enabled. */
3937 num_active += (new_plane_state->fb != NULL);
3944 * Sets whether interrupts should be enabled on a specific CRTC.
3945 * We require that the stream be enabled and that there exist active
3946 * DC planes on the stream.
3949 dm_update_crtc_interrupt_state(struct drm_crtc *crtc,
3950 struct drm_crtc_state *new_crtc_state)
3952 struct dm_crtc_state *dm_new_crtc_state =
3953 to_dm_crtc_state(new_crtc_state);
3955 dm_new_crtc_state->active_planes = 0;
3956 dm_new_crtc_state->interrupts_enabled = false;
3958 if (!dm_new_crtc_state->stream)
3961 dm_new_crtc_state->active_planes =
3962 count_crtc_active_planes(new_crtc_state);
3964 dm_new_crtc_state->interrupts_enabled =
3965 dm_new_crtc_state->active_planes > 0;
3968 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
3969 struct drm_crtc_state *state)
3971 struct amdgpu_device *adev = crtc->dev->dev_private;
3972 struct dc *dc = adev->dm.dc;
3973 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
3977 * Update interrupt state for the CRTC. This needs to happen whenever
3978 * the CRTC has changed or whenever any of its planes have changed.
3979 * Atomic check satisfies both of these requirements since the CRTC
3980 * is added to the state by DRM during drm_atomic_helper_check_planes.
3982 dm_update_crtc_interrupt_state(crtc, state);
3984 if (unlikely(!dm_crtc_state->stream &&
3985 modeset_required(state, NULL, dm_crtc_state->stream))) {
3990 /* In some use cases, like reset, no stream is attached */
3991 if (!dm_crtc_state->stream)
3995 * We want at least one hardware plane enabled to use
3996 * the stream with a cursor enabled.
3998 if (state->enable && state->active &&
3999 does_crtc_have_active_cursor(state) &&
4000 dm_crtc_state->active_planes == 0)
4003 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
4009 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
4010 const struct drm_display_mode *mode,
4011 struct drm_display_mode *adjusted_mode)
4016 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
4017 .disable = dm_crtc_helper_disable,
4018 .atomic_check = dm_crtc_helper_atomic_check,
4019 .mode_fixup = dm_crtc_helper_mode_fixup
4022 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
4027 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
4028 struct drm_crtc_state *crtc_state,
4029 struct drm_connector_state *conn_state)
4034 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
4035 .disable = dm_encoder_helper_disable,
4036 .atomic_check = dm_encoder_helper_atomic_check
4039 static void dm_drm_plane_reset(struct drm_plane *plane)
4041 struct dm_plane_state *amdgpu_state = NULL;
4044 plane->funcs->atomic_destroy_state(plane, plane->state);
4046 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
4047 WARN_ON(amdgpu_state == NULL);
4050 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
4053 static struct drm_plane_state *
4054 dm_drm_plane_duplicate_state(struct drm_plane *plane)
4056 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
4058 old_dm_plane_state = to_dm_plane_state(plane->state);
4059 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
4060 if (!dm_plane_state)
4063 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
4065 if (old_dm_plane_state->dc_state) {
4066 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
4067 dc_plane_state_retain(dm_plane_state->dc_state);
4070 return &dm_plane_state->base;
4073 void dm_drm_plane_destroy_state(struct drm_plane *plane,
4074 struct drm_plane_state *state)
4076 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
4078 if (dm_plane_state->dc_state)
4079 dc_plane_state_release(dm_plane_state->dc_state);
4081 drm_atomic_helper_plane_destroy_state(plane, state);
4084 static const struct drm_plane_funcs dm_plane_funcs = {
4085 .update_plane = drm_atomic_helper_update_plane,
4086 .disable_plane = drm_atomic_helper_disable_plane,
4087 .destroy = drm_primary_helper_destroy,
4088 .reset = dm_drm_plane_reset,
4089 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
4090 .atomic_destroy_state = dm_drm_plane_destroy_state,
4093 static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
4094 struct drm_plane_state *new_state)
4096 struct amdgpu_framebuffer *afb;
4097 struct drm_gem_object *obj;
4098 struct amdgpu_device *adev;
4099 struct amdgpu_bo *rbo;
4100 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
4101 uint64_t tiling_flags;
4105 dm_plane_state_old = to_dm_plane_state(plane->state);
4106 dm_plane_state_new = to_dm_plane_state(new_state);
4108 if (!new_state->fb) {
4109 DRM_DEBUG_DRIVER("No FB bound\n");
4113 afb = to_amdgpu_framebuffer(new_state->fb);
4114 obj = new_state->fb->obj[0];
4115 rbo = gem_to_amdgpu_bo(obj);
4116 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
4117 r = amdgpu_bo_reserve(rbo, false);
4118 if (unlikely(r != 0))
4121 if (plane->type != DRM_PLANE_TYPE_CURSOR)
4122 domain = amdgpu_display_supported_domains(adev);
4124 domain = AMDGPU_GEM_DOMAIN_VRAM;
4126 r = amdgpu_bo_pin(rbo, domain);
4127 if (unlikely(r != 0)) {
4128 if (r != -ERESTARTSYS)
4129 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
4130 amdgpu_bo_unreserve(rbo);
4134 r = amdgpu_ttm_alloc_gart(&rbo->tbo);
4135 if (unlikely(r != 0)) {
4136 amdgpu_bo_unpin(rbo);
4137 amdgpu_bo_unreserve(rbo);
4138 DRM_ERROR("%p bind failed\n", rbo);
4142 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
4144 amdgpu_bo_unreserve(rbo);
4146 afb->address = amdgpu_bo_gpu_offset(rbo);
4150 if (dm_plane_state_new->dc_state &&
4151 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
4152 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
4154 fill_plane_buffer_attributes(
4155 adev, afb, plane_state->format, plane_state->rotation,
4156 tiling_flags, &plane_state->tiling_info,
4157 &plane_state->plane_size, &plane_state->dcc,
4158 &plane_state->address);
4164 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
4165 struct drm_plane_state *old_state)
4167 struct amdgpu_bo *rbo;
4173 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
4174 r = amdgpu_bo_reserve(rbo, false);
4176 DRM_ERROR("failed to reserve rbo before unpin\n");
4180 amdgpu_bo_unpin(rbo);
4181 amdgpu_bo_unreserve(rbo);
4182 amdgpu_bo_unref(&rbo);
4185 static int dm_plane_atomic_check(struct drm_plane *plane,
4186 struct drm_plane_state *state)
4188 struct amdgpu_device *adev = plane->dev->dev_private;
4189 struct dc *dc = adev->dm.dc;
4190 struct dm_plane_state *dm_plane_state;
4191 struct dc_scaling_info scaling_info;
4194 dm_plane_state = to_dm_plane_state(state);
4196 if (!dm_plane_state->dc_state)
4199 ret = fill_dc_scaling_info(state, &scaling_info);
4203 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
4209 static int dm_plane_atomic_async_check(struct drm_plane *plane,
4210 struct drm_plane_state *new_plane_state)
4212 struct drm_plane_state *old_plane_state =
4213 drm_atomic_get_old_plane_state(new_plane_state->state, plane);
4215 /* Only support async updates on cursor planes. */
4216 if (plane->type != DRM_PLANE_TYPE_CURSOR)
4220 * DRM calls prepare_fb and cleanup_fb on new_plane_state for
4221 * async commits so don't allow fb changes.
4223 if (old_plane_state->fb != new_plane_state->fb)
4229 static void dm_plane_atomic_async_update(struct drm_plane *plane,
4230 struct drm_plane_state *new_state)
4232 struct drm_plane_state *old_state =
4233 drm_atomic_get_old_plane_state(new_state->state, plane);
4235 swap(plane->state->fb, new_state->fb);
4237 plane->state->src_x = new_state->src_x;
4238 plane->state->src_y = new_state->src_y;
4239 plane->state->src_w = new_state->src_w;
4240 plane->state->src_h = new_state->src_h;
4241 plane->state->crtc_x = new_state->crtc_x;
4242 plane->state->crtc_y = new_state->crtc_y;
4243 plane->state->crtc_w = new_state->crtc_w;
4244 plane->state->crtc_h = new_state->crtc_h;
4246 handle_cursor_update(plane, old_state);
4249 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
4250 .prepare_fb = dm_plane_helper_prepare_fb,
4251 .cleanup_fb = dm_plane_helper_cleanup_fb,
4252 .atomic_check = dm_plane_atomic_check,
4253 .atomic_async_check = dm_plane_atomic_async_check,
4254 .atomic_async_update = dm_plane_atomic_async_update
4258 * TODO: these are currently initialized to rgb formats only.
4259 * For future use cases we should either initialize them dynamically based on
4260 * plane capabilities, or initialize this array to all formats, so internal drm
4261 * check will succeed, and let DC implement proper check
4263 static const uint32_t rgb_formats[] = {
4264 DRM_FORMAT_XRGB8888,
4265 DRM_FORMAT_ARGB8888,
4266 DRM_FORMAT_RGBA8888,
4267 DRM_FORMAT_XRGB2101010,
4268 DRM_FORMAT_XBGR2101010,
4269 DRM_FORMAT_ARGB2101010,
4270 DRM_FORMAT_ABGR2101010,
4271 DRM_FORMAT_XBGR8888,
4272 DRM_FORMAT_ABGR8888,
4276 static const uint32_t overlay_formats[] = {
4277 DRM_FORMAT_XRGB8888,
4278 DRM_FORMAT_ARGB8888,
4279 DRM_FORMAT_RGBA8888,
4280 DRM_FORMAT_XBGR8888,
4281 DRM_FORMAT_ABGR8888,
4285 static const u32 cursor_formats[] = {
4289 static int get_plane_formats(const struct drm_plane *plane,
4290 const struct dc_plane_cap *plane_cap,
4291 uint32_t *formats, int max_formats)
4293 int i, num_formats = 0;
4296 * TODO: Query support for each group of formats directly from
4297 * DC plane caps. This will require adding more formats to the
4301 switch (plane->type) {
4302 case DRM_PLANE_TYPE_PRIMARY:
4303 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) {
4304 if (num_formats >= max_formats)
4307 formats[num_formats++] = rgb_formats[i];
4310 if (plane_cap && plane_cap->pixel_format_support.nv12)
4311 formats[num_formats++] = DRM_FORMAT_NV12;
4314 case DRM_PLANE_TYPE_OVERLAY:
4315 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) {
4316 if (num_formats >= max_formats)
4319 formats[num_formats++] = overlay_formats[i];
4323 case DRM_PLANE_TYPE_CURSOR:
4324 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) {
4325 if (num_formats >= max_formats)
4328 formats[num_formats++] = cursor_formats[i];
4336 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
4337 struct drm_plane *plane,
4338 unsigned long possible_crtcs,
4339 const struct dc_plane_cap *plane_cap)
4341 uint32_t formats[32];
4345 num_formats = get_plane_formats(plane, plane_cap, formats,
4346 ARRAY_SIZE(formats));
4348 res = drm_universal_plane_init(dm->adev->ddev, plane, possible_crtcs,
4349 &dm_plane_funcs, formats, num_formats,
4350 NULL, plane->type, NULL);
4354 if (plane->type == DRM_PLANE_TYPE_OVERLAY &&
4355 plane_cap && plane_cap->per_pixel_alpha) {
4356 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
4357 BIT(DRM_MODE_BLEND_PREMULTI);
4359 drm_plane_create_alpha_property(plane);
4360 drm_plane_create_blend_mode_property(plane, blend_caps);
4363 if (plane->type == DRM_PLANE_TYPE_PRIMARY &&
4364 plane_cap && plane_cap->pixel_format_support.nv12) {
4365 /* This only affects YUV formats. */
4366 drm_plane_create_color_properties(
4368 BIT(DRM_COLOR_YCBCR_BT601) |
4369 BIT(DRM_COLOR_YCBCR_BT709),
4370 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
4371 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
4372 DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE);
4375 drm_plane_helper_add(plane, &dm_plane_helper_funcs);
4377 /* Create (reset) the plane state */
4378 if (plane->funcs->reset)
4379 plane->funcs->reset(plane);
4384 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
4385 struct drm_plane *plane,
4386 uint32_t crtc_index)
4388 struct amdgpu_crtc *acrtc = NULL;
4389 struct drm_plane *cursor_plane;
4393 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
4397 cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
4398 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
4400 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
4404 res = drm_crtc_init_with_planes(
4409 &amdgpu_dm_crtc_funcs, NULL);
4414 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
4416 /* Create (reset) the plane state */
4417 if (acrtc->base.funcs->reset)
4418 acrtc->base.funcs->reset(&acrtc->base);
4420 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
4421 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
4423 acrtc->crtc_id = crtc_index;
4424 acrtc->base.enabled = false;
4425 acrtc->otg_inst = -1;
4427 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
4428 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
4429 true, MAX_COLOR_LUT_ENTRIES);
4430 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
4436 kfree(cursor_plane);
4441 static int to_drm_connector_type(enum signal_type st)
4444 case SIGNAL_TYPE_HDMI_TYPE_A:
4445 return DRM_MODE_CONNECTOR_HDMIA;
4446 case SIGNAL_TYPE_EDP:
4447 return DRM_MODE_CONNECTOR_eDP;
4448 case SIGNAL_TYPE_LVDS:
4449 return DRM_MODE_CONNECTOR_LVDS;
4450 case SIGNAL_TYPE_RGB:
4451 return DRM_MODE_CONNECTOR_VGA;
4452 case SIGNAL_TYPE_DISPLAY_PORT:
4453 case SIGNAL_TYPE_DISPLAY_PORT_MST:
4454 return DRM_MODE_CONNECTOR_DisplayPort;
4455 case SIGNAL_TYPE_DVI_DUAL_LINK:
4456 case SIGNAL_TYPE_DVI_SINGLE_LINK:
4457 return DRM_MODE_CONNECTOR_DVID;
4458 case SIGNAL_TYPE_VIRTUAL:
4459 return DRM_MODE_CONNECTOR_VIRTUAL;
4462 return DRM_MODE_CONNECTOR_Unknown;
4466 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
4468 return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]);
4471 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
4473 struct drm_encoder *encoder;
4474 struct amdgpu_encoder *amdgpu_encoder;
4476 encoder = amdgpu_dm_connector_to_encoder(connector);
4478 if (encoder == NULL)
4481 amdgpu_encoder = to_amdgpu_encoder(encoder);
4483 amdgpu_encoder->native_mode.clock = 0;
4485 if (!list_empty(&connector->probed_modes)) {
4486 struct drm_display_mode *preferred_mode = NULL;
4488 list_for_each_entry(preferred_mode,
4489 &connector->probed_modes,
4491 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
4492 amdgpu_encoder->native_mode = *preferred_mode;
4500 static struct drm_display_mode *
4501 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
4503 int hdisplay, int vdisplay)
4505 struct drm_device *dev = encoder->dev;
4506 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
4507 struct drm_display_mode *mode = NULL;
4508 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
4510 mode = drm_mode_duplicate(dev, native_mode);
4515 mode->hdisplay = hdisplay;
4516 mode->vdisplay = vdisplay;
4517 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
4518 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
4524 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
4525 struct drm_connector *connector)
4527 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
4528 struct drm_display_mode *mode = NULL;
4529 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
4530 struct amdgpu_dm_connector *amdgpu_dm_connector =
4531 to_amdgpu_dm_connector(connector);
4535 char name[DRM_DISPLAY_MODE_LEN];
4538 } common_modes[] = {
4539 { "640x480", 640, 480},
4540 { "800x600", 800, 600},
4541 { "1024x768", 1024, 768},
4542 { "1280x720", 1280, 720},
4543 { "1280x800", 1280, 800},
4544 {"1280x1024", 1280, 1024},
4545 { "1440x900", 1440, 900},
4546 {"1680x1050", 1680, 1050},
4547 {"1600x1200", 1600, 1200},
4548 {"1920x1080", 1920, 1080},
4549 {"1920x1200", 1920, 1200}
4552 n = ARRAY_SIZE(common_modes);
4554 for (i = 0; i < n; i++) {
4555 struct drm_display_mode *curmode = NULL;
4556 bool mode_existed = false;
4558 if (common_modes[i].w > native_mode->hdisplay ||
4559 common_modes[i].h > native_mode->vdisplay ||
4560 (common_modes[i].w == native_mode->hdisplay &&
4561 common_modes[i].h == native_mode->vdisplay))
4564 list_for_each_entry(curmode, &connector->probed_modes, head) {
4565 if (common_modes[i].w == curmode->hdisplay &&
4566 common_modes[i].h == curmode->vdisplay) {
4567 mode_existed = true;
4575 mode = amdgpu_dm_create_common_mode(encoder,
4576 common_modes[i].name, common_modes[i].w,
4578 drm_mode_probed_add(connector, mode);
4579 amdgpu_dm_connector->num_modes++;
4583 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
4586 struct amdgpu_dm_connector *amdgpu_dm_connector =
4587 to_amdgpu_dm_connector(connector);
4590 /* empty probed_modes */
4591 INIT_LIST_HEAD(&connector->probed_modes);
4592 amdgpu_dm_connector->num_modes =
4593 drm_add_edid_modes(connector, edid);
4595 amdgpu_dm_get_native_mode(connector);
4597 amdgpu_dm_connector->num_modes = 0;
4601 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
4603 struct amdgpu_dm_connector *amdgpu_dm_connector =
4604 to_amdgpu_dm_connector(connector);
4605 struct drm_encoder *encoder;
4606 struct edid *edid = amdgpu_dm_connector->edid;
4608 encoder = amdgpu_dm_connector_to_encoder(connector);
4610 if (!edid || !drm_edid_is_valid(edid)) {
4611 amdgpu_dm_connector->num_modes =
4612 drm_add_modes_noedid(connector, 640, 480);
4614 amdgpu_dm_connector_ddc_get_modes(connector, edid);
4615 amdgpu_dm_connector_add_common_modes(encoder, connector);
4617 amdgpu_dm_fbc_init(connector);
4619 return amdgpu_dm_connector->num_modes;
4622 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
4623 struct amdgpu_dm_connector *aconnector,
4625 struct dc_link *link,
4628 struct amdgpu_device *adev = dm->ddev->dev_private;
4630 aconnector->connector_id = link_index;
4631 aconnector->dc_link = link;
4632 aconnector->base.interlace_allowed = false;
4633 aconnector->base.doublescan_allowed = false;
4634 aconnector->base.stereo_allowed = false;
4635 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
4636 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
4637 mutex_init(&aconnector->hpd_lock);
4640 * configure support HPD hot plug connector_>polled default value is 0
4641 * which means HPD hot plug not supported
4643 switch (connector_type) {
4644 case DRM_MODE_CONNECTOR_HDMIA:
4645 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
4646 aconnector->base.ycbcr_420_allowed =
4647 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
4649 case DRM_MODE_CONNECTOR_DisplayPort:
4650 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
4651 aconnector->base.ycbcr_420_allowed =
4652 link->link_enc->features.dp_ycbcr420_supported ? true : false;
4654 case DRM_MODE_CONNECTOR_DVID:
4655 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
4661 drm_object_attach_property(&aconnector->base.base,
4662 dm->ddev->mode_config.scaling_mode_property,
4663 DRM_MODE_SCALE_NONE);
4665 drm_object_attach_property(&aconnector->base.base,
4666 adev->mode_info.underscan_property,
4668 drm_object_attach_property(&aconnector->base.base,
4669 adev->mode_info.underscan_hborder_property,
4671 drm_object_attach_property(&aconnector->base.base,
4672 adev->mode_info.underscan_vborder_property,
4674 drm_object_attach_property(&aconnector->base.base,
4675 adev->mode_info.max_bpc_property,
4678 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
4679 dc_is_dmcu_initialized(adev->dm.dc)) {
4680 drm_object_attach_property(&aconnector->base.base,
4681 adev->mode_info.abm_level_property, 0);
4684 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
4685 connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4686 connector_type == DRM_MODE_CONNECTOR_eDP) {
4687 drm_connector_attach_vrr_capable_property(
4692 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
4693 struct i2c_msg *msgs, int num)
4695 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
4696 struct ddc_service *ddc_service = i2c->ddc_service;
4697 struct i2c_command cmd;
4701 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
4706 cmd.number_of_payloads = num;
4707 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
4710 for (i = 0; i < num; i++) {
4711 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
4712 cmd.payloads[i].address = msgs[i].addr;
4713 cmd.payloads[i].length = msgs[i].len;
4714 cmd.payloads[i].data = msgs[i].buf;
4718 ddc_service->ctx->dc,
4719 ddc_service->ddc_pin->hw_info.ddc_channel,
4723 kfree(cmd.payloads);
4727 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
4729 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
4732 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
4733 .master_xfer = amdgpu_dm_i2c_xfer,
4734 .functionality = amdgpu_dm_i2c_func,
4737 static struct amdgpu_i2c_adapter *
4738 create_i2c(struct ddc_service *ddc_service,
4742 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
4743 struct amdgpu_i2c_adapter *i2c;
4745 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
4748 i2c->base.owner = THIS_MODULE;
4749 i2c->base.class = I2C_CLASS_DDC;
4750 i2c->base.dev.parent = &adev->pdev->dev;
4751 i2c->base.algo = &amdgpu_dm_i2c_algo;
4752 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
4753 i2c_set_adapdata(&i2c->base, i2c);
4754 i2c->ddc_service = ddc_service;
4755 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
4762 * Note: this function assumes that dc_link_detect() was called for the
4763 * dc_link which will be represented by this aconnector.
4765 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
4766 struct amdgpu_dm_connector *aconnector,
4767 uint32_t link_index,
4768 struct amdgpu_encoder *aencoder)
4772 struct dc *dc = dm->dc;
4773 struct dc_link *link = dc_get_link_at_index(dc, link_index);
4774 struct amdgpu_i2c_adapter *i2c;
4776 link->priv = aconnector;
4778 DRM_DEBUG_DRIVER("%s()\n", __func__);
4780 i2c = create_i2c(link->ddc, link->link_index, &res);
4782 DRM_ERROR("Failed to create i2c adapter data\n");
4786 aconnector->i2c = i2c;
4787 res = i2c_add_adapter(&i2c->base);
4790 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
4794 connector_type = to_drm_connector_type(link->connector_signal);
4796 res = drm_connector_init(
4799 &amdgpu_dm_connector_funcs,
4803 DRM_ERROR("connector_init failed\n");
4804 aconnector->connector_id = -1;
4808 drm_connector_helper_add(
4810 &amdgpu_dm_connector_helper_funcs);
4812 if (aconnector->base.funcs->reset)
4813 aconnector->base.funcs->reset(&aconnector->base);
4815 amdgpu_dm_connector_init_helper(
4822 drm_connector_attach_encoder(
4823 &aconnector->base, &aencoder->base);
4825 drm_connector_register(&aconnector->base);
4826 #if defined(CONFIG_DEBUG_FS)
4827 res = connector_debugfs_init(aconnector);
4829 DRM_ERROR("Failed to create debugfs for connector");
4832 aconnector->debugfs_dpcd_address = 0;
4833 aconnector->debugfs_dpcd_size = 0;
4836 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
4837 || connector_type == DRM_MODE_CONNECTOR_eDP)
4838 amdgpu_dm_initialize_dp_connector(dm, aconnector);
4843 aconnector->i2c = NULL;
4848 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
4850 switch (adev->mode_info.num_crtc) {
4867 static int amdgpu_dm_encoder_init(struct drm_device *dev,
4868 struct amdgpu_encoder *aencoder,
4869 uint32_t link_index)
4871 struct amdgpu_device *adev = dev->dev_private;
4873 int res = drm_encoder_init(dev,
4875 &amdgpu_dm_encoder_funcs,
4876 DRM_MODE_ENCODER_TMDS,
4879 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
4882 aencoder->encoder_id = link_index;
4884 aencoder->encoder_id = -1;
4886 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
4891 static void manage_dm_interrupts(struct amdgpu_device *adev,
4892 struct amdgpu_crtc *acrtc,
4896 * this is not correct translation but will work as soon as VBLANK
4897 * constant is the same as PFLIP
4900 amdgpu_display_crtc_idx_to_irq_type(
4905 drm_crtc_vblank_on(&acrtc->base);
4908 &adev->pageflip_irq,
4914 &adev->pageflip_irq,
4916 drm_crtc_vblank_off(&acrtc->base);
4921 is_scaling_state_different(const struct dm_connector_state *dm_state,
4922 const struct dm_connector_state *old_dm_state)
4924 if (dm_state->scaling != old_dm_state->scaling)
4926 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
4927 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
4929 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
4930 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
4932 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
4933 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
4938 static void remove_stream(struct amdgpu_device *adev,
4939 struct amdgpu_crtc *acrtc,
4940 struct dc_stream_state *stream)
4942 /* this is the update mode case */
4944 acrtc->otg_inst = -1;
4945 acrtc->enabled = false;
4948 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
4949 struct dc_cursor_position *position)
4951 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
4953 int xorigin = 0, yorigin = 0;
4955 if (!crtc || !plane->state->fb) {
4956 position->enable = false;
4962 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
4963 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
4964 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
4966 plane->state->crtc_w,
4967 plane->state->crtc_h);
4971 x = plane->state->crtc_x;
4972 y = plane->state->crtc_y;
4974 if (crtc->primary->state) {
4975 /* avivo cursor are offset into the total surface */
4976 x += crtc->primary->state->src_x >> 16;
4977 y += crtc->primary->state->src_y >> 16;
4981 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
4985 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
4988 position->enable = true;
4991 position->x_hotspot = xorigin;
4992 position->y_hotspot = yorigin;
4997 static void handle_cursor_update(struct drm_plane *plane,
4998 struct drm_plane_state *old_plane_state)
5000 struct amdgpu_device *adev = plane->dev->dev_private;
5001 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
5002 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
5003 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
5004 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
5005 uint64_t address = afb ? afb->address : 0;
5006 struct dc_cursor_position position;
5007 struct dc_cursor_attributes attributes;
5010 if (!plane->state->fb && !old_plane_state->fb)
5013 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
5015 amdgpu_crtc->crtc_id,
5016 plane->state->crtc_w,
5017 plane->state->crtc_h);
5019 ret = get_cursor_position(plane, crtc, &position);
5023 if (!position.enable) {
5024 /* turn off cursor */
5025 if (crtc_state && crtc_state->stream) {
5026 mutex_lock(&adev->dm.dc_lock);
5027 dc_stream_set_cursor_position(crtc_state->stream,
5029 mutex_unlock(&adev->dm.dc_lock);
5034 amdgpu_crtc->cursor_width = plane->state->crtc_w;
5035 amdgpu_crtc->cursor_height = plane->state->crtc_h;
5037 memset(&attributes, 0, sizeof(attributes));
5038 attributes.address.high_part = upper_32_bits(address);
5039 attributes.address.low_part = lower_32_bits(address);
5040 attributes.width = plane->state->crtc_w;
5041 attributes.height = plane->state->crtc_h;
5042 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
5043 attributes.rotation_angle = 0;
5044 attributes.attribute_flags.value = 0;
5046 attributes.pitch = attributes.width;
5048 if (crtc_state->stream) {
5049 mutex_lock(&adev->dm.dc_lock);
5050 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
5052 DRM_ERROR("DC failed to set cursor attributes\n");
5054 if (!dc_stream_set_cursor_position(crtc_state->stream,
5056 DRM_ERROR("DC failed to set cursor position\n");
5057 mutex_unlock(&adev->dm.dc_lock);
5061 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
5064 assert_spin_locked(&acrtc->base.dev->event_lock);
5065 WARN_ON(acrtc->event);
5067 acrtc->event = acrtc->base.state->event;
5069 /* Set the flip status */
5070 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
5072 /* Mark this event as consumed */
5073 acrtc->base.state->event = NULL;
5075 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
5079 static void update_freesync_state_on_stream(
5080 struct amdgpu_display_manager *dm,
5081 struct dm_crtc_state *new_crtc_state,
5082 struct dc_stream_state *new_stream,
5083 struct dc_plane_state *surface,
5084 u32 flip_timestamp_in_us)
5086 struct mod_vrr_params vrr_params;
5087 struct dc_info_packet vrr_infopacket = {0};
5088 struct amdgpu_device *adev = dm->adev;
5089 unsigned long flags;
5095 * TODO: Determine why min/max totals and vrefresh can be 0 here.
5096 * For now it's sufficient to just guard against these conditions.
5099 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
5102 spin_lock_irqsave(&adev->ddev->event_lock, flags);
5103 vrr_params = new_crtc_state->vrr_params;
5106 mod_freesync_handle_preflip(
5107 dm->freesync_module,
5110 flip_timestamp_in_us,
5113 if (adev->family < AMDGPU_FAMILY_AI &&
5114 amdgpu_dm_vrr_active(new_crtc_state)) {
5115 mod_freesync_handle_v_update(dm->freesync_module,
5116 new_stream, &vrr_params);
5120 mod_freesync_build_vrr_infopacket(
5121 dm->freesync_module,
5125 TRANSFER_FUNC_UNKNOWN,
5128 new_crtc_state->freesync_timing_changed |=
5129 (memcmp(&new_crtc_state->vrr_params.adjust,
5131 sizeof(vrr_params.adjust)) != 0);
5133 new_crtc_state->freesync_vrr_info_changed |=
5134 (memcmp(&new_crtc_state->vrr_infopacket,
5136 sizeof(vrr_infopacket)) != 0);
5138 new_crtc_state->vrr_params = vrr_params;
5139 new_crtc_state->vrr_infopacket = vrr_infopacket;
5141 new_stream->adjust = new_crtc_state->vrr_params.adjust;
5142 new_stream->vrr_infopacket = vrr_infopacket;
5144 if (new_crtc_state->freesync_vrr_info_changed)
5145 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
5146 new_crtc_state->base.crtc->base.id,
5147 (int)new_crtc_state->base.vrr_enabled,
5148 (int)vrr_params.state);
5150 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
5153 static void pre_update_freesync_state_on_stream(
5154 struct amdgpu_display_manager *dm,
5155 struct dm_crtc_state *new_crtc_state)
5157 struct dc_stream_state *new_stream = new_crtc_state->stream;
5158 struct mod_vrr_params vrr_params;
5159 struct mod_freesync_config config = new_crtc_state->freesync_config;
5160 struct amdgpu_device *adev = dm->adev;
5161 unsigned long flags;
5167 * TODO: Determine why min/max totals and vrefresh can be 0 here.
5168 * For now it's sufficient to just guard against these conditions.
5170 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
5173 spin_lock_irqsave(&adev->ddev->event_lock, flags);
5174 vrr_params = new_crtc_state->vrr_params;
5176 if (new_crtc_state->vrr_supported &&
5177 config.min_refresh_in_uhz &&
5178 config.max_refresh_in_uhz) {
5179 config.state = new_crtc_state->base.vrr_enabled ?
5180 VRR_STATE_ACTIVE_VARIABLE :
5183 config.state = VRR_STATE_UNSUPPORTED;
5186 mod_freesync_build_vrr_params(dm->freesync_module,
5188 &config, &vrr_params);
5190 new_crtc_state->freesync_timing_changed |=
5191 (memcmp(&new_crtc_state->vrr_params.adjust,
5193 sizeof(vrr_params.adjust)) != 0);
5195 new_crtc_state->vrr_params = vrr_params;
5196 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
5199 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
5200 struct dm_crtc_state *new_state)
5202 bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
5203 bool new_vrr_active = amdgpu_dm_vrr_active(new_state);
5205 if (!old_vrr_active && new_vrr_active) {
5206 /* Transition VRR inactive -> active:
5207 * While VRR is active, we must not disable vblank irq, as a
5208 * reenable after disable would compute bogus vblank/pflip
5209 * timestamps if it likely happened inside display front-porch.
5211 * We also need vupdate irq for the actual core vblank handling
5214 dm_set_vupdate_irq(new_state->base.crtc, true);
5215 drm_crtc_vblank_get(new_state->base.crtc);
5216 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
5217 __func__, new_state->base.crtc->base.id);
5218 } else if (old_vrr_active && !new_vrr_active) {
5219 /* Transition VRR active -> inactive:
5220 * Allow vblank irq disable again for fixed refresh rate.
5222 dm_set_vupdate_irq(new_state->base.crtc, false);
5223 drm_crtc_vblank_put(new_state->base.crtc);
5224 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
5225 __func__, new_state->base.crtc->base.id);
5229 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
5231 struct drm_plane *plane;
5232 struct drm_plane_state *old_plane_state, *new_plane_state;
5236 * TODO: Make this per-stream so we don't issue redundant updates for
5237 * commits with multiple streams.
5239 for_each_oldnew_plane_in_state(state, plane, old_plane_state,
5241 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5242 handle_cursor_update(plane, old_plane_state);
5245 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
5246 struct dc_state *dc_state,
5247 struct drm_device *dev,
5248 struct amdgpu_display_manager *dm,
5249 struct drm_crtc *pcrtc,
5250 bool wait_for_vblank)
5253 uint64_t timestamp_ns;
5254 struct drm_plane *plane;
5255 struct drm_plane_state *old_plane_state, *new_plane_state;
5256 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
5257 struct drm_crtc_state *new_pcrtc_state =
5258 drm_atomic_get_new_crtc_state(state, pcrtc);
5259 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
5260 struct dm_crtc_state *dm_old_crtc_state =
5261 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
5262 int planes_count = 0, vpos, hpos;
5264 unsigned long flags;
5265 struct amdgpu_bo *abo;
5266 uint64_t tiling_flags;
5267 uint32_t target_vblank, last_flip_vblank;
5268 bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
5269 bool pflip_present = false;
5271 struct dc_surface_update surface_updates[MAX_SURFACES];
5272 struct dc_plane_info plane_infos[MAX_SURFACES];
5273 struct dc_scaling_info scaling_infos[MAX_SURFACES];
5274 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
5275 struct dc_stream_update stream_update;
5278 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
5281 dm_error("Failed to allocate update bundle\n");
5286 * Disable the cursor first if we're disabling all the planes.
5287 * It'll remain on the screen after the planes are re-enabled
5290 if (acrtc_state->active_planes == 0)
5291 amdgpu_dm_commit_cursors(state);
5293 /* update planes when needed */
5294 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
5295 struct drm_crtc *crtc = new_plane_state->crtc;
5296 struct drm_crtc_state *new_crtc_state;
5297 struct drm_framebuffer *fb = new_plane_state->fb;
5298 bool plane_needs_flip;
5299 struct dc_plane_state *dc_plane;
5300 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
5302 /* Cursor plane is handled after stream updates */
5303 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5306 if (!fb || !crtc || pcrtc != crtc)
5309 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
5310 if (!new_crtc_state->active)
5313 dc_plane = dm_new_plane_state->dc_state;
5315 bundle->surface_updates[planes_count].surface = dc_plane;
5316 if (new_pcrtc_state->color_mgmt_changed) {
5317 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
5318 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
5321 fill_dc_scaling_info(new_plane_state,
5322 &bundle->scaling_infos[planes_count]);
5324 bundle->surface_updates[planes_count].scaling_info =
5325 &bundle->scaling_infos[planes_count];
5327 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
5329 pflip_present = pflip_present || plane_needs_flip;
5331 if (!plane_needs_flip) {
5336 abo = gem_to_amdgpu_bo(fb->obj[0]);
5339 * Wait for all fences on this FB. Do limited wait to avoid
5340 * deadlock during GPU reset when this fence will not signal
5341 * but we hold reservation lock for the BO.
5343 r = reservation_object_wait_timeout_rcu(abo->tbo.resv, true,
5345 msecs_to_jiffies(5000));
5346 if (unlikely(r <= 0))
5347 DRM_ERROR("Waiting for fences timed out or interrupted!");
5350 * TODO This might fail and hence better not used, wait
5351 * explicitly on fences instead
5352 * and in general should be called for
5353 * blocking commit to as per framework helpers
5355 r = amdgpu_bo_reserve(abo, true);
5356 if (unlikely(r != 0))
5357 DRM_ERROR("failed to reserve buffer before flip\n");
5359 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
5361 amdgpu_bo_unreserve(abo);
5363 fill_dc_plane_info_and_addr(
5364 dm->adev, new_plane_state, tiling_flags,
5365 &bundle->plane_infos[planes_count],
5366 &bundle->flip_addrs[planes_count].address);
5368 bundle->surface_updates[planes_count].plane_info =
5369 &bundle->plane_infos[planes_count];
5371 bundle->flip_addrs[planes_count].flip_immediate =
5372 (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
5374 timestamp_ns = ktime_get_ns();
5375 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
5376 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
5377 bundle->surface_updates[planes_count].surface = dc_plane;
5379 if (!bundle->surface_updates[planes_count].surface) {
5380 DRM_ERROR("No surface for CRTC: id=%d\n",
5381 acrtc_attach->crtc_id);
5385 if (plane == pcrtc->primary)
5386 update_freesync_state_on_stream(
5389 acrtc_state->stream,
5391 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
5393 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n",
5395 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
5396 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
5402 if (pflip_present) {
5404 /* Use old throttling in non-vrr fixed refresh rate mode
5405 * to keep flip scheduling based on target vblank counts
5406 * working in a backwards compatible way, e.g., for
5407 * clients using the GLX_OML_sync_control extension or
5408 * DRI3/Present extension with defined target_msc.
5410 last_flip_vblank = amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id);
5413 /* For variable refresh rate mode only:
5414 * Get vblank of last completed flip to avoid > 1 vrr
5415 * flips per video frame by use of throttling, but allow
5416 * flip programming anywhere in the possibly large
5417 * variable vrr vblank interval for fine-grained flip
5418 * timing control and more opportunity to avoid stutter
5419 * on late submission of flips.
5421 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
5422 last_flip_vblank = acrtc_attach->last_flip_vblank;
5423 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
5426 target_vblank = last_flip_vblank + wait_for_vblank;
5429 * Wait until we're out of the vertical blank period before the one
5430 * targeted by the flip
5432 while ((acrtc_attach->enabled &&
5433 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
5434 0, &vpos, &hpos, NULL,
5435 NULL, &pcrtc->hwmode)
5436 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
5437 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
5438 (int)(target_vblank -
5439 amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id)) > 0)) {
5440 usleep_range(1000, 1100);
5443 if (acrtc_attach->base.state->event) {
5444 drm_crtc_vblank_get(pcrtc);
5446 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
5448 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
5449 prepare_flip_isr(acrtc_attach);
5451 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
5454 if (acrtc_state->stream) {
5456 if (acrtc_state->freesync_timing_changed)
5457 bundle->stream_update.adjust =
5458 &acrtc_state->stream->adjust;
5460 if (acrtc_state->freesync_vrr_info_changed)
5461 bundle->stream_update.vrr_infopacket =
5462 &acrtc_state->stream->vrr_infopacket;
5466 /* Update the planes if changed or disable if we don't have any. */
5467 if (planes_count || acrtc_state->active_planes == 0) {
5468 if (new_pcrtc_state->mode_changed) {
5469 bundle->stream_update.src = acrtc_state->stream->src;
5470 bundle->stream_update.dst = acrtc_state->stream->dst;
5473 if (new_pcrtc_state->color_mgmt_changed)
5474 bundle->stream_update.out_transfer_func = acrtc_state->stream->out_transfer_func;
5476 acrtc_state->stream->abm_level = acrtc_state->abm_level;
5477 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
5478 bundle->stream_update.abm_level = &acrtc_state->abm_level;
5480 mutex_lock(&dm->dc_lock);
5481 dc_commit_updates_for_stream(dm->dc,
5482 bundle->surface_updates,
5484 acrtc_state->stream,
5485 &bundle->stream_update,
5487 mutex_unlock(&dm->dc_lock);
5491 * Update cursor state *after* programming all the planes.
5492 * This avoids redundant programming in the case where we're going
5493 * to be disabling a single plane - those pipes are being disabled.
5495 if (acrtc_state->active_planes)
5496 amdgpu_dm_commit_cursors(state);
5503 * Enable interrupts on CRTCs that are newly active, undergone
5504 * a modeset, or have active planes again.
5506 * Done in two passes, based on the for_modeset flag:
5507 * Pass 1: For CRTCs going through modeset
5508 * Pass 2: For CRTCs going from 0 to n active planes
5510 * Interrupts can only be enabled after the planes are programmed,
5511 * so this requires a two-pass approach since we don't want to
5512 * just defer the interrupts until after commit planes every time.
5514 static void amdgpu_dm_enable_crtc_interrupts(struct drm_device *dev,
5515 struct drm_atomic_state *state,
5518 struct amdgpu_device *adev = dev->dev_private;
5519 struct drm_crtc *crtc;
5520 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
5523 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
5524 new_crtc_state, i) {
5525 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5526 struct dm_crtc_state *dm_new_crtc_state =
5527 to_dm_crtc_state(new_crtc_state);
5528 struct dm_crtc_state *dm_old_crtc_state =
5529 to_dm_crtc_state(old_crtc_state);
5530 bool modeset = drm_atomic_crtc_needs_modeset(new_crtc_state);
5533 run_pass = (for_modeset && modeset) ||
5534 (!for_modeset && !modeset &&
5535 !dm_old_crtc_state->interrupts_enabled);
5540 if (!dm_new_crtc_state->interrupts_enabled)
5543 manage_dm_interrupts(adev, acrtc, true);
5545 #ifdef CONFIG_DEBUG_FS
5546 /* The stream has changed so CRC capture needs to re-enabled. */
5547 if (dm_new_crtc_state->crc_enabled) {
5548 dm_new_crtc_state->crc_enabled = false;
5549 amdgpu_dm_crtc_set_crc_source(crtc, "auto");
5556 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
5557 * @crtc_state: the DRM CRTC state
5558 * @stream_state: the DC stream state.
5560 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
5561 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
5563 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
5564 struct dc_stream_state *stream_state)
5566 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
5569 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
5570 struct drm_atomic_state *state,
5573 struct drm_crtc *crtc;
5574 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
5575 struct amdgpu_device *adev = dev->dev_private;
5579 * We evade vblank and pflip interrupts on CRTCs that are undergoing
5580 * a modeset, being disabled, or have no active planes.
5582 * It's done in atomic commit rather than commit tail for now since
5583 * some of these interrupt handlers access the current CRTC state and
5584 * potentially the stream pointer itself.
5586 * Since the atomic state is swapped within atomic commit and not within
5587 * commit tail this would leave to new state (that hasn't been committed yet)
5588 * being accesssed from within the handlers.
5590 * TODO: Fix this so we can do this in commit tail and not have to block
5593 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5594 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5595 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5596 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5598 if (dm_old_crtc_state->interrupts_enabled &&
5599 (!dm_new_crtc_state->interrupts_enabled ||
5600 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
5602 * Drop the extra vblank reference added by CRC
5603 * capture if applicable.
5605 if (dm_new_crtc_state->crc_enabled)
5606 drm_crtc_vblank_put(crtc);
5609 * Only keep CRC capture enabled if there's
5610 * still a stream for the CRTC.
5612 if (!dm_new_crtc_state->stream)
5613 dm_new_crtc_state->crc_enabled = false;
5615 manage_dm_interrupts(adev, acrtc, false);
5619 * Add check here for SoC's that support hardware cursor plane, to
5620 * unset legacy_cursor_update
5623 return drm_atomic_helper_commit(dev, state, nonblock);
5625 /*TODO Handle EINTR, reenable IRQ*/
5629 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
5630 * @state: The atomic state to commit
5632 * This will tell DC to commit the constructed DC state from atomic_check,
5633 * programming the hardware. Any failures here implies a hardware failure, since
5634 * atomic check should have filtered anything non-kosher.
5636 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
5638 struct drm_device *dev = state->dev;
5639 struct amdgpu_device *adev = dev->dev_private;
5640 struct amdgpu_display_manager *dm = &adev->dm;
5641 struct dm_atomic_state *dm_state;
5642 struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
5644 struct drm_crtc *crtc;
5645 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
5646 unsigned long flags;
5647 bool wait_for_vblank = true;
5648 struct drm_connector *connector;
5649 struct drm_connector_state *old_con_state, *new_con_state;
5650 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
5651 int crtc_disable_count = 0;
5653 drm_atomic_helper_update_legacy_modeset_state(dev, state);
5655 dm_state = dm_atomic_get_new_state(state);
5656 if (dm_state && dm_state->context) {
5657 dc_state = dm_state->context;
5659 /* No state changes, retain current state. */
5660 dc_state_temp = dc_create_state(dm->dc);
5661 ASSERT(dc_state_temp);
5662 dc_state = dc_state_temp;
5663 dc_resource_state_copy_construct_current(dm->dc, dc_state);
5666 /* update changed items */
5667 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5668 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5670 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5671 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5674 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
5675 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
5676 "connectors_changed:%d\n",
5678 new_crtc_state->enable,
5679 new_crtc_state->active,
5680 new_crtc_state->planes_changed,
5681 new_crtc_state->mode_changed,
5682 new_crtc_state->active_changed,
5683 new_crtc_state->connectors_changed);
5685 /* Copy all transient state flags into dc state */
5686 if (dm_new_crtc_state->stream) {
5687 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
5688 dm_new_crtc_state->stream);
5691 /* handles headless hotplug case, updating new_state and
5692 * aconnector as needed
5695 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
5697 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
5699 if (!dm_new_crtc_state->stream) {
5701 * this could happen because of issues with
5702 * userspace notifications delivery.
5703 * In this case userspace tries to set mode on
5704 * display which is disconnected in fact.
5705 * dc_sink is NULL in this case on aconnector.
5706 * We expect reset mode will come soon.
5708 * This can also happen when unplug is done
5709 * during resume sequence ended
5711 * In this case, we want to pretend we still
5712 * have a sink to keep the pipe running so that
5713 * hw state is consistent with the sw state
5715 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
5716 __func__, acrtc->base.base.id);
5720 if (dm_old_crtc_state->stream)
5721 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
5723 pm_runtime_get_noresume(dev->dev);
5725 acrtc->enabled = true;
5726 acrtc->hw_mode = new_crtc_state->mode;
5727 crtc->hwmode = new_crtc_state->mode;
5728 } else if (modereset_required(new_crtc_state)) {
5729 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
5731 /* i.e. reset mode */
5732 if (dm_old_crtc_state->stream)
5733 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
5735 } /* for_each_crtc_in_state() */
5738 dm_enable_per_frame_crtc_master_sync(dc_state);
5739 mutex_lock(&dm->dc_lock);
5740 WARN_ON(!dc_commit_state(dm->dc, dc_state));
5741 mutex_unlock(&dm->dc_lock);
5744 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
5745 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5747 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5749 if (dm_new_crtc_state->stream != NULL) {
5750 const struct dc_stream_status *status =
5751 dc_stream_get_status(dm_new_crtc_state->stream);
5754 status = dc_stream_get_status_from_state(dc_state,
5755 dm_new_crtc_state->stream);
5758 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
5760 acrtc->otg_inst = status->primary_otg_inst;
5764 /* Handle connector state changes */
5765 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
5766 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
5767 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
5768 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
5769 struct dc_surface_update dummy_updates[MAX_SURFACES];
5770 struct dc_stream_update stream_update;
5771 struct dc_stream_status *status = NULL;
5773 memset(&dummy_updates, 0, sizeof(dummy_updates));
5774 memset(&stream_update, 0, sizeof(stream_update));
5777 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
5778 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
5781 /* Skip any modesets/resets */
5782 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
5785 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5786 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5788 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state) &&
5789 (dm_new_crtc_state->abm_level == dm_old_crtc_state->abm_level))
5792 if (is_scaling_state_different(dm_new_con_state, dm_old_con_state)) {
5793 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
5794 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
5796 stream_update.src = dm_new_crtc_state->stream->src;
5797 stream_update.dst = dm_new_crtc_state->stream->dst;
5800 if (dm_new_crtc_state->abm_level != dm_old_crtc_state->abm_level) {
5801 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
5803 stream_update.abm_level = &dm_new_crtc_state->abm_level;
5806 status = dc_stream_get_status(dm_new_crtc_state->stream);
5808 WARN_ON(!status->plane_count);
5811 * TODO: DC refuses to perform stream updates without a dc_surface_update.
5812 * Here we create an empty update on each plane.
5813 * To fix this, DC should permit updating only stream properties.
5815 for (j = 0; j < status->plane_count; j++)
5816 dummy_updates[j].surface = status->plane_states[0];
5819 mutex_lock(&dm->dc_lock);
5820 dc_commit_updates_for_stream(dm->dc,
5822 status->plane_count,
5823 dm_new_crtc_state->stream,
5826 mutex_unlock(&dm->dc_lock);
5829 /* Count number of newly disabled CRTCs for dropping PM refs later. */
5830 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
5831 new_crtc_state, i) {
5832 if (old_crtc_state->active && !new_crtc_state->active)
5833 crtc_disable_count++;
5835 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5836 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5838 /* Update freesync active state. */
5839 pre_update_freesync_state_on_stream(dm, dm_new_crtc_state);
5841 /* Handle vrr on->off / off->on transitions */
5842 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
5846 /* Enable interrupts for CRTCs going through a modeset. */
5847 amdgpu_dm_enable_crtc_interrupts(dev, state, true);
5849 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
5850 if (new_crtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC)
5851 wait_for_vblank = false;
5853 /* update planes when needed per crtc*/
5854 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
5855 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5857 if (dm_new_crtc_state->stream)
5858 amdgpu_dm_commit_planes(state, dc_state, dev,
5859 dm, crtc, wait_for_vblank);
5862 /* Enable interrupts for CRTCs going from 0 to n active planes. */
5863 amdgpu_dm_enable_crtc_interrupts(dev, state, false);
5866 * send vblank event on all events not handled in flip and
5867 * mark consumed event for drm_atomic_helper_commit_hw_done
5869 spin_lock_irqsave(&adev->ddev->event_lock, flags);
5870 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
5872 if (new_crtc_state->event)
5873 drm_send_event_locked(dev, &new_crtc_state->event->base);
5875 new_crtc_state->event = NULL;
5877 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
5879 /* Signal HW programming completion */
5880 drm_atomic_helper_commit_hw_done(state);
5882 if (wait_for_vblank)
5883 drm_atomic_helper_wait_for_flip_done(dev, state);
5885 drm_atomic_helper_cleanup_planes(dev, state);
5888 * Finally, drop a runtime PM reference for each newly disabled CRTC,
5889 * so we can put the GPU into runtime suspend if we're not driving any
5892 for (i = 0; i < crtc_disable_count; i++)
5893 pm_runtime_put_autosuspend(dev->dev);
5894 pm_runtime_mark_last_busy(dev->dev);
5897 dc_release_state(dc_state_temp);
5901 static int dm_force_atomic_commit(struct drm_connector *connector)
5904 struct drm_device *ddev = connector->dev;
5905 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
5906 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
5907 struct drm_plane *plane = disconnected_acrtc->base.primary;
5908 struct drm_connector_state *conn_state;
5909 struct drm_crtc_state *crtc_state;
5910 struct drm_plane_state *plane_state;
5915 state->acquire_ctx = ddev->mode_config.acquire_ctx;
5917 /* Construct an atomic state to restore previous display setting */
5920 * Attach connectors to drm_atomic_state
5922 conn_state = drm_atomic_get_connector_state(state, connector);
5924 ret = PTR_ERR_OR_ZERO(conn_state);
5928 /* Attach crtc to drm_atomic_state*/
5929 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
5931 ret = PTR_ERR_OR_ZERO(crtc_state);
5935 /* force a restore */
5936 crtc_state->mode_changed = true;
5938 /* Attach plane to drm_atomic_state */
5939 plane_state = drm_atomic_get_plane_state(state, plane);
5941 ret = PTR_ERR_OR_ZERO(plane_state);
5946 /* Call commit internally with the state we just constructed */
5947 ret = drm_atomic_commit(state);
5952 DRM_ERROR("Restoring old state failed with %i\n", ret);
5953 drm_atomic_state_put(state);
5959 * This function handles all cases when set mode does not come upon hotplug.
5960 * This includes when a display is unplugged then plugged back into the
5961 * same port and when running without usermode desktop manager supprot
5963 void dm_restore_drm_connector_state(struct drm_device *dev,
5964 struct drm_connector *connector)
5966 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5967 struct amdgpu_crtc *disconnected_acrtc;
5968 struct dm_crtc_state *acrtc_state;
5970 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
5973 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
5974 if (!disconnected_acrtc)
5977 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
5978 if (!acrtc_state->stream)
5982 * If the previous sink is not released and different from the current,
5983 * we deduce we are in a state where we can not rely on usermode call
5984 * to turn on the display, so we do it here
5986 if (acrtc_state->stream->sink != aconnector->dc_sink)
5987 dm_force_atomic_commit(&aconnector->base);
5991 * Grabs all modesetting locks to serialize against any blocking commits,
5992 * Waits for completion of all non blocking commits.
5994 static int do_aquire_global_lock(struct drm_device *dev,
5995 struct drm_atomic_state *state)
5997 struct drm_crtc *crtc;
5998 struct drm_crtc_commit *commit;
6002 * Adding all modeset locks to aquire_ctx will
6003 * ensure that when the framework release it the
6004 * extra locks we are locking here will get released to
6006 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
6010 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6011 spin_lock(&crtc->commit_lock);
6012 commit = list_first_entry_or_null(&crtc->commit_list,
6013 struct drm_crtc_commit, commit_entry);
6015 drm_crtc_commit_get(commit);
6016 spin_unlock(&crtc->commit_lock);
6022 * Make sure all pending HW programming completed and
6025 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
6028 ret = wait_for_completion_interruptible_timeout(
6029 &commit->flip_done, 10*HZ);
6032 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
6033 "timed out\n", crtc->base.id, crtc->name);
6035 drm_crtc_commit_put(commit);
6038 return ret < 0 ? ret : 0;
6041 static void get_freesync_config_for_crtc(
6042 struct dm_crtc_state *new_crtc_state,
6043 struct dm_connector_state *new_con_state)
6045 struct mod_freesync_config config = {0};
6046 struct amdgpu_dm_connector *aconnector =
6047 to_amdgpu_dm_connector(new_con_state->base.connector);
6048 struct drm_display_mode *mode = &new_crtc_state->base.mode;
6049 int vrefresh = drm_mode_vrefresh(mode);
6051 new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
6052 vrefresh >= aconnector->min_vfreq &&
6053 vrefresh <= aconnector->max_vfreq;
6055 if (new_crtc_state->vrr_supported) {
6056 new_crtc_state->stream->ignore_msa_timing_param = true;
6057 config.state = new_crtc_state->base.vrr_enabled ?
6058 VRR_STATE_ACTIVE_VARIABLE :
6060 config.min_refresh_in_uhz =
6061 aconnector->min_vfreq * 1000000;
6062 config.max_refresh_in_uhz =
6063 aconnector->max_vfreq * 1000000;
6064 config.vsif_supported = true;
6068 new_crtc_state->freesync_config = config;
6071 static void reset_freesync_config_for_crtc(
6072 struct dm_crtc_state *new_crtc_state)
6074 new_crtc_state->vrr_supported = false;
6076 memset(&new_crtc_state->vrr_params, 0,
6077 sizeof(new_crtc_state->vrr_params));
6078 memset(&new_crtc_state->vrr_infopacket, 0,
6079 sizeof(new_crtc_state->vrr_infopacket));
6082 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
6083 struct drm_atomic_state *state,
6084 struct drm_crtc *crtc,
6085 struct drm_crtc_state *old_crtc_state,
6086 struct drm_crtc_state *new_crtc_state,
6088 bool *lock_and_validation_needed)
6090 struct dm_atomic_state *dm_state = NULL;
6091 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
6092 struct dc_stream_state *new_stream;
6096 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
6097 * update changed items
6099 struct amdgpu_crtc *acrtc = NULL;
6100 struct amdgpu_dm_connector *aconnector = NULL;
6101 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
6102 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
6106 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6107 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6108 acrtc = to_amdgpu_crtc(crtc);
6109 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
6111 /* TODO This hack should go away */
6112 if (aconnector && enable) {
6113 /* Make sure fake sink is created in plug-in scenario */
6114 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
6116 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
6119 if (IS_ERR(drm_new_conn_state)) {
6120 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
6124 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
6125 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
6127 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6130 new_stream = create_stream_for_sink(aconnector,
6131 &new_crtc_state->mode,
6133 dm_old_crtc_state->stream);
6136 * we can have no stream on ACTION_SET if a display
6137 * was disconnected during S3, in this case it is not an
6138 * error, the OS will be updated after detection, and
6139 * will do the right thing on next atomic commit
6143 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
6144 __func__, acrtc->base.base.id);
6149 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
6151 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
6152 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
6153 new_crtc_state->mode_changed = false;
6154 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
6155 new_crtc_state->mode_changed);
6159 /* mode_changed flag may get updated above, need to check again */
6160 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6164 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
6165 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
6166 "connectors_changed:%d\n",
6168 new_crtc_state->enable,
6169 new_crtc_state->active,
6170 new_crtc_state->planes_changed,
6171 new_crtc_state->mode_changed,
6172 new_crtc_state->active_changed,
6173 new_crtc_state->connectors_changed);
6175 /* Remove stream for any changed/disabled CRTC */
6178 if (!dm_old_crtc_state->stream)
6181 ret = dm_atomic_get_state(state, &dm_state);
6185 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
6188 /* i.e. reset mode */
6189 if (dc_remove_stream_from_ctx(
6192 dm_old_crtc_state->stream) != DC_OK) {
6197 dc_stream_release(dm_old_crtc_state->stream);
6198 dm_new_crtc_state->stream = NULL;
6200 reset_freesync_config_for_crtc(dm_new_crtc_state);
6202 *lock_and_validation_needed = true;
6204 } else {/* Add stream for any updated/enabled CRTC */
6206 * Quick fix to prevent NULL pointer on new_stream when
6207 * added MST connectors not found in existing crtc_state in the chained mode
6208 * TODO: need to dig out the root cause of that
6210 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
6213 if (modereset_required(new_crtc_state))
6216 if (modeset_required(new_crtc_state, new_stream,
6217 dm_old_crtc_state->stream)) {
6219 WARN_ON(dm_new_crtc_state->stream);
6221 ret = dm_atomic_get_state(state, &dm_state);
6225 dm_new_crtc_state->stream = new_stream;
6227 dc_stream_retain(new_stream);
6229 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
6232 if (dc_add_stream_to_ctx(
6235 dm_new_crtc_state->stream) != DC_OK) {
6240 *lock_and_validation_needed = true;
6245 /* Release extra reference */
6247 dc_stream_release(new_stream);
6250 * We want to do dc stream updates that do not require a
6251 * full modeset below.
6253 if (!(enable && aconnector && new_crtc_state->enable &&
6254 new_crtc_state->active))
6257 * Given above conditions, the dc state cannot be NULL because:
6258 * 1. We're in the process of enabling CRTCs (just been added
6259 * to the dc context, or already is on the context)
6260 * 2. Has a valid connector attached, and
6261 * 3. Is currently active and enabled.
6262 * => The dc stream state currently exists.
6264 BUG_ON(dm_new_crtc_state->stream == NULL);
6266 /* Scaling or underscan settings */
6267 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
6268 update_stream_scaling_settings(
6269 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
6272 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
6275 * Color management settings. We also update color properties
6276 * when a modeset is needed, to ensure it gets reprogrammed.
6278 if (dm_new_crtc_state->base.color_mgmt_changed ||
6279 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
6280 ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
6283 amdgpu_dm_set_ctm(dm_new_crtc_state);
6286 /* Update Freesync settings. */
6287 get_freesync_config_for_crtc(dm_new_crtc_state,
6294 dc_stream_release(new_stream);
6298 static bool should_reset_plane(struct drm_atomic_state *state,
6299 struct drm_plane *plane,
6300 struct drm_plane_state *old_plane_state,
6301 struct drm_plane_state *new_plane_state)
6303 struct drm_plane *other;
6304 struct drm_plane_state *old_other_state, *new_other_state;
6305 struct drm_crtc_state *new_crtc_state;
6309 * TODO: Remove this hack once the checks below are sufficient
6310 * enough to determine when we need to reset all the planes on
6313 if (state->allow_modeset)
6316 /* Exit early if we know that we're adding or removing the plane. */
6317 if (old_plane_state->crtc != new_plane_state->crtc)
6320 /* old crtc == new_crtc == NULL, plane not in context. */
6321 if (!new_plane_state->crtc)
6325 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
6327 if (!new_crtc_state)
6330 if (drm_atomic_crtc_needs_modeset(new_crtc_state))
6334 * If there are any new primary or overlay planes being added or
6335 * removed then the z-order can potentially change. To ensure
6336 * correct z-order and pipe acquisition the current DC architecture
6337 * requires us to remove and recreate all existing planes.
6339 * TODO: Come up with a more elegant solution for this.
6341 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
6342 if (other->type == DRM_PLANE_TYPE_CURSOR)
6345 if (old_other_state->crtc != new_plane_state->crtc &&
6346 new_other_state->crtc != new_plane_state->crtc)
6349 if (old_other_state->crtc != new_other_state->crtc)
6352 /* TODO: Remove this once we can handle fast format changes. */
6353 if (old_other_state->fb && new_other_state->fb &&
6354 old_other_state->fb->format != new_other_state->fb->format)
6361 static int dm_update_plane_state(struct dc *dc,
6362 struct drm_atomic_state *state,
6363 struct drm_plane *plane,
6364 struct drm_plane_state *old_plane_state,
6365 struct drm_plane_state *new_plane_state,
6367 bool *lock_and_validation_needed)
6370 struct dm_atomic_state *dm_state = NULL;
6371 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
6372 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
6373 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
6374 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
6379 new_plane_crtc = new_plane_state->crtc;
6380 old_plane_crtc = old_plane_state->crtc;
6381 dm_new_plane_state = to_dm_plane_state(new_plane_state);
6382 dm_old_plane_state = to_dm_plane_state(old_plane_state);
6384 /*TODO Implement atomic check for cursor plane */
6385 if (plane->type == DRM_PLANE_TYPE_CURSOR)
6388 needs_reset = should_reset_plane(state, plane, old_plane_state,
6391 /* Remove any changed/removed planes */
6396 if (!old_plane_crtc)
6399 old_crtc_state = drm_atomic_get_old_crtc_state(
6400 state, old_plane_crtc);
6401 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6403 if (!dm_old_crtc_state->stream)
6406 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
6407 plane->base.id, old_plane_crtc->base.id);
6409 ret = dm_atomic_get_state(state, &dm_state);
6413 if (!dc_remove_plane_from_context(
6415 dm_old_crtc_state->stream,
6416 dm_old_plane_state->dc_state,
6417 dm_state->context)) {
6424 dc_plane_state_release(dm_old_plane_state->dc_state);
6425 dm_new_plane_state->dc_state = NULL;
6427 *lock_and_validation_needed = true;
6429 } else { /* Add new planes */
6430 struct dc_plane_state *dc_new_plane_state;
6432 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
6435 if (!new_plane_crtc)
6438 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
6439 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6441 if (!dm_new_crtc_state->stream)
6447 WARN_ON(dm_new_plane_state->dc_state);
6449 dc_new_plane_state = dc_create_plane_state(dc);
6450 if (!dc_new_plane_state)
6453 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
6454 plane->base.id, new_plane_crtc->base.id);
6456 ret = fill_dc_plane_attributes(
6457 new_plane_crtc->dev->dev_private,
6462 dc_plane_state_release(dc_new_plane_state);
6466 ret = dm_atomic_get_state(state, &dm_state);
6468 dc_plane_state_release(dc_new_plane_state);
6473 * Any atomic check errors that occur after this will
6474 * not need a release. The plane state will be attached
6475 * to the stream, and therefore part of the atomic
6476 * state. It'll be released when the atomic state is
6479 if (!dc_add_plane_to_context(
6481 dm_new_crtc_state->stream,
6483 dm_state->context)) {
6485 dc_plane_state_release(dc_new_plane_state);
6489 dm_new_plane_state->dc_state = dc_new_plane_state;
6491 /* Tell DC to do a full surface update every time there
6492 * is a plane change. Inefficient, but works for now.
6494 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
6496 *lock_and_validation_needed = true;
6504 dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
6505 struct drm_atomic_state *state,
6506 enum surface_update_type *out_type)
6508 struct dc *dc = dm->dc;
6509 struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL;
6510 int i, j, num_plane, ret = 0;
6511 struct drm_plane_state *old_plane_state, *new_plane_state;
6512 struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
6513 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
6514 struct drm_plane *plane;
6516 struct drm_crtc *crtc;
6517 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
6518 struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state;
6519 struct dc_stream_status *status = NULL;
6521 struct dc_surface_update *updates;
6522 enum surface_update_type update_type = UPDATE_TYPE_FAST;
6524 updates = kcalloc(MAX_SURFACES, sizeof(*updates), GFP_KERNEL);
6527 DRM_ERROR("Failed to allocate plane updates\n");
6528 /* Set type to FULL to avoid crashing in DC*/
6529 update_type = UPDATE_TYPE_FULL;
6533 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6534 struct dc_scaling_info scaling_info;
6535 struct dc_stream_update stream_update;
6537 memset(&stream_update, 0, sizeof(stream_update));
6539 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
6540 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
6543 if (new_dm_crtc_state->stream != old_dm_crtc_state->stream) {
6544 update_type = UPDATE_TYPE_FULL;
6548 if (!new_dm_crtc_state->stream)
6551 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
6552 new_plane_crtc = new_plane_state->crtc;
6553 old_plane_crtc = old_plane_state->crtc;
6554 new_dm_plane_state = to_dm_plane_state(new_plane_state);
6555 old_dm_plane_state = to_dm_plane_state(old_plane_state);
6557 if (plane->type == DRM_PLANE_TYPE_CURSOR)
6560 if (new_dm_plane_state->dc_state != old_dm_plane_state->dc_state) {
6561 update_type = UPDATE_TYPE_FULL;
6565 if (crtc != new_plane_crtc)
6568 updates[num_plane].surface = new_dm_plane_state->dc_state;
6570 if (new_crtc_state->mode_changed) {
6571 stream_update.dst = new_dm_crtc_state->stream->dst;
6572 stream_update.src = new_dm_crtc_state->stream->src;
6575 if (new_crtc_state->color_mgmt_changed) {
6576 updates[num_plane].gamma =
6577 new_dm_plane_state->dc_state->gamma_correction;
6578 updates[num_plane].in_transfer_func =
6579 new_dm_plane_state->dc_state->in_transfer_func;
6580 stream_update.gamut_remap =
6581 &new_dm_crtc_state->stream->gamut_remap_matrix;
6582 stream_update.out_transfer_func =
6583 new_dm_crtc_state->stream->out_transfer_func;
6586 ret = fill_dc_scaling_info(new_plane_state,
6591 updates[num_plane].scaling_info = &scaling_info;
6599 ret = dm_atomic_get_state(state, &dm_state);
6603 old_dm_state = dm_atomic_get_old_state(state);
6604 if (!old_dm_state) {
6609 status = dc_stream_get_status_from_state(old_dm_state->context,
6610 new_dm_crtc_state->stream);
6613 * TODO: DC modifies the surface during this call so we need
6614 * to lock here - find a way to do this without locking.
6616 mutex_lock(&dm->dc_lock);
6617 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
6618 &stream_update, status);
6619 mutex_unlock(&dm->dc_lock);
6621 if (update_type > UPDATE_TYPE_MED) {
6622 update_type = UPDATE_TYPE_FULL;
6630 *out_type = update_type;
6635 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
6636 * @dev: The DRM device
6637 * @state: The atomic state to commit
6639 * Validate that the given atomic state is programmable by DC into hardware.
6640 * This involves constructing a &struct dc_state reflecting the new hardware
6641 * state we wish to commit, then querying DC to see if it is programmable. It's
6642 * important not to modify the existing DC state. Otherwise, atomic_check
6643 * may unexpectedly commit hardware changes.
6645 * When validating the DC state, it's important that the right locks are
6646 * acquired. For full updates case which removes/adds/updates streams on one
6647 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
6648 * that any such full update commit will wait for completion of any outstanding
6649 * flip using DRMs synchronization events. See
6650 * dm_determine_update_type_for_commit()
6652 * Note that DM adds the affected connectors for all CRTCs in state, when that
6653 * might not seem necessary. This is because DC stream creation requires the
6654 * DC sink, which is tied to the DRM connector state. Cleaning this up should
6655 * be possible but non-trivial - a possible TODO item.
6657 * Return: -Error code if validation failed.
6659 static int amdgpu_dm_atomic_check(struct drm_device *dev,
6660 struct drm_atomic_state *state)
6662 struct amdgpu_device *adev = dev->dev_private;
6663 struct dm_atomic_state *dm_state = NULL;
6664 struct dc *dc = adev->dm.dc;
6665 struct drm_connector *connector;
6666 struct drm_connector_state *old_con_state, *new_con_state;
6667 struct drm_crtc *crtc;
6668 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
6669 struct drm_plane *plane;
6670 struct drm_plane_state *old_plane_state, *new_plane_state;
6671 enum surface_update_type update_type = UPDATE_TYPE_FAST;
6672 enum surface_update_type overall_update_type = UPDATE_TYPE_FAST;
6677 * This bool will be set for true for any modeset/reset
6678 * or plane update which implies non fast surface update.
6680 bool lock_and_validation_needed = false;
6682 ret = drm_atomic_helper_check_modeset(dev, state);
6686 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6687 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
6688 !new_crtc_state->color_mgmt_changed &&
6689 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled)
6692 if (!new_crtc_state->enable)
6695 ret = drm_atomic_add_affected_connectors(state, crtc);
6699 ret = drm_atomic_add_affected_planes(state, crtc);
6705 * Add all primary and overlay planes on the CRTC to the state
6706 * whenever a plane is enabled to maintain correct z-ordering
6707 * and to enable fast surface updates.
6709 drm_for_each_crtc(crtc, dev) {
6710 bool modified = false;
6712 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
6713 if (plane->type == DRM_PLANE_TYPE_CURSOR)
6716 if (new_plane_state->crtc == crtc ||
6717 old_plane_state->crtc == crtc) {
6726 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
6727 if (plane->type == DRM_PLANE_TYPE_CURSOR)
6731 drm_atomic_get_plane_state(state, plane);
6733 if (IS_ERR(new_plane_state)) {
6734 ret = PTR_ERR(new_plane_state);
6740 /* Remove exiting planes if they are modified */
6741 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
6742 ret = dm_update_plane_state(dc, state, plane,
6746 &lock_and_validation_needed);
6751 /* Disable all crtcs which require disable */
6752 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6753 ret = dm_update_crtc_state(&adev->dm, state, crtc,
6757 &lock_and_validation_needed);
6762 /* Enable all crtcs which require enable */
6763 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6764 ret = dm_update_crtc_state(&adev->dm, state, crtc,
6768 &lock_and_validation_needed);
6773 /* Add new/modified planes */
6774 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
6775 ret = dm_update_plane_state(dc, state, plane,
6779 &lock_and_validation_needed);
6784 /* Run this here since we want to validate the streams we created */
6785 ret = drm_atomic_helper_check_planes(dev, state);
6789 /* Check scaling and underscan changes*/
6790 /* TODO Removed scaling changes validation due to inability to commit
6791 * new stream into context w\o causing full reset. Need to
6792 * decide how to handle.
6794 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
6795 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
6796 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
6797 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
6799 /* Skip any modesets/resets */
6800 if (!acrtc || drm_atomic_crtc_needs_modeset(
6801 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
6804 /* Skip any thing not scale or underscan changes */
6805 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
6808 overall_update_type = UPDATE_TYPE_FULL;
6809 lock_and_validation_needed = true;
6812 ret = dm_determine_update_type_for_commit(&adev->dm, state, &update_type);
6816 if (overall_update_type < update_type)
6817 overall_update_type = update_type;
6820 * lock_and_validation_needed was an old way to determine if we need to set
6821 * the global lock. Leaving it in to check if we broke any corner cases
6822 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED
6823 * lock_and_validation_needed false = UPDATE_TYPE_FAST
6825 if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST)
6826 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL");
6828 if (overall_update_type > UPDATE_TYPE_FAST) {
6829 ret = dm_atomic_get_state(state, &dm_state);
6833 ret = do_aquire_global_lock(dev, state);
6837 if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) {
6841 } else if (state->legacy_cursor_update) {
6843 * This is a fast cursor update coming from the plane update
6844 * helper, check if it can be done asynchronously for better
6847 state->async_update = !drm_atomic_helper_async_check(dev, state);
6850 /* Must be success */
6855 if (ret == -EDEADLK)
6856 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
6857 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
6858 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
6860 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
6865 static bool is_dp_capable_without_timing_msa(struct dc *dc,
6866 struct amdgpu_dm_connector *amdgpu_dm_connector)
6869 bool capable = false;
6871 if (amdgpu_dm_connector->dc_link &&
6872 dm_helpers_dp_read_dpcd(
6874 amdgpu_dm_connector->dc_link,
6875 DP_DOWN_STREAM_PORT_COUNT,
6877 sizeof(dpcd_data))) {
6878 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
6883 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
6887 bool edid_check_required;
6888 struct detailed_timing *timing;
6889 struct detailed_non_pixel *data;
6890 struct detailed_data_monitor_range *range;
6891 struct amdgpu_dm_connector *amdgpu_dm_connector =
6892 to_amdgpu_dm_connector(connector);
6893 struct dm_connector_state *dm_con_state = NULL;
6895 struct drm_device *dev = connector->dev;
6896 struct amdgpu_device *adev = dev->dev_private;
6897 bool freesync_capable = false;
6899 if (!connector->state) {
6900 DRM_ERROR("%s - Connector has no state", __func__);
6905 dm_con_state = to_dm_connector_state(connector->state);
6907 amdgpu_dm_connector->min_vfreq = 0;
6908 amdgpu_dm_connector->max_vfreq = 0;
6909 amdgpu_dm_connector->pixel_clock_mhz = 0;
6914 dm_con_state = to_dm_connector_state(connector->state);
6916 edid_check_required = false;
6917 if (!amdgpu_dm_connector->dc_sink) {
6918 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
6921 if (!adev->dm.freesync_module)
6924 * if edid non zero restrict freesync only for dp and edp
6927 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
6928 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
6929 edid_check_required = is_dp_capable_without_timing_msa(
6931 amdgpu_dm_connector);
6934 if (edid_check_required == true && (edid->version > 1 ||
6935 (edid->version == 1 && edid->revision > 1))) {
6936 for (i = 0; i < 4; i++) {
6938 timing = &edid->detailed_timings[i];
6939 data = &timing->data.other_data;
6940 range = &data->data.range;
6942 * Check if monitor has continuous frequency mode
6944 if (data->type != EDID_DETAIL_MONITOR_RANGE)
6947 * Check for flag range limits only. If flag == 1 then
6948 * no additional timing information provided.
6949 * Default GTF, GTF Secondary curve and CVT are not
6952 if (range->flags != 1)
6955 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
6956 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
6957 amdgpu_dm_connector->pixel_clock_mhz =
6958 range->pixel_clock_mhz * 10;
6962 if (amdgpu_dm_connector->max_vfreq -
6963 amdgpu_dm_connector->min_vfreq > 10) {
6965 freesync_capable = true;
6971 dm_con_state->freesync_capable = freesync_capable;
6973 if (connector->vrr_capable_property)
6974 drm_connector_set_vrr_capable_property(connector,