drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services_types.h"
  27 #include "dc.h"
  28 #include "dc/inc/core_types.h"
  29
  30 #include "vid.h"
  31 #include "amdgpu.h"
  32 #include "amdgpu_display.h"
  33 #include "amdgpu_ucode.h"
  34 #include "atom.h"
  35 #include "amdgpu_dm.h"
  36 #include "amdgpu_pm.h"
  37
  38 #include "amd_shared.h"
  39 #include "amdgpu_dm_irq.h"
  40 #include "dm_helpers.h"
  41 #include "dm_services_types.h"
  42 #include "amdgpu_dm_mst_types.h"
  43 #if defined(CONFIG_DEBUG_FS)
  44 #include "amdgpu_dm_debugfs.h"
  45 #endif
  46
  47 #include "ivsrcid/ivsrcid_vislands30.h"
  48
  49 #include <linux/module.h>
  50 #include <linux/moduleparam.h>
  51 #include <linux/version.h>
  52 #include <linux/types.h>
  53 #include <linux/pm_runtime.h>
  54 #include <linux/firmware.h>
  55
  56 #include <drm/drmP.h>
  57 #include <drm/drm_atomic.h>
  58 #include <drm/drm_atomic_helper.h>
  59 #include <drm/drm_dp_mst_helper.h>
  60 #include <drm/drm_fb_helper.h>
  61 #include <drm/drm_edid.h>
  62
  63 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
  64 #include "ivsrcid/irqsrcs_dcn_1_0.h"
  65
  66 #include "dcn/dcn_1_0_offset.h"
  67 #include "dcn/dcn_1_0_sh_mask.h"
  68 #include "soc15_hw_ip.h"
  69 #include "vega10_ip_offset.h"
  70
  71 #include "soc15_common.h"
  72 #endif
  73
  74 #include "modules/inc/mod_freesync.h"
  75
  76 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
  77 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
  78
  79 /* basic init/fini API */
  80 static int amdgpu_dm_init(struct amdgpu_device *adev);
  81 static void amdgpu_dm_fini(struct amdgpu_device *adev);
  82
  83 /*
  84  * initializes drm_device display related structures, based on the information
  85  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
  86  * drm_encoder, drm_mode_config
  87  *
  88  * Returns 0 on success
  89  */
  90 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
  91 /* removes and deallocates the drm structures, created by the above function */
  92 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
  93
  94 static void
  95 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
  96
  97 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
  98                                 struct amdgpu_plane *aplane,
  99                                 unsigned long possible_crtcs);
 100 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
 101                                struct drm_plane *plane,
 102                                uint32_t link_index);
 103 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 104                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 105                                     uint32_t link_index,
 106                                     struct amdgpu_encoder *amdgpu_encoder);
 107 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 108                                   struct amdgpu_encoder *aencoder,
 109                                   uint32_t link_index);
 110
 111 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 112
 113 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
 114                                    struct drm_atomic_state *state,
 115                                    bool nonblock);
 116
 117 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 118
 119 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 120                                   struct drm_atomic_state *state);
 121
 122
 123
 124
 125 static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
 126         DRM_PLANE_TYPE_PRIMARY,
 127         DRM_PLANE_TYPE_PRIMARY,
 128         DRM_PLANE_TYPE_PRIMARY,
 129         DRM_PLANE_TYPE_PRIMARY,
 130         DRM_PLANE_TYPE_PRIMARY,
 131         DRM_PLANE_TYPE_PRIMARY,
 132 };
 133
 134 static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
 135         DRM_PLANE_TYPE_PRIMARY,
 136         DRM_PLANE_TYPE_PRIMARY,
 137         DRM_PLANE_TYPE_PRIMARY,
 138         DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
 139 };
 140
 141 static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
 142         DRM_PLANE_TYPE_PRIMARY,
 143         DRM_PLANE_TYPE_PRIMARY,
 144         DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
 145 };
 146
 147 /*
 148  * dm_vblank_get_counter
 149  *
 150  * @brief
 151  * Get counter for number of vertical blanks
 152  *
 153  * @param
 154  * struct amdgpu_device *adev - [in] desired amdgpu device
 155  * int disp_idx - [in] which CRTC to get the counter from
 156  *
 157  * @return
 158  * Counter for vertical blanks
 159  */
 160 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 161 {
 162         if (crtc >= adev->mode_info.num_crtc)
 163                 return 0;
 164         else {
 165                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 166                 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
 167                                 acrtc->base.state);
 168
 169
 170                 if (acrtc_state->stream == NULL) {
 171                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 172                                   crtc);
 173                         return 0;
 174                 }
 175
 176                 return dc_stream_get_vblank_counter(acrtc_state->stream);
 177         }
 178 }
 179
 180 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 181                                   u32 *vbl, u32 *position)
 182 {
 183         uint32_t v_blank_start, v_blank_end, h_position, v_position;
 184
 185         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 186                 return -EINVAL;
 187         else {
 188                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 189                 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
 190                                                 acrtc->base.state);
 191
 192                 if (acrtc_state->stream ==  NULL) {
 193                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 194                                   crtc);
 195                         return 0;
 196                 }
 197
 198                 /*
 199                  * TODO rework base driver to use values directly.
 200                  * for now parse it back into reg-format
 201                  */
 202                 dc_stream_get_scanoutpos(acrtc_state->stream,
 203                                          &v_blank_start,
 204                                          &v_blank_end,
 205                                          &h_position,
 206                                          &v_position);
 207
 208                 *position = v_position | (h_position << 16);
 209                 *vbl = v_blank_start | (v_blank_end << 16);
 210         }
 211
 212         return 0;
 213 }
 214
 215 static bool dm_is_idle(void *handle)
 216 {
 217         /* XXX todo */
 218         return true;
 219 }
 220
 221 static int dm_wait_for_idle(void *handle)
 222 {
 223         /* XXX todo */
 224         return 0;
 225 }
 226
 227 static bool dm_check_soft_reset(void *handle)
 228 {
 229         return false;
 230 }
 231
 232 static int dm_soft_reset(void *handle)
 233 {
 234         /* XXX todo */
 235         return 0;
 236 }
 237
 238 static struct amdgpu_crtc *
 239 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 240                      int otg_inst)
 241 {
 242         struct drm_device *dev = adev->ddev;
 243         struct drm_crtc *crtc;
 244         struct amdgpu_crtc *amdgpu_crtc;
 245
 246         if (otg_inst == -1) {
 247                 WARN_ON(1);
 248                 return adev->mode_info.crtcs[0];
 249         }
 250
 251         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 252                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 253
 254                 if (amdgpu_crtc->otg_inst == otg_inst)
 255                         return amdgpu_crtc;
 256         }
 257
 258         return NULL;
 259 }
 260
 261 static void dm_pflip_high_irq(void *interrupt_params)
 262 {
 263         struct amdgpu_crtc *amdgpu_crtc;
 264         struct common_irq_params *irq_params = interrupt_params;
 265         struct amdgpu_device *adev = irq_params->adev;
 266         unsigned long flags;
 267
 268         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 269
 270         /* IRQ could occur when in initial stage */
 271         /* TODO work and BO cleanup */
 272         if (amdgpu_crtc == NULL) {
 273                 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
 274                 return;
 275         }
 276
 277         spin_lock_irqsave(&adev->ddev->event_lock, flags);
 278
 279         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
 280                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
 281                                                  amdgpu_crtc->pflip_status,
 282                                                  AMDGPU_FLIP_SUBMITTED,
 283                                                  amdgpu_crtc->crtc_id,
 284                                                  amdgpu_crtc);
 285                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 286                 return;
 287         }
 288
 289
 290         /* wake up userspace */
 291         if (amdgpu_crtc->event) {
 292                 /* Update to correct count(s) if racing with vblank irq */
 293                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 294
 295                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
 296
 297                 /* page flip completed. clean up */
 298                 amdgpu_crtc->event = NULL;
 299
 300         } else
 301                 WARN_ON(1);
 302
 303         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 304         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 305
 306         DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
 307                                         __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
 308
 309         drm_crtc_vblank_put(&amdgpu_crtc->base);
 310 }
 311
 312 static void dm_crtc_high_irq(void *interrupt_params)
 313 {
 314         struct common_irq_params *irq_params = interrupt_params;
 315         struct amdgpu_device *adev = irq_params->adev;
 316         struct amdgpu_crtc *acrtc;
 317
 318         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 319
 320         if (acrtc) {
 321                 drm_crtc_handle_vblank(&acrtc->base);
 322                 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 323         }
 324 }
 325
 326 static int dm_set_clockgating_state(void *handle,
 327                   enum amd_clockgating_state state)
 328 {
 329         return 0;
 330 }
 331
 332 static int dm_set_powergating_state(void *handle,
 333                   enum amd_powergating_state state)
 334 {
 335         return 0;
 336 }
 337
 338 /* Prototypes of private functions */
 339 static int dm_early_init(void* handle);
 340
 341 /* Allocate memory for FBC compressed data  */
 342 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 343 {
 344         struct drm_device *dev = connector->dev;
 345         struct amdgpu_device *adev = dev->dev_private;
 346         struct dm_comressor_info *compressor = &adev->dm.compressor;
 347         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 348         struct drm_display_mode *mode;
 349         unsigned long max_size = 0;
 350
 351         if (adev->dm.dc->fbc_compressor == NULL)
 352                 return;
 353
 354         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 355                 return;
 356
 357         if (compressor->bo_ptr)
 358                 return;
 359
 360
 361         list_for_each_entry(mode, &connector->modes, head) {
 362                 if (max_size < mode->htotal * mode->vtotal)
 363                         max_size = mode->htotal * mode->vtotal;
 364         }
 365
 366         if (max_size) {
 367                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 368                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 369                             &compressor->gpu_addr, &compressor->cpu_addr);
 370
 371                 if (r)
 372                         DRM_ERROR("DM: Failed to initialize FBC\n");
 373                 else {
 374                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 375                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 376                 }
 377
 378         }
 379
 380 }
 381
 382 /*
 383  * Init display KMS
 384  *
 385  * Returns 0 on success
 386  */
 387 static int amdgpu_dm_init(struct amdgpu_device *adev)
 388 {
 389         struct dc_init_data init_data;
 390         adev->dm.ddev = adev->ddev;
 391         adev->dm.adev = adev;
 392
 393         /* Zero all the fields */
 394         memset(&init_data, 0, sizeof(init_data));
 395
 396         if(amdgpu_dm_irq_init(adev)) {
 397                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
 398                 goto error;
 399         }
 400
 401         init_data.asic_id.chip_family = adev->family;
 402
 403         init_data.asic_id.pci_revision_id = adev->rev_id;
 404         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
 405
 406         init_data.asic_id.vram_width = adev->gmc.vram_width;
 407         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
 408         init_data.asic_id.atombios_base_address =
 409                 adev->mode_info.atom_context->bios;
 410
 411         init_data.driver = adev;
 412
 413         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
 414
 415         if (!adev->dm.cgs_device) {
 416                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
 417                 goto error;
 418         }
 419
 420         init_data.cgs_device = adev->dm.cgs_device;
 421
 422         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
 423
 424         /*
 425          * TODO debug why this doesn't work on Raven
 426          */
 427         if (adev->flags & AMD_IS_APU &&
 428             adev->asic_type >= CHIP_CARRIZO &&
 429             adev->asic_type < CHIP_RAVEN)
 430                 init_data.flags.gpu_vm_support = true;
 431
 432         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
 433                 init_data.flags.fbc_support = true;
 434
 435         /* Display Core create. */
 436         adev->dm.dc = dc_create(&init_data);
 437
 438         if (adev->dm.dc) {
 439                 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
 440         } else {
 441                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
 442                 goto error;
 443         }
 444
 445         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
 446         if (!adev->dm.freesync_module) {
 447                 DRM_ERROR(
 448                 "amdgpu: failed to initialize freesync_module.\n");
 449         } else
 450                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
 451                                 adev->dm.freesync_module);
 452
 453         amdgpu_dm_init_color_mod();
 454
 455         if (amdgpu_dm_initialize_drm_device(adev)) {
 456                 DRM_ERROR(
 457                 "amdgpu: failed to initialize sw for display support.\n");
 458                 goto error;
 459         }
 460
 461         /* Update the actual used number of crtc */
 462         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
 463
 464         /* TODO: Add_display_info? */
 465
 466         /* TODO use dynamic cursor width */
 467         adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
 468         adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
 469
 470         if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
 471                 DRM_ERROR(
 472                 "amdgpu: failed to initialize sw for display support.\n");
 473                 goto error;
 474         }
 475
 476 #if defined(CONFIG_DEBUG_FS)
 477         if (dtn_debugfs_init(adev))
 478                 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
 479 #endif
 480
 481         DRM_DEBUG_DRIVER("KMS initialized.\n");
 482
 483         return 0;
 484 error:
 485         amdgpu_dm_fini(adev);
 486
 487         return -EINVAL;
 488 }
 489
 490 static void amdgpu_dm_fini(struct amdgpu_device *adev)
 491 {
 492         amdgpu_dm_destroy_drm_device(&adev->dm);
 493         /*
 494          * TODO: pageflip, vlank interrupt
 495          *
 496          * amdgpu_dm_irq_fini(adev);
 497          */
 498
 499         if (adev->dm.cgs_device) {
 500                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
 501                 adev->dm.cgs_device = NULL;
 502         }
 503         if (adev->dm.freesync_module) {
 504                 mod_freesync_destroy(adev->dm.freesync_module);
 505                 adev->dm.freesync_module = NULL;
 506         }
 507         /* DC Destroy TODO: Replace destroy DAL */
 508         if (adev->dm.dc)
 509                 dc_destroy(&adev->dm.dc);
 510         return;
 511 }
 512
 513 static int load_dmcu_fw(struct amdgpu_device *adev)
 514 {
 515         const char *fw_name_dmcu;
 516         int r;
 517         const struct dmcu_firmware_header_v1_0 *hdr;
 518
 519         switch(adev->asic_type) {
 520         case CHIP_BONAIRE:
 521         case CHIP_HAWAII:
 522         case CHIP_KAVERI:
 523         case CHIP_KABINI:
 524         case CHIP_MULLINS:
 525         case CHIP_TONGA:
 526         case CHIP_FIJI:
 527         case CHIP_CARRIZO:
 528         case CHIP_STONEY:
 529         case CHIP_POLARIS11:
 530         case CHIP_POLARIS10:
 531         case CHIP_POLARIS12:
 532         case CHIP_VEGAM:
 533         case CHIP_VEGA10:
 534         case CHIP_VEGA12:
 535         case CHIP_VEGA20:
 536                 return 0;
 537         case CHIP_RAVEN:
 538                 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
 539                 break;
 540         default:
 541                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
 542                 return -EINVAL;
 543         }
 544
 545         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 546                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
 547                 return 0;
 548         }
 549
 550         r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
 551         if (r == -ENOENT) {
 552                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
 553                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
 554                 adev->dm.fw_dmcu = NULL;
 555                 return 0;
 556         }
 557         if (r) {
 558                 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
 559                         fw_name_dmcu);
 560                 return r;
 561         }
 562
 563         r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
 564         if (r) {
 565                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
 566                         fw_name_dmcu);
 567                 release_firmware(adev->dm.fw_dmcu);
 568                 adev->dm.fw_dmcu = NULL;
 569                 return r;
 570         }
 571
 572         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
 573         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
 574         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
 575         adev->firmware.fw_size +=
 576                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
 577
 578         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
 579         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
 580         adev->firmware.fw_size +=
 581                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
 582
 583         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
 584
 585         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
 586
 587         return 0;
 588 }
 589
 590 static int dm_sw_init(void *handle)
 591 {
 592         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 593
 594         return load_dmcu_fw(adev);
 595 }
 596
 597 static int dm_sw_fini(void *handle)
 598 {
 599         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 600
 601         if(adev->dm.fw_dmcu) {
 602                 release_firmware(adev->dm.fw_dmcu);
 603                 adev->dm.fw_dmcu = NULL;
 604         }
 605
 606         return 0;
 607 }
 608
 609 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
 610 {
 611         struct amdgpu_dm_connector *aconnector;
 612         struct drm_connector *connector;
 613         int ret = 0;
 614
 615         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 616
 617         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 618                 aconnector = to_amdgpu_dm_connector(connector);
 619                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
 620                     aconnector->mst_mgr.aux) {
 621                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
 622                                         aconnector, aconnector->base.base.id);
 623
 624                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
 625                         if (ret < 0) {
 626                                 DRM_ERROR("DM_MST: Failed to start MST\n");
 627                                 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
 628                                 return ret;
 629                                 }
 630                         }
 631         }
 632
 633         drm_modeset_unlock(&dev->mode_config.connection_mutex);
 634         return ret;
 635 }
 636
 637 static int dm_late_init(void *handle)
 638 {
 639         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 640
 641         return detect_mst_link_for_all_connectors(adev->ddev);
 642 }
 643
 644 static void s3_handle_mst(struct drm_device *dev, bool suspend)
 645 {
 646         struct amdgpu_dm_connector *aconnector;
 647         struct drm_connector *connector;
 648
 649         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 650
 651         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 652                    aconnector = to_amdgpu_dm_connector(connector);
 653                    if (aconnector->dc_link->type == dc_connection_mst_branch &&
 654                                    !aconnector->mst_port) {
 655
 656                            if (suspend)
 657                                    drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
 658                            else
 659                                    drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
 660                    }
 661         }
 662
 663         drm_modeset_unlock(&dev->mode_config.connection_mutex);
 664 }
 665
 666 static int dm_hw_init(void *handle)
 667 {
 668         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 669         /* Create DAL display manager */
 670         amdgpu_dm_init(adev);
 671         amdgpu_dm_hpd_init(adev);
 672
 673         return 0;
 674 }
 675
 676 static int dm_hw_fini(void *handle)
 677 {
 678         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 679
 680         amdgpu_dm_hpd_fini(adev);
 681
 682         amdgpu_dm_irq_fini(adev);
 683         amdgpu_dm_fini(adev);
 684         return 0;
 685 }
 686
 687 static int dm_suspend(void *handle)
 688 {
 689         struct amdgpu_device *adev = handle;
 690         struct amdgpu_display_manager *dm = &adev->dm;
 691         int ret = 0;
 692
 693         s3_handle_mst(adev->ddev, true);
 694
 695         amdgpu_dm_irq_suspend(adev);
 696
 697         WARN_ON(adev->dm.cached_state);
 698         adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
 699
 700         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
 701
 702         return ret;
 703 }
 704
 705 static struct amdgpu_dm_connector *
 706 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
 707                                              struct drm_crtc *crtc)
 708 {
 709         uint32_t i;
 710         struct drm_connector_state *new_con_state;
 711         struct drm_connector *connector;
 712         struct drm_crtc *crtc_from_state;
 713
 714         for_each_new_connector_in_state(state, connector, new_con_state, i) {
 715                 crtc_from_state = new_con_state->crtc;
 716
 717                 if (crtc_from_state == crtc)
 718                         return to_amdgpu_dm_connector(connector);
 719         }
 720
 721         return NULL;
 722 }
 723
 724 static void emulated_link_detect(struct dc_link *link)
 725 {
 726         struct dc_sink_init_data sink_init_data = { 0 };
 727         struct display_sink_capability sink_caps = { 0 };
 728         enum dc_edid_status edid_status;
 729         struct dc_context *dc_ctx = link->ctx;
 730         struct dc_sink *sink = NULL;
 731         struct dc_sink *prev_sink = NULL;
 732
 733         link->type = dc_connection_none;
 734         prev_sink = link->local_sink;
 735
 736         if (prev_sink != NULL)
 737                 dc_sink_retain(prev_sink);
 738
 739         switch (link->connector_signal) {
 740         case SIGNAL_TYPE_HDMI_TYPE_A: {
 741                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 742                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 743                 break;
 744         }
 745
 746         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
 747                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 748                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 749                 break;
 750         }
 751
 752         case SIGNAL_TYPE_DVI_DUAL_LINK: {
 753                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 754                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 755                 break;
 756         }
 757
 758         case SIGNAL_TYPE_LVDS: {
 759                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 760                 sink_caps.signal = SIGNAL_TYPE_LVDS;
 761                 break;
 762         }
 763
 764         case SIGNAL_TYPE_EDP: {
 765                 sink_caps.transaction_type =
 766                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 767                 sink_caps.signal = SIGNAL_TYPE_EDP;
 768                 break;
 769         }
 770
 771         case SIGNAL_TYPE_DISPLAY_PORT: {
 772                 sink_caps.transaction_type =
 773                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 774                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
 775                 break;
 776         }
 777
 778         default:
 779                 DC_ERROR("Invalid connector type! signal:%d\n",
 780                         link->connector_signal);
 781                 return;
 782         }
 783
 784         sink_init_data.link = link;
 785         sink_init_data.sink_signal = sink_caps.signal;
 786
 787         sink = dc_sink_create(&sink_init_data);
 788         if (!sink) {
 789                 DC_ERROR("Failed to create sink!\n");
 790                 return;
 791         }
 792
 793         link->local_sink = sink;
 794
 795         edid_status = dm_helpers_read_local_edid(
 796                         link->ctx,
 797                         link,
 798                         sink);
 799
 800         if (edid_status != EDID_OK)
 801                 DC_ERROR("Failed to read EDID");
 802
 803 }
 804
 805 static int dm_resume(void *handle)
 806 {
 807         struct amdgpu_device *adev = handle;
 808         struct drm_device *ddev = adev->ddev;
 809         struct amdgpu_display_manager *dm = &adev->dm;
 810         struct amdgpu_dm_connector *aconnector;
 811         struct drm_connector *connector;
 812         struct drm_crtc *crtc;
 813         struct drm_crtc_state *new_crtc_state;
 814         struct dm_crtc_state *dm_new_crtc_state;
 815         struct drm_plane *plane;
 816         struct drm_plane_state *new_plane_state;
 817         struct dm_plane_state *dm_new_plane_state;
 818         enum dc_connection_type new_connection_type = dc_connection_none;
 819         int ret;
 820         int i;
 821
 822         /* power on hardware */
 823         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
 824
 825         /* program HPD filter */
 826         dc_resume(dm->dc);
 827
 828         /* On resume we need to  rewrite the MSTM control bits to enamble MST*/
 829         s3_handle_mst(ddev, false);
 830
 831         /*
 832          * early enable HPD Rx IRQ, should be done before set mode as short
 833          * pulse interrupts are used for MST
 834          */
 835         amdgpu_dm_irq_resume_early(adev);
 836
 837         /* Do detection*/
 838         list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
 839                 aconnector = to_amdgpu_dm_connector(connector);
 840
 841                 /*
 842                  * this is the case when traversing through already created
 843                  * MST connectors, should be skipped
 844                  */
 845                 if (aconnector->mst_port)
 846                         continue;
 847
 848                 mutex_lock(&aconnector->hpd_lock);
 849                 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
 850                         DRM_ERROR("KMS: Failed to detect connector\n");
 851
 852                 if (aconnector->base.force && new_connection_type == dc_connection_none)
 853                         emulated_link_detect(aconnector->dc_link);
 854                 else
 855                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
 856
 857                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
 858                         aconnector->fake_enable = false;
 859
 860                 aconnector->dc_sink = NULL;
 861                 amdgpu_dm_update_connector_after_detect(aconnector);
 862                 mutex_unlock(&aconnector->hpd_lock);
 863         }
 864
 865         /* Force mode set in atomic commit */
 866         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
 867                 new_crtc_state->active_changed = true;
 868
 869         /*
 870          * atomic_check is expected to create the dc states. We need to release
 871          * them here, since they were duplicated as part of the suspend
 872          * procedure.
 873          */
 874         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
 875                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
 876                 if (dm_new_crtc_state->stream) {
 877                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
 878                         dc_stream_release(dm_new_crtc_state->stream);
 879                         dm_new_crtc_state->stream = NULL;
 880                 }
 881         }
 882
 883         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
 884                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
 885                 if (dm_new_plane_state->dc_state) {
 886                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
 887                         dc_plane_state_release(dm_new_plane_state->dc_state);
 888                         dm_new_plane_state->dc_state = NULL;
 889                 }
 890         }
 891
 892         ret = drm_atomic_helper_resume(ddev, dm->cached_state);
 893
 894         dm->cached_state = NULL;
 895
 896         amdgpu_dm_irq_resume_late(adev);
 897
 898         return ret;
 899 }
 900
 901 static const struct amd_ip_funcs amdgpu_dm_funcs = {
 902         .name = "dm",
 903         .early_init = dm_early_init,
 904         .late_init = dm_late_init,
 905         .sw_init = dm_sw_init,
 906         .sw_fini = dm_sw_fini,
 907         .hw_init = dm_hw_init,
 908         .hw_fini = dm_hw_fini,
 909         .suspend = dm_suspend,
 910         .resume = dm_resume,
 911         .is_idle = dm_is_idle,
 912         .wait_for_idle = dm_wait_for_idle,
 913         .check_soft_reset = dm_check_soft_reset,
 914         .soft_reset = dm_soft_reset,
 915         .set_clockgating_state = dm_set_clockgating_state,
 916         .set_powergating_state = dm_set_powergating_state,
 917 };
 918
 919 const struct amdgpu_ip_block_version dm_ip_block =
 920 {
 921         .type = AMD_IP_BLOCK_TYPE_DCE,
 922         .major = 1,
 923         .minor = 0,
 924         .rev = 0,
 925         .funcs = &amdgpu_dm_funcs,
 926 };
 927
 928
 929 static struct drm_atomic_state *
 930 dm_atomic_state_alloc(struct drm_device *dev)
 931 {
 932         struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
 933
 934         if (!state)
 935                 return NULL;
 936
 937         if (drm_atomic_state_init(dev, &state->base) < 0)
 938                 goto fail;
 939
 940         return &state->base;
 941
 942 fail:
 943         kfree(state);
 944         return NULL;
 945 }
 946
 947 static void
 948 dm_atomic_state_clear(struct drm_atomic_state *state)
 949 {
 950         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
 951
 952         if (dm_state->context) {
 953                 dc_release_state(dm_state->context);
 954                 dm_state->context = NULL;
 955         }
 956
 957         drm_atomic_state_default_clear(state);
 958 }
 959
 960 static void
 961 dm_atomic_state_alloc_free(struct drm_atomic_state *state)
 962 {
 963         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
 964         drm_atomic_state_default_release(state);
 965         kfree(dm_state);
 966 }
 967
 968 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
 969         .fb_create = amdgpu_display_user_framebuffer_create,
 970         .output_poll_changed = drm_fb_helper_output_poll_changed,
 971         .atomic_check = amdgpu_dm_atomic_check,
 972         .atomic_commit = amdgpu_dm_atomic_commit,
 973         .atomic_state_alloc = dm_atomic_state_alloc,
 974         .atomic_state_clear = dm_atomic_state_clear,
 975         .atomic_state_free = dm_atomic_state_alloc_free
 976 };
 977
 978 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
 979         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
 980 };
 981
 982 static void
 983 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
 984 {
 985         struct drm_connector *connector = &aconnector->base;
 986         struct drm_device *dev = connector->dev;
 987         struct dc_sink *sink;
 988
 989         /* MST handled by drm_mst framework */
 990         if (aconnector->mst_mgr.mst_state == true)
 991                 return;
 992
 993
 994         sink = aconnector->dc_link->local_sink;
 995
 996         /*
 997          * Edid mgmt connector gets first update only in mode_valid hook and then
 998          * the connector sink is set to either fake or physical sink depends on link status.
 999          * Skip if already done during boot.
1000          */
1001         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
1002                         && aconnector->dc_em_sink) {
1003
1004                 /*
1005                  * For S3 resume with headless use eml_sink to fake stream
1006                  * because on resume connector->sink is set to NULL
1007                  */
1008                 mutex_lock(&dev->mode_config.mutex);
1009
1010                 if (sink) {
1011                         if (aconnector->dc_sink) {
1012                                 amdgpu_dm_update_freesync_caps(connector, NULL);
1013                                 /*
1014                                  * retain and release below are used to
1015                                  * bump up refcount for sink because the link doesn't point
1016                                  * to it anymore after disconnect, so on next crtc to connector
1017                                  * reshuffle by UMD we will get into unwanted dc_sink release
1018                                  */
1019                                 if (aconnector->dc_sink != aconnector->dc_em_sink)
1020                                         dc_sink_release(aconnector->dc_sink);
1021                         }
1022                         aconnector->dc_sink = sink;
1023                         amdgpu_dm_update_freesync_caps(connector,
1024                                         aconnector->edid);
1025                 } else {
1026                         amdgpu_dm_update_freesync_caps(connector, NULL);
1027                         if (!aconnector->dc_sink)
1028                                 aconnector->dc_sink = aconnector->dc_em_sink;
1029                         else if (aconnector->dc_sink != aconnector->dc_em_sink)
1030                                 dc_sink_retain(aconnector->dc_sink);
1031                 }
1032
1033                 mutex_unlock(&dev->mode_config.mutex);
1034                 return;
1035         }
1036
1037         /*
1038          * TODO: temporary guard to look for proper fix
1039          * if this sink is MST sink, we should not do anything
1040          */
1041         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
1042                 return;
1043
1044         if (aconnector->dc_sink == sink) {
1045                 /*
1046                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
1047                  * Do nothing!!
1048                  */
1049                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
1050                                 aconnector->connector_id);
1051                 return;
1052         }
1053
1054         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
1055                 aconnector->connector_id, aconnector->dc_sink, sink);
1056
1057         mutex_lock(&dev->mode_config.mutex);
1058
1059         /*
1060          * 1. Update status of the drm connector
1061          * 2. Send an event and let userspace tell us what to do
1062          */
1063         if (sink) {
1064                 /*
1065                  * TODO: check if we still need the S3 mode update workaround.
1066                  * If yes, put it here.
1067                  */
1068                 if (aconnector->dc_sink)
1069                         amdgpu_dm_update_freesync_caps(connector, NULL);
1070
1071                 aconnector->dc_sink = sink;
1072                 if (sink->dc_edid.length == 0) {
1073                         aconnector->edid = NULL;
1074                         drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
1075                 } else {
1076                         aconnector->edid =
1077                                 (struct edid *) sink->dc_edid.raw_edid;
1078
1079
1080                         drm_connector_update_edid_property(connector,
1081                                         aconnector->edid);
1082                         drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
1083                                             aconnector->edid);
1084                 }
1085                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
1086
1087         } else {
1088                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
1089                 amdgpu_dm_update_freesync_caps(connector, NULL);
1090                 drm_connector_update_edid_property(connector, NULL);
1091                 aconnector->num_modes = 0;
1092                 aconnector->dc_sink = NULL;
1093                 aconnector->edid = NULL;
1094         }
1095
1096         mutex_unlock(&dev->mode_config.mutex);
1097 }
1098
1099 static void handle_hpd_irq(void *param)
1100 {
1101         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1102         struct drm_connector *connector = &aconnector->base;
1103         struct drm_device *dev = connector->dev;
1104         enum dc_connection_type new_connection_type = dc_connection_none;
1105
1106         /*
1107          * In case of failure or MST no need to update connector status or notify the OS
1108          * since (for MST case) MST does this in its own context.
1109          */
1110         mutex_lock(&aconnector->hpd_lock);
1111
1112         if (aconnector->fake_enable)
1113                 aconnector->fake_enable = false;
1114
1115         if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1116                 DRM_ERROR("KMS: Failed to detect connector\n");
1117
1118         if (aconnector->base.force && new_connection_type == dc_connection_none) {
1119                 emulated_link_detect(aconnector->dc_link);
1120
1121
1122                 drm_modeset_lock_all(dev);
1123                 dm_restore_drm_connector_state(dev, connector);
1124                 drm_modeset_unlock_all(dev);
1125
1126                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1127                         drm_kms_helper_hotplug_event(dev);
1128
1129         } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
1130                 amdgpu_dm_update_connector_after_detect(aconnector);
1131
1132
1133                 drm_modeset_lock_all(dev);
1134                 dm_restore_drm_connector_state(dev, connector);
1135                 drm_modeset_unlock_all(dev);
1136
1137                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1138                         drm_kms_helper_hotplug_event(dev);
1139         }
1140         mutex_unlock(&aconnector->hpd_lock);
1141
1142 }
1143
1144 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
1145 {
1146         uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
1147         uint8_t dret;
1148         bool new_irq_handled = false;
1149         int dpcd_addr;
1150         int dpcd_bytes_to_read;
1151
1152         const int max_process_count = 30;
1153         int process_count = 0;
1154
1155         const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
1156
1157         if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
1158                 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
1159                 /* DPCD 0x200 - 0x201 for downstream IRQ */
1160                 dpcd_addr = DP_SINK_COUNT;
1161         } else {
1162                 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
1163                 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
1164                 dpcd_addr = DP_SINK_COUNT_ESI;
1165         }
1166
1167         dret = drm_dp_dpcd_read(
1168                 &aconnector->dm_dp_aux.aux,
1169                 dpcd_addr,
1170                 esi,
1171                 dpcd_bytes_to_read);
1172
1173         while (dret == dpcd_bytes_to_read &&
1174                 process_count < max_process_count) {
1175                 uint8_t retry;
1176                 dret = 0;
1177
1178                 process_count++;
1179
1180                 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
1181                 /* handle HPD short pulse irq */
1182                 if (aconnector->mst_mgr.mst_state)
1183                         drm_dp_mst_hpd_irq(
1184                                 &aconnector->mst_mgr,
1185                                 esi,
1186                                 &new_irq_handled);
1187
1188                 if (new_irq_handled) {
1189                         /* ACK at DPCD to notify down stream */
1190                         const int ack_dpcd_bytes_to_write =
1191                                 dpcd_bytes_to_read - 1;
1192
1193                         for (retry = 0; retry < 3; retry++) {
1194                                 uint8_t wret;
1195
1196                                 wret = drm_dp_dpcd_write(
1197                                         &aconnector->dm_dp_aux.aux,
1198                                         dpcd_addr + 1,
1199                                         &esi[1],
1200                                         ack_dpcd_bytes_to_write);
1201                                 if (wret == ack_dpcd_bytes_to_write)
1202                                         break;
1203                         }
1204
1205                         /* check if there is new irq to be handled */
1206                         dret = drm_dp_dpcd_read(
1207                                 &aconnector->dm_dp_aux.aux,
1208                                 dpcd_addr,
1209                                 esi,
1210                                 dpcd_bytes_to_read);
1211
1212                         new_irq_handled = false;
1213                 } else {
1214                         break;
1215                 }
1216         }
1217
1218         if (process_count == max_process_count)
1219                 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
1220 }
1221
1222 static void handle_hpd_rx_irq(void *param)
1223 {
1224         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1225         struct drm_connector *connector = &aconnector->base;
1226         struct drm_device *dev = connector->dev;
1227         struct dc_link *dc_link = aconnector->dc_link;
1228         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
1229         enum dc_connection_type new_connection_type = dc_connection_none;
1230
1231         /*
1232          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1233          * conflict, after implement i2c helper, this mutex should be
1234          * retired.
1235          */
1236         if (dc_link->type != dc_connection_mst_branch)
1237                 mutex_lock(&aconnector->hpd_lock);
1238
1239         if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
1240                         !is_mst_root_connector) {
1241                 /* Downstream Port status changed. */
1242                 if (!dc_link_detect_sink(dc_link, &new_connection_type))
1243                         DRM_ERROR("KMS: Failed to detect connector\n");
1244
1245                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1246                         emulated_link_detect(dc_link);
1247
1248                         if (aconnector->fake_enable)
1249                                 aconnector->fake_enable = false;
1250
1251                         amdgpu_dm_update_connector_after_detect(aconnector);
1252
1253
1254                         drm_modeset_lock_all(dev);
1255                         dm_restore_drm_connector_state(dev, connector);
1256                         drm_modeset_unlock_all(dev);
1257
1258                         drm_kms_helper_hotplug_event(dev);
1259                 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
1260
1261                         if (aconnector->fake_enable)
1262                                 aconnector->fake_enable = false;
1263
1264                         amdgpu_dm_update_connector_after_detect(aconnector);
1265
1266
1267                         drm_modeset_lock_all(dev);
1268                         dm_restore_drm_connector_state(dev, connector);
1269                         drm_modeset_unlock_all(dev);
1270
1271                         drm_kms_helper_hotplug_event(dev);
1272                 }
1273         }
1274         if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1275             (dc_link->type == dc_connection_mst_branch))
1276                 dm_handle_hpd_rx_irq(aconnector);
1277
1278         if (dc_link->type != dc_connection_mst_branch) {
1279                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
1280                 mutex_unlock(&aconnector->hpd_lock);
1281         }
1282 }
1283
1284 static void register_hpd_handlers(struct amdgpu_device *adev)
1285 {
1286         struct drm_device *dev = adev->ddev;
1287         struct drm_connector *connector;
1288         struct amdgpu_dm_connector *aconnector;
1289         const struct dc_link *dc_link;
1290         struct dc_interrupt_params int_params = {0};
1291
1292         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1293         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1294
1295         list_for_each_entry(connector,
1296                         &dev->mode_config.connector_list, head) {
1297
1298                 aconnector = to_amdgpu_dm_connector(connector);
1299                 dc_link = aconnector->dc_link;
1300
1301                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1302                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1303                         int_params.irq_source = dc_link->irq_source_hpd;
1304
1305                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
1306                                         handle_hpd_irq,
1307                                         (void *) aconnector);
1308                 }
1309
1310                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1311
1312                         /* Also register for DP short pulse (hpd_rx). */
1313                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1314                         int_params.irq_source = dc_link->irq_source_hpd_rx;
1315
1316                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
1317                                         handle_hpd_rx_irq,
1318                                         (void *) aconnector);
1319                 }
1320         }
1321 }
1322
1323 /* Register IRQ sources and initialize IRQ callbacks */
1324 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1325 {
1326         struct dc *dc = adev->dm.dc;
1327         struct common_irq_params *c_irq_params;
1328         struct dc_interrupt_params int_params = {0};
1329         int r;
1330         int i;
1331         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
1332
1333         if (adev->asic_type == CHIP_VEGA10 ||
1334             adev->asic_type == CHIP_VEGA12 ||
1335             adev->asic_type == CHIP_VEGA20 ||
1336             adev->asic_type == CHIP_RAVEN)
1337                 client_id = SOC15_IH_CLIENTID_DCE;
1338
1339         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1340         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1341
1342         /*
1343          * Actions of amdgpu_irq_add_id():
1344          * 1. Register a set() function with base driver.
1345          *    Base driver will call set() function to enable/disable an
1346          *    interrupt in DC hardware.
1347          * 2. Register amdgpu_dm_irq_handler().
1348          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1349          *    coming from DC hardware.
1350          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1351          *    for acknowledging and handling. */
1352
1353         /* Use VBLANK interrupt */
1354         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
1355                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
1356                 if (r) {
1357                         DRM_ERROR("Failed to add crtc irq id!\n");
1358                         return r;
1359                 }
1360
1361                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1362                 int_params.irq_source =
1363                         dc_interrupt_to_irq_source(dc, i, 0);
1364
1365                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1366
1367                 c_irq_params->adev = adev;
1368                 c_irq_params->irq_src = int_params.irq_source;
1369
1370                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1371                                 dm_crtc_high_irq, c_irq_params);
1372         }
1373
1374         /* Use GRPH_PFLIP interrupt */
1375         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1376                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
1377                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
1378                 if (r) {
1379                         DRM_ERROR("Failed to add page flip irq id!\n");
1380                         return r;
1381                 }
1382
1383                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1384                 int_params.irq_source =
1385                         dc_interrupt_to_irq_source(dc, i, 0);
1386
1387                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1388
1389                 c_irq_params->adev = adev;
1390                 c_irq_params->irq_src = int_params.irq_source;
1391
1392                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1393                                 dm_pflip_high_irq, c_irq_params);
1394
1395         }
1396
1397         /* HPD */
1398         r = amdgpu_irq_add_id(adev, client_id,
1399                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
1400         if (r) {
1401                 DRM_ERROR("Failed to add hpd irq id!\n");
1402                 return r;
1403         }
1404
1405         register_hpd_handlers(adev);
1406
1407         return 0;
1408 }
1409
1410 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1411 /* Register IRQ sources and initialize IRQ callbacks */
1412 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1413 {
1414         struct dc *dc = adev->dm.dc;
1415         struct common_irq_params *c_irq_params;
1416         struct dc_interrupt_params int_params = {0};
1417         int r;
1418         int i;
1419
1420         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1421         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1422
1423         /*
1424          * Actions of amdgpu_irq_add_id():
1425          * 1. Register a set() function with base driver.
1426          *    Base driver will call set() function to enable/disable an
1427          *    interrupt in DC hardware.
1428          * 2. Register amdgpu_dm_irq_handler().
1429          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1430          *    coming from DC hardware.
1431          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1432          *    for acknowledging and handling.
1433          */
1434
1435         /* Use VSTARTUP interrupt */
1436         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1437                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1438                         i++) {
1439                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1440
1441                 if (r) {
1442                         DRM_ERROR("Failed to add crtc irq id!\n");
1443                         return r;
1444                 }
1445
1446                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1447                 int_params.irq_source =
1448                         dc_interrupt_to_irq_source(dc, i, 0);
1449
1450                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1451
1452                 c_irq_params->adev = adev;
1453                 c_irq_params->irq_src = int_params.irq_source;
1454
1455                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1456                                 dm_crtc_high_irq, c_irq_params);
1457         }
1458
1459         /* Use GRPH_PFLIP interrupt */
1460         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1461                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1462                         i++) {
1463                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1464                 if (r) {
1465                         DRM_ERROR("Failed to add page flip irq id!\n");
1466                         return r;
1467                 }
1468
1469                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1470                 int_params.irq_source =
1471                         dc_interrupt_to_irq_source(dc, i, 0);
1472
1473                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1474
1475                 c_irq_params->adev = adev;
1476                 c_irq_params->irq_src = int_params.irq_source;
1477
1478                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1479                                 dm_pflip_high_irq, c_irq_params);
1480
1481         }
1482
1483         /* HPD */
1484         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1485                         &adev->hpd_irq);
1486         if (r) {
1487                 DRM_ERROR("Failed to add hpd irq id!\n");
1488                 return r;
1489         }
1490
1491         register_hpd_handlers(adev);
1492
1493         return 0;
1494 }
1495 #endif
1496
1497 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1498 {
1499         int r;
1500
1501         adev->mode_info.mode_config_initialized = true;
1502
1503         adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
1504         adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
1505
1506         adev->ddev->mode_config.max_width = 16384;
1507         adev->ddev->mode_config.max_height = 16384;
1508
1509         adev->ddev->mode_config.preferred_depth = 24;
1510         adev->ddev->mode_config.prefer_shadow = 1;
1511         /* indicates support for immediate flip */
1512         adev->ddev->mode_config.async_page_flip = true;
1513
1514         adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
1515
1516         r = amdgpu_display_modeset_create_props(adev);
1517         if (r)
1518                 return r;
1519
1520         return 0;
1521 }
1522
1523 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1524         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1525
1526 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1527 {
1528         struct amdgpu_display_manager *dm = bl_get_data(bd);
1529
1530         if (dc_link_set_backlight_level(dm->backlight_link,
1531                         bd->props.brightness, 0, 0))
1532                 return 0;
1533         else
1534                 return 1;
1535 }
1536
1537 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1538 {
1539         struct amdgpu_display_manager *dm = bl_get_data(bd);
1540         int ret = dc_link_get_backlight_level(dm->backlight_link);
1541
1542         if (ret == DC_ERROR_UNEXPECTED)
1543                 return bd->props.brightness;
1544         return ret;
1545 }
1546
1547 static const struct backlight_ops amdgpu_dm_backlight_ops = {
1548         .get_brightness = amdgpu_dm_backlight_get_brightness,
1549         .update_status  = amdgpu_dm_backlight_update_status,
1550 };
1551
1552 static void
1553 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
1554 {
1555         char bl_name[16];
1556         struct backlight_properties props = { 0 };
1557
1558         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
1559         props.brightness = AMDGPU_MAX_BL_LEVEL;
1560         props.type = BACKLIGHT_RAW;
1561
1562         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1563                         dm->adev->ddev->primary->index);
1564
1565         dm->backlight_dev = backlight_device_register(bl_name,
1566                         dm->adev->ddev->dev,
1567                         dm,
1568                         &amdgpu_dm_backlight_ops,
1569                         &props);
1570
1571         if (IS_ERR(dm->backlight_dev))
1572                 DRM_ERROR("DM: Backlight registration failed!\n");
1573         else
1574                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
1575 }
1576
1577 #endif
1578
1579 static int initialize_plane(struct amdgpu_display_manager *dm,
1580                              struct amdgpu_mode_info *mode_info,
1581                              int plane_id)
1582 {
1583         struct amdgpu_plane *plane;
1584         unsigned long possible_crtcs;
1585         int ret = 0;
1586
1587         plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL);
1588         mode_info->planes[plane_id] = plane;
1589
1590         if (!plane) {
1591                 DRM_ERROR("KMS: Failed to allocate plane\n");
1592                 return -ENOMEM;
1593         }
1594         plane->base.type = mode_info->plane_type[plane_id];
1595
1596         /*
1597          * HACK: IGT tests expect that each plane can only have
1598          * one possible CRTC. For now, set one CRTC for each
1599          * plane that is not an underlay, but still allow multiple
1600          * CRTCs for underlay planes.
1601          */
1602         possible_crtcs = 1 << plane_id;
1603         if (plane_id >= dm->dc->caps.max_streams)
1604                 possible_crtcs = 0xff;
1605
1606         ret = amdgpu_dm_plane_init(dm, mode_info->planes[plane_id], possible_crtcs);
1607
1608         if (ret) {
1609                 DRM_ERROR("KMS: Failed to initialize plane\n");
1610                 return ret;
1611         }
1612
1613         return ret;
1614 }
1615
1616
1617 static void register_backlight_device(struct amdgpu_display_manager *dm,
1618                                       struct dc_link *link)
1619 {
1620 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1621         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1622
1623         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
1624             link->type != dc_connection_none) {
1625                 /*
1626                  * Event if registration failed, we should continue with
1627                  * DM initialization because not having a backlight control
1628                  * is better then a black screen.
1629                  */
1630                 amdgpu_dm_register_backlight_device(dm);
1631
1632                 if (dm->backlight_dev)
1633                         dm->backlight_link = link;
1634         }
1635 #endif
1636 }
1637
1638
1639 /*
1640  * In this architecture, the association
1641  * connector -> encoder -> crtc
1642  * id not really requried. The crtc and connector will hold the
1643  * display_index as an abstraction to use with DAL component
1644  *
1645  * Returns 0 on success
1646  */
1647 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
1648 {
1649         struct amdgpu_display_manager *dm = &adev->dm;
1650         int32_t i;
1651         struct amdgpu_dm_connector *aconnector = NULL;
1652         struct amdgpu_encoder *aencoder = NULL;
1653         struct amdgpu_mode_info *mode_info = &adev->mode_info;
1654         uint32_t link_cnt;
1655         int32_t total_overlay_planes, total_primary_planes;
1656         enum dc_connection_type new_connection_type = dc_connection_none;
1657
1658         link_cnt = dm->dc->caps.max_links;
1659         if (amdgpu_dm_mode_config_init(dm->adev)) {
1660                 DRM_ERROR("DM: Failed to initialize mode config\n");
1661                 return -EINVAL;
1662         }
1663
1664         /* Identify the number of planes to be initialized */
1665         total_overlay_planes = dm->dc->caps.max_slave_planes;
1666         total_primary_planes = dm->dc->caps.max_planes - dm->dc->caps.max_slave_planes;
1667
1668         /* First initialize overlay planes, index starting after primary planes */
1669         for (i = (total_overlay_planes - 1); i >= 0; i--) {
1670                 if (initialize_plane(dm, mode_info, (total_primary_planes + i))) {
1671                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
1672                         goto fail;
1673                 }
1674         }
1675
1676         /* Initialize primary planes */
1677         for (i = (total_primary_planes - 1); i >= 0; i--) {
1678                 if (initialize_plane(dm, mode_info, i)) {
1679                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
1680                         goto fail;
1681                 }
1682         }
1683
1684         for (i = 0; i < dm->dc->caps.max_streams; i++)
1685                 if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
1686                         DRM_ERROR("KMS: Failed to initialize crtc\n");
1687                         goto fail;
1688                 }
1689
1690         dm->display_indexes_num = dm->dc->caps.max_streams;
1691
1692         /* loops over all connectors on the board */
1693         for (i = 0; i < link_cnt; i++) {
1694                 struct dc_link *link = NULL;
1695
1696                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1697                         DRM_ERROR(
1698                                 "KMS: Cannot support more than %d display indexes\n",
1699                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
1700                         continue;
1701                 }
1702
1703                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1704                 if (!aconnector)
1705                         goto fail;
1706
1707                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
1708                 if (!aencoder)
1709                         goto fail;
1710
1711                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1712                         DRM_ERROR("KMS: Failed to initialize encoder\n");
1713                         goto fail;
1714                 }
1715
1716                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1717                         DRM_ERROR("KMS: Failed to initialize connector\n");
1718                         goto fail;
1719                 }
1720
1721                 link = dc_get_link_at_index(dm->dc, i);
1722
1723                 if (!dc_link_detect_sink(link, &new_connection_type))
1724                         DRM_ERROR("KMS: Failed to detect connector\n");
1725
1726                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1727                         emulated_link_detect(link);
1728                         amdgpu_dm_update_connector_after_detect(aconnector);
1729
1730                 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
1731                         amdgpu_dm_update_connector_after_detect(aconnector);
1732                         register_backlight_device(dm, link);
1733                 }
1734
1735
1736         }
1737
1738         /* Software is initialized. Now we can register interrupt handlers. */
1739         switch (adev->asic_type) {
1740         case CHIP_BONAIRE:
1741         case CHIP_HAWAII:
1742         case CHIP_KAVERI:
1743         case CHIP_KABINI:
1744         case CHIP_MULLINS:
1745         case CHIP_TONGA:
1746         case CHIP_FIJI:
1747         case CHIP_CARRIZO:
1748         case CHIP_STONEY:
1749         case CHIP_POLARIS11:
1750         case CHIP_POLARIS10:
1751         case CHIP_POLARIS12:
1752         case CHIP_VEGAM:
1753         case CHIP_VEGA10:
1754         case CHIP_VEGA12:
1755         case CHIP_VEGA20:
1756                 if (dce110_register_irq_handlers(dm->adev)) {
1757                         DRM_ERROR("DM: Failed to initialize IRQ\n");
1758                         goto fail;
1759                 }
1760                 break;
1761 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1762         case CHIP_RAVEN:
1763                 if (dcn10_register_irq_handlers(dm->adev)) {
1764                         DRM_ERROR("DM: Failed to initialize IRQ\n");
1765                         goto fail;
1766                 }
1767                 break;
1768 #endif
1769         default:
1770                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
1771                 goto fail;
1772         }
1773
1774         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1775                 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1776
1777         return 0;
1778 fail:
1779         kfree(aencoder);
1780         kfree(aconnector);
1781         for (i = 0; i < dm->dc->caps.max_planes; i++)
1782                 kfree(mode_info->planes[i]);
1783         return -EINVAL;
1784 }
1785
1786 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
1787 {
1788         drm_mode_config_cleanup(dm->ddev);
1789         return;
1790 }
1791
1792 /******************************************************************************
1793  * amdgpu_display_funcs functions
1794  *****************************************************************************/
1795
1796 /*
1797  * dm_bandwidth_update - program display watermarks
1798  *
1799  * @adev: amdgpu_device pointer
1800  *
1801  * Calculate and program the display watermarks and line buffer allocation.
1802  */
1803 static void dm_bandwidth_update(struct amdgpu_device *adev)
1804 {
1805         /* TODO: implement later */
1806 }
1807
1808 static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
1809                                 struct drm_file *filp)
1810 {
1811         struct drm_atomic_state *state;
1812         struct drm_modeset_acquire_ctx ctx;
1813         struct drm_crtc *crtc;
1814         struct drm_connector *connector;
1815         struct drm_connector_state *old_con_state, *new_con_state;
1816         int ret = 0;
1817         uint8_t i;
1818         bool enable = false;
1819
1820         drm_modeset_acquire_init(&ctx, 0);
1821
1822         state = drm_atomic_state_alloc(dev);
1823         if (!state) {
1824                 ret = -ENOMEM;
1825                 goto out;
1826         }
1827         state->acquire_ctx = &ctx;
1828
1829 retry:
1830         drm_for_each_crtc(crtc, dev) {
1831                 ret = drm_atomic_add_affected_connectors(state, crtc);
1832                 if (ret)
1833                         goto fail;
1834
1835                 /* TODO rework amdgpu_dm_commit_planes so we don't need this */
1836                 ret = drm_atomic_add_affected_planes(state, crtc);
1837                 if (ret)
1838                         goto fail;
1839         }
1840
1841         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
1842                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
1843                 struct drm_crtc_state *new_crtc_state;
1844                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
1845                 struct dm_crtc_state *dm_new_crtc_state;
1846
1847                 if (!acrtc) {
1848                         ASSERT(0);
1849                         continue;
1850                 }
1851
1852                 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
1853                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1854
1855                 dm_new_crtc_state->freesync_enabled = enable;
1856         }
1857
1858         ret = drm_atomic_commit(state);
1859
1860 fail:
1861         if (ret == -EDEADLK) {
1862                 drm_atomic_state_clear(state);
1863                 drm_modeset_backoff(&ctx);
1864                 goto retry;
1865         }
1866
1867         drm_atomic_state_put(state);
1868
1869 out:
1870         drm_modeset_drop_locks(&ctx);
1871         drm_modeset_acquire_fini(&ctx);
1872         return ret;
1873 }
1874
1875 static const struct amdgpu_display_funcs dm_display_funcs = {
1876         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
1877         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
1878         .backlight_set_level = NULL, /* never called for DC */
1879         .backlight_get_level = NULL, /* never called for DC */
1880         .hpd_sense = NULL,/* called unconditionally */
1881         .hpd_set_polarity = NULL, /* called unconditionally */
1882         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
1883         .page_flip_get_scanoutpos =
1884                 dm_crtc_get_scanoutpos,/* called unconditionally */
1885         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
1886         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
1887         .notify_freesync = amdgpu_notify_freesync,
1888
1889 };
1890
1891 #if defined(CONFIG_DEBUG_KERNEL_DC)
1892
1893 static ssize_t s3_debug_store(struct device *device,
1894                               struct device_attribute *attr,
1895                               const char *buf,
1896                               size_t count)
1897 {
1898         int ret;
1899         int s3_state;
1900         struct pci_dev *pdev = to_pci_dev(device);
1901         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1902         struct amdgpu_device *adev = drm_dev->dev_private;
1903
1904         ret = kstrtoint(buf, 0, &s3_state);
1905
1906         if (ret == 0) {
1907                 if (s3_state) {
1908                         dm_resume(adev);
1909                         drm_kms_helper_hotplug_event(adev->ddev);
1910                 } else
1911                         dm_suspend(adev);
1912         }
1913
1914         return ret == 0 ? count : 0;
1915 }
1916
1917 DEVICE_ATTR_WO(s3_debug);
1918
1919 #endif
1920
1921 static int dm_early_init(void *handle)
1922 {
1923         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1924
1925         switch (adev->asic_type) {
1926         case CHIP_BONAIRE:
1927         case CHIP_HAWAII:
1928                 adev->mode_info.num_crtc = 6;
1929                 adev->mode_info.num_hpd = 6;
1930                 adev->mode_info.num_dig = 6;
1931                 adev->mode_info.plane_type = dm_plane_type_default;
1932                 break;
1933         case CHIP_KAVERI:
1934                 adev->mode_info.num_crtc = 4;
1935                 adev->mode_info.num_hpd = 6;
1936                 adev->mode_info.num_dig = 7;
1937                 adev->mode_info.plane_type = dm_plane_type_default;
1938                 break;
1939         case CHIP_KABINI:
1940         case CHIP_MULLINS:
1941                 adev->mode_info.num_crtc = 2;
1942                 adev->mode_info.num_hpd = 6;
1943                 adev->mode_info.num_dig = 6;
1944                 adev->mode_info.plane_type = dm_plane_type_default;
1945                 break;
1946         case CHIP_FIJI:
1947         case CHIP_TONGA:
1948                 adev->mode_info.num_crtc = 6;
1949                 adev->mode_info.num_hpd = 6;
1950                 adev->mode_info.num_dig = 7;
1951                 adev->mode_info.plane_type = dm_plane_type_default;
1952                 break;
1953         case CHIP_CARRIZO:
1954                 adev->mode_info.num_crtc = 3;
1955                 adev->mode_info.num_hpd = 6;
1956                 adev->mode_info.num_dig = 9;
1957                 adev->mode_info.plane_type = dm_plane_type_carizzo;
1958                 break;
1959         case CHIP_STONEY:
1960                 adev->mode_info.num_crtc = 2;
1961                 adev->mode_info.num_hpd = 6;
1962                 adev->mode_info.num_dig = 9;
1963                 adev->mode_info.plane_type = dm_plane_type_stoney;
1964                 break;
1965         case CHIP_POLARIS11:
1966         case CHIP_POLARIS12:
1967                 adev->mode_info.num_crtc = 5;
1968                 adev->mode_info.num_hpd = 5;
1969                 adev->mode_info.num_dig = 5;
1970                 adev->mode_info.plane_type = dm_plane_type_default;
1971                 break;
1972         case CHIP_POLARIS10:
1973         case CHIP_VEGAM:
1974                 adev->mode_info.num_crtc = 6;
1975                 adev->mode_info.num_hpd = 6;
1976                 adev->mode_info.num_dig = 6;
1977                 adev->mode_info.plane_type = dm_plane_type_default;
1978                 break;
1979         case CHIP_VEGA10:
1980         case CHIP_VEGA12:
1981         case CHIP_VEGA20:
1982                 adev->mode_info.num_crtc = 6;
1983                 adev->mode_info.num_hpd = 6;
1984                 adev->mode_info.num_dig = 6;
1985                 adev->mode_info.plane_type = dm_plane_type_default;
1986                 break;
1987 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1988         case CHIP_RAVEN:
1989                 adev->mode_info.num_crtc = 4;
1990                 adev->mode_info.num_hpd = 4;
1991                 adev->mode_info.num_dig = 4;
1992                 adev->mode_info.plane_type = dm_plane_type_default;
1993                 break;
1994 #endif
1995         default:
1996                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
1997                 return -EINVAL;
1998         }
1999
2000         amdgpu_dm_set_irq_funcs(adev);
2001
2002         if (adev->mode_info.funcs == NULL)
2003                 adev->mode_info.funcs = &dm_display_funcs;
2004
2005         /*
2006          * Note: Do NOT change adev->audio_endpt_rreg and
2007          * adev->audio_endpt_wreg because they are initialised in
2008          * amdgpu_device_init()
2009          */
2010 #if defined(CONFIG_DEBUG_KERNEL_DC)
2011         device_create_file(
2012                 adev->ddev->dev,
2013                 &dev_attr_s3_debug);
2014 #endif
2015
2016         return 0;
2017 }
2018
2019 static bool modeset_required(struct drm_crtc_state *crtc_state,
2020                              struct dc_stream_state *new_stream,
2021                              struct dc_stream_state *old_stream)
2022 {
2023         if (!drm_atomic_crtc_needs_modeset(crtc_state))
2024                 return false;
2025
2026         if (!crtc_state->enable)
2027                 return false;
2028
2029         return crtc_state->active;
2030 }
2031
2032 static bool modereset_required(struct drm_crtc_state *crtc_state)
2033 {
2034         if (!drm_atomic_crtc_needs_modeset(crtc_state))
2035                 return false;
2036
2037         return !crtc_state->enable || !crtc_state->active;
2038 }
2039
2040 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
2041 {
2042         drm_encoder_cleanup(encoder);
2043         kfree(encoder);
2044 }
2045
2046 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
2047         .destroy = amdgpu_dm_encoder_destroy,
2048 };
2049
2050 static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
2051                                         struct dc_plane_state *plane_state)
2052 {
2053         plane_state->src_rect.x = state->src_x >> 16;
2054         plane_state->src_rect.y = state->src_y >> 16;
2055         /* we ignore the mantissa for now and do not deal with floating pixels :( */
2056         plane_state->src_rect.width = state->src_w >> 16;
2057
2058         if (plane_state->src_rect.width == 0)
2059                 return false;
2060
2061         plane_state->src_rect.height = state->src_h >> 16;
2062         if (plane_state->src_rect.height == 0)
2063                 return false;
2064
2065         plane_state->dst_rect.x = state->crtc_x;
2066         plane_state->dst_rect.y = state->crtc_y;
2067
2068         if (state->crtc_w == 0)
2069                 return false;
2070
2071         plane_state->dst_rect.width = state->crtc_w;
2072
2073         if (state->crtc_h == 0)
2074                 return false;
2075
2076         plane_state->dst_rect.height = state->crtc_h;
2077
2078         plane_state->clip_rect = plane_state->dst_rect;
2079
2080         switch (state->rotation & DRM_MODE_ROTATE_MASK) {
2081         case DRM_MODE_ROTATE_0:
2082                 plane_state->rotation = ROTATION_ANGLE_0;
2083                 break;
2084         case DRM_MODE_ROTATE_90:
2085                 plane_state->rotation = ROTATION_ANGLE_90;
2086                 break;
2087         case DRM_MODE_ROTATE_180:
2088                 plane_state->rotation = ROTATION_ANGLE_180;
2089                 break;
2090         case DRM_MODE_ROTATE_270:
2091                 plane_state->rotation = ROTATION_ANGLE_270;
2092                 break;
2093         default:
2094                 plane_state->rotation = ROTATION_ANGLE_0;
2095                 break;
2096         }
2097
2098         return true;
2099 }
2100 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
2101                        uint64_t *tiling_flags)
2102 {
2103         struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
2104         int r = amdgpu_bo_reserve(rbo, false);
2105
2106         if (unlikely(r)) {
2107                 /* Don't show error message when returning -ERESTARTSYS */
2108                 if (r != -ERESTARTSYS)
2109                         DRM_ERROR("Unable to reserve buffer: %d\n", r);
2110                 return r;
2111         }
2112
2113         if (tiling_flags)
2114                 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
2115
2116         amdgpu_bo_unreserve(rbo);
2117
2118         return r;
2119 }
2120
2121 static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
2122                                          struct dc_plane_state *plane_state,
2123                                          const struct amdgpu_framebuffer *amdgpu_fb)
2124 {
2125         uint64_t tiling_flags;
2126         unsigned int awidth;
2127         const struct drm_framebuffer *fb = &amdgpu_fb->base;
2128         int ret = 0;
2129         struct drm_format_name_buf format_name;
2130
2131         ret = get_fb_info(
2132                 amdgpu_fb,
2133                 &tiling_flags);
2134
2135         if (ret)
2136                 return ret;
2137
2138         switch (fb->format->format) {
2139         case DRM_FORMAT_C8:
2140                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
2141                 break;
2142         case DRM_FORMAT_RGB565:
2143                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
2144                 break;
2145         case DRM_FORMAT_XRGB8888:
2146         case DRM_FORMAT_ARGB8888:
2147                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
2148                 break;
2149         case DRM_FORMAT_XRGB2101010:
2150         case DRM_FORMAT_ARGB2101010:
2151                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
2152                 break;
2153         case DRM_FORMAT_XBGR2101010:
2154         case DRM_FORMAT_ABGR2101010:
2155                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
2156                 break;
2157         case DRM_FORMAT_XBGR8888:
2158         case DRM_FORMAT_ABGR8888:
2159                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
2160                 break;
2161         case DRM_FORMAT_NV21:
2162                 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
2163                 break;
2164         case DRM_FORMAT_NV12:
2165                 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
2166                 break;
2167         default:
2168                 DRM_ERROR("Unsupported screen format %s\n",
2169                           drm_get_format_name(fb->format->format, &format_name));
2170                 return -EINVAL;
2171         }
2172
2173         if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2174                 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
2175                 plane_state->plane_size.grph.surface_size.x = 0;
2176                 plane_state->plane_size.grph.surface_size.y = 0;
2177                 plane_state->plane_size.grph.surface_size.width = fb->width;
2178                 plane_state->plane_size.grph.surface_size.height = fb->height;
2179                 plane_state->plane_size.grph.surface_pitch =
2180                                 fb->pitches[0] / fb->format->cpp[0];
2181                 /* TODO: unhardcode */
2182                 plane_state->color_space = COLOR_SPACE_SRGB;
2183
2184         } else {
2185                 awidth = ALIGN(fb->width, 64);
2186                 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
2187                 plane_state->plane_size.video.luma_size.x = 0;
2188                 plane_state->plane_size.video.luma_size.y = 0;
2189                 plane_state->plane_size.video.luma_size.width = awidth;
2190                 plane_state->plane_size.video.luma_size.height = fb->height;
2191                 /* TODO: unhardcode */
2192                 plane_state->plane_size.video.luma_pitch = awidth;
2193
2194                 plane_state->plane_size.video.chroma_size.x = 0;
2195                 plane_state->plane_size.video.chroma_size.y = 0;
2196                 plane_state->plane_size.video.chroma_size.width = awidth;
2197                 plane_state->plane_size.video.chroma_size.height = fb->height;
2198                 plane_state->plane_size.video.chroma_pitch = awidth / 2;
2199
2200                 /* TODO: unhardcode */
2201                 plane_state->color_space = COLOR_SPACE_YCBCR709;
2202         }
2203
2204         memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
2205
2206         /* Fill GFX8 params */
2207         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
2208                 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
2209
2210                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2211                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2212                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2213                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2214                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2215
2216                 /* XXX fix me for VI */
2217                 plane_state->tiling_info.gfx8.num_banks = num_banks;
2218                 plane_state->tiling_info.gfx8.array_mode =
2219                                 DC_ARRAY_2D_TILED_THIN1;
2220                 plane_state->tiling_info.gfx8.tile_split = tile_split;
2221                 plane_state->tiling_info.gfx8.bank_width = bankw;
2222                 plane_state->tiling_info.gfx8.bank_height = bankh;
2223                 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
2224                 plane_state->tiling_info.gfx8.tile_mode =
2225                                 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
2226         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
2227                         == DC_ARRAY_1D_TILED_THIN1) {
2228                 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
2229         }
2230
2231         plane_state->tiling_info.gfx8.pipe_config =
2232                         AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2233
2234         if (adev->asic_type == CHIP_VEGA10 ||
2235             adev->asic_type == CHIP_VEGA12 ||
2236             adev->asic_type == CHIP_VEGA20 ||
2237             adev->asic_type == CHIP_RAVEN) {
2238                 /* Fill GFX9 params */
2239                 plane_state->tiling_info.gfx9.num_pipes =
2240                         adev->gfx.config.gb_addr_config_fields.num_pipes;
2241                 plane_state->tiling_info.gfx9.num_banks =
2242                         adev->gfx.config.gb_addr_config_fields.num_banks;
2243                 plane_state->tiling_info.gfx9.pipe_interleave =
2244                         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
2245                 plane_state->tiling_info.gfx9.num_shader_engines =
2246                         adev->gfx.config.gb_addr_config_fields.num_se;
2247                 plane_state->tiling_info.gfx9.max_compressed_frags =
2248                         adev->gfx.config.gb_addr_config_fields.max_compress_frags;
2249                 plane_state->tiling_info.gfx9.num_rb_per_se =
2250                         adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
2251                 plane_state->tiling_info.gfx9.swizzle =
2252                         AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
2253                 plane_state->tiling_info.gfx9.shaderEnable = 1;
2254         }
2255
2256         plane_state->visible = true;
2257         plane_state->scaling_quality.h_taps_c = 0;
2258         plane_state->scaling_quality.v_taps_c = 0;
2259
2260         /* is this needed? is plane_state zeroed at allocation? */
2261         plane_state->scaling_quality.h_taps = 0;
2262         plane_state->scaling_quality.v_taps = 0;
2263         plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
2264
2265         return ret;
2266
2267 }
2268
2269 static int fill_plane_attributes(struct amdgpu_device *adev,
2270                                  struct dc_plane_state *dc_plane_state,
2271                                  struct drm_plane_state *plane_state,
2272                                  struct drm_crtc_state *crtc_state)
2273 {
2274         const struct amdgpu_framebuffer *amdgpu_fb =
2275                 to_amdgpu_framebuffer(plane_state->fb);
2276         const struct drm_crtc *crtc = plane_state->crtc;
2277         int ret = 0;
2278
2279         if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
2280                 return -EINVAL;
2281
2282         ret = fill_plane_attributes_from_fb(
2283                 crtc->dev->dev_private,
2284                 dc_plane_state,
2285                 amdgpu_fb);
2286
2287         if (ret)
2288                 return ret;
2289
2290         /*
2291          * Always set input transfer function, since plane state is refreshed
2292          * every time.
2293          */
2294         ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
2295         if (ret) {
2296                 dc_transfer_func_release(dc_plane_state->in_transfer_func);
2297                 dc_plane_state->in_transfer_func = NULL;
2298         }
2299
2300         return ret;
2301 }
2302
2303 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2304                                            const struct dm_connector_state *dm_state,
2305                                            struct dc_stream_state *stream)
2306 {
2307         enum amdgpu_rmx_type rmx_type;
2308
2309         struct rect src = { 0 }; /* viewport in composition space*/
2310         struct rect dst = { 0 }; /* stream addressable area */
2311
2312         /* no mode. nothing to be done */
2313         if (!mode)
2314                 return;
2315
2316         /* Full screen scaling by default */
2317         src.width = mode->hdisplay;
2318         src.height = mode->vdisplay;
2319         dst.width = stream->timing.h_addressable;
2320         dst.height = stream->timing.v_addressable;
2321
2322         if (dm_state) {
2323                 rmx_type = dm_state->scaling;
2324                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2325                         if (src.width * dst.height <
2326                                         src.height * dst.width) {
2327                                 /* height needs less upscaling/more downscaling */
2328                                 dst.width = src.width *
2329                                                 dst.height / src.height;
2330                         } else {
2331                                 /* width needs less upscaling/more downscaling */
2332                                 dst.height = src.height *
2333                                                 dst.width / src.width;
2334                         }
2335                 } else if (rmx_type == RMX_CENTER) {
2336                         dst = src;
2337                 }
2338
2339                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2340                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
2341
2342                 if (dm_state->underscan_enable) {
2343                         dst.x += dm_state->underscan_hborder / 2;
2344                         dst.y += dm_state->underscan_vborder / 2;
2345                         dst.width -= dm_state->underscan_hborder;
2346                         dst.height -= dm_state->underscan_vborder;
2347                 }
2348         }
2349
2350         stream->src = src;
2351         stream->dst = dst;
2352
2353         DRM_DEBUG_DRIVER("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
2354                         dst.x, dst.y, dst.width, dst.height);
2355
2356 }
2357
2358 static enum dc_color_depth
2359 convert_color_depth_from_display_info(const struct drm_connector *connector)
2360 {
2361         struct dm_connector_state *dm_conn_state =
2362                 to_dm_connector_state(connector->state);
2363         uint32_t bpc = connector->display_info.bpc;
2364
2365         /* TODO: Remove this when there's support for max_bpc in drm */
2366         if (dm_conn_state && bpc > dm_conn_state->max_bpc)
2367                 /* Round down to nearest even number. */
2368                 bpc = dm_conn_state->max_bpc - (dm_conn_state->max_bpc & 1);
2369
2370         switch (bpc) {
2371         case 0:
2372                 /*
2373                  * Temporary Work around, DRM doesn't parse color depth for
2374                  * EDID revision before 1.4
2375                  * TODO: Fix edid parsing
2376                  */
2377                 return COLOR_DEPTH_888;
2378         case 6:
2379                 return COLOR_DEPTH_666;
2380         case 8:
2381                 return COLOR_DEPTH_888;
2382         case 10:
2383                 return COLOR_DEPTH_101010;
2384         case 12:
2385                 return COLOR_DEPTH_121212;
2386         case 14:
2387                 return COLOR_DEPTH_141414;
2388         case 16:
2389                 return COLOR_DEPTH_161616;
2390         default:
2391                 return COLOR_DEPTH_UNDEFINED;
2392         }
2393 }
2394
2395 static enum dc_aspect_ratio
2396 get_aspect_ratio(const struct drm_display_mode *mode_in)
2397 {
2398         /* 1-1 mapping, since both enums follow the HDMI spec. */
2399         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
2400 }
2401
2402 static enum dc_color_space
2403 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
2404 {
2405         enum dc_color_space color_space = COLOR_SPACE_SRGB;
2406
2407         switch (dc_crtc_timing->pixel_encoding) {
2408         case PIXEL_ENCODING_YCBCR422:
2409         case PIXEL_ENCODING_YCBCR444:
2410         case PIXEL_ENCODING_YCBCR420:
2411         {
2412                 /*
2413                  * 27030khz is the separation point between HDTV and SDTV
2414                  * according to HDMI spec, we use YCbCr709 and YCbCr601
2415                  * respectively
2416                  */
2417                 if (dc_crtc_timing->pix_clk_khz > 27030) {
2418                         if (dc_crtc_timing->flags.Y_ONLY)
2419                                 color_space =
2420                                         COLOR_SPACE_YCBCR709_LIMITED;
2421                         else
2422                                 color_space = COLOR_SPACE_YCBCR709;
2423                 } else {
2424                         if (dc_crtc_timing->flags.Y_ONLY)
2425                                 color_space =
2426                                         COLOR_SPACE_YCBCR601_LIMITED;
2427                         else
2428                                 color_space = COLOR_SPACE_YCBCR601;
2429                 }
2430
2431         }
2432         break;
2433         case PIXEL_ENCODING_RGB:
2434                 color_space = COLOR_SPACE_SRGB;
2435                 break;
2436
2437         default:
2438                 WARN_ON(1);
2439                 break;
2440         }
2441
2442         return color_space;
2443 }
2444
2445 static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
2446 {
2447         if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2448                 return;
2449
2450         timing_out->display_color_depth--;
2451 }
2452
2453 static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,
2454                                                 const struct drm_display_info *info)
2455 {
2456         int normalized_clk;
2457         if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2458                 return;
2459         do {
2460                 normalized_clk = timing_out->pix_clk_khz;
2461                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
2462                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2463                         normalized_clk /= 2;
2464                 /* Adjusting pix clock following on HDMI spec based on colour depth */
2465                 switch (timing_out->display_color_depth) {
2466                 case COLOR_DEPTH_101010:
2467                         normalized_clk = (normalized_clk * 30) / 24;
2468                         break;
2469                 case COLOR_DEPTH_121212:
2470                         normalized_clk = (normalized_clk * 36) / 24;
2471                         break;
2472                 case COLOR_DEPTH_161616:
2473                         normalized_clk = (normalized_clk * 48) / 24;
2474                         break;
2475                 default:
2476                         return;
2477                 }
2478                 if (normalized_clk <= info->max_tmds_clock)
2479                         return;
2480                 reduce_mode_colour_depth(timing_out);
2481
2482         } while (timing_out->display_color_depth > COLOR_DEPTH_888);
2483
2484 }
2485
2486 static void
2487 fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2488                                              const struct drm_display_mode *mode_in,
2489                                              const struct drm_connector *connector)
2490 {
2491         struct dc_crtc_timing *timing_out = &stream->timing;
2492         const struct drm_display_info *info = &connector->display_info;
2493
2494         memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2495
2496         timing_out->h_border_left = 0;
2497         timing_out->h_border_right = 0;
2498         timing_out->v_border_top = 0;
2499         timing_out->v_border_bottom = 0;
2500         /* TODO: un-hardcode */
2501         if (drm_mode_is_420_only(info, mode_in)
2502                         && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2503                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
2504         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
2505                         && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2506                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2507         else
2508                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2509
2510         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2511         timing_out->display_color_depth = convert_color_depth_from_display_info(
2512                         connector);
2513         timing_out->scan_type = SCANNING_TYPE_NODATA;
2514         timing_out->hdmi_vic = 0;
2515         timing_out->vic = drm_match_cea_mode(mode_in);
2516
2517         timing_out->h_addressable = mode_in->crtc_hdisplay;
2518         timing_out->h_total = mode_in->crtc_htotal;
2519         timing_out->h_sync_width =
2520                 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2521         timing_out->h_front_porch =
2522                 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2523         timing_out->v_total = mode_in->crtc_vtotal;
2524         timing_out->v_addressable = mode_in->crtc_vdisplay;
2525         timing_out->v_front_porch =
2526                 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2527         timing_out->v_sync_width =
2528                 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2529         timing_out->pix_clk_khz = mode_in->crtc_clock;
2530         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
2531         if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2532                 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2533         if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2534                 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2535
2536         stream->output_color_space = get_output_color_space(timing_out);
2537
2538         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
2539         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
2540         if (stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2541                 adjust_colour_depth_from_display_info(timing_out, info);
2542 }
2543
2544 static void fill_audio_info(struct audio_info *audio_info,
2545                             const struct drm_connector *drm_connector,
2546                             const struct dc_sink *dc_sink)
2547 {
2548         int i = 0;
2549         int cea_revision = 0;
2550         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2551
2552         audio_info->manufacture_id = edid_caps->manufacturer_id;
2553         audio_info->product_id = edid_caps->product_id;
2554
2555         cea_revision = drm_connector->display_info.cea_rev;
2556
2557         strncpy(audio_info->display_name,
2558                 edid_caps->display_name,
2559                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1);
2560
2561         if (cea_revision >= 3) {
2562                 audio_info->mode_count = edid_caps->audio_mode_count;
2563
2564                 for (i = 0; i < audio_info->mode_count; ++i) {
2565                         audio_info->modes[i].format_code =
2566                                         (enum audio_format_code)
2567                                         (edid_caps->audio_modes[i].format_code);
2568                         audio_info->modes[i].channel_count =
2569                                         edid_caps->audio_modes[i].channel_count;
2570                         audio_info->modes[i].sample_rates.all =
2571                                         edid_caps->audio_modes[i].sample_rate;
2572                         audio_info->modes[i].sample_size =
2573                                         edid_caps->audio_modes[i].sample_size;
2574                 }
2575         }
2576
2577         audio_info->flags.all = edid_caps->speaker_flags;
2578
2579         /* TODO: We only check for the progressive mode, check for interlace mode too */
2580         if (drm_connector->latency_present[0]) {
2581                 audio_info->video_latency = drm_connector->video_latency[0];
2582                 audio_info->audio_latency = drm_connector->audio_latency[0];
2583         }
2584
2585         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2586
2587 }
2588
2589 static void
2590 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2591                                       struct drm_display_mode *dst_mode)
2592 {
2593         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2594         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2595         dst_mode->crtc_clock = src_mode->crtc_clock;
2596         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2597         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
2598         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
2599         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2600         dst_mode->crtc_htotal = src_mode->crtc_htotal;
2601         dst_mode->crtc_hskew = src_mode->crtc_hskew;
2602         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2603         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2604         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2605         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2606         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2607 }
2608
2609 static void
2610 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2611                                         const struct drm_display_mode *native_mode,
2612                                         bool scale_enabled)
2613 {
2614         if (scale_enabled) {
2615                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2616         } else if (native_mode->clock == drm_mode->clock &&
2617                         native_mode->htotal == drm_mode->htotal &&
2618                         native_mode->vtotal == drm_mode->vtotal) {
2619                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2620         } else {
2621                 /* no scaling nor amdgpu inserted, no need to patch */
2622         }
2623 }
2624
2625 static struct dc_sink *
2626 create_fake_sink(struct amdgpu_dm_connector *aconnector)
2627 {
2628         struct dc_sink_init_data sink_init_data = { 0 };
2629         struct dc_sink *sink = NULL;
2630         sink_init_data.link = aconnector->dc_link;
2631         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2632
2633         sink = dc_sink_create(&sink_init_data);
2634         if (!sink) {
2635                 DRM_ERROR("Failed to create sink!\n");
2636                 return NULL;
2637         }
2638         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
2639
2640         return sink;
2641 }
2642
2643 static void set_multisync_trigger_params(
2644                 struct dc_stream_state *stream)
2645 {
2646         if (stream->triggered_crtc_reset.enabled) {
2647                 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
2648                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
2649         }
2650 }
2651
2652 static void set_master_stream(struct dc_stream_state *stream_set[],
2653                               int stream_count)
2654 {
2655         int j, highest_rfr = 0, master_stream = 0;
2656
2657         for (j = 0;  j < stream_count; j++) {
2658                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
2659                         int refresh_rate = 0;
2660
2661                         refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/
2662                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
2663                         if (refresh_rate > highest_rfr) {
2664                                 highest_rfr = refresh_rate;
2665                                 master_stream = j;
2666                         }
2667                 }
2668         }
2669         for (j = 0;  j < stream_count; j++) {
2670                 if (stream_set[j])
2671                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
2672         }
2673 }
2674
2675 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
2676 {
2677         int i = 0;
2678
2679         if (context->stream_count < 2)
2680                 return;
2681         for (i = 0; i < context->stream_count ; i++) {
2682                 if (!context->streams[i])
2683                         continue;
2684                 /*
2685                  * TODO: add a function to read AMD VSDB bits and set
2686                  * crtc_sync_master.multi_sync_enabled flag
2687                  * For now it's set to false
2688                  */
2689                 set_multisync_trigger_params(context->streams[i]);
2690         }
2691         set_master_stream(context->streams, context->stream_count);
2692 }
2693
2694 static struct dc_stream_state *
2695 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2696                        const struct drm_display_mode *drm_mode,
2697                        const struct dm_connector_state *dm_state)
2698 {
2699         struct drm_display_mode *preferred_mode = NULL;
2700         struct drm_connector *drm_connector;
2701         struct dc_stream_state *stream = NULL;
2702         struct drm_display_mode mode = *drm_mode;
2703         bool native_mode_found = false;
2704         struct dc_sink *sink = NULL;
2705         if (aconnector == NULL) {
2706                 DRM_ERROR("aconnector is NULL!\n");
2707                 return stream;
2708         }
2709
2710         drm_connector = &aconnector->base;
2711
2712         if (!aconnector->dc_sink) {
2713                 if (!aconnector->mst_port) {
2714                         sink = create_fake_sink(aconnector);
2715                         if (!sink)
2716                                 return stream;
2717                 }
2718         } else {
2719                 sink = aconnector->dc_sink;
2720         }
2721
2722         stream = dc_create_stream_for_sink(sink);
2723
2724         if (stream == NULL) {
2725                 DRM_ERROR("Failed to create stream for sink!\n");
2726                 goto finish;
2727         }
2728
2729         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2730                 /* Search for preferred mode */
2731                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2732                         native_mode_found = true;
2733                         break;
2734                 }
2735         }
2736         if (!native_mode_found)
2737                 preferred_mode = list_first_entry_or_null(
2738                                 &aconnector->base.modes,
2739                                 struct drm_display_mode,
2740                                 head);
2741
2742         if (preferred_mode == NULL) {
2743                 /*
2744                  * This may not be an error, the use case is when we have no
2745                  * usermode calls to reset and set mode upon hotplug. In this
2746                  * case, we call set mode ourselves to restore the previous mode
2747                  * and the modelist may not be filled in in time.
2748                  */
2749                 DRM_DEBUG_DRIVER("No preferred mode found\n");
2750         } else {
2751                 decide_crtc_timing_for_drm_display_mode(
2752                                 &mode, preferred_mode,
2753                                 dm_state ? (dm_state->scaling != RMX_OFF) : false);
2754         }
2755
2756         if (!dm_state)
2757                 drm_mode_set_crtcinfo(&mode, 0);
2758
2759         fill_stream_properties_from_drm_display_mode(stream,
2760                         &mode, &aconnector->base);
2761         update_stream_scaling_settings(&mode, dm_state, stream);
2762
2763         fill_audio_info(
2764                 &stream->audio_info,
2765                 drm_connector,
2766                 sink);
2767
2768         update_stream_signal(stream);
2769
2770         if (dm_state && dm_state->freesync_capable)
2771                 stream->ignore_msa_timing_param = true;
2772 finish:
2773         if (sink && sink->sink_signal == SIGNAL_TYPE_VIRTUAL && aconnector->base.force != DRM_FORCE_ON)
2774                 dc_sink_release(sink);
2775
2776         return stream;
2777 }
2778
2779 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
2780 {
2781         drm_crtc_cleanup(crtc);
2782         kfree(crtc);
2783 }
2784
2785 static void dm_crtc_destroy_state(struct drm_crtc *crtc,
2786                                   struct drm_crtc_state *state)
2787 {
2788         struct dm_crtc_state *cur = to_dm_crtc_state(state);
2789
2790         /* TODO Destroy dc_stream objects are stream object is flattened */
2791         if (cur->stream)
2792                 dc_stream_release(cur->stream);
2793
2794
2795         __drm_atomic_helper_crtc_destroy_state(state);
2796
2797
2798         kfree(state);
2799 }
2800
2801 static void dm_crtc_reset_state(struct drm_crtc *crtc)
2802 {
2803         struct dm_crtc_state *state;
2804
2805         if (crtc->state)
2806                 dm_crtc_destroy_state(crtc, crtc->state);
2807
2808         state = kzalloc(sizeof(*state), GFP_KERNEL);
2809         if (WARN_ON(!state))
2810                 return;
2811
2812         crtc->state = &state->base;
2813         crtc->state->crtc = crtc;
2814
2815 }
2816
2817 static struct drm_crtc_state *
2818 dm_crtc_duplicate_state(struct drm_crtc *crtc)
2819 {
2820         struct dm_crtc_state *state, *cur;
2821
2822         cur = to_dm_crtc_state(crtc->state);
2823
2824         if (WARN_ON(!crtc->state))
2825                 return NULL;
2826
2827         state = kzalloc(sizeof(*state), GFP_KERNEL);
2828         if (!state)
2829                 return NULL;
2830
2831         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
2832
2833         if (cur->stream) {
2834                 state->stream = cur->stream;
2835                 dc_stream_retain(state->stream);
2836         }
2837
2838         state->adjust = cur->adjust;
2839         state->vrr_infopacket = cur->vrr_infopacket;
2840         state->freesync_enabled = cur->freesync_enabled;
2841
2842         /* TODO Duplicate dc_stream after objects are stream object is flattened */
2843
2844         return &state->base;
2845 }
2846
2847
2848 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
2849 {
2850         enum dc_irq_source irq_source;
2851         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2852         struct amdgpu_device *adev = crtc->dev->dev_private;
2853
2854         irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
2855         return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2856 }
2857
2858 static int dm_enable_vblank(struct drm_crtc *crtc)
2859 {
2860         return dm_set_vblank(crtc, true);
2861 }
2862
2863 static void dm_disable_vblank(struct drm_crtc *crtc)
2864 {
2865         dm_set_vblank(crtc, false);
2866 }
2867
2868 /* Implemented only the options currently availible for the driver */
2869 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
2870         .reset = dm_crtc_reset_state,
2871         .destroy = amdgpu_dm_crtc_destroy,
2872         .gamma_set = drm_atomic_helper_legacy_gamma_set,
2873         .set_config = drm_atomic_helper_set_config,
2874         .page_flip = drm_atomic_helper_page_flip,
2875         .atomic_duplicate_state = dm_crtc_duplicate_state,
2876         .atomic_destroy_state = dm_crtc_destroy_state,
2877         .set_crc_source = amdgpu_dm_crtc_set_crc_source,
2878         .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
2879         .enable_vblank = dm_enable_vblank,
2880         .disable_vblank = dm_disable_vblank,
2881 };
2882
2883 static enum drm_connector_status
2884 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
2885 {
2886         bool connected;
2887         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2888
2889         /*
2890          * Notes:
2891          * 1. This interface is NOT called in context of HPD irq.
2892          * 2. This interface *is called* in context of user-mode ioctl. Which
2893          * makes it a bad place for *any* MST-related activity.
2894          */
2895
2896         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
2897             !aconnector->fake_enable)
2898                 connected = (aconnector->dc_sink != NULL);
2899         else
2900                 connected = (aconnector->base.force == DRM_FORCE_ON);
2901
2902         return (connected ? connector_status_connected :
2903                         connector_status_disconnected);
2904 }
2905
2906 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
2907                                             struct drm_connector_state *connector_state,
2908                                             struct drm_property *property,
2909                                             uint64_t val)
2910 {
2911         struct drm_device *dev = connector->dev;
2912         struct amdgpu_device *adev = dev->dev_private;
2913         struct dm_connector_state *dm_old_state =
2914                 to_dm_connector_state(connector->state);
2915         struct dm_connector_state *dm_new_state =
2916                 to_dm_connector_state(connector_state);
2917
2918         int ret = -EINVAL;
2919
2920         if (property == dev->mode_config.scaling_mode_property) {
2921                 enum amdgpu_rmx_type rmx_type;
2922
2923                 switch (val) {
2924                 case DRM_MODE_SCALE_CENTER:
2925                         rmx_type = RMX_CENTER;
2926                         break;
2927                 case DRM_MODE_SCALE_ASPECT:
2928                         rmx_type = RMX_ASPECT;
2929                         break;
2930                 case DRM_MODE_SCALE_FULLSCREEN:
2931                         rmx_type = RMX_FULL;
2932                         break;
2933                 case DRM_MODE_SCALE_NONE:
2934                 default:
2935                         rmx_type = RMX_OFF;
2936                         break;
2937                 }
2938
2939                 if (dm_old_state->scaling == rmx_type)
2940                         return 0;
2941
2942                 dm_new_state->scaling = rmx_type;
2943                 ret = 0;
2944         } else if (property == adev->mode_info.underscan_hborder_property) {
2945                 dm_new_state->underscan_hborder = val;
2946                 ret = 0;
2947         } else if (property == adev->mode_info.underscan_vborder_property) {
2948                 dm_new_state->underscan_vborder = val;
2949                 ret = 0;
2950         } else if (property == adev->mode_info.underscan_property) {
2951                 dm_new_state->underscan_enable = val;
2952                 ret = 0;
2953         } else if (property == adev->mode_info.max_bpc_property) {
2954                 dm_new_state->max_bpc = val;
2955                 ret = 0;
2956         }
2957
2958         return ret;
2959 }
2960
2961 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
2962                                             const struct drm_connector_state *state,
2963                                             struct drm_property *property,
2964                                             uint64_t *val)
2965 {
2966         struct drm_device *dev = connector->dev;
2967         struct amdgpu_device *adev = dev->dev_private;
2968         struct dm_connector_state *dm_state =
2969                 to_dm_connector_state(state);
2970         int ret = -EINVAL;
2971
2972         if (property == dev->mode_config.scaling_mode_property) {
2973                 switch (dm_state->scaling) {
2974                 case RMX_CENTER:
2975                         *val = DRM_MODE_SCALE_CENTER;
2976                         break;
2977                 case RMX_ASPECT:
2978                         *val = DRM_MODE_SCALE_ASPECT;
2979                         break;
2980                 case RMX_FULL:
2981                         *val = DRM_MODE_SCALE_FULLSCREEN;
2982                         break;
2983                 case RMX_OFF:
2984                 default:
2985                         *val = DRM_MODE_SCALE_NONE;
2986                         break;
2987                 }
2988                 ret = 0;
2989         } else if (property == adev->mode_info.underscan_hborder_property) {
2990                 *val = dm_state->underscan_hborder;
2991                 ret = 0;
2992         } else if (property == adev->mode_info.underscan_vborder_property) {
2993                 *val = dm_state->underscan_vborder;
2994                 ret = 0;
2995         } else if (property == adev->mode_info.underscan_property) {
2996                 *val = dm_state->underscan_enable;
2997                 ret = 0;
2998         } else if (property == adev->mode_info.max_bpc_property) {
2999                 *val = dm_state->max_bpc;
3000                 ret = 0;
3001         }
3002         return ret;
3003 }
3004
3005 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
3006 {
3007         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3008         const struct dc_link *link = aconnector->dc_link;
3009         struct amdgpu_device *adev = connector->dev->dev_private;
3010         struct amdgpu_display_manager *dm = &adev->dm;
3011
3012 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3013         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3014
3015         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
3016             link->type != dc_connection_none &&
3017             dm->backlight_dev) {
3018                 backlight_device_unregister(dm->backlight_dev);
3019                 dm->backlight_dev = NULL;
3020         }
3021 #endif
3022         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
3023         drm_connector_unregister(connector);
3024         drm_connector_cleanup(connector);
3025         kfree(connector);
3026 }
3027
3028 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
3029 {
3030         struct dm_connector_state *state =
3031                 to_dm_connector_state(connector->state);
3032
3033         if (connector->state)
3034                 __drm_atomic_helper_connector_destroy_state(connector->state);
3035
3036         kfree(state);
3037
3038         state = kzalloc(sizeof(*state), GFP_KERNEL);
3039
3040         if (state) {
3041                 state->scaling = RMX_OFF;
3042                 state->underscan_enable = false;
3043                 state->underscan_hborder = 0;
3044                 state->underscan_vborder = 0;
3045
3046                 __drm_atomic_helper_connector_reset(connector, &state->base);
3047         }
3048 }
3049
3050 struct drm_connector_state *
3051 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
3052 {
3053         struct dm_connector_state *state =
3054                 to_dm_connector_state(connector->state);
3055
3056         struct dm_connector_state *new_state =
3057                         kmemdup(state, sizeof(*state), GFP_KERNEL);
3058
3059         if (!new_state)
3060                 return NULL;
3061
3062         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
3063
3064         new_state->freesync_capable = state->freesync_capable;
3065         new_state->freesync_enable = state->freesync_enable;
3066
3067         return &new_state->base;
3068 }
3069
3070 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
3071         .reset = amdgpu_dm_connector_funcs_reset,
3072         .detect = amdgpu_dm_connector_detect,
3073         .fill_modes = drm_helper_probe_single_connector_modes,
3074         .destroy = amdgpu_dm_connector_destroy,
3075         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
3076         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
3077         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
3078         .atomic_get_property = amdgpu_dm_connector_atomic_get_property
3079 };
3080
3081 static int get_modes(struct drm_connector *connector)
3082 {
3083         return amdgpu_dm_connector_get_modes(connector);
3084 }
3085
3086 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
3087 {
3088         struct dc_sink_init_data init_params = {
3089                         .link = aconnector->dc_link,
3090                         .sink_signal = SIGNAL_TYPE_VIRTUAL
3091         };
3092         struct edid *edid;
3093
3094         if (!aconnector->base.edid_blob_ptr) {
3095                 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
3096                                 aconnector->base.name);
3097
3098                 aconnector->base.force = DRM_FORCE_OFF;
3099                 aconnector->base.override_edid = false;
3100                 return;
3101         }
3102
3103         edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
3104
3105         aconnector->edid = edid;
3106
3107         aconnector->dc_em_sink = dc_link_add_remote_sink(
3108                 aconnector->dc_link,
3109                 (uint8_t *)edid,
3110                 (edid->extensions + 1) * EDID_LENGTH,
3111                 &init_params);
3112
3113         if (aconnector->base.force == DRM_FORCE_ON)
3114                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
3115                 aconnector->dc_link->local_sink :
3116                 aconnector->dc_em_sink;
3117 }
3118
3119 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
3120 {
3121         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
3122
3123         /*
3124          * In case of headless boot with force on for DP managed connector
3125          * Those settings have to be != 0 to get initial modeset
3126          */
3127         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
3128                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
3129                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
3130         }
3131
3132
3133         aconnector->base.override_edid = true;
3134         create_eml_sink(aconnector);
3135 }
3136
3137 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
3138                                    struct drm_display_mode *mode)
3139 {
3140         int result = MODE_ERROR;
3141         struct dc_sink *dc_sink;
3142         struct amdgpu_device *adev = connector->dev->dev_private;
3143         /* TODO: Unhardcode stream count */
3144         struct dc_stream_state *stream;
3145         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3146         enum dc_status dc_result = DC_OK;
3147
3148         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
3149                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
3150                 return result;
3151
3152         /*
3153          * Only run this the first time mode_valid is called to initilialize
3154          * EDID mgmt
3155          */
3156         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
3157                 !aconnector->dc_em_sink)
3158                 handle_edid_mgmt(aconnector);
3159
3160         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
3161
3162         if (dc_sink == NULL) {
3163                 DRM_ERROR("dc_sink is NULL!\n");
3164                 goto fail;
3165         }
3166
3167         stream = create_stream_for_sink(aconnector, mode, NULL);
3168         if (stream == NULL) {
3169                 DRM_ERROR("Failed to create stream for sink!\n");
3170                 goto fail;
3171         }
3172
3173         dc_result = dc_validate_stream(adev->dm.dc, stream);
3174
3175         if (dc_result == DC_OK)
3176                 result = MODE_OK;
3177         else
3178                 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
3179                               mode->vdisplay,
3180                               mode->hdisplay,
3181                               mode->clock,
3182                               dc_result);
3183
3184         dc_stream_release(stream);
3185
3186 fail:
3187         /* TODO: error handling*/
3188         return result;
3189 }
3190
3191 static const struct drm_connector_helper_funcs
3192 amdgpu_dm_connector_helper_funcs = {
3193         /*
3194          * If hotplugging a second bigger display in FB Con mode, bigger resolution
3195          * modes will be filtered by drm_mode_validate_size(), and those modes
3196          * are missing after user start lightdm. So we need to renew modes list.
3197          * in get_modes call back, not just return the modes count
3198          */
3199         .get_modes = get_modes,
3200         .mode_valid = amdgpu_dm_connector_mode_valid,
3201         .best_encoder = drm_atomic_helper_best_encoder
3202 };
3203
3204 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
3205 {
3206 }
3207
3208 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
3209                                        struct drm_crtc_state *state)
3210 {
3211         struct amdgpu_device *adev = crtc->dev->dev_private;
3212         struct dc *dc = adev->dm.dc;
3213         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
3214         int ret = -EINVAL;
3215
3216         if (unlikely(!dm_crtc_state->stream &&
3217                      modeset_required(state, NULL, dm_crtc_state->stream))) {
3218                 WARN_ON(1);
3219                 return ret;
3220         }
3221
3222         /* In some use cases, like reset, no stream is attached */
3223         if (!dm_crtc_state->stream)
3224                 return 0;
3225
3226         if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
3227                 return 0;
3228
3229         return ret;
3230 }
3231
3232 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
3233                                       const struct drm_display_mode *mode,
3234                                       struct drm_display_mode *adjusted_mode)
3235 {
3236         return true;
3237 }
3238
3239 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
3240         .disable = dm_crtc_helper_disable,
3241         .atomic_check = dm_crtc_helper_atomic_check,
3242         .mode_fixup = dm_crtc_helper_mode_fixup
3243 };
3244
3245 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
3246 {
3247
3248 }
3249
3250 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
3251                                           struct drm_crtc_state *crtc_state,
3252                                           struct drm_connector_state *conn_state)
3253 {
3254         return 0;
3255 }
3256
3257 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
3258         .disable = dm_encoder_helper_disable,
3259         .atomic_check = dm_encoder_helper_atomic_check
3260 };
3261
3262 static void dm_drm_plane_reset(struct drm_plane *plane)
3263 {
3264         struct dm_plane_state *amdgpu_state = NULL;
3265
3266         if (plane->state)
3267                 plane->funcs->atomic_destroy_state(plane, plane->state);
3268
3269         amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
3270         WARN_ON(amdgpu_state == NULL);
3271
3272         if (amdgpu_state) {
3273                 plane->state = &amdgpu_state->base;
3274                 plane->state->plane = plane;
3275                 plane->state->rotation = DRM_MODE_ROTATE_0;
3276         }
3277 }
3278
3279 static struct drm_plane_state *
3280 dm_drm_plane_duplicate_state(struct drm_plane *plane)
3281 {
3282         struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
3283
3284         old_dm_plane_state = to_dm_plane_state(plane->state);
3285         dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
3286         if (!dm_plane_state)
3287                 return NULL;
3288
3289         __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
3290
3291         if (old_dm_plane_state->dc_state) {
3292                 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
3293                 dc_plane_state_retain(dm_plane_state->dc_state);
3294         }
3295
3296         return &dm_plane_state->base;
3297 }
3298
3299 void dm_drm_plane_destroy_state(struct drm_plane *plane,
3300                                 struct drm_plane_state *state)
3301 {
3302         struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3303
3304         if (dm_plane_state->dc_state)
3305                 dc_plane_state_release(dm_plane_state->dc_state);
3306
3307         drm_atomic_helper_plane_destroy_state(plane, state);
3308 }
3309
3310 static const struct drm_plane_funcs dm_plane_funcs = {
3311         .update_plane   = drm_atomic_helper_update_plane,
3312         .disable_plane  = drm_atomic_helper_disable_plane,
3313         .destroy        = drm_primary_helper_destroy,
3314         .reset = dm_drm_plane_reset,
3315         .atomic_duplicate_state = dm_drm_plane_duplicate_state,
3316         .atomic_destroy_state = dm_drm_plane_destroy_state,
3317 };
3318
3319 static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
3320                                       struct drm_plane_state *new_state)
3321 {
3322         struct amdgpu_framebuffer *afb;
3323         struct drm_gem_object *obj;
3324         struct amdgpu_device *adev;
3325         struct amdgpu_bo *rbo;
3326         uint64_t chroma_addr = 0;
3327         struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
3328         unsigned int awidth;
3329         uint32_t domain;
3330         int r;
3331
3332         dm_plane_state_old = to_dm_plane_state(plane->state);
3333         dm_plane_state_new = to_dm_plane_state(new_state);
3334
3335         if (!new_state->fb) {
3336                 DRM_DEBUG_DRIVER("No FB bound\n");
3337                 return 0;
3338         }
3339
3340         afb = to_amdgpu_framebuffer(new_state->fb);
3341         obj = new_state->fb->obj[0];
3342         rbo = gem_to_amdgpu_bo(obj);
3343         adev = amdgpu_ttm_adev(rbo->tbo.bdev);
3344         r = amdgpu_bo_reserve(rbo, false);
3345         if (unlikely(r != 0))
3346                 return r;
3347
3348         if (plane->type != DRM_PLANE_TYPE_CURSOR)
3349                 domain = amdgpu_display_supported_domains(adev);
3350         else
3351                 domain = AMDGPU_GEM_DOMAIN_VRAM;
3352
3353         r = amdgpu_bo_pin(rbo, domain);
3354         if (unlikely(r != 0)) {
3355                 if (r != -ERESTARTSYS)
3356                         DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
3357                 amdgpu_bo_unreserve(rbo);
3358                 return r;
3359         }
3360
3361         r = amdgpu_ttm_alloc_gart(&rbo->tbo);
3362         if (unlikely(r != 0)) {
3363                 amdgpu_bo_unpin(rbo);
3364                 amdgpu_bo_unreserve(rbo);
3365                 DRM_ERROR("%p bind failed\n", rbo);
3366                 return r;
3367         }
3368         amdgpu_bo_unreserve(rbo);
3369
3370         afb->address = amdgpu_bo_gpu_offset(rbo);
3371
3372         amdgpu_bo_ref(rbo);
3373
3374         if (dm_plane_state_new->dc_state &&
3375                         dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
3376                 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
3377
3378                 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
3379                         plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
3380                         plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
3381                 } else {
3382                         awidth = ALIGN(new_state->fb->width, 64);
3383                         plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3384                         plane_state->address.video_progressive.luma_addr.low_part
3385                                                         = lower_32_bits(afb->address);
3386                         plane_state->address.video_progressive.luma_addr.high_part
3387                                                         = upper_32_bits(afb->address);
3388                         chroma_addr = afb->address + (u64)awidth * new_state->fb->height;
3389                         plane_state->address.video_progressive.chroma_addr.low_part
3390                                                         = lower_32_bits(chroma_addr);
3391                         plane_state->address.video_progressive.chroma_addr.high_part
3392                                                         = upper_32_bits(chroma_addr);
3393                 }
3394         }
3395
3396         return 0;
3397 }
3398
3399 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
3400                                        struct drm_plane_state *old_state)
3401 {
3402         struct amdgpu_bo *rbo;
3403         int r;
3404
3405         if (!old_state->fb)
3406                 return;
3407
3408         rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
3409         r = amdgpu_bo_reserve(rbo, false);
3410         if (unlikely(r)) {
3411                 DRM_ERROR("failed to reserve rbo before unpin\n");
3412                 return;
3413         }
3414
3415         amdgpu_bo_unpin(rbo);
3416         amdgpu_bo_unreserve(rbo);
3417         amdgpu_bo_unref(&rbo);
3418 }
3419
3420 static int dm_plane_atomic_check(struct drm_plane *plane,
3421                                  struct drm_plane_state *state)
3422 {
3423         struct amdgpu_device *adev = plane->dev->dev_private;
3424         struct dc *dc = adev->dm.dc;
3425         struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3426
3427         if (!dm_plane_state->dc_state)
3428                 return 0;
3429
3430         if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state))
3431                 return -EINVAL;
3432
3433         if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
3434                 return 0;
3435
3436         return -EINVAL;
3437 }
3438
3439 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3440         .prepare_fb = dm_plane_helper_prepare_fb,
3441         .cleanup_fb = dm_plane_helper_cleanup_fb,
3442         .atomic_check = dm_plane_atomic_check,
3443 };
3444
3445 /*
3446  * TODO: these are currently initialized to rgb formats only.
3447  * For future use cases we should either initialize them dynamically based on
3448  * plane capabilities, or initialize this array to all formats, so internal drm
3449  * check will succeed, and let DC implement proper check
3450  */
3451 static const uint32_t rgb_formats[] = {
3452         DRM_FORMAT_RGB888,
3453         DRM_FORMAT_XRGB8888,
3454         DRM_FORMAT_ARGB8888,
3455         DRM_FORMAT_RGBA8888,
3456         DRM_FORMAT_XRGB2101010,
3457         DRM_FORMAT_XBGR2101010,
3458         DRM_FORMAT_ARGB2101010,
3459         DRM_FORMAT_ABGR2101010,
3460         DRM_FORMAT_XBGR8888,
3461         DRM_FORMAT_ABGR8888,
3462 };
3463
3464 static const uint32_t yuv_formats[] = {
3465         DRM_FORMAT_NV12,
3466         DRM_FORMAT_NV21,
3467 };
3468
3469 static const u32 cursor_formats[] = {
3470         DRM_FORMAT_ARGB8888
3471 };
3472
3473 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
3474                                 struct amdgpu_plane *aplane,
3475                                 unsigned long possible_crtcs)
3476 {
3477         int res = -EPERM;
3478
3479         switch (aplane->base.type) {
3480         case DRM_PLANE_TYPE_PRIMARY:
3481                 res = drm_universal_plane_init(
3482                                 dm->adev->ddev,
3483                                 &aplane->base,
3484                                 possible_crtcs,
3485                                 &dm_plane_funcs,
3486                                 rgb_formats,
3487                                 ARRAY_SIZE(rgb_formats),
3488                                 NULL, aplane->base.type, NULL);
3489                 break;
3490         case DRM_PLANE_TYPE_OVERLAY:
3491                 res = drm_universal_plane_init(
3492                                 dm->adev->ddev,
3493                                 &aplane->base,
3494                                 possible_crtcs,
3495                                 &dm_plane_funcs,
3496                                 yuv_formats,
3497                                 ARRAY_SIZE(yuv_formats),
3498                                 NULL, aplane->base.type, NULL);
3499                 break;
3500         case DRM_PLANE_TYPE_CURSOR:
3501                 res = drm_universal_plane_init(
3502                                 dm->adev->ddev,
3503                                 &aplane->base,
3504                                 possible_crtcs,
3505                                 &dm_plane_funcs,
3506                                 cursor_formats,
3507                                 ARRAY_SIZE(cursor_formats),
3508                                 NULL, aplane->base.type, NULL);
3509                 break;
3510         }
3511
3512         drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
3513
3514         /* Create (reset) the plane state */
3515         if (aplane->base.funcs->reset)
3516                 aplane->base.funcs->reset(&aplane->base);
3517
3518
3519         return res;
3520 }
3521
3522 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3523                                struct drm_plane *plane,
3524                                uint32_t crtc_index)
3525 {
3526         struct amdgpu_crtc *acrtc = NULL;
3527         struct amdgpu_plane *cursor_plane;
3528
3529         int res = -ENOMEM;
3530
3531         cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3532         if (!cursor_plane)
3533                 goto fail;
3534
3535         cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
3536         res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3537
3538         acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3539         if (!acrtc)
3540                 goto fail;
3541
3542         res = drm_crtc_init_with_planes(
3543                         dm->ddev,
3544                         &acrtc->base,
3545                         plane,
3546                         &cursor_plane->base,
3547                         &amdgpu_dm_crtc_funcs, NULL);
3548
3549         if (res)
3550                 goto fail;
3551
3552         drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3553
3554         /* Create (reset) the plane state */
3555         if (acrtc->base.funcs->reset)
3556                 acrtc->base.funcs->reset(&acrtc->base);
3557
3558         acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3559         acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3560
3561         acrtc->crtc_id = crtc_index;
3562         acrtc->base.enabled = false;
3563         acrtc->otg_inst = -1;
3564
3565         dm->adev->mode_info.crtcs[crtc_index] = acrtc;
3566         drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
3567                                    true, MAX_COLOR_LUT_ENTRIES);
3568         drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
3569
3570         return 0;
3571
3572 fail:
3573         kfree(acrtc);
3574         kfree(cursor_plane);
3575         return res;
3576 }
3577
3578
3579 static int to_drm_connector_type(enum signal_type st)
3580 {
3581         switch (st) {
3582         case SIGNAL_TYPE_HDMI_TYPE_A:
3583                 return DRM_MODE_CONNECTOR_HDMIA;
3584         case SIGNAL_TYPE_EDP:
3585                 return DRM_MODE_CONNECTOR_eDP;
3586         case SIGNAL_TYPE_LVDS:
3587                 return DRM_MODE_CONNECTOR_LVDS;
3588         case SIGNAL_TYPE_RGB:
3589                 return DRM_MODE_CONNECTOR_VGA;
3590         case SIGNAL_TYPE_DISPLAY_PORT:
3591         case SIGNAL_TYPE_DISPLAY_PORT_MST:
3592                 return DRM_MODE_CONNECTOR_DisplayPort;
3593         case SIGNAL_TYPE_DVI_DUAL_LINK:
3594         case SIGNAL_TYPE_DVI_SINGLE_LINK:
3595                 return DRM_MODE_CONNECTOR_DVID;
3596         case SIGNAL_TYPE_VIRTUAL:
3597                 return DRM_MODE_CONNECTOR_VIRTUAL;
3598
3599         default:
3600                 return DRM_MODE_CONNECTOR_Unknown;
3601         }
3602 }
3603
3604 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3605 {
3606         const struct drm_connector_helper_funcs *helper =
3607                 connector->helper_private;
3608         struct drm_encoder *encoder;
3609         struct amdgpu_encoder *amdgpu_encoder;
3610
3611         encoder = helper->best_encoder(connector);
3612
3613         if (encoder == NULL)
3614                 return;
3615
3616         amdgpu_encoder = to_amdgpu_encoder(encoder);
3617
3618         amdgpu_encoder->native_mode.clock = 0;
3619
3620         if (!list_empty(&connector->probed_modes)) {
3621                 struct drm_display_mode *preferred_mode = NULL;
3622
3623                 list_for_each_entry(preferred_mode,
3624                                     &connector->probed_modes,
3625                                     head) {
3626                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3627                                 amdgpu_encoder->native_mode = *preferred_mode;
3628
3629                         break;
3630                 }
3631
3632         }
3633 }
3634
3635 static struct drm_display_mode *
3636 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
3637                              char *name,
3638                              int hdisplay, int vdisplay)
3639 {
3640         struct drm_device *dev = encoder->dev;
3641         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3642         struct drm_display_mode *mode = NULL;
3643         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3644
3645         mode = drm_mode_duplicate(dev, native_mode);
3646
3647         if (mode == NULL)
3648                 return NULL;
3649
3650         mode->hdisplay = hdisplay;
3651         mode->vdisplay = vdisplay;
3652         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3653         strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
3654
3655         return mode;
3656
3657 }
3658
3659 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3660                                                  struct drm_connector *connector)
3661 {
3662         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3663         struct drm_display_mode *mode = NULL;
3664         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3665         struct amdgpu_dm_connector *amdgpu_dm_connector =
3666                                 to_amdgpu_dm_connector(connector);
3667         int i;
3668         int n;
3669         struct mode_size {
3670                 char name[DRM_DISPLAY_MODE_LEN];
3671                 int w;
3672                 int h;
3673         } common_modes[] = {
3674                 {  "640x480",  640,  480},
3675                 {  "800x600",  800,  600},
3676                 { "1024x768", 1024,  768},
3677                 { "1280x720", 1280,  720},
3678                 { "1280x800", 1280,  800},
3679                 {"1280x1024", 1280, 1024},
3680                 { "1440x900", 1440,  900},
3681                 {"1680x1050", 1680, 1050},
3682                 {"1600x1200", 1600, 1200},
3683                 {"1920x1080", 1920, 1080},
3684                 {"1920x1200", 1920, 1200}
3685         };
3686
3687         n = ARRAY_SIZE(common_modes);
3688
3689         for (i = 0; i < n; i++) {
3690                 struct drm_display_mode *curmode = NULL;
3691                 bool mode_existed = false;
3692
3693                 if (common_modes[i].w > native_mode->hdisplay ||
3694                     common_modes[i].h > native_mode->vdisplay ||
3695                    (common_modes[i].w == native_mode->hdisplay &&
3696                     common_modes[i].h == native_mode->vdisplay))
3697                         continue;
3698
3699                 list_for_each_entry(curmode, &connector->probed_modes, head) {
3700                         if (common_modes[i].w == curmode->hdisplay &&
3701                             common_modes[i].h == curmode->vdisplay) {
3702                                 mode_existed = true;
3703                                 break;
3704                         }
3705                 }
3706
3707                 if (mode_existed)
3708                         continue;
3709
3710                 mode = amdgpu_dm_create_common_mode(encoder,
3711                                 common_modes[i].name, common_modes[i].w,
3712                                 common_modes[i].h);
3713                 drm_mode_probed_add(connector, mode);
3714                 amdgpu_dm_connector->num_modes++;
3715         }
3716 }
3717
3718 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
3719                                               struct edid *edid)
3720 {
3721         struct amdgpu_dm_connector *amdgpu_dm_connector =
3722                         to_amdgpu_dm_connector(connector);
3723
3724         if (edid) {
3725                 /* empty probed_modes */
3726                 INIT_LIST_HEAD(&connector->probed_modes);
3727                 amdgpu_dm_connector->num_modes =
3728                                 drm_add_edid_modes(connector, edid);
3729
3730                 amdgpu_dm_get_native_mode(connector);
3731         } else {
3732                 amdgpu_dm_connector->num_modes = 0;
3733         }
3734 }
3735
3736 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
3737 {
3738         const struct drm_connector_helper_funcs *helper =
3739                         connector->helper_private;
3740         struct amdgpu_dm_connector *amdgpu_dm_connector =
3741                         to_amdgpu_dm_connector(connector);
3742         struct drm_encoder *encoder;
3743         struct edid *edid = amdgpu_dm_connector->edid;
3744
3745         encoder = helper->best_encoder(connector);
3746
3747         if (!edid || !drm_edid_is_valid(edid)) {
3748                 amdgpu_dm_connector->num_modes =
3749                                 drm_add_modes_noedid(connector, 640, 480);
3750         } else {
3751                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
3752                 amdgpu_dm_connector_add_common_modes(encoder, connector);
3753         }
3754         amdgpu_dm_fbc_init(connector);
3755
3756         return amdgpu_dm_connector->num_modes;
3757 }
3758
3759 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
3760                                      struct amdgpu_dm_connector *aconnector,
3761                                      int connector_type,
3762                                      struct dc_link *link,
3763                                      int link_index)
3764 {
3765         struct amdgpu_device *adev = dm->ddev->dev_private;
3766
3767         aconnector->connector_id = link_index;
3768         aconnector->dc_link = link;
3769         aconnector->base.interlace_allowed = false;
3770         aconnector->base.doublescan_allowed = false;
3771         aconnector->base.stereo_allowed = false;
3772         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
3773         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
3774         mutex_init(&aconnector->hpd_lock);
3775
3776         /*
3777          * configure support HPD hot plug connector_>polled default value is 0
3778          * which means HPD hot plug not supported
3779          */
3780         switch (connector_type) {
3781         case DRM_MODE_CONNECTOR_HDMIA:
3782                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3783                 aconnector->base.ycbcr_420_allowed =
3784                         link->link_enc->features.ycbcr420_supported ? true : false;
3785                 break;
3786         case DRM_MODE_CONNECTOR_DisplayPort:
3787                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3788                 aconnector->base.ycbcr_420_allowed =
3789                         link->link_enc->features.ycbcr420_supported ? true : false;
3790                 break;
3791         case DRM_MODE_CONNECTOR_DVID:
3792                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3793                 break;
3794         default:
3795                 break;
3796         }
3797
3798         drm_object_attach_property(&aconnector->base.base,
3799                                 dm->ddev->mode_config.scaling_mode_property,
3800                                 DRM_MODE_SCALE_NONE);
3801
3802         drm_object_attach_property(&aconnector->base.base,
3803                                 adev->mode_info.underscan_property,
3804                                 UNDERSCAN_OFF);
3805         drm_object_attach_property(&aconnector->base.base,
3806                                 adev->mode_info.underscan_hborder_property,
3807                                 0);
3808         drm_object_attach_property(&aconnector->base.base,
3809                                 adev->mode_info.underscan_vborder_property,
3810                                 0);
3811         drm_object_attach_property(&aconnector->base.base,
3812                                 adev->mode_info.max_bpc_property,
3813                                 0);
3814
3815 }
3816
3817 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
3818                               struct i2c_msg *msgs, int num)
3819 {
3820         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
3821         struct ddc_service *ddc_service = i2c->ddc_service;
3822         struct i2c_command cmd;
3823         int i;
3824         int result = -EIO;
3825
3826         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
3827
3828         if (!cmd.payloads)
3829                 return result;
3830
3831         cmd.number_of_payloads = num;
3832         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
3833         cmd.speed = 100;
3834
3835         for (i = 0; i < num; i++) {
3836                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
3837                 cmd.payloads[i].address = msgs[i].addr;
3838                 cmd.payloads[i].length = msgs[i].len;
3839                 cmd.payloads[i].data = msgs[i].buf;
3840         }
3841
3842         if (dc_submit_i2c(
3843                         ddc_service->ctx->dc,
3844                         ddc_service->ddc_pin->hw_info.ddc_channel,
3845                         &cmd))
3846                 result = num;
3847
3848         kfree(cmd.payloads);
3849         return result;
3850 }
3851
3852 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
3853 {
3854         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3855 }
3856
3857 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
3858         .master_xfer = amdgpu_dm_i2c_xfer,
3859         .functionality = amdgpu_dm_i2c_func,
3860 };
3861
3862 static struct amdgpu_i2c_adapter *
3863 create_i2c(struct ddc_service *ddc_service,
3864            int link_index,
3865            int *res)
3866 {
3867         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
3868         struct amdgpu_i2c_adapter *i2c;
3869
3870         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
3871         if (!i2c)
3872                 return NULL;
3873         i2c->base.owner = THIS_MODULE;
3874         i2c->base.class = I2C_CLASS_DDC;
3875         i2c->base.dev.parent = &adev->pdev->dev;
3876         i2c->base.algo = &amdgpu_dm_i2c_algo;
3877         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
3878         i2c_set_adapdata(&i2c->base, i2c);
3879         i2c->ddc_service = ddc_service;
3880         i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
3881
3882         return i2c;
3883 }
3884
3885
3886 /*
3887  * Note: this function assumes that dc_link_detect() was called for the
3888  * dc_link which will be represented by this aconnector.
3889  */
3890 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
3891                                     struct amdgpu_dm_connector *aconnector,
3892                                     uint32_t link_index,
3893                                     struct amdgpu_encoder *aencoder)
3894 {
3895         int res = 0;
3896         int connector_type;
3897         struct dc *dc = dm->dc;
3898         struct dc_link *link = dc_get_link_at_index(dc, link_index);
3899         struct amdgpu_i2c_adapter *i2c;
3900
3901         link->priv = aconnector;
3902
3903         DRM_DEBUG_DRIVER("%s()\n", __func__);
3904
3905         i2c = create_i2c(link->ddc, link->link_index, &res);
3906         if (!i2c) {
3907                 DRM_ERROR("Failed to create i2c adapter data\n");
3908                 return -ENOMEM;
3909         }
3910
3911         aconnector->i2c = i2c;
3912         res = i2c_add_adapter(&i2c->base);
3913
3914         if (res) {
3915                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
3916                 goto out_free;
3917         }
3918
3919         connector_type = to_drm_connector_type(link->connector_signal);
3920
3921         res = drm_connector_init(
3922                         dm->ddev,
3923                         &aconnector->base,
3924                         &amdgpu_dm_connector_funcs,
3925                         connector_type);
3926
3927         if (res) {
3928                 DRM_ERROR("connector_init failed\n");
3929                 aconnector->connector_id = -1;
3930                 goto out_free;
3931         }
3932
3933         drm_connector_helper_add(
3934                         &aconnector->base,
3935                         &amdgpu_dm_connector_helper_funcs);
3936
3937         if (aconnector->base.funcs->reset)
3938                 aconnector->base.funcs->reset(&aconnector->base);
3939
3940         amdgpu_dm_connector_init_helper(
3941                 dm,
3942                 aconnector,
3943                 connector_type,
3944                 link,
3945                 link_index);
3946
3947         drm_connector_attach_encoder(
3948                 &aconnector->base, &aencoder->base);
3949
3950         drm_connector_register(&aconnector->base);
3951 #if defined(CONFIG_DEBUG_FS)
3952         res = connector_debugfs_init(aconnector);
3953         if (res) {
3954                 DRM_ERROR("Failed to create debugfs for connector");
3955                 goto out_free;
3956         }
3957 #endif
3958
3959         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
3960                 || connector_type == DRM_MODE_CONNECTOR_eDP)
3961                 amdgpu_dm_initialize_dp_connector(dm, aconnector);
3962
3963 out_free:
3964         if (res) {
3965                 kfree(i2c);
3966                 aconnector->i2c = NULL;
3967         }
3968         return res;
3969 }
3970
3971 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
3972 {
3973         switch (adev->mode_info.num_crtc) {
3974         case 1:
3975                 return 0x1;
3976         case 2:
3977                 return 0x3;
3978         case 3:
3979                 return 0x7;
3980         case 4:
3981                 return 0xf;
3982         case 5:
3983                 return 0x1f;
3984         case 6:
3985         default:
3986                 return 0x3f;
3987         }
3988 }
3989
3990 static int amdgpu_dm_encoder_init(struct drm_device *dev,
3991                                   struct amdgpu_encoder *aencoder,
3992                                   uint32_t link_index)
3993 {
3994         struct amdgpu_device *adev = dev->dev_private;
3995
3996         int res = drm_encoder_init(dev,
3997                                    &aencoder->base,
3998                                    &amdgpu_dm_encoder_funcs,
3999                                    DRM_MODE_ENCODER_TMDS,
4000                                    NULL);
4001
4002         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
4003
4004         if (!res)
4005                 aencoder->encoder_id = link_index;
4006         else
4007                 aencoder->encoder_id = -1;
4008
4009         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
4010
4011         return res;
4012 }
4013
4014 static void manage_dm_interrupts(struct amdgpu_device *adev,
4015                                  struct amdgpu_crtc *acrtc,
4016                                  bool enable)
4017 {
4018         /*
4019          * this is not correct translation but will work as soon as VBLANK
4020          * constant is the same as PFLIP
4021          */
4022         int irq_type =
4023                 amdgpu_display_crtc_idx_to_irq_type(
4024                         adev,
4025                         acrtc->crtc_id);
4026
4027         if (enable) {
4028                 drm_crtc_vblank_on(&acrtc->base);
4029                 amdgpu_irq_get(
4030                         adev,
4031                         &adev->pageflip_irq,
4032                         irq_type);
4033         } else {
4034
4035                 amdgpu_irq_put(
4036                         adev,
4037                         &adev->pageflip_irq,
4038                         irq_type);
4039                 drm_crtc_vblank_off(&acrtc->base);
4040         }
4041 }
4042
4043 static bool
4044 is_scaling_state_different(const struct dm_connector_state *dm_state,
4045                            const struct dm_connector_state *old_dm_state)
4046 {
4047         if (dm_state->scaling != old_dm_state->scaling)
4048                 return true;
4049         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
4050                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
4051                         return true;
4052         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
4053                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
4054                         return true;
4055         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
4056                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
4057                 return true;
4058         return false;
4059 }
4060
4061 static void remove_stream(struct amdgpu_device *adev,
4062                           struct amdgpu_crtc *acrtc,
4063                           struct dc_stream_state *stream)
4064 {
4065         /* this is the update mode case */
4066
4067         acrtc->otg_inst = -1;
4068         acrtc->enabled = false;
4069 }
4070
4071 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
4072                                struct dc_cursor_position *position)
4073 {
4074         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
4075         int x, y;
4076         int xorigin = 0, yorigin = 0;
4077
4078         if (!crtc || !plane->state->fb) {
4079                 position->enable = false;
4080                 position->x = 0;
4081                 position->y = 0;
4082                 return 0;
4083         }
4084
4085         if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
4086             (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
4087                 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
4088                           __func__,
4089                           plane->state->crtc_w,
4090                           plane->state->crtc_h);
4091                 return -EINVAL;
4092         }
4093
4094         x = plane->state->crtc_x;
4095         y = plane->state->crtc_y;
4096         /* avivo cursor are offset into the total surface */
4097         x += crtc->primary->state->src_x >> 16;
4098         y += crtc->primary->state->src_y >> 16;
4099         if (x < 0) {
4100                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
4101                 x = 0;
4102         }
4103         if (y < 0) {
4104                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
4105                 y = 0;
4106         }
4107         position->enable = true;
4108         position->x = x;
4109         position->y = y;
4110         position->x_hotspot = xorigin;
4111         position->y_hotspot = yorigin;
4112
4113         return 0;
4114 }
4115
4116 static void handle_cursor_update(struct drm_plane *plane,
4117                                  struct drm_plane_state *old_plane_state)
4118 {
4119         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
4120         struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
4121         struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
4122         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
4123         uint64_t address = afb ? afb->address : 0;
4124         struct dc_cursor_position position;
4125         struct dc_cursor_attributes attributes;
4126         int ret;
4127
4128         if (!plane->state->fb && !old_plane_state->fb)
4129                 return;
4130
4131         DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
4132                          __func__,
4133                          amdgpu_crtc->crtc_id,
4134                          plane->state->crtc_w,
4135                          plane->state->crtc_h);
4136
4137         ret = get_cursor_position(plane, crtc, &position);
4138         if (ret)
4139                 return;
4140
4141         if (!position.enable) {
4142                 /* turn off cursor */
4143                 if (crtc_state && crtc_state->stream)
4144                         dc_stream_set_cursor_position(crtc_state->stream,
4145                                                       &position);
4146                 return;
4147         }
4148
4149         amdgpu_crtc->cursor_width = plane->state->crtc_w;
4150         amdgpu_crtc->cursor_height = plane->state->crtc_h;
4151
4152         attributes.address.high_part = upper_32_bits(address);
4153         attributes.address.low_part  = lower_32_bits(address);
4154         attributes.width             = plane->state->crtc_w;
4155         attributes.height            = plane->state->crtc_h;
4156         attributes.color_format      = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
4157         attributes.rotation_angle    = 0;
4158         attributes.attribute_flags.value = 0;
4159
4160         attributes.pitch = attributes.width;
4161
4162         if (crtc_state->stream) {
4163                 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
4164                                                          &attributes))
4165                         DRM_ERROR("DC failed to set cursor attributes\n");
4166
4167                 if (!dc_stream_set_cursor_position(crtc_state->stream,
4168                                                    &position))
4169                         DRM_ERROR("DC failed to set cursor position\n");
4170         }
4171 }
4172
4173 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
4174 {
4175
4176         assert_spin_locked(&acrtc->base.dev->event_lock);
4177         WARN_ON(acrtc->event);
4178
4179         acrtc->event = acrtc->base.state->event;
4180
4181         /* Set the flip status */
4182         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
4183
4184         /* Mark this event as consumed */
4185         acrtc->base.state->event = NULL;
4186
4187         DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
4188                                                  acrtc->crtc_id);
4189 }
4190
4191 /*
4192  * Executes flip
4193  *
4194  * Waits on all BO's fences and for proper vblank count
4195  */
4196 static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
4197                               struct drm_framebuffer *fb,
4198                               uint32_t target,
4199                               struct dc_state *state)
4200 {
4201         unsigned long flags;
4202         uint32_t target_vblank;
4203         int r, vpos, hpos;
4204         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4205         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
4206         struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
4207         struct amdgpu_device *adev = crtc->dev->dev_private;
4208         bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
4209         struct dc_flip_addrs addr = { {0} };
4210         /* TODO eliminate or rename surface_update */
4211         struct dc_surface_update surface_updates[1] = { {0} };
4212         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
4213         struct dc_stream_status *stream_status;
4214
4215
4216         /* Prepare wait for target vblank early - before the fence-waits */
4217         target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
4218                         amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
4219
4220         /*
4221          * TODO This might fail and hence better not used, wait
4222          * explicitly on fences instead
4223          * and in general should be called for
4224          * blocking commit to as per framework helpers
4225          */
4226         r = amdgpu_bo_reserve(abo, true);
4227         if (unlikely(r != 0)) {
4228                 DRM_ERROR("failed to reserve buffer before flip\n");
4229                 WARN_ON(1);
4230         }
4231
4232         /* Wait for all fences on this FB */
4233         WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
4234                                                                     MAX_SCHEDULE_TIMEOUT) < 0);
4235
4236         amdgpu_bo_unreserve(abo);
4237
4238         /*
4239          * Wait until we're out of the vertical blank period before the one
4240          * targeted by the flip
4241          */
4242         while ((acrtc->enabled &&
4243                 (amdgpu_display_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id,
4244                                                     0, &vpos, &hpos, NULL,
4245                                                     NULL, &crtc->hwmode)
4246                  & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
4247                 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
4248                 (int)(target_vblank -
4249                   amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
4250                 usleep_range(1000, 1100);
4251         }
4252
4253         /* Flip */
4254         spin_lock_irqsave(&crtc->dev->event_lock, flags);
4255
4256         WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
4257         WARN_ON(!acrtc_state->stream);
4258
4259         addr.address.grph.addr.low_part = lower_32_bits(afb->address);
4260         addr.address.grph.addr.high_part = upper_32_bits(afb->address);
4261         addr.flip_immediate = async_flip;
4262
4263
4264         if (acrtc->base.state->event)
4265                 prepare_flip_isr(acrtc);
4266
4267         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4268
4269         stream_status = dc_stream_get_status(acrtc_state->stream);
4270         if (!stream_status) {
4271                 DRM_ERROR("No stream status for CRTC: id=%d\n",
4272                         acrtc->crtc_id);
4273                 return;
4274         }
4275
4276         surface_updates->surface = stream_status->plane_states[0];
4277         if (!surface_updates->surface) {
4278                 DRM_ERROR("No surface for CRTC: id=%d\n",
4279                         acrtc->crtc_id);
4280                 return;
4281         }
4282         surface_updates->flip_addr = &addr;
4283
4284         dc_commit_updates_for_stream(adev->dm.dc,
4285                                              surface_updates,
4286                                              1,
4287                                              acrtc_state->stream,
4288                                              NULL,
4289                                              &surface_updates->surface,
4290                                              state);
4291
4292         DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
4293                          __func__,
4294                          addr.address.grph.addr.high_part,
4295                          addr.address.grph.addr.low_part);
4296 }
4297
4298 /*
4299  * TODO this whole function needs to go
4300  *
4301  * dc_surface_update is needlessly complex. See if we can just replace this
4302  * with a dc_plane_state and follow the atomic model a bit more closely here.
4303  */
4304 static bool commit_planes_to_stream(
4305                 struct dc *dc,
4306                 struct dc_plane_state **plane_states,
4307                 uint8_t new_plane_count,
4308                 struct dm_crtc_state *dm_new_crtc_state,
4309                 struct dm_crtc_state *dm_old_crtc_state,
4310                 struct dc_state *state)
4311 {
4312         /* no need to dynamically allocate this. it's pretty small */
4313         struct dc_surface_update updates[MAX_SURFACES];
4314         struct dc_flip_addrs *flip_addr;
4315         struct dc_plane_info *plane_info;
4316         struct dc_scaling_info *scaling_info;
4317         int i;
4318         struct dc_stream_state *dc_stream = dm_new_crtc_state->stream;
4319         struct dc_stream_update *stream_update =
4320                         kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL);
4321
4322         if (!stream_update) {
4323                 BREAK_TO_DEBUGGER();
4324                 return false;
4325         }
4326
4327         flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs),
4328                             GFP_KERNEL);
4329         plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info),
4330                              GFP_KERNEL);
4331         scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info),
4332                                GFP_KERNEL);
4333
4334         if (!flip_addr || !plane_info || !scaling_info) {
4335                 kfree(flip_addr);
4336                 kfree(plane_info);
4337                 kfree(scaling_info);
4338                 kfree(stream_update);
4339                 return false;
4340         }
4341
4342         memset(updates, 0, sizeof(updates));
4343
4344         stream_update->src = dc_stream->src;
4345         stream_update->dst = dc_stream->dst;
4346         stream_update->out_transfer_func = dc_stream->out_transfer_func;
4347
4348         if (dm_new_crtc_state->freesync_enabled != dm_old_crtc_state->freesync_enabled) {
4349                 stream_update->vrr_infopacket = &dc_stream->vrr_infopacket;
4350                 stream_update->adjust = &dc_stream->adjust;
4351         }
4352
4353         for (i = 0; i < new_plane_count; i++) {
4354                 updates[i].surface = plane_states[i];
4355                 updates[i].gamma =
4356                         (struct dc_gamma *)plane_states[i]->gamma_correction;
4357                 updates[i].in_transfer_func = plane_states[i]->in_transfer_func;
4358                 flip_addr[i].address = plane_states[i]->address;
4359                 flip_addr[i].flip_immediate = plane_states[i]->flip_immediate;
4360                 plane_info[i].color_space = plane_states[i]->color_space;
4361                 plane_info[i].format = plane_states[i]->format;
4362                 plane_info[i].plane_size = plane_states[i]->plane_size;
4363                 plane_info[i].rotation = plane_states[i]->rotation;
4364                 plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror;
4365                 plane_info[i].stereo_format = plane_states[i]->stereo_format;
4366                 plane_info[i].tiling_info = plane_states[i]->tiling_info;
4367                 plane_info[i].visible = plane_states[i]->visible;
4368                 plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha;
4369                 plane_info[i].dcc = plane_states[i]->dcc;
4370                 scaling_info[i].scaling_quality = plane_states[i]->scaling_quality;
4371                 scaling_info[i].src_rect = plane_states[i]->src_rect;
4372                 scaling_info[i].dst_rect = plane_states[i]->dst_rect;
4373                 scaling_info[i].clip_rect = plane_states[i]->clip_rect;
4374
4375                 updates[i].flip_addr = &flip_addr[i];
4376                 updates[i].plane_info = &plane_info[i];
4377                 updates[i].scaling_info = &scaling_info[i];
4378         }
4379
4380         dc_commit_updates_for_stream(
4381                         dc,
4382                         updates,
4383                         new_plane_count,
4384                         dc_stream, stream_update, plane_states, state);
4385
4386         kfree(flip_addr);
4387         kfree(plane_info);
4388         kfree(scaling_info);
4389         kfree(stream_update);
4390         return true;
4391 }
4392
4393 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
4394                                     struct drm_device *dev,
4395                                     struct amdgpu_display_manager *dm,
4396                                     struct drm_crtc *pcrtc,
4397                                     bool *wait_for_vblank)
4398 {
4399         uint32_t i;
4400         struct drm_plane *plane;
4401         struct drm_plane_state *old_plane_state, *new_plane_state;
4402         struct dc_stream_state *dc_stream_attach;
4403         struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
4404         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
4405         struct drm_crtc_state *new_pcrtc_state =
4406                         drm_atomic_get_new_crtc_state(state, pcrtc);
4407         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
4408         struct dm_crtc_state *dm_old_crtc_state =
4409                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
4410         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4411         int planes_count = 0;
4412         unsigned long flags;
4413
4414         /* update planes when needed */
4415         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4416                 struct drm_crtc *crtc = new_plane_state->crtc;
4417                 struct drm_crtc_state *new_crtc_state;
4418                 struct drm_framebuffer *fb = new_plane_state->fb;
4419                 bool pflip_needed;
4420                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
4421
4422                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
4423                         handle_cursor_update(plane, old_plane_state);
4424                         continue;
4425                 }
4426
4427                 if (!fb || !crtc || pcrtc != crtc)
4428                         continue;
4429
4430                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
4431                 if (!new_crtc_state->active)
4432                         continue;
4433
4434                 pflip_needed = !state->allow_modeset;
4435
4436                 spin_lock_irqsave(&crtc->dev->event_lock, flags);
4437                 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
4438                         DRM_ERROR("%s: acrtc %d, already busy\n",
4439                                   __func__,
4440                                   acrtc_attach->crtc_id);
4441                         /* In commit tail framework this cannot happen */
4442                         WARN_ON(1);
4443                 }
4444                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4445
4446                 if (!pflip_needed || plane->type == DRM_PLANE_TYPE_OVERLAY) {
4447                         WARN_ON(!dm_new_plane_state->dc_state);
4448
4449                         plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
4450
4451                         dc_stream_attach = acrtc_state->stream;
4452                         planes_count++;
4453
4454                 } else if (new_crtc_state->planes_changed) {
4455                         /* Assume even ONE crtc with immediate flip means
4456                          * entire can't wait for VBLANK
4457                          * TODO Check if it's correct
4458                          */
4459                         *wait_for_vblank =
4460                                         new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
4461                                 false : true;
4462
4463                         /* TODO: Needs rework for multiplane flip */
4464                         if (plane->type == DRM_PLANE_TYPE_PRIMARY)
4465                                 drm_crtc_vblank_get(crtc);
4466
4467                         amdgpu_dm_do_flip(
4468                                 crtc,
4469                                 fb,
4470                                 (uint32_t)drm_crtc_vblank_count(crtc) + *wait_for_vblank,
4471                                 dm_state->context);
4472                 }
4473
4474         }
4475
4476         if (planes_count) {
4477                 unsigned long flags;
4478
4479                 if (new_pcrtc_state->event) {
4480
4481                         drm_crtc_vblank_get(pcrtc);
4482
4483                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
4484                         prepare_flip_isr(acrtc_attach);
4485                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
4486                 }
4487
4488                 dc_stream_attach->adjust = acrtc_state->adjust;
4489                 dc_stream_attach->vrr_infopacket = acrtc_state->vrr_infopacket;
4490
4491                 if (false == commit_planes_to_stream(dm->dc,
4492                                                         plane_states_constructed,
4493                                                         planes_count,
4494                                                         acrtc_state,
4495                                                         dm_old_crtc_state,
4496                                                         dm_state->context))
4497                         dm_error("%s: Failed to attach plane!\n", __func__);
4498         } else {
4499                 /*TODO BUG Here should go disable planes on CRTC. */
4500         }
4501 }
4502
4503 /*
4504  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
4505  * @crtc_state: the DRM CRTC state
4506  * @stream_state: the DC stream state.
4507  *
4508  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
4509  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
4510  */
4511 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
4512                                                 struct dc_stream_state *stream_state)
4513 {
4514         stream_state->mode_changed = crtc_state->mode_changed;
4515 }
4516
4517 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
4518                                    struct drm_atomic_state *state,
4519                                    bool nonblock)
4520 {
4521         struct drm_crtc *crtc;
4522         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4523         struct amdgpu_device *adev = dev->dev_private;
4524         int i;
4525
4526         /*
4527          * We evade vblanks and pflips on crtc that
4528          * should be changed. We do it here to flush & disable
4529          * interrupts before drm_swap_state is called in drm_atomic_helper_commit
4530          * it will update crtc->dm_crtc_state->stream pointer which is used in
4531          * the ISRs.
4532          */
4533         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4534                 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4535                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4536
4537                 if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream)
4538                         manage_dm_interrupts(adev, acrtc, false);
4539         }
4540         /*
4541          * Add check here for SoC's that support hardware cursor plane, to
4542          * unset legacy_cursor_update
4543          */
4544
4545         return drm_atomic_helper_commit(dev, state, nonblock);
4546
4547         /*TODO Handle EINTR, reenable IRQ*/
4548 }
4549
4550 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
4551 {
4552         struct drm_device *dev = state->dev;
4553         struct amdgpu_device *adev = dev->dev_private;
4554         struct amdgpu_display_manager *dm = &adev->dm;
4555         struct dm_atomic_state *dm_state;
4556         uint32_t i, j;
4557         struct drm_crtc *crtc;
4558         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4559         unsigned long flags;
4560         bool wait_for_vblank = true;
4561         struct drm_connector *connector;
4562         struct drm_connector_state *old_con_state, *new_con_state;
4563         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
4564         int crtc_disable_count = 0;
4565
4566         drm_atomic_helper_update_legacy_modeset_state(dev, state);
4567
4568         dm_state = to_dm_atomic_state(state);
4569
4570         /* update changed items */
4571         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4572                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4573
4574                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4575                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4576
4577                 DRM_DEBUG_DRIVER(
4578                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4579                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4580                         "connectors_changed:%d\n",
4581                         acrtc->crtc_id,
4582                         new_crtc_state->enable,
4583                         new_crtc_state->active,
4584                         new_crtc_state->planes_changed,
4585                         new_crtc_state->mode_changed,
4586                         new_crtc_state->active_changed,
4587                         new_crtc_state->connectors_changed);
4588
4589                 /* Copy all transient state flags into dc state */
4590                 if (dm_new_crtc_state->stream) {
4591                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
4592                                                             dm_new_crtc_state->stream);
4593                 }
4594
4595                 /* handles headless hotplug case, updating new_state and
4596                  * aconnector as needed
4597                  */
4598
4599                 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
4600
4601                         DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
4602
4603                         if (!dm_new_crtc_state->stream) {
4604                                 /*
4605                                  * this could happen because of issues with
4606                                  * userspace notifications delivery.
4607                                  * In this case userspace tries to set mode on
4608                                  * display which is disconnected in fact.
4609                                  * dc_sink is NULL in this case on aconnector.
4610                                  * We expect reset mode will come soon.
4611                                  *
4612                                  * This can also happen when unplug is done
4613                                  * during resume sequence ended
4614                                  *
4615                                  * In this case, we want to pretend we still
4616                                  * have a sink to keep the pipe running so that
4617                                  * hw state is consistent with the sw state
4618                                  */
4619                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
4620                                                 __func__, acrtc->base.base.id);
4621                                 continue;
4622                         }
4623
4624                         if (dm_old_crtc_state->stream)
4625                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
4626
4627                         pm_runtime_get_noresume(dev->dev);
4628
4629                         acrtc->enabled = true;
4630                         acrtc->hw_mode = new_crtc_state->mode;
4631                         crtc->hwmode = new_crtc_state->mode;
4632                 } else if (modereset_required(new_crtc_state)) {
4633                         DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
4634
4635                         /* i.e. reset mode */
4636                         if (dm_old_crtc_state->stream)
4637                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
4638                 }
4639         } /* for_each_crtc_in_state() */
4640
4641         if (dm_state->context) {
4642                 dm_enable_per_frame_crtc_master_sync(dm_state->context);
4643                 WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
4644         }
4645
4646         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
4647                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4648
4649                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4650
4651                 if (dm_new_crtc_state->stream != NULL) {
4652                         const struct dc_stream_status *status =
4653                                         dc_stream_get_status(dm_new_crtc_state->stream);
4654
4655                         if (!status)
4656                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
4657                         else
4658                                 acrtc->otg_inst = status->primary_otg_inst;
4659                 }
4660         }
4661
4662         /* Handle scaling and underscan changes*/
4663         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
4664                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4665                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4666                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
4667                 struct dc_stream_status *status = NULL;
4668
4669                 if (acrtc) {
4670                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
4671                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
4672                 }
4673
4674                 /* Skip any modesets/resets */
4675                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
4676                         continue;
4677
4678                 /* Skip anything that is not scaling or underscan changes */
4679                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
4680                         continue;
4681
4682                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4683
4684                 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
4685                                 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
4686
4687                 if (!dm_new_crtc_state->stream)
4688                         continue;
4689
4690                 status = dc_stream_get_status(dm_new_crtc_state->stream);
4691                 WARN_ON(!status);
4692                 WARN_ON(!status->plane_count);
4693
4694                 dm_new_crtc_state->stream->adjust = dm_new_crtc_state->adjust;
4695                 dm_new_crtc_state->stream->vrr_infopacket = dm_new_crtc_state->vrr_infopacket;
4696
4697                 /*TODO How it works with MPO ?*/
4698                 if (!commit_planes_to_stream(
4699                                 dm->dc,
4700                                 status->plane_states,
4701                                 status->plane_count,
4702                                 dm_new_crtc_state,
4703                                 to_dm_crtc_state(old_crtc_state),
4704                                 dm_state->context))
4705                         dm_error("%s: Failed to update stream scaling!\n", __func__);
4706         }
4707
4708         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
4709                         new_crtc_state, i) {
4710                 /*
4711                  * loop to enable interrupts on newly arrived crtc
4712                  */
4713                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4714                 bool modeset_needed;
4715
4716                 if (old_crtc_state->active && !new_crtc_state->active)
4717                         crtc_disable_count++;
4718
4719                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4720                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4721                 modeset_needed = modeset_required(
4722                                 new_crtc_state,
4723                                 dm_new_crtc_state->stream,
4724                                 dm_old_crtc_state->stream);
4725
4726                 if (dm_new_crtc_state->stream == NULL || !modeset_needed)
4727                         continue;
4728
4729                 manage_dm_interrupts(adev, acrtc, true);
4730         }
4731
4732         /* update planes when needed per crtc*/
4733         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
4734                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4735
4736                 if (dm_new_crtc_state->stream)
4737                         amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank);
4738         }
4739
4740
4741         /*
4742          * send vblank event on all events not handled in flip and
4743          * mark consumed event for drm_atomic_helper_commit_hw_done
4744          */
4745         spin_lock_irqsave(&adev->ddev->event_lock, flags);
4746         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
4747
4748                 if (new_crtc_state->event)
4749                         drm_send_event_locked(dev, &new_crtc_state->event->base);
4750
4751                 new_crtc_state->event = NULL;
4752         }
4753         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
4754
4755
4756         if (wait_for_vblank)
4757                 drm_atomic_helper_wait_for_flip_done(dev, state);
4758
4759         /*
4760          * FIXME:
4761          * Delay hw_done() until flip_done() is signaled. This is to block
4762          * another commit from freeing the CRTC state while we're still
4763          * waiting on flip_done.
4764          */
4765         drm_atomic_helper_commit_hw_done(state);
4766
4767         drm_atomic_helper_cleanup_planes(dev, state);
4768
4769         /*
4770          * Finally, drop a runtime PM reference for each newly disabled CRTC,
4771          * so we can put the GPU into runtime suspend if we're not driving any
4772          * displays anymore
4773          */
4774         for (i = 0; i < crtc_disable_count; i++)
4775                 pm_runtime_put_autosuspend(dev->dev);
4776         pm_runtime_mark_last_busy(dev->dev);
4777 }
4778
4779
4780 static int dm_force_atomic_commit(struct drm_connector *connector)
4781 {
4782         int ret = 0;
4783         struct drm_device *ddev = connector->dev;
4784         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
4785         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4786         struct drm_plane *plane = disconnected_acrtc->base.primary;
4787         struct drm_connector_state *conn_state;
4788         struct drm_crtc_state *crtc_state;
4789         struct drm_plane_state *plane_state;
4790
4791         if (!state)
4792                 return -ENOMEM;
4793
4794         state->acquire_ctx = ddev->mode_config.acquire_ctx;
4795
4796         /* Construct an atomic state to restore previous display setting */
4797
4798         /*
4799          * Attach connectors to drm_atomic_state
4800          */
4801         conn_state = drm_atomic_get_connector_state(state, connector);
4802
4803         ret = PTR_ERR_OR_ZERO(conn_state);
4804         if (ret)
4805                 goto err;
4806
4807         /* Attach crtc to drm_atomic_state*/
4808         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
4809
4810         ret = PTR_ERR_OR_ZERO(crtc_state);
4811         if (ret)
4812                 goto err;
4813
4814         /* force a restore */
4815         crtc_state->mode_changed = true;
4816
4817         /* Attach plane to drm_atomic_state */
4818         plane_state = drm_atomic_get_plane_state(state, plane);
4819
4820         ret = PTR_ERR_OR_ZERO(plane_state);
4821         if (ret)
4822                 goto err;
4823
4824
4825         /* Call commit internally with the state we just constructed */
4826         ret = drm_atomic_commit(state);
4827         if (!ret)
4828                 return 0;
4829
4830 err:
4831         DRM_ERROR("Restoring old state failed with %i\n", ret);
4832         drm_atomic_state_put(state);
4833
4834         return ret;
4835 }
4836
4837 /*
4838  * This function handles all cases when set mode does not come upon hotplug.
4839  * This includes when a display is unplugged then plugged back into the
4840  * same port and when running without usermode desktop manager supprot
4841  */
4842 void dm_restore_drm_connector_state(struct drm_device *dev,
4843                                     struct drm_connector *connector)
4844 {
4845         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
4846         struct amdgpu_crtc *disconnected_acrtc;
4847         struct dm_crtc_state *acrtc_state;
4848
4849         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
4850                 return;
4851
4852         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4853         if (!disconnected_acrtc)
4854                 return;
4855
4856         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
4857         if (!acrtc_state->stream)
4858                 return;
4859
4860         /*
4861          * If the previous sink is not released and different from the current,
4862          * we deduce we are in a state where we can not rely on usermode call
4863          * to turn on the display, so we do it here
4864          */
4865         if (acrtc_state->stream->sink != aconnector->dc_sink)
4866                 dm_force_atomic_commit(&aconnector->base);
4867 }
4868
4869 /*
4870  * Grabs all modesetting locks to serialize against any blocking commits,
4871  * Waits for completion of all non blocking commits.
4872  */
4873 static int do_aquire_global_lock(struct drm_device *dev,
4874                                  struct drm_atomic_state *state)
4875 {
4876         struct drm_crtc *crtc;
4877         struct drm_crtc_commit *commit;
4878         long ret;
4879
4880         /*
4881          * Adding all modeset locks to aquire_ctx will
4882          * ensure that when the framework release it the
4883          * extra locks we are locking here will get released to
4884          */
4885         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
4886         if (ret)
4887                 return ret;
4888
4889         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4890                 spin_lock(&crtc->commit_lock);
4891                 commit = list_first_entry_or_null(&crtc->commit_list,
4892                                 struct drm_crtc_commit, commit_entry);
4893                 if (commit)
4894                         drm_crtc_commit_get(commit);
4895                 spin_unlock(&crtc->commit_lock);
4896
4897                 if (!commit)
4898                         continue;
4899
4900                 /*
4901                  * Make sure all pending HW programming completed and
4902                  * page flips done
4903                  */
4904                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
4905
4906                 if (ret > 0)
4907                         ret = wait_for_completion_interruptible_timeout(
4908                                         &commit->flip_done, 10*HZ);
4909
4910                 if (ret == 0)
4911                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
4912                                   "timed out\n", crtc->base.id, crtc->name);
4913
4914                 drm_crtc_commit_put(commit);
4915         }
4916
4917         return ret < 0 ? ret : 0;
4918 }
4919
4920 void set_freesync_on_stream(struct amdgpu_display_manager *dm,
4921                             struct dm_crtc_state *new_crtc_state,
4922                             struct dm_connector_state *new_con_state,
4923                             struct dc_stream_state *new_stream)
4924 {
4925         struct mod_freesync_config config = {0};
4926         struct mod_vrr_params vrr = {0};
4927         struct dc_info_packet vrr_infopacket = {0};
4928         struct amdgpu_dm_connector *aconnector =
4929                         to_amdgpu_dm_connector(new_con_state->base.connector);
4930
4931         if (new_con_state->freesync_capable &&
4932             new_con_state->freesync_enable) {
4933                 config.state = new_crtc_state->freesync_enabled ?
4934                                 VRR_STATE_ACTIVE_VARIABLE :
4935                                 VRR_STATE_INACTIVE;
4936                 config.min_refresh_in_uhz =
4937                                 aconnector->min_vfreq * 1000000;
4938                 config.max_refresh_in_uhz =
4939                                 aconnector->max_vfreq * 1000000;
4940                 config.vsif_supported = true;
4941         }
4942
4943         mod_freesync_build_vrr_params(dm->freesync_module,
4944                                       new_stream,
4945                                       &config, &vrr);
4946
4947         mod_freesync_build_vrr_infopacket(dm->freesync_module,
4948                                           new_stream,
4949                                           &vrr,
4950                                           packet_type_fs1,
4951                                           NULL,
4952                                           &vrr_infopacket);
4953
4954         new_crtc_state->adjust = vrr.adjust;
4955         new_crtc_state->vrr_infopacket = vrr_infopacket;
4956 }
4957
4958 static int dm_update_crtcs_state(struct amdgpu_display_manager *dm,
4959                                  struct drm_atomic_state *state,
4960                                  bool enable,
4961                                  bool *lock_and_validation_needed)
4962 {
4963         struct drm_crtc *crtc;
4964         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4965         int i;
4966         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
4967         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4968         struct dc_stream_state *new_stream;
4969         int ret = 0;
4970
4971         /*
4972          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
4973          * update changed items
4974          */
4975         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4976                 struct amdgpu_crtc *acrtc = NULL;
4977                 struct amdgpu_dm_connector *aconnector = NULL;
4978                 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
4979                 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
4980                 struct drm_plane_state *new_plane_state = NULL;
4981
4982                 new_stream = NULL;
4983
4984                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4985                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4986                 acrtc = to_amdgpu_crtc(crtc);
4987
4988                 new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary);
4989
4990                 if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) {
4991                         ret = -EINVAL;
4992                         goto fail;
4993                 }
4994
4995                 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
4996
4997                 /* TODO This hack should go away */
4998                 if (aconnector && enable) {
4999                         /* Make sure fake sink is created in plug-in scenario */
5000                         drm_new_conn_state = drm_atomic_get_new_connector_state(state,
5001                                                                     &aconnector->base);
5002                         drm_old_conn_state = drm_atomic_get_old_connector_state(state,
5003                                                                     &aconnector->base);
5004
5005                         if (IS_ERR(drm_new_conn_state)) {
5006                                 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
5007                                 break;
5008                         }
5009
5010                         dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
5011                         dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
5012
5013                         new_stream = create_stream_for_sink(aconnector,
5014                                                              &new_crtc_state->mode,
5015                                                             dm_new_conn_state);
5016
5017                         /*
5018                          * we can have no stream on ACTION_SET if a display
5019                          * was disconnected during S3, in this case it is not an
5020                          * error, the OS will be updated after detection, and
5021                          * will do the right thing on next atomic commit
5022                          */
5023
5024                         if (!new_stream) {
5025                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
5026                                                 __func__, acrtc->base.base.id);
5027                                 break;
5028                         }
5029
5030                         set_freesync_on_stream(dm, dm_new_crtc_state,
5031                                                dm_new_conn_state, new_stream);
5032
5033                         if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
5034                             dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
5035                                 new_crtc_state->mode_changed = false;
5036                                 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
5037                                                  new_crtc_state->mode_changed);
5038                         }
5039                 }
5040
5041                 if (dm_old_crtc_state->freesync_enabled != dm_new_crtc_state->freesync_enabled)
5042                         new_crtc_state->mode_changed = true;
5043
5044                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
5045                         goto next_crtc;
5046
5047                 DRM_DEBUG_DRIVER(
5048                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
5049                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
5050                         "connectors_changed:%d\n",
5051                         acrtc->crtc_id,
5052                         new_crtc_state->enable,
5053                         new_crtc_state->active,
5054                         new_crtc_state->planes_changed,
5055                         new_crtc_state->mode_changed,
5056                         new_crtc_state->active_changed,
5057                         new_crtc_state->connectors_changed);
5058
5059                 /* Remove stream for any changed/disabled CRTC */
5060                 if (!enable) {
5061
5062                         if (!dm_old_crtc_state->stream)
5063                                 goto next_crtc;
5064
5065                         DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
5066                                         crtc->base.id);
5067
5068                         /* i.e. reset mode */
5069                         if (dc_remove_stream_from_ctx(
5070                                         dm->dc,
5071                                         dm_state->context,
5072                                         dm_old_crtc_state->stream) != DC_OK) {
5073                                 ret = -EINVAL;
5074                                 goto fail;
5075                         }
5076
5077                         dc_stream_release(dm_old_crtc_state->stream);
5078                         dm_new_crtc_state->stream = NULL;
5079
5080                         *lock_and_validation_needed = true;
5081
5082                 } else {/* Add stream for any updated/enabled CRTC */
5083                         /*
5084                          * Quick fix to prevent NULL pointer on new_stream when
5085                          * added MST connectors not found in existing crtc_state in the chained mode
5086                          * TODO: need to dig out the root cause of that
5087                          */
5088                         if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
5089                                 goto next_crtc;
5090
5091                         if (modereset_required(new_crtc_state))
5092                                 goto next_crtc;
5093
5094                         if (modeset_required(new_crtc_state, new_stream,
5095                                              dm_old_crtc_state->stream)) {
5096
5097                                 WARN_ON(dm_new_crtc_state->stream);
5098
5099                                 dm_new_crtc_state->stream = new_stream;
5100
5101                                 dc_stream_retain(new_stream);
5102
5103                                 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
5104                                                         crtc->base.id);
5105
5106                                 if (dc_add_stream_to_ctx(
5107                                                 dm->dc,
5108                                                 dm_state->context,
5109                                                 dm_new_crtc_state->stream) != DC_OK) {
5110                                         ret = -EINVAL;
5111                                         goto fail;
5112                                 }
5113
5114                                 *lock_and_validation_needed = true;
5115                         }
5116                 }
5117
5118 next_crtc:
5119                 /* Release extra reference */
5120                 if (new_stream)
5121                          dc_stream_release(new_stream);
5122
5123                 /*
5124                  * We want to do dc stream updates that do not require a
5125                  * full modeset below.
5126                  */
5127                 if (!(enable && aconnector && new_crtc_state->enable &&
5128                       new_crtc_state->active))
5129                         continue;
5130                 /*
5131                  * Given above conditions, the dc state cannot be NULL because:
5132                  * 1. We're in the process of enabling CRTCs (just been added
5133                  *    to the dc context, or already is on the context)
5134                  * 2. Has a valid connector attached, and
5135                  * 3. Is currently active and enabled.
5136                  * => The dc stream state currently exists.
5137                  */
5138                 BUG_ON(dm_new_crtc_state->stream == NULL);
5139
5140                 /* Scaling or underscan settings */
5141                 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
5142                         update_stream_scaling_settings(
5143                                 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
5144
5145                 /*
5146                  * Color management settings. We also update color properties
5147                  * when a modeset is needed, to ensure it gets reprogrammed.
5148                  */
5149                 if (dm_new_crtc_state->base.color_mgmt_changed ||
5150                     drm_atomic_crtc_needs_modeset(new_crtc_state)) {
5151                         ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
5152                         if (ret)
5153                                 goto fail;
5154                         amdgpu_dm_set_ctm(dm_new_crtc_state);
5155                 }
5156
5157
5158         }
5159
5160         return ret;
5161
5162 fail:
5163         if (new_stream)
5164                 dc_stream_release(new_stream);
5165         return ret;
5166 }
5167
5168 static int dm_update_planes_state(struct dc *dc,
5169                                   struct drm_atomic_state *state,
5170                                   bool enable,
5171                                   bool *lock_and_validation_needed)
5172 {
5173         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
5174         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
5175         struct drm_plane *plane;
5176         struct drm_plane_state *old_plane_state, *new_plane_state;
5177         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
5178         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
5179         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
5180         int i ;
5181         /* TODO return page_flip_needed() function */
5182         bool pflip_needed  = !state->allow_modeset;
5183         int ret = 0;
5184
5185
5186         /* Add new planes, in reverse order as DC expectation */
5187         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
5188                 new_plane_crtc = new_plane_state->crtc;
5189                 old_plane_crtc = old_plane_state->crtc;
5190                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
5191                 dm_old_plane_state = to_dm_plane_state(old_plane_state);
5192
5193                 /*TODO Implement atomic check for cursor plane */
5194                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5195                         continue;
5196
5197                 /* Remove any changed/removed planes */
5198                 if (!enable) {
5199                         if (pflip_needed &&
5200                             plane->type != DRM_PLANE_TYPE_OVERLAY)
5201                                 continue;
5202
5203                         if (!old_plane_crtc)
5204                                 continue;
5205
5206                         old_crtc_state = drm_atomic_get_old_crtc_state(
5207                                         state, old_plane_crtc);
5208                         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5209
5210                         if (!dm_old_crtc_state->stream)
5211                                 continue;
5212
5213                         DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
5214                                         plane->base.id, old_plane_crtc->base.id);
5215
5216                         if (!dc_remove_plane_from_context(
5217                                         dc,
5218                                         dm_old_crtc_state->stream,
5219                                         dm_old_plane_state->dc_state,
5220                                         dm_state->context)) {
5221
5222                                 ret = EINVAL;
5223                                 return ret;
5224                         }
5225
5226
5227                         dc_plane_state_release(dm_old_plane_state->dc_state);
5228                         dm_new_plane_state->dc_state = NULL;
5229
5230                         *lock_and_validation_needed = true;
5231
5232                 } else { /* Add new planes */
5233                         struct dc_plane_state *dc_new_plane_state;
5234
5235                         if (drm_atomic_plane_disabling(plane->state, new_plane_state))
5236                                 continue;
5237
5238                         if (!new_plane_crtc)
5239                                 continue;
5240
5241                         new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
5242                         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5243
5244                         if (!dm_new_crtc_state->stream)
5245                                 continue;
5246
5247                         if (pflip_needed &&
5248                             plane->type != DRM_PLANE_TYPE_OVERLAY)
5249                                 continue;
5250
5251                         WARN_ON(dm_new_plane_state->dc_state);
5252
5253                         dc_new_plane_state = dc_create_plane_state(dc);
5254                         if (!dc_new_plane_state)
5255                                 return -ENOMEM;
5256
5257                         DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
5258                                         plane->base.id, new_plane_crtc->base.id);
5259
5260                         ret = fill_plane_attributes(
5261                                 new_plane_crtc->dev->dev_private,
5262                                 dc_new_plane_state,
5263                                 new_plane_state,
5264                                 new_crtc_state);
5265                         if (ret) {
5266                                 dc_plane_state_release(dc_new_plane_state);
5267                                 return ret;
5268                         }
5269
5270                         /*
5271                          * Any atomic check errors that occur after this will
5272                          * not need a release. The plane state will be attached
5273                          * to the stream, and therefore part of the atomic
5274                          * state. It'll be released when the atomic state is
5275                          * cleaned.
5276                          */
5277                         if (!dc_add_plane_to_context(
5278                                         dc,
5279                                         dm_new_crtc_state->stream,
5280                                         dc_new_plane_state,
5281                                         dm_state->context)) {
5282
5283                                 dc_plane_state_release(dc_new_plane_state);
5284                                 return -EINVAL;
5285                         }
5286
5287                         dm_new_plane_state->dc_state = dc_new_plane_state;
5288
5289                         /* Tell DC to do a full surface update every time there
5290                          * is a plane change. Inefficient, but works for now.
5291                          */
5292                         dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
5293
5294                         *lock_and_validation_needed = true;
5295                 }
5296         }
5297
5298
5299         return ret;
5300 }
5301 enum surface_update_type dm_determine_update_type_for_commit(struct dc *dc, struct drm_atomic_state *state)
5302 {
5303
5304
5305         int i, j, num_plane;
5306         struct drm_plane_state *old_plane_state, *new_plane_state;
5307         struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
5308         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
5309         struct drm_plane *plane;
5310
5311         struct drm_crtc *crtc;
5312         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
5313         struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state;
5314         struct dc_stream_status *status = NULL;
5315
5316         struct dc_surface_update *updates = kzalloc(MAX_SURFACES * sizeof(struct dc_surface_update), GFP_KERNEL);
5317         struct dc_plane_state *surface = kzalloc(MAX_SURFACES * sizeof(struct dc_plane_state), GFP_KERNEL);
5318         struct dc_stream_update stream_update;
5319         enum surface_update_type update_type = UPDATE_TYPE_FAST;
5320
5321
5322         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5323                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
5324                 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
5325                 num_plane = 0;
5326
5327                 if (new_dm_crtc_state->stream) {
5328
5329                         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
5330                                 new_plane_crtc = new_plane_state->crtc;
5331                                 old_plane_crtc = old_plane_state->crtc;
5332                                 new_dm_plane_state = to_dm_plane_state(new_plane_state);
5333                                 old_dm_plane_state = to_dm_plane_state(old_plane_state);
5334
5335                                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5336                                         continue;
5337
5338                                 if (!state->allow_modeset)
5339                                         continue;
5340
5341                                 if (crtc == new_plane_crtc) {
5342                                         updates[num_plane].surface = &surface[num_plane];
5343
5344                                         if (new_crtc_state->mode_changed) {
5345                                                 updates[num_plane].surface->src_rect =
5346                                                                         new_dm_plane_state->dc_state->src_rect;
5347                                                 updates[num_plane].surface->dst_rect =
5348                                                                         new_dm_plane_state->dc_state->dst_rect;
5349                                                 updates[num_plane].surface->rotation =
5350                                                                         new_dm_plane_state->dc_state->rotation;
5351                                                 updates[num_plane].surface->in_transfer_func =
5352                                                                         new_dm_plane_state->dc_state->in_transfer_func;
5353                                                 stream_update.dst = new_dm_crtc_state->stream->dst;
5354                                                 stream_update.src = new_dm_crtc_state->stream->src;
5355                                         }
5356
5357                                         if (new_crtc_state->color_mgmt_changed) {
5358                                                 updates[num_plane].gamma =
5359                                                                 new_dm_plane_state->dc_state->gamma_correction;
5360                                                 updates[num_plane].in_transfer_func =
5361                                                                 new_dm_plane_state->dc_state->in_transfer_func;
5362                                                 stream_update.gamut_remap =
5363                                                                 &new_dm_crtc_state->stream->gamut_remap_matrix;
5364                                                 stream_update.out_transfer_func =
5365                                                                 new_dm_crtc_state->stream->out_transfer_func;
5366                                         }
5367
5368                                         num_plane++;
5369                                 }
5370                         }
5371
5372                         if (num_plane > 0) {
5373                                 status = dc_stream_get_status(new_dm_crtc_state->stream);
5374                                 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
5375                                                                                   &stream_update, status);
5376
5377                                 if (update_type > UPDATE_TYPE_MED) {
5378                                         update_type = UPDATE_TYPE_FULL;
5379                                         goto ret;
5380                                 }
5381                         }
5382
5383                 } else if (!new_dm_crtc_state->stream && old_dm_crtc_state->stream) {
5384                         update_type = UPDATE_TYPE_FULL;
5385                         goto ret;
5386                 }
5387         }
5388
5389 ret:
5390         kfree(updates);
5391         kfree(surface);
5392
5393         return update_type;
5394 }
5395
5396 static int amdgpu_dm_atomic_check(struct drm_device *dev,
5397                                   struct drm_atomic_state *state)
5398 {
5399         struct amdgpu_device *adev = dev->dev_private;
5400         struct dc *dc = adev->dm.dc;
5401         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
5402         struct drm_connector *connector;
5403         struct drm_connector_state *old_con_state, *new_con_state;
5404         struct drm_crtc *crtc;
5405         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
5406         enum surface_update_type update_type = UPDATE_TYPE_FAST;
5407         enum surface_update_type overall_update_type = UPDATE_TYPE_FAST;
5408
5409         int ret, i;
5410
5411         /*
5412          * This bool will be set for true for any modeset/reset
5413          * or plane update which implies non fast surface update.
5414          */
5415         bool lock_and_validation_needed = false;
5416
5417         ret = drm_atomic_helper_check_modeset(dev, state);
5418         if (ret)
5419                 goto fail;
5420
5421         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5422                 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5423                 struct dm_crtc_state *dm_old_crtc_state  = to_dm_crtc_state(old_crtc_state);
5424
5425                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
5426                     !new_crtc_state->color_mgmt_changed &&
5427                     (dm_old_crtc_state->freesync_enabled == dm_new_crtc_state->freesync_enabled))
5428                         continue;
5429
5430                 if (!new_crtc_state->enable)
5431                         continue;
5432
5433                 ret = drm_atomic_add_affected_connectors(state, crtc);
5434                 if (ret)
5435                         return ret;
5436
5437                 ret = drm_atomic_add_affected_planes(state, crtc);
5438                 if (ret)
5439                         goto fail;
5440         }
5441
5442         dm_state->context = dc_create_state();
5443         ASSERT(dm_state->context);
5444         dc_resource_state_copy_construct_current(dc, dm_state->context);
5445
5446         /* Remove exiting planes if they are modified */
5447         ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
5448         if (ret) {
5449                 goto fail;
5450         }
5451
5452         /* Disable all crtcs which require disable */
5453         ret = dm_update_crtcs_state(&adev->dm, state, false, &lock_and_validation_needed);
5454         if (ret) {
5455                 goto fail;
5456         }
5457
5458         /* Enable all crtcs which require enable */
5459         ret = dm_update_crtcs_state(&adev->dm, state, true, &lock_and_validation_needed);
5460         if (ret) {
5461                 goto fail;
5462         }
5463
5464         /* Add new/modified planes */
5465         ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
5466         if (ret) {
5467                 goto fail;
5468         }
5469
5470         /* Run this here since we want to validate the streams we created */
5471         ret = drm_atomic_helper_check_planes(dev, state);
5472         if (ret)
5473                 goto fail;
5474
5475         /* Check scaling and underscan changes*/
5476         /* TODO Removed scaling changes validation due to inability to commit
5477          * new stream into context w\o causing full reset. Need to
5478          * decide how to handle.
5479          */
5480         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
5481                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
5482                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
5483                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
5484
5485                 /* Skip any modesets/resets */
5486                 if (!acrtc || drm_atomic_crtc_needs_modeset(
5487                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
5488                         continue;
5489
5490                 /* Skip any thing not scale or underscan changes */
5491                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
5492                         continue;
5493
5494                 overall_update_type = UPDATE_TYPE_FULL;
5495                 lock_and_validation_needed = true;
5496         }
5497
5498         /*
5499          * For full updates case when
5500          * removing/adding/updating streams on one CRTC while flipping
5501          * on another CRTC,
5502          * acquiring global lock  will guarantee that any such full
5503          * update commit
5504          * will wait for completion of any outstanding flip using DRMs
5505          * synchronization events.
5506          */
5507         update_type = dm_determine_update_type_for_commit(dc, state);
5508
5509         if (overall_update_type < update_type)
5510                 overall_update_type = update_type;
5511
5512         /*
5513          * lock_and_validation_needed was an old way to determine if we need to set
5514          * the global lock. Leaving it in to check if we broke any corner cases
5515          * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED
5516          * lock_and_validation_needed false = UPDATE_TYPE_FAST
5517          */
5518         if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST)
5519                 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL");
5520         else if (!lock_and_validation_needed && overall_update_type > UPDATE_TYPE_FAST)
5521                 WARN(1, "Global lock should NOT be set, overall_update_type should be UPDATE_TYPE_FAST");
5522
5523
5524         if (overall_update_type > UPDATE_TYPE_FAST) {
5525
5526                 ret = do_aquire_global_lock(dev, state);
5527                 if (ret)
5528                         goto fail;
5529
5530                 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
5531                         ret = -EINVAL;
5532                         goto fail;
5533                 }
5534         }
5535
5536         /* Must be success */
5537         WARN_ON(ret);
5538         return ret;
5539
5540 fail:
5541         if (ret == -EDEADLK)
5542                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
5543         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
5544                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
5545         else
5546                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
5547
5548         return ret;
5549 }
5550
5551 static bool is_dp_capable_without_timing_msa(struct dc *dc,
5552                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
5553 {
5554         uint8_t dpcd_data;
5555         bool capable = false;
5556
5557         if (amdgpu_dm_connector->dc_link &&
5558                 dm_helpers_dp_read_dpcd(
5559                                 NULL,
5560                                 amdgpu_dm_connector->dc_link,
5561                                 DP_DOWN_STREAM_PORT_COUNT,
5562                                 &dpcd_data,
5563                                 sizeof(dpcd_data))) {
5564                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
5565         }
5566
5567         return capable;
5568 }
5569 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
5570                                         struct edid *edid)
5571 {
5572         int i;
5573         bool edid_check_required;
5574         struct detailed_timing *timing;
5575         struct detailed_non_pixel *data;
5576         struct detailed_data_monitor_range *range;
5577         struct amdgpu_dm_connector *amdgpu_dm_connector =
5578                         to_amdgpu_dm_connector(connector);
5579         struct dm_connector_state *dm_con_state;
5580
5581         struct drm_device *dev = connector->dev;
5582         struct amdgpu_device *adev = dev->dev_private;
5583
5584         if (!connector->state) {
5585                 DRM_ERROR("%s - Connector has no state", __func__);
5586                 return;
5587         }
5588
5589         if (!edid) {
5590                 dm_con_state = to_dm_connector_state(connector->state);
5591
5592                 amdgpu_dm_connector->min_vfreq = 0;
5593                 amdgpu_dm_connector->max_vfreq = 0;
5594                 amdgpu_dm_connector->pixel_clock_mhz = 0;
5595
5596                 dm_con_state->freesync_capable = false;
5597                 dm_con_state->freesync_enable = false;
5598                 return;
5599         }
5600
5601         dm_con_state = to_dm_connector_state(connector->state);
5602
5603         edid_check_required = false;
5604         if (!amdgpu_dm_connector->dc_sink) {
5605                 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
5606                 return;
5607         }
5608         if (!adev->dm.freesync_module)
5609                 return;
5610         /*
5611          * if edid non zero restrict freesync only for dp and edp
5612          */
5613         if (edid) {
5614                 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
5615                         || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
5616                         edid_check_required = is_dp_capable_without_timing_msa(
5617                                                 adev->dm.dc,
5618                                                 amdgpu_dm_connector);
5619                 }
5620         }
5621         dm_con_state->freesync_capable = false;
5622         if (edid_check_required == true && (edid->version > 1 ||
5623            (edid->version == 1 && edid->revision > 1))) {
5624                 for (i = 0; i < 4; i++) {
5625
5626                         timing  = &edid->detailed_timings[i];
5627                         data    = &timing->data.other_data;
5628                         range   = &data->data.range;
5629                         /*
5630                          * Check if monitor has continuous frequency mode
5631                          */
5632                         if (data->type != EDID_DETAIL_MONITOR_RANGE)
5633                                 continue;
5634                         /*
5635                          * Check for flag range limits only. If flag == 1 then
5636                          * no additional timing information provided.
5637                          * Default GTF, GTF Secondary curve and CVT are not
5638                          * supported
5639                          */
5640                         if (range->flags != 1)
5641                                 continue;
5642
5643                         amdgpu_dm_connector->min_vfreq = range->min_vfreq;
5644                         amdgpu_dm_connector->max_vfreq = range->max_vfreq;
5645                         amdgpu_dm_connector->pixel_clock_mhz =
5646                                 range->pixel_clock_mhz * 10;
5647                         break;
5648                 }
5649
5650                 if (amdgpu_dm_connector->max_vfreq -
5651                     amdgpu_dm_connector->min_vfreq > 10) {
5652
5653                         dm_con_state->freesync_capable = true;
5654                 }
5655         }
5656 }
5657