2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/printk.h>
25 #include <linux/slab.h>
26 #include <linux/mm_types.h>
29 #include "kfd_mqd_manager.h"
30 #include "vi_structs.h"
31 #include "gca/gfx_8_0_sh_mask.h"
32 #include "gca/gfx_8_0_enum.h"
34 #define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8
36 static inline struct vi_mqd *get_mqd(void *mqd)
38 return (struct vi_mqd *)mqd;
41 static int init_mqd(struct mqd_manager *mm, void **mqd,
42 struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
43 struct queue_properties *q)
49 retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct vi_mqd),
54 m = (struct vi_mqd *) (*mqd_mem_obj)->cpu_ptr;
55 addr = (*mqd_mem_obj)->gpu_addr;
57 memset(m, 0, sizeof(struct vi_mqd));
59 m->header = 0xC0310800;
60 m->compute_pipelinestat_enable = 1;
61 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF;
62 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
63 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
64 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
66 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
67 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;
69 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT |
70 MTYPE_UC << CP_MQD_CONTROL__MTYPE__SHIFT;
72 m->cp_mqd_base_addr_lo = lower_32_bits(addr);
73 m->cp_mqd_base_addr_hi = upper_32_bits(addr);
75 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT |
76 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT |
77 10 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT;
79 m->cp_hqd_pipe_priority = 1;
80 m->cp_hqd_queue_priority = 15;
82 m->cp_hqd_eop_rptr = 1 << CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT;
84 if (q->format == KFD_QUEUE_FORMAT_AQL)
85 m->cp_hqd_iq_rptr = 1;
90 retval = mm->update_mqd(mm, m, q);
95 static int load_mqd(struct mqd_manager *mm, void *mqd,
96 uint32_t pipe_id, uint32_t queue_id,
97 struct queue_properties *p, struct mm_struct *mms)
99 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */
100 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);
101 uint32_t wptr_mask = (uint32_t)((p->queue_size / sizeof(uint32_t)) - 1);
103 return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id,
104 (uint32_t __user *)p->write_ptr,
105 wptr_shift, wptr_mask, mms);
108 static int __update_mqd(struct mqd_manager *mm, void *mqd,
109 struct queue_properties *q, unsigned int mtype,
110 unsigned int atc_bit)
116 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT |
117 atc_bit << CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT |
118 mtype << CP_HQD_PQ_CONTROL__MTYPE__SHIFT;
119 m->cp_hqd_pq_control |=
120 ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1;
121 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
123 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
124 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
126 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
127 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
129 m->cp_hqd_pq_doorbell_control =
131 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
132 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
133 m->cp_hqd_pq_doorbell_control);
135 m->cp_hqd_eop_control = atc_bit << CP_HQD_EOP_CONTROL__EOP_ATC__SHIFT |
136 mtype << CP_HQD_EOP_CONTROL__MTYPE__SHIFT;
138 m->cp_hqd_ib_control = atc_bit << CP_HQD_IB_CONTROL__IB_ATC__SHIFT |
139 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT |
140 mtype << CP_HQD_IB_CONTROL__MTYPE__SHIFT;
143 * HW does not clamp this field correctly. Maximum EOP queue size
144 * is constrained by per-SE EOP done signal count, which is 8-bit.
145 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit
146 * more than (EOP entry count - 1) so a queue size of 0x800 dwords
147 * is safe, giving a maximum field value of 0xA.
149 m->cp_hqd_eop_control |= min(0xA,
150 ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1);
151 m->cp_hqd_eop_base_addr_lo =
152 lower_32_bits(q->eop_ring_buffer_address >> 8);
153 m->cp_hqd_eop_base_addr_hi =
154 upper_32_bits(q->eop_ring_buffer_address >> 8);
156 m->cp_hqd_iq_timer = atc_bit << CP_HQD_IQ_TIMER__IQ_ATC__SHIFT |
157 mtype << CP_HQD_IQ_TIMER__MTYPE__SHIFT;
159 m->cp_hqd_vmid = q->vmid;
161 if (q->format == KFD_QUEUE_FORMAT_AQL) {
162 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK |
163 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT;
166 q->is_active = (q->queue_size > 0 &&
167 q->queue_address != 0 &&
168 q->queue_percent > 0);
174 static int update_mqd(struct mqd_manager *mm, void *mqd,
175 struct queue_properties *q)
177 return __update_mqd(mm, mqd, q, MTYPE_CC, 1);
180 static int destroy_mqd(struct mqd_manager *mm, void *mqd,
181 enum kfd_preempt_type type,
182 unsigned int timeout, uint32_t pipe_id,
185 return mm->dev->kfd2kgd->hqd_destroy
186 (mm->dev->kgd, mqd, type, timeout,
190 static void uninit_mqd(struct mqd_manager *mm, void *mqd,
191 struct kfd_mem_obj *mqd_mem_obj)
193 kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
196 static bool is_occupied(struct mqd_manager *mm, void *mqd,
197 uint64_t queue_address, uint32_t pipe_id,
200 return mm->dev->kfd2kgd->hqd_is_occupied(
201 mm->dev->kgd, queue_address,
205 static int init_mqd_hiq(struct mqd_manager *mm, void **mqd,
206 struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
207 struct queue_properties *q)
210 int retval = init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q);
217 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT |
218 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;
223 static int update_mqd_hiq(struct mqd_manager *mm, void *mqd,
224 struct queue_properties *q)
227 int retval = __update_mqd(mm, mqd, q, MTYPE_UC, 0);
233 m->cp_hqd_vmid = q->vmid;
237 struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
240 struct mqd_manager *mqd;
242 if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
245 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
252 case KFD_MQD_TYPE_CP:
253 case KFD_MQD_TYPE_COMPUTE:
254 mqd->init_mqd = init_mqd;
255 mqd->uninit_mqd = uninit_mqd;
256 mqd->load_mqd = load_mqd;
257 mqd->update_mqd = update_mqd;
258 mqd->destroy_mqd = destroy_mqd;
259 mqd->is_occupied = is_occupied;
261 case KFD_MQD_TYPE_HIQ:
262 mqd->init_mqd = init_mqd_hiq;
263 mqd->uninit_mqd = uninit_mqd;
264 mqd->load_mqd = load_mqd;
265 mqd->update_mqd = update_mqd_hiq;
266 mqd->destroy_mqd = destroy_mqd;
267 mqd->is_occupied = is_occupied;
269 case KFD_MQD_TYPE_SDMA: