2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/device.h>
24 #include <linux/export.h>
25 #include <linux/err.h>
27 #include <linux/file.h>
28 #include <linux/sched.h>
29 #include <linux/slab.h>
30 #include <linux/uaccess.h>
31 #include <linux/compat.h>
32 #include <uapi/linux/kfd_ioctl.h>
33 #include <linux/time.h>
35 #include <linux/mman.h>
36 #include <asm/processor.h>
38 #include "kfd_device_queue_manager.h"
39 #include "kfd_dbgmgr.h"
41 static long kfd_ioctl(struct file *, unsigned int, unsigned long);
42 static int kfd_open(struct inode *, struct file *);
43 static int kfd_mmap(struct file *, struct vm_area_struct *);
45 static const char kfd_dev_name[] = "kfd";
47 static const struct file_operations kfd_fops = {
49 .unlocked_ioctl = kfd_ioctl,
50 .compat_ioctl = kfd_ioctl,
55 static int kfd_char_dev_major = -1;
56 static struct class *kfd_class;
57 struct device *kfd_device;
59 int kfd_chardev_init(void)
63 kfd_char_dev_major = register_chrdev(0, kfd_dev_name, &kfd_fops);
64 err = kfd_char_dev_major;
66 goto err_register_chrdev;
68 kfd_class = class_create(THIS_MODULE, kfd_dev_name);
69 err = PTR_ERR(kfd_class);
70 if (IS_ERR(kfd_class))
71 goto err_class_create;
73 kfd_device = device_create(kfd_class, NULL,
74 MKDEV(kfd_char_dev_major, 0),
76 err = PTR_ERR(kfd_device);
77 if (IS_ERR(kfd_device))
78 goto err_device_create;
83 class_destroy(kfd_class);
85 unregister_chrdev(kfd_char_dev_major, kfd_dev_name);
90 void kfd_chardev_exit(void)
92 device_destroy(kfd_class, MKDEV(kfd_char_dev_major, 0));
93 class_destroy(kfd_class);
94 unregister_chrdev(kfd_char_dev_major, kfd_dev_name);
97 struct device *kfd_chardev(void)
103 static int kfd_open(struct inode *inode, struct file *filep)
105 struct kfd_process *process;
106 bool is_32bit_user_mode;
108 if (iminor(inode) != 0)
111 is_32bit_user_mode = in_compat_syscall();
113 if (is_32bit_user_mode) {
115 "Process %d (32-bit) failed to open /dev/kfd\n"
116 "32-bit processes are not supported by amdkfd\n",
121 process = kfd_create_process(filep);
123 return PTR_ERR(process);
125 dev_dbg(kfd_device, "process %d opened, compat mode (32 bit) - %d\n",
126 process->pasid, process->is_32bit_user_mode);
131 static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p,
134 struct kfd_ioctl_get_version_args *args = data;
136 args->major_version = KFD_IOCTL_MAJOR_VERSION;
137 args->minor_version = KFD_IOCTL_MINOR_VERSION;
142 static int set_queue_properties_from_user(struct queue_properties *q_properties,
143 struct kfd_ioctl_create_queue_args *args)
145 if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) {
146 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
150 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
151 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n");
155 if ((args->ring_base_address) &&
156 (!access_ok(VERIFY_WRITE,
157 (const void __user *) args->ring_base_address,
158 sizeof(uint64_t)))) {
159 pr_err("Can't access ring base address\n");
163 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
164 pr_err("Ring size must be a power of 2 or 0\n");
168 if (!access_ok(VERIFY_WRITE,
169 (const void __user *) args->read_pointer_address,
171 pr_err("Can't access read pointer\n");
175 if (!access_ok(VERIFY_WRITE,
176 (const void __user *) args->write_pointer_address,
178 pr_err("Can't access write pointer\n");
182 if (args->eop_buffer_address &&
183 !access_ok(VERIFY_WRITE,
184 (const void __user *) args->eop_buffer_address,
186 pr_debug("Can't access eop buffer");
190 if (args->ctx_save_restore_address &&
191 !access_ok(VERIFY_WRITE,
192 (const void __user *) args->ctx_save_restore_address,
194 pr_debug("Can't access ctx save restore buffer");
198 q_properties->is_interop = false;
199 q_properties->queue_percent = args->queue_percentage;
200 q_properties->priority = args->queue_priority;
201 q_properties->queue_address = args->ring_base_address;
202 q_properties->queue_size = args->ring_size;
203 q_properties->read_ptr = (uint32_t *) args->read_pointer_address;
204 q_properties->write_ptr = (uint32_t *) args->write_pointer_address;
205 q_properties->eop_ring_buffer_address = args->eop_buffer_address;
206 q_properties->eop_ring_buffer_size = args->eop_buffer_size;
207 q_properties->ctx_save_restore_area_address =
208 args->ctx_save_restore_address;
209 q_properties->ctx_save_restore_area_size = args->ctx_save_restore_size;
210 q_properties->ctl_stack_size = args->ctl_stack_size;
211 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE ||
212 args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
213 q_properties->type = KFD_QUEUE_TYPE_COMPUTE;
214 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA)
215 q_properties->type = KFD_QUEUE_TYPE_SDMA;
219 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
220 q_properties->format = KFD_QUEUE_FORMAT_AQL;
222 q_properties->format = KFD_QUEUE_FORMAT_PM4;
224 pr_debug("Queue Percentage: %d, %d\n",
225 q_properties->queue_percent, args->queue_percentage);
227 pr_debug("Queue Priority: %d, %d\n",
228 q_properties->priority, args->queue_priority);
230 pr_debug("Queue Address: 0x%llX, 0x%llX\n",
231 q_properties->queue_address, args->ring_base_address);
233 pr_debug("Queue Size: 0x%llX, %u\n",
234 q_properties->queue_size, args->ring_size);
236 pr_debug("Queue r/w Pointers: %p, %p\n",
237 q_properties->read_ptr,
238 q_properties->write_ptr);
240 pr_debug("Queue Format: %d\n", q_properties->format);
242 pr_debug("Queue EOP: 0x%llX\n", q_properties->eop_ring_buffer_address);
244 pr_debug("Queue CTX save area: 0x%llX\n",
245 q_properties->ctx_save_restore_area_address);
250 static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
253 struct kfd_ioctl_create_queue_args *args = data;
256 unsigned int queue_id;
257 struct kfd_process_device *pdd;
258 struct queue_properties q_properties;
260 memset(&q_properties, 0, sizeof(struct queue_properties));
262 pr_debug("Creating queue ioctl\n");
264 err = set_queue_properties_from_user(&q_properties, args);
268 pr_debug("Looking for gpu id 0x%x\n", args->gpu_id);
269 dev = kfd_device_by_id(args->gpu_id);
271 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id);
275 mutex_lock(&p->mutex);
277 pdd = kfd_bind_process_to_device(dev, p);
280 goto err_bind_process;
283 pr_debug("Creating queue for PASID %d on gpu 0x%x\n",
287 err = pqm_create_queue(&p->pqm, dev, filep, &q_properties, &queue_id);
289 goto err_create_queue;
291 args->queue_id = queue_id;
294 /* Return gpu_id as doorbell offset for mmap usage */
295 args->doorbell_offset = (KFD_MMAP_DOORBELL_MASK | args->gpu_id);
296 args->doorbell_offset <<= PAGE_SHIFT;
298 mutex_unlock(&p->mutex);
300 pr_debug("Queue id %d was created successfully\n", args->queue_id);
302 pr_debug("Ring buffer address == 0x%016llX\n",
303 args->ring_base_address);
305 pr_debug("Read ptr address == 0x%016llX\n",
306 args->read_pointer_address);
308 pr_debug("Write ptr address == 0x%016llX\n",
309 args->write_pointer_address);
315 mutex_unlock(&p->mutex);
319 static int kfd_ioctl_destroy_queue(struct file *filp, struct kfd_process *p,
323 struct kfd_ioctl_destroy_queue_args *args = data;
325 pr_debug("Destroying queue id %d for pasid %d\n",
329 mutex_lock(&p->mutex);
331 retval = pqm_destroy_queue(&p->pqm, args->queue_id);
333 mutex_unlock(&p->mutex);
337 static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p,
341 struct kfd_ioctl_update_queue_args *args = data;
342 struct queue_properties properties;
344 if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) {
345 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
349 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
350 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n");
354 if ((args->ring_base_address) &&
355 (!access_ok(VERIFY_WRITE,
356 (const void __user *) args->ring_base_address,
357 sizeof(uint64_t)))) {
358 pr_err("Can't access ring base address\n");
362 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
363 pr_err("Ring size must be a power of 2 or 0\n");
367 properties.queue_address = args->ring_base_address;
368 properties.queue_size = args->ring_size;
369 properties.queue_percent = args->queue_percentage;
370 properties.priority = args->queue_priority;
372 pr_debug("Updating queue id %d for pasid %d\n",
373 args->queue_id, p->pasid);
375 mutex_lock(&p->mutex);
377 retval = pqm_update_queue(&p->pqm, args->queue_id, &properties);
379 mutex_unlock(&p->mutex);
384 static int kfd_ioctl_set_memory_policy(struct file *filep,
385 struct kfd_process *p, void *data)
387 struct kfd_ioctl_set_memory_policy_args *args = data;
390 struct kfd_process_device *pdd;
391 enum cache_policy default_policy, alternate_policy;
393 if (args->default_policy != KFD_IOC_CACHE_POLICY_COHERENT
394 && args->default_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
398 if (args->alternate_policy != KFD_IOC_CACHE_POLICY_COHERENT
399 && args->alternate_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
403 dev = kfd_device_by_id(args->gpu_id);
407 mutex_lock(&p->mutex);
409 pdd = kfd_bind_process_to_device(dev, p);
415 default_policy = (args->default_policy == KFD_IOC_CACHE_POLICY_COHERENT)
416 ? cache_policy_coherent : cache_policy_noncoherent;
419 (args->alternate_policy == KFD_IOC_CACHE_POLICY_COHERENT)
420 ? cache_policy_coherent : cache_policy_noncoherent;
422 if (!dev->dqm->ops.set_cache_memory_policy(dev->dqm,
426 (void __user *)args->alternate_aperture_base,
427 args->alternate_aperture_size))
431 mutex_unlock(&p->mutex);
436 static int kfd_ioctl_set_trap_handler(struct file *filep,
437 struct kfd_process *p, void *data)
439 struct kfd_ioctl_set_trap_handler_args *args = data;
442 struct kfd_process_device *pdd;
444 dev = kfd_device_by_id(args->gpu_id);
448 mutex_lock(&p->mutex);
450 pdd = kfd_bind_process_to_device(dev, p);
456 if (dev->dqm->ops.set_trap_handler(dev->dqm,
463 mutex_unlock(&p->mutex);
468 static int kfd_ioctl_dbg_register(struct file *filep,
469 struct kfd_process *p, void *data)
471 struct kfd_ioctl_dbg_register_args *args = data;
473 struct kfd_dbgmgr *dbgmgr_ptr;
474 struct kfd_process_device *pdd;
478 dev = kfd_device_by_id(args->gpu_id);
482 if (dev->device_info->asic_family == CHIP_CARRIZO) {
483 pr_debug("kfd_ioctl_dbg_register not supported on CZ\n");
487 mutex_lock(&p->mutex);
488 mutex_lock(kfd_get_dbgmgr_mutex());
491 * make sure that we have pdd, if this the first queue created for
494 pdd = kfd_bind_process_to_device(dev, p);
496 status = PTR_ERR(pdd);
501 /* In case of a legal call, we have no dbgmgr yet */
502 create_ok = kfd_dbgmgr_create(&dbgmgr_ptr, dev);
504 status = kfd_dbgmgr_register(dbgmgr_ptr, p);
506 kfd_dbgmgr_destroy(dbgmgr_ptr);
508 dev->dbgmgr = dbgmgr_ptr;
511 pr_debug("debugger already registered\n");
516 mutex_unlock(kfd_get_dbgmgr_mutex());
517 mutex_unlock(&p->mutex);
522 static int kfd_ioctl_dbg_unregister(struct file *filep,
523 struct kfd_process *p, void *data)
525 struct kfd_ioctl_dbg_unregister_args *args = data;
529 dev = kfd_device_by_id(args->gpu_id);
530 if (!dev || !dev->dbgmgr)
533 if (dev->device_info->asic_family == CHIP_CARRIZO) {
534 pr_debug("kfd_ioctl_dbg_unregister not supported on CZ\n");
538 mutex_lock(kfd_get_dbgmgr_mutex());
540 status = kfd_dbgmgr_unregister(dev->dbgmgr, p);
542 kfd_dbgmgr_destroy(dev->dbgmgr);
546 mutex_unlock(kfd_get_dbgmgr_mutex());
552 * Parse and generate variable size data structure for address watch.
553 * Total size of the buffer and # watch points is limited in order
554 * to prevent kernel abuse. (no bearing to the much smaller HW limitation
555 * which is enforced by dbgdev module)
556 * please also note that the watch address itself are not "copied from user",
557 * since it be set into the HW in user mode values.
560 static int kfd_ioctl_dbg_address_watch(struct file *filep,
561 struct kfd_process *p, void *data)
563 struct kfd_ioctl_dbg_address_watch_args *args = data;
565 struct dbg_address_watch_info aw_info;
566 unsigned char *args_buff;
568 void __user *cmd_from_user;
569 uint64_t watch_mask_value = 0;
570 unsigned int args_idx = 0;
572 memset((void *) &aw_info, 0, sizeof(struct dbg_address_watch_info));
574 dev = kfd_device_by_id(args->gpu_id);
578 if (dev->device_info->asic_family == CHIP_CARRIZO) {
579 pr_debug("kfd_ioctl_dbg_wave_control not supported on CZ\n");
583 cmd_from_user = (void __user *) args->content_ptr;
585 /* Validate arguments */
587 if ((args->buf_size_in_bytes > MAX_ALLOWED_AW_BUFF_SIZE) ||
588 (args->buf_size_in_bytes <= sizeof(*args) + sizeof(int) * 2) ||
589 (cmd_from_user == NULL))
592 /* this is the actual buffer to work with */
593 args_buff = memdup_user(cmd_from_user,
594 args->buf_size_in_bytes - sizeof(*args));
595 if (IS_ERR(args_buff))
596 return PTR_ERR(args_buff);
600 aw_info.num_watch_points = *((uint32_t *)(&args_buff[args_idx]));
601 args_idx += sizeof(aw_info.num_watch_points);
603 aw_info.watch_mode = (enum HSA_DBG_WATCH_MODE *) &args_buff[args_idx];
604 args_idx += sizeof(enum HSA_DBG_WATCH_MODE) * aw_info.num_watch_points;
607 * set watch address base pointer to point on the array base
610 aw_info.watch_address = (uint64_t *) &args_buff[args_idx];
612 /* skip over the addresses buffer */
613 args_idx += sizeof(aw_info.watch_address) * aw_info.num_watch_points;
615 if (args_idx >= args->buf_size_in_bytes - sizeof(*args)) {
620 watch_mask_value = (uint64_t) args_buff[args_idx];
622 if (watch_mask_value > 0) {
624 * There is an array of masks.
625 * set watch mask base pointer to point on the array base
628 aw_info.watch_mask = (uint64_t *) &args_buff[args_idx];
630 /* skip over the masks buffer */
631 args_idx += sizeof(aw_info.watch_mask) *
632 aw_info.num_watch_points;
634 /* just the NULL mask, set to NULL and skip over it */
635 aw_info.watch_mask = NULL;
636 args_idx += sizeof(aw_info.watch_mask);
639 if (args_idx >= args->buf_size_in_bytes - sizeof(args)) {
644 /* Currently HSA Event is not supported for DBG */
645 aw_info.watch_event = NULL;
647 mutex_lock(kfd_get_dbgmgr_mutex());
649 status = kfd_dbgmgr_address_watch(dev->dbgmgr, &aw_info);
651 mutex_unlock(kfd_get_dbgmgr_mutex());
659 /* Parse and generate fixed size data structure for wave control */
660 static int kfd_ioctl_dbg_wave_control(struct file *filep,
661 struct kfd_process *p, void *data)
663 struct kfd_ioctl_dbg_wave_control_args *args = data;
665 struct dbg_wave_control_info wac_info;
666 unsigned char *args_buff;
667 uint32_t computed_buff_size;
669 void __user *cmd_from_user;
670 unsigned int args_idx = 0;
672 memset((void *) &wac_info, 0, sizeof(struct dbg_wave_control_info));
674 /* we use compact form, independent of the packing attribute value */
675 computed_buff_size = sizeof(*args) +
676 sizeof(wac_info.mode) +
677 sizeof(wac_info.operand) +
678 sizeof(wac_info.dbgWave_msg.DbgWaveMsg) +
679 sizeof(wac_info.dbgWave_msg.MemoryVA) +
680 sizeof(wac_info.trapId);
682 dev = kfd_device_by_id(args->gpu_id);
686 if (dev->device_info->asic_family == CHIP_CARRIZO) {
687 pr_debug("kfd_ioctl_dbg_wave_control not supported on CZ\n");
691 /* input size must match the computed "compact" size */
692 if (args->buf_size_in_bytes != computed_buff_size) {
693 pr_debug("size mismatch, computed : actual %u : %u\n",
694 args->buf_size_in_bytes, computed_buff_size);
698 cmd_from_user = (void __user *) args->content_ptr;
700 if (cmd_from_user == NULL)
703 /* copy the entire buffer from user */
705 args_buff = memdup_user(cmd_from_user,
706 args->buf_size_in_bytes - sizeof(*args));
707 if (IS_ERR(args_buff))
708 return PTR_ERR(args_buff);
710 /* move ptr to the start of the "pay-load" area */
711 wac_info.process = p;
713 wac_info.operand = *((enum HSA_DBG_WAVEOP *)(&args_buff[args_idx]));
714 args_idx += sizeof(wac_info.operand);
716 wac_info.mode = *((enum HSA_DBG_WAVEMODE *)(&args_buff[args_idx]));
717 args_idx += sizeof(wac_info.mode);
719 wac_info.trapId = *((uint32_t *)(&args_buff[args_idx]));
720 args_idx += sizeof(wac_info.trapId);
722 wac_info.dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value =
723 *((uint32_t *)(&args_buff[args_idx]));
724 wac_info.dbgWave_msg.MemoryVA = NULL;
726 mutex_lock(kfd_get_dbgmgr_mutex());
728 pr_debug("Calling dbg manager process %p, operand %u, mode %u, trapId %u, message %u\n",
729 wac_info.process, wac_info.operand,
730 wac_info.mode, wac_info.trapId,
731 wac_info.dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value);
733 status = kfd_dbgmgr_wave_control(dev->dbgmgr, &wac_info);
735 pr_debug("Returned status of dbg manager is %ld\n", status);
737 mutex_unlock(kfd_get_dbgmgr_mutex());
744 static int kfd_ioctl_get_clock_counters(struct file *filep,
745 struct kfd_process *p, void *data)
747 struct kfd_ioctl_get_clock_counters_args *args = data;
749 struct timespec64 time;
751 dev = kfd_device_by_id(args->gpu_id);
755 /* Reading GPU clock counter from KGD */
756 args->gpu_clock_counter =
757 dev->kfd2kgd->get_gpu_clock_counter(dev->kgd);
759 /* No access to rdtsc. Using raw monotonic time */
760 getrawmonotonic64(&time);
761 args->cpu_clock_counter = (uint64_t)timespec64_to_ns(&time);
763 get_monotonic_boottime64(&time);
764 args->system_clock_counter = (uint64_t)timespec64_to_ns(&time);
766 /* Since the counter is in nano-seconds we use 1GHz frequency */
767 args->system_clock_freq = 1000000000;
773 static int kfd_ioctl_get_process_apertures(struct file *filp,
774 struct kfd_process *p, void *data)
776 struct kfd_ioctl_get_process_apertures_args *args = data;
777 struct kfd_process_device_apertures *pAperture;
778 struct kfd_process_device *pdd;
780 dev_dbg(kfd_device, "get apertures for PASID %d", p->pasid);
782 args->num_of_nodes = 0;
784 mutex_lock(&p->mutex);
786 /*if the process-device list isn't empty*/
787 if (kfd_has_process_device_data(p)) {
788 /* Run over all pdd of the process */
789 pdd = kfd_get_first_process_device_data(p);
792 &args->process_apertures[args->num_of_nodes];
793 pAperture->gpu_id = pdd->dev->id;
794 pAperture->lds_base = pdd->lds_base;
795 pAperture->lds_limit = pdd->lds_limit;
796 pAperture->gpuvm_base = pdd->gpuvm_base;
797 pAperture->gpuvm_limit = pdd->gpuvm_limit;
798 pAperture->scratch_base = pdd->scratch_base;
799 pAperture->scratch_limit = pdd->scratch_limit;
802 "node id %u\n", args->num_of_nodes);
804 "gpu id %u\n", pdd->dev->id);
806 "lds_base %llX\n", pdd->lds_base);
808 "lds_limit %llX\n", pdd->lds_limit);
810 "gpuvm_base %llX\n", pdd->gpuvm_base);
812 "gpuvm_limit %llX\n", pdd->gpuvm_limit);
814 "scratch_base %llX\n", pdd->scratch_base);
816 "scratch_limit %llX\n", pdd->scratch_limit);
818 args->num_of_nodes++;
820 pdd = kfd_get_next_process_device_data(p, pdd);
821 } while (pdd && (args->num_of_nodes < NUM_OF_SUPPORTED_GPUS));
824 mutex_unlock(&p->mutex);
829 static int kfd_ioctl_get_process_apertures_new(struct file *filp,
830 struct kfd_process *p, void *data)
832 struct kfd_ioctl_get_process_apertures_new_args *args = data;
833 struct kfd_process_device_apertures *pa;
834 struct kfd_process_device *pdd;
838 dev_dbg(kfd_device, "get apertures for PASID %d", p->pasid);
840 if (args->num_of_nodes == 0) {
841 /* Return number of nodes, so that user space can alloacate
844 mutex_lock(&p->mutex);
846 if (!kfd_has_process_device_data(p))
849 /* Run over all pdd of the process */
850 pdd = kfd_get_first_process_device_data(p);
852 args->num_of_nodes++;
853 pdd = kfd_get_next_process_device_data(p, pdd);
859 /* Fill in process-aperture information for all available
860 * nodes, but not more than args->num_of_nodes as that is
861 * the amount of memory allocated by user
863 pa = kzalloc((sizeof(struct kfd_process_device_apertures) *
864 args->num_of_nodes), GFP_KERNEL);
868 mutex_lock(&p->mutex);
870 if (!kfd_has_process_device_data(p)) {
871 args->num_of_nodes = 0;
876 /* Run over all pdd of the process */
877 pdd = kfd_get_first_process_device_data(p);
879 pa[nodes].gpu_id = pdd->dev->id;
880 pa[nodes].lds_base = pdd->lds_base;
881 pa[nodes].lds_limit = pdd->lds_limit;
882 pa[nodes].gpuvm_base = pdd->gpuvm_base;
883 pa[nodes].gpuvm_limit = pdd->gpuvm_limit;
884 pa[nodes].scratch_base = pdd->scratch_base;
885 pa[nodes].scratch_limit = pdd->scratch_limit;
888 "gpu id %u\n", pdd->dev->id);
890 "lds_base %llX\n", pdd->lds_base);
892 "lds_limit %llX\n", pdd->lds_limit);
894 "gpuvm_base %llX\n", pdd->gpuvm_base);
896 "gpuvm_limit %llX\n", pdd->gpuvm_limit);
898 "scratch_base %llX\n", pdd->scratch_base);
900 "scratch_limit %llX\n", pdd->scratch_limit);
903 pdd = kfd_get_next_process_device_data(p, pdd);
904 } while (pdd && (nodes < args->num_of_nodes));
905 mutex_unlock(&p->mutex);
907 args->num_of_nodes = nodes;
909 (void __user *)args->kfd_process_device_apertures_ptr,
911 (nodes * sizeof(struct kfd_process_device_apertures)));
913 return ret ? -EFAULT : 0;
916 mutex_unlock(&p->mutex);
920 static int kfd_ioctl_create_event(struct file *filp, struct kfd_process *p,
923 struct kfd_ioctl_create_event_args *args = data;
926 /* For dGPUs the event page is allocated in user mode. The
927 * handle is passed to KFD with the first call to this IOCTL
928 * through the event_page_offset field.
930 if (args->event_page_offset) {
932 struct kfd_process_device *pdd;
933 void *mem, *kern_addr;
936 if (p->signal_page) {
937 pr_err("Event page is already set\n");
941 kfd = kfd_device_by_id(GET_GPU_ID(args->event_page_offset));
943 pr_err("Getting device by id failed in %s\n", __func__);
947 mutex_lock(&p->mutex);
948 pdd = kfd_bind_process_to_device(kfd, p);
954 mem = kfd_process_device_translate_handle(pdd,
955 GET_IDR_HANDLE(args->event_page_offset));
957 pr_err("Can't find BO, offset is 0x%llx\n",
958 args->event_page_offset);
962 mutex_unlock(&p->mutex);
964 err = kfd->kfd2kgd->map_gtt_bo_to_kernel(kfd->kgd,
965 mem, &kern_addr, &size);
967 pr_err("Failed to map event page to kernel\n");
971 err = kfd_event_page_set(p, kern_addr, size);
973 pr_err("Failed to set event page\n");
978 err = kfd_event_create(filp, p, args->event_type,
979 args->auto_reset != 0, args->node_id,
980 &args->event_id, &args->event_trigger_data,
981 &args->event_page_offset,
982 &args->event_slot_index);
987 mutex_unlock(&p->mutex);
991 static int kfd_ioctl_destroy_event(struct file *filp, struct kfd_process *p,
994 struct kfd_ioctl_destroy_event_args *args = data;
996 return kfd_event_destroy(p, args->event_id);
999 static int kfd_ioctl_set_event(struct file *filp, struct kfd_process *p,
1002 struct kfd_ioctl_set_event_args *args = data;
1004 return kfd_set_event(p, args->event_id);
1007 static int kfd_ioctl_reset_event(struct file *filp, struct kfd_process *p,
1010 struct kfd_ioctl_reset_event_args *args = data;
1012 return kfd_reset_event(p, args->event_id);
1015 static int kfd_ioctl_wait_events(struct file *filp, struct kfd_process *p,
1018 struct kfd_ioctl_wait_events_args *args = data;
1021 err = kfd_wait_on_events(p, args->num_events,
1022 (void __user *)args->events_ptr,
1023 (args->wait_for_all != 0),
1024 args->timeout, &args->wait_result);
1028 static int kfd_ioctl_set_scratch_backing_va(struct file *filep,
1029 struct kfd_process *p, void *data)
1031 struct kfd_ioctl_set_scratch_backing_va_args *args = data;
1032 struct kfd_process_device *pdd;
1033 struct kfd_dev *dev;
1036 dev = kfd_device_by_id(args->gpu_id);
1040 mutex_lock(&p->mutex);
1042 pdd = kfd_bind_process_to_device(dev, p);
1045 goto bind_process_to_device_fail;
1048 pdd->qpd.sh_hidden_private_base = args->va_addr;
1050 mutex_unlock(&p->mutex);
1052 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS &&
1054 dev->kfd2kgd->set_scratch_backing_va(
1055 dev->kgd, args->va_addr, pdd->qpd.vmid);
1059 bind_process_to_device_fail:
1060 mutex_unlock(&p->mutex);
1064 static int kfd_ioctl_get_tile_config(struct file *filep,
1065 struct kfd_process *p, void *data)
1067 struct kfd_ioctl_get_tile_config_args *args = data;
1068 struct kfd_dev *dev;
1069 struct tile_config config;
1072 dev = kfd_device_by_id(args->gpu_id);
1076 dev->kfd2kgd->get_tile_config(dev->kgd, &config);
1078 args->gb_addr_config = config.gb_addr_config;
1079 args->num_banks = config.num_banks;
1080 args->num_ranks = config.num_ranks;
1082 if (args->num_tile_configs > config.num_tile_configs)
1083 args->num_tile_configs = config.num_tile_configs;
1084 err = copy_to_user((void __user *)args->tile_config_ptr,
1085 config.tile_config_ptr,
1086 args->num_tile_configs * sizeof(uint32_t));
1088 args->num_tile_configs = 0;
1092 if (args->num_macro_tile_configs > config.num_macro_tile_configs)
1093 args->num_macro_tile_configs =
1094 config.num_macro_tile_configs;
1095 err = copy_to_user((void __user *)args->macro_tile_config_ptr,
1096 config.macro_tile_config_ptr,
1097 args->num_macro_tile_configs * sizeof(uint32_t));
1099 args->num_macro_tile_configs = 0;
1106 static int kfd_ioctl_acquire_vm(struct file *filep, struct kfd_process *p,
1109 struct kfd_ioctl_acquire_vm_args *args = data;
1110 struct kfd_process_device *pdd;
1111 struct kfd_dev *dev;
1112 struct file *drm_file;
1115 dev = kfd_device_by_id(args->gpu_id);
1119 drm_file = fget(args->drm_fd);
1123 mutex_lock(&p->mutex);
1125 pdd = kfd_get_process_device_data(dev, p);
1131 if (pdd->drm_file) {
1132 ret = pdd->drm_file == drm_file ? 0 : -EBUSY;
1136 ret = kfd_process_device_init_vm(pdd, drm_file);
1139 /* On success, the PDD keeps the drm_file reference */
1140 mutex_unlock(&p->mutex);
1145 mutex_unlock(&p->mutex);
1150 bool kfd_dev_is_large_bar(struct kfd_dev *dev)
1152 struct kfd_local_mem_info mem_info;
1154 if (debug_largebar) {
1155 pr_debug("Simulate large-bar allocation on non large-bar machine\n");
1159 if (dev->device_info->needs_iommu_device)
1162 dev->kfd2kgd->get_local_mem_info(dev->kgd, &mem_info);
1163 if (mem_info.local_mem_size_private == 0 &&
1164 mem_info.local_mem_size_public > 0)
1169 static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep,
1170 struct kfd_process *p, void *data)
1172 struct kfd_ioctl_alloc_memory_of_gpu_args *args = data;
1173 struct kfd_process_device *pdd;
1175 struct kfd_dev *dev;
1178 uint64_t offset = args->mmap_offset;
1179 uint32_t flags = args->flags;
1181 if (args->size == 0)
1184 dev = kfd_device_by_id(args->gpu_id);
1188 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) &&
1189 (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) &&
1190 !kfd_dev_is_large_bar(dev)) {
1191 pr_err("Alloc host visible vram on small bar is not allowed\n");
1195 mutex_lock(&p->mutex);
1197 pdd = kfd_bind_process_to_device(dev, p);
1203 err = dev->kfd2kgd->alloc_memory_of_gpu(
1204 dev->kgd, args->va_addr, args->size,
1205 pdd->vm, (struct kgd_mem **) &mem, &offset,
1211 idr_handle = kfd_process_device_create_obj_handle(pdd, mem);
1212 if (idr_handle < 0) {
1217 mutex_unlock(&p->mutex);
1219 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle);
1220 args->mmap_offset = offset;
1225 dev->kfd2kgd->free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem);
1227 mutex_unlock(&p->mutex);
1231 static int kfd_ioctl_free_memory_of_gpu(struct file *filep,
1232 struct kfd_process *p, void *data)
1234 struct kfd_ioctl_free_memory_of_gpu_args *args = data;
1235 struct kfd_process_device *pdd;
1237 struct kfd_dev *dev;
1240 dev = kfd_device_by_id(GET_GPU_ID(args->handle));
1244 mutex_lock(&p->mutex);
1246 pdd = kfd_get_process_device_data(dev, p);
1248 pr_err("Process device data doesn't exist\n");
1253 mem = kfd_process_device_translate_handle(
1254 pdd, GET_IDR_HANDLE(args->handle));
1260 ret = dev->kfd2kgd->free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem);
1262 /* If freeing the buffer failed, leave the handle in place for
1263 * clean-up during process tear-down.
1266 kfd_process_device_remove_obj_handle(
1267 pdd, GET_IDR_HANDLE(args->handle));
1270 mutex_unlock(&p->mutex);
1274 static int kfd_ioctl_map_memory_to_gpu(struct file *filep,
1275 struct kfd_process *p, void *data)
1277 struct kfd_ioctl_map_memory_to_gpu_args *args = data;
1278 struct kfd_process_device *pdd, *peer_pdd;
1280 struct kfd_dev *dev, *peer;
1283 uint32_t *devices_arr = NULL;
1285 dev = kfd_device_by_id(GET_GPU_ID(args->handle));
1289 if (!args->n_devices) {
1290 pr_debug("Device IDs array empty\n");
1293 if (args->n_success > args->n_devices) {
1294 pr_debug("n_success exceeds n_devices\n");
1298 devices_arr = kmalloc(args->n_devices * sizeof(*devices_arr),
1303 err = copy_from_user(devices_arr,
1304 (void __user *)args->device_ids_array_ptr,
1305 args->n_devices * sizeof(*devices_arr));
1308 goto copy_from_user_failed;
1311 mutex_lock(&p->mutex);
1313 pdd = kfd_bind_process_to_device(dev, p);
1316 goto bind_process_to_device_failed;
1319 mem = kfd_process_device_translate_handle(pdd,
1320 GET_IDR_HANDLE(args->handle));
1323 goto get_mem_obj_from_handle_failed;
1326 for (i = args->n_success; i < args->n_devices; i++) {
1327 peer = kfd_device_by_id(devices_arr[i]);
1329 pr_debug("Getting device by id failed for 0x%x\n",
1332 goto get_mem_obj_from_handle_failed;
1335 peer_pdd = kfd_bind_process_to_device(peer, p);
1336 if (IS_ERR(peer_pdd)) {
1337 err = PTR_ERR(peer_pdd);
1338 goto get_mem_obj_from_handle_failed;
1340 err = peer->kfd2kgd->map_memory_to_gpu(
1341 peer->kgd, (struct kgd_mem *)mem, peer_pdd->vm);
1343 pr_err("Failed to map to gpu %d/%d\n",
1344 i, args->n_devices);
1345 goto map_memory_to_gpu_failed;
1347 args->n_success = i+1;
1350 mutex_unlock(&p->mutex);
1352 err = dev->kfd2kgd->sync_memory(dev->kgd, (struct kgd_mem *) mem, true);
1354 pr_debug("Sync memory failed, wait interrupted by user signal\n");
1355 goto sync_memory_failed;
1358 /* Flush TLBs after waiting for the page table updates to complete */
1359 for (i = 0; i < args->n_devices; i++) {
1360 peer = kfd_device_by_id(devices_arr[i]);
1361 if (WARN_ON_ONCE(!peer))
1363 peer_pdd = kfd_get_process_device_data(peer, p);
1364 if (WARN_ON_ONCE(!peer_pdd))
1366 kfd_flush_tlb(peer_pdd);
1373 bind_process_to_device_failed:
1374 get_mem_obj_from_handle_failed:
1375 map_memory_to_gpu_failed:
1376 mutex_unlock(&p->mutex);
1377 copy_from_user_failed:
1384 static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep,
1385 struct kfd_process *p, void *data)
1387 struct kfd_ioctl_unmap_memory_from_gpu_args *args = data;
1388 struct kfd_process_device *pdd, *peer_pdd;
1390 struct kfd_dev *dev, *peer;
1392 uint32_t *devices_arr = NULL, i;
1394 dev = kfd_device_by_id(GET_GPU_ID(args->handle));
1398 if (!args->n_devices) {
1399 pr_debug("Device IDs array empty\n");
1402 if (args->n_success > args->n_devices) {
1403 pr_debug("n_success exceeds n_devices\n");
1407 devices_arr = kmalloc(args->n_devices * sizeof(*devices_arr),
1412 err = copy_from_user(devices_arr,
1413 (void __user *)args->device_ids_array_ptr,
1414 args->n_devices * sizeof(*devices_arr));
1417 goto copy_from_user_failed;
1420 mutex_lock(&p->mutex);
1422 pdd = kfd_get_process_device_data(dev, p);
1425 goto bind_process_to_device_failed;
1428 mem = kfd_process_device_translate_handle(pdd,
1429 GET_IDR_HANDLE(args->handle));
1432 goto get_mem_obj_from_handle_failed;
1435 for (i = args->n_success; i < args->n_devices; i++) {
1436 peer = kfd_device_by_id(devices_arr[i]);
1439 goto get_mem_obj_from_handle_failed;
1442 peer_pdd = kfd_get_process_device_data(peer, p);
1445 goto get_mem_obj_from_handle_failed;
1447 err = dev->kfd2kgd->unmap_memory_to_gpu(
1448 peer->kgd, (struct kgd_mem *)mem, peer_pdd->vm);
1450 pr_err("Failed to unmap from gpu %d/%d\n",
1451 i, args->n_devices);
1452 goto unmap_memory_from_gpu_failed;
1454 args->n_success = i+1;
1458 mutex_unlock(&p->mutex);
1462 bind_process_to_device_failed:
1463 get_mem_obj_from_handle_failed:
1464 unmap_memory_from_gpu_failed:
1465 mutex_unlock(&p->mutex);
1466 copy_from_user_failed:
1471 #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \
1472 [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \
1473 .cmd_drv = 0, .name = #ioctl}
1476 static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = {
1477 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_VERSION,
1478 kfd_ioctl_get_version, 0),
1480 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_QUEUE,
1481 kfd_ioctl_create_queue, 0),
1483 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_QUEUE,
1484 kfd_ioctl_destroy_queue, 0),
1486 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_MEMORY_POLICY,
1487 kfd_ioctl_set_memory_policy, 0),
1489 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_CLOCK_COUNTERS,
1490 kfd_ioctl_get_clock_counters, 0),
1492 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES,
1493 kfd_ioctl_get_process_apertures, 0),
1495 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UPDATE_QUEUE,
1496 kfd_ioctl_update_queue, 0),
1498 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_EVENT,
1499 kfd_ioctl_create_event, 0),
1501 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_EVENT,
1502 kfd_ioctl_destroy_event, 0),
1504 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_EVENT,
1505 kfd_ioctl_set_event, 0),
1507 AMDKFD_IOCTL_DEF(AMDKFD_IOC_RESET_EVENT,
1508 kfd_ioctl_reset_event, 0),
1510 AMDKFD_IOCTL_DEF(AMDKFD_IOC_WAIT_EVENTS,
1511 kfd_ioctl_wait_events, 0),
1513 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_REGISTER,
1514 kfd_ioctl_dbg_register, 0),
1516 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_UNREGISTER,
1517 kfd_ioctl_dbg_unregister, 0),
1519 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_ADDRESS_WATCH,
1520 kfd_ioctl_dbg_address_watch, 0),
1522 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_WAVE_CONTROL,
1523 kfd_ioctl_dbg_wave_control, 0),
1525 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_SCRATCH_BACKING_VA,
1526 kfd_ioctl_set_scratch_backing_va, 0),
1528 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_TILE_CONFIG,
1529 kfd_ioctl_get_tile_config, 0),
1531 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_TRAP_HANDLER,
1532 kfd_ioctl_set_trap_handler, 0),
1534 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES_NEW,
1535 kfd_ioctl_get_process_apertures_new, 0),
1537 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ACQUIRE_VM,
1538 kfd_ioctl_acquire_vm, 0),
1540 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_MEMORY_OF_GPU,
1541 kfd_ioctl_alloc_memory_of_gpu, 0),
1543 AMDKFD_IOCTL_DEF(AMDKFD_IOC_FREE_MEMORY_OF_GPU,
1544 kfd_ioctl_free_memory_of_gpu, 0),
1546 AMDKFD_IOCTL_DEF(AMDKFD_IOC_MAP_MEMORY_TO_GPU,
1547 kfd_ioctl_map_memory_to_gpu, 0),
1549 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU,
1550 kfd_ioctl_unmap_memory_from_gpu, 0),
1554 #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls)
1556 static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
1558 struct kfd_process *process;
1559 amdkfd_ioctl_t *func;
1560 const struct amdkfd_ioctl_desc *ioctl = NULL;
1561 unsigned int nr = _IOC_NR(cmd);
1562 char stack_kdata[128];
1564 unsigned int usize, asize;
1565 int retcode = -EINVAL;
1567 if (nr >= AMDKFD_CORE_IOCTL_COUNT)
1570 if ((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) {
1573 ioctl = &amdkfd_ioctls[nr];
1575 amdkfd_size = _IOC_SIZE(ioctl->cmd);
1576 usize = asize = _IOC_SIZE(cmd);
1577 if (amdkfd_size > asize)
1578 asize = amdkfd_size;
1584 dev_dbg(kfd_device, "ioctl cmd 0x%x (#%d), arg 0x%lx\n", cmd, nr, arg);
1586 process = kfd_get_process(current);
1587 if (IS_ERR(process)) {
1588 dev_dbg(kfd_device, "no process\n");
1592 /* Do not trust userspace, use our own definition */
1595 if (unlikely(!func)) {
1596 dev_dbg(kfd_device, "no function\n");
1601 if (cmd & (IOC_IN | IOC_OUT)) {
1602 if (asize <= sizeof(stack_kdata)) {
1603 kdata = stack_kdata;
1605 kdata = kmalloc(asize, GFP_KERNEL);
1612 memset(kdata + usize, 0, asize - usize);
1616 if (copy_from_user(kdata, (void __user *)arg, usize) != 0) {
1620 } else if (cmd & IOC_OUT) {
1621 memset(kdata, 0, usize);
1624 retcode = func(filep, process, kdata);
1627 if (copy_to_user((void __user *)arg, kdata, usize) != 0)
1632 dev_dbg(kfd_device, "invalid ioctl: pid=%d, cmd=0x%02x, nr=0x%02x\n",
1633 task_pid_nr(current), cmd, nr);
1635 if (kdata != stack_kdata)
1639 dev_dbg(kfd_device, "ret = %d\n", retcode);
1644 static int kfd_mmap(struct file *filp, struct vm_area_struct *vma)
1646 struct kfd_process *process;
1648 process = kfd_get_process(current);
1649 if (IS_ERR(process))
1650 return PTR_ERR(process);
1652 if ((vma->vm_pgoff & KFD_MMAP_DOORBELL_MASK) ==
1653 KFD_MMAP_DOORBELL_MASK) {
1654 vma->vm_pgoff = vma->vm_pgoff ^ KFD_MMAP_DOORBELL_MASK;
1655 return kfd_doorbell_mmap(process, vma);
1656 } else if ((vma->vm_pgoff & KFD_MMAP_EVENTS_MASK) ==
1657 KFD_MMAP_EVENTS_MASK) {
1658 vma->vm_pgoff = vma->vm_pgoff ^ KFD_MMAP_EVENTS_MASK;
1659 return kfd_event_mmap(process, vma);
1660 } else if ((vma->vm_pgoff & KFD_MMAP_RESERVED_MEM_MASK) ==
1661 KFD_MMAP_RESERVED_MEM_MASK) {
1662 vma->vm_pgoff = vma->vm_pgoff ^ KFD_MMAP_RESERVED_MEM_MASK;
1663 return kfd_reserved_mem_mmap(process, vma);