2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/device.h>
24 #include <linux/export.h>
25 #include <linux/err.h>
27 #include <linux/file.h>
28 #include <linux/sched.h>
29 #include <linux/slab.h>
30 #include <linux/uaccess.h>
31 #include <linux/compat.h>
32 #include <uapi/linux/kfd_ioctl.h>
33 #include <linux/time.h>
35 #include <linux/mman.h>
36 #include <linux/dma-buf.h>
37 #include <asm/processor.h>
39 #include "kfd_device_queue_manager.h"
40 #include "kfd_dbgmgr.h"
41 #include "amdgpu_amdkfd.h"
43 static long kfd_ioctl(struct file *, unsigned int, unsigned long);
44 static int kfd_open(struct inode *, struct file *);
45 static int kfd_mmap(struct file *, struct vm_area_struct *);
47 static const char kfd_dev_name[] = "kfd";
49 static const struct file_operations kfd_fops = {
51 .unlocked_ioctl = kfd_ioctl,
52 .compat_ioctl = kfd_ioctl,
57 static int kfd_char_dev_major = -1;
58 static struct class *kfd_class;
59 struct device *kfd_device;
61 int kfd_chardev_init(void)
65 kfd_char_dev_major = register_chrdev(0, kfd_dev_name, &kfd_fops);
66 err = kfd_char_dev_major;
68 goto err_register_chrdev;
70 kfd_class = class_create(THIS_MODULE, kfd_dev_name);
71 err = PTR_ERR(kfd_class);
72 if (IS_ERR(kfd_class))
73 goto err_class_create;
75 kfd_device = device_create(kfd_class, NULL,
76 MKDEV(kfd_char_dev_major, 0),
78 err = PTR_ERR(kfd_device);
79 if (IS_ERR(kfd_device))
80 goto err_device_create;
85 class_destroy(kfd_class);
87 unregister_chrdev(kfd_char_dev_major, kfd_dev_name);
92 void kfd_chardev_exit(void)
94 device_destroy(kfd_class, MKDEV(kfd_char_dev_major, 0));
95 class_destroy(kfd_class);
96 unregister_chrdev(kfd_char_dev_major, kfd_dev_name);
99 struct device *kfd_chardev(void)
105 static int kfd_open(struct inode *inode, struct file *filep)
107 struct kfd_process *process;
108 bool is_32bit_user_mode;
110 if (iminor(inode) != 0)
113 is_32bit_user_mode = in_compat_syscall();
115 if (is_32bit_user_mode) {
117 "Process %d (32-bit) failed to open /dev/kfd\n"
118 "32-bit processes are not supported by amdkfd\n",
123 process = kfd_create_process(filep);
125 return PTR_ERR(process);
130 dev_dbg(kfd_device, "process %d opened, compat mode (32 bit) - %d\n",
131 process->pasid, process->is_32bit_user_mode);
136 static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p,
139 struct kfd_ioctl_get_version_args *args = data;
141 args->major_version = KFD_IOCTL_MAJOR_VERSION;
142 args->minor_version = KFD_IOCTL_MINOR_VERSION;
147 static int set_queue_properties_from_user(struct queue_properties *q_properties,
148 struct kfd_ioctl_create_queue_args *args)
150 if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) {
151 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
155 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
156 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n");
160 if ((args->ring_base_address) &&
161 (!access_ok((const void __user *) args->ring_base_address,
162 sizeof(uint64_t)))) {
163 pr_err("Can't access ring base address\n");
167 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
168 pr_err("Ring size must be a power of 2 or 0\n");
172 if (!access_ok((const void __user *) args->read_pointer_address,
174 pr_err("Can't access read pointer\n");
178 if (!access_ok((const void __user *) args->write_pointer_address,
180 pr_err("Can't access write pointer\n");
184 if (args->eop_buffer_address &&
185 !access_ok((const void __user *) args->eop_buffer_address,
187 pr_debug("Can't access eop buffer");
191 if (args->ctx_save_restore_address &&
192 !access_ok((const void __user *) args->ctx_save_restore_address,
194 pr_debug("Can't access ctx save restore buffer");
198 q_properties->is_interop = false;
199 q_properties->queue_percent = args->queue_percentage;
200 q_properties->priority = args->queue_priority;
201 q_properties->queue_address = args->ring_base_address;
202 q_properties->queue_size = args->ring_size;
203 q_properties->read_ptr = (uint32_t *) args->read_pointer_address;
204 q_properties->write_ptr = (uint32_t *) args->write_pointer_address;
205 q_properties->eop_ring_buffer_address = args->eop_buffer_address;
206 q_properties->eop_ring_buffer_size = args->eop_buffer_size;
207 q_properties->ctx_save_restore_area_address =
208 args->ctx_save_restore_address;
209 q_properties->ctx_save_restore_area_size = args->ctx_save_restore_size;
210 q_properties->ctl_stack_size = args->ctl_stack_size;
211 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE ||
212 args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
213 q_properties->type = KFD_QUEUE_TYPE_COMPUTE;
214 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA)
215 q_properties->type = KFD_QUEUE_TYPE_SDMA;
216 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA_XGMI)
217 q_properties->type = KFD_QUEUE_TYPE_SDMA_XGMI;
221 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
222 q_properties->format = KFD_QUEUE_FORMAT_AQL;
224 q_properties->format = KFD_QUEUE_FORMAT_PM4;
226 pr_debug("Queue Percentage: %d, %d\n",
227 q_properties->queue_percent, args->queue_percentage);
229 pr_debug("Queue Priority: %d, %d\n",
230 q_properties->priority, args->queue_priority);
232 pr_debug("Queue Address: 0x%llX, 0x%llX\n",
233 q_properties->queue_address, args->ring_base_address);
235 pr_debug("Queue Size: 0x%llX, %u\n",
236 q_properties->queue_size, args->ring_size);
238 pr_debug("Queue r/w Pointers: %px, %px\n",
239 q_properties->read_ptr,
240 q_properties->write_ptr);
242 pr_debug("Queue Format: %d\n", q_properties->format);
244 pr_debug("Queue EOP: 0x%llX\n", q_properties->eop_ring_buffer_address);
246 pr_debug("Queue CTX save area: 0x%llX\n",
247 q_properties->ctx_save_restore_area_address);
252 static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
255 struct kfd_ioctl_create_queue_args *args = data;
258 unsigned int queue_id;
259 struct kfd_process_device *pdd;
260 struct queue_properties q_properties;
262 memset(&q_properties, 0, sizeof(struct queue_properties));
264 pr_debug("Creating queue ioctl\n");
266 err = set_queue_properties_from_user(&q_properties, args);
270 pr_debug("Looking for gpu id 0x%x\n", args->gpu_id);
271 dev = kfd_device_by_id(args->gpu_id);
273 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id);
277 mutex_lock(&p->mutex);
279 pdd = kfd_bind_process_to_device(dev, p);
282 goto err_bind_process;
285 pr_debug("Creating queue for PASID %d on gpu 0x%x\n",
289 err = pqm_create_queue(&p->pqm, dev, filep, &q_properties, &queue_id);
291 goto err_create_queue;
293 args->queue_id = queue_id;
296 /* Return gpu_id as doorbell offset for mmap usage */
297 args->doorbell_offset = KFD_MMAP_TYPE_DOORBELL;
298 args->doorbell_offset |= KFD_MMAP_GPU_ID(args->gpu_id);
299 args->doorbell_offset <<= PAGE_SHIFT;
300 if (KFD_IS_SOC15(dev->device_info->asic_family))
301 /* On SOC15 ASICs, doorbell allocation must be
302 * per-device, and independent from the per-process
303 * queue_id. Return the doorbell offset within the
304 * doorbell aperture to user mode.
306 args->doorbell_offset |= q_properties.doorbell_off;
308 mutex_unlock(&p->mutex);
310 pr_debug("Queue id %d was created successfully\n", args->queue_id);
312 pr_debug("Ring buffer address == 0x%016llX\n",
313 args->ring_base_address);
315 pr_debug("Read ptr address == 0x%016llX\n",
316 args->read_pointer_address);
318 pr_debug("Write ptr address == 0x%016llX\n",
319 args->write_pointer_address);
325 mutex_unlock(&p->mutex);
329 static int kfd_ioctl_destroy_queue(struct file *filp, struct kfd_process *p,
333 struct kfd_ioctl_destroy_queue_args *args = data;
335 pr_debug("Destroying queue id %d for pasid %d\n",
339 mutex_lock(&p->mutex);
341 retval = pqm_destroy_queue(&p->pqm, args->queue_id);
343 mutex_unlock(&p->mutex);
347 static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p,
351 struct kfd_ioctl_update_queue_args *args = data;
352 struct queue_properties properties;
354 if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) {
355 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
359 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
360 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n");
364 if ((args->ring_base_address) &&
365 (!access_ok((const void __user *) args->ring_base_address,
366 sizeof(uint64_t)))) {
367 pr_err("Can't access ring base address\n");
371 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
372 pr_err("Ring size must be a power of 2 or 0\n");
376 properties.queue_address = args->ring_base_address;
377 properties.queue_size = args->ring_size;
378 properties.queue_percent = args->queue_percentage;
379 properties.priority = args->queue_priority;
381 pr_debug("Updating queue id %d for pasid %d\n",
382 args->queue_id, p->pasid);
384 mutex_lock(&p->mutex);
386 retval = pqm_update_queue(&p->pqm, args->queue_id, &properties);
388 mutex_unlock(&p->mutex);
393 static int kfd_ioctl_set_cu_mask(struct file *filp, struct kfd_process *p,
397 const int max_num_cus = 1024;
398 struct kfd_ioctl_set_cu_mask_args *args = data;
399 struct queue_properties properties;
400 uint32_t __user *cu_mask_ptr = (uint32_t __user *)args->cu_mask_ptr;
401 size_t cu_mask_size = sizeof(uint32_t) * (args->num_cu_mask / 32);
403 if ((args->num_cu_mask % 32) != 0) {
404 pr_debug("num_cu_mask 0x%x must be a multiple of 32",
409 properties.cu_mask_count = args->num_cu_mask;
410 if (properties.cu_mask_count == 0) {
411 pr_debug("CU mask cannot be 0");
415 /* To prevent an unreasonably large CU mask size, set an arbitrary
416 * limit of max_num_cus bits. We can then just drop any CU mask bits
417 * past max_num_cus bits and just use the first max_num_cus bits.
419 if (properties.cu_mask_count > max_num_cus) {
420 pr_debug("CU mask cannot be greater than 1024 bits");
421 properties.cu_mask_count = max_num_cus;
422 cu_mask_size = sizeof(uint32_t) * (max_num_cus/32);
425 properties.cu_mask = kzalloc(cu_mask_size, GFP_KERNEL);
426 if (!properties.cu_mask)
429 retval = copy_from_user(properties.cu_mask, cu_mask_ptr, cu_mask_size);
431 pr_debug("Could not copy CU mask from userspace");
432 kfree(properties.cu_mask);
436 mutex_lock(&p->mutex);
438 retval = pqm_set_cu_mask(&p->pqm, args->queue_id, &properties);
440 mutex_unlock(&p->mutex);
443 kfree(properties.cu_mask);
448 static int kfd_ioctl_get_queue_wave_state(struct file *filep,
449 struct kfd_process *p, void *data)
451 struct kfd_ioctl_get_queue_wave_state_args *args = data;
454 mutex_lock(&p->mutex);
456 r = pqm_get_wave_state(&p->pqm, args->queue_id,
457 (void __user *)args->ctl_stack_address,
458 &args->ctl_stack_used_size,
459 &args->save_area_used_size);
461 mutex_unlock(&p->mutex);
466 static int kfd_ioctl_set_memory_policy(struct file *filep,
467 struct kfd_process *p, void *data)
469 struct kfd_ioctl_set_memory_policy_args *args = data;
472 struct kfd_process_device *pdd;
473 enum cache_policy default_policy, alternate_policy;
475 if (args->default_policy != KFD_IOC_CACHE_POLICY_COHERENT
476 && args->default_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
480 if (args->alternate_policy != KFD_IOC_CACHE_POLICY_COHERENT
481 && args->alternate_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
485 dev = kfd_device_by_id(args->gpu_id);
489 mutex_lock(&p->mutex);
491 pdd = kfd_bind_process_to_device(dev, p);
497 default_policy = (args->default_policy == KFD_IOC_CACHE_POLICY_COHERENT)
498 ? cache_policy_coherent : cache_policy_noncoherent;
501 (args->alternate_policy == KFD_IOC_CACHE_POLICY_COHERENT)
502 ? cache_policy_coherent : cache_policy_noncoherent;
504 if (!dev->dqm->ops.set_cache_memory_policy(dev->dqm,
508 (void __user *)args->alternate_aperture_base,
509 args->alternate_aperture_size))
513 mutex_unlock(&p->mutex);
518 static int kfd_ioctl_set_trap_handler(struct file *filep,
519 struct kfd_process *p, void *data)
521 struct kfd_ioctl_set_trap_handler_args *args = data;
524 struct kfd_process_device *pdd;
526 dev = kfd_device_by_id(args->gpu_id);
530 mutex_lock(&p->mutex);
532 pdd = kfd_bind_process_to_device(dev, p);
538 if (dev->dqm->ops.set_trap_handler(dev->dqm,
545 mutex_unlock(&p->mutex);
550 static int kfd_ioctl_dbg_register(struct file *filep,
551 struct kfd_process *p, void *data)
553 struct kfd_ioctl_dbg_register_args *args = data;
555 struct kfd_dbgmgr *dbgmgr_ptr;
556 struct kfd_process_device *pdd;
560 dev = kfd_device_by_id(args->gpu_id);
564 if (dev->device_info->asic_family == CHIP_CARRIZO) {
565 pr_debug("kfd_ioctl_dbg_register not supported on CZ\n");
569 mutex_lock(&p->mutex);
570 mutex_lock(kfd_get_dbgmgr_mutex());
573 * make sure that we have pdd, if this the first queue created for
576 pdd = kfd_bind_process_to_device(dev, p);
578 status = PTR_ERR(pdd);
583 /* In case of a legal call, we have no dbgmgr yet */
584 create_ok = kfd_dbgmgr_create(&dbgmgr_ptr, dev);
586 status = kfd_dbgmgr_register(dbgmgr_ptr, p);
588 kfd_dbgmgr_destroy(dbgmgr_ptr);
590 dev->dbgmgr = dbgmgr_ptr;
593 pr_debug("debugger already registered\n");
598 mutex_unlock(kfd_get_dbgmgr_mutex());
599 mutex_unlock(&p->mutex);
604 static int kfd_ioctl_dbg_unregister(struct file *filep,
605 struct kfd_process *p, void *data)
607 struct kfd_ioctl_dbg_unregister_args *args = data;
611 dev = kfd_device_by_id(args->gpu_id);
612 if (!dev || !dev->dbgmgr)
615 if (dev->device_info->asic_family == CHIP_CARRIZO) {
616 pr_debug("kfd_ioctl_dbg_unregister not supported on CZ\n");
620 mutex_lock(kfd_get_dbgmgr_mutex());
622 status = kfd_dbgmgr_unregister(dev->dbgmgr, p);
624 kfd_dbgmgr_destroy(dev->dbgmgr);
628 mutex_unlock(kfd_get_dbgmgr_mutex());
634 * Parse and generate variable size data structure for address watch.
635 * Total size of the buffer and # watch points is limited in order
636 * to prevent kernel abuse. (no bearing to the much smaller HW limitation
637 * which is enforced by dbgdev module)
638 * please also note that the watch address itself are not "copied from user",
639 * since it be set into the HW in user mode values.
642 static int kfd_ioctl_dbg_address_watch(struct file *filep,
643 struct kfd_process *p, void *data)
645 struct kfd_ioctl_dbg_address_watch_args *args = data;
647 struct dbg_address_watch_info aw_info;
648 unsigned char *args_buff;
650 void __user *cmd_from_user;
651 uint64_t watch_mask_value = 0;
652 unsigned int args_idx = 0;
654 memset((void *) &aw_info, 0, sizeof(struct dbg_address_watch_info));
656 dev = kfd_device_by_id(args->gpu_id);
660 if (dev->device_info->asic_family == CHIP_CARRIZO) {
661 pr_debug("kfd_ioctl_dbg_wave_control not supported on CZ\n");
665 cmd_from_user = (void __user *) args->content_ptr;
667 /* Validate arguments */
669 if ((args->buf_size_in_bytes > MAX_ALLOWED_AW_BUFF_SIZE) ||
670 (args->buf_size_in_bytes <= sizeof(*args) + sizeof(int) * 2) ||
671 (cmd_from_user == NULL))
674 /* this is the actual buffer to work with */
675 args_buff = memdup_user(cmd_from_user,
676 args->buf_size_in_bytes - sizeof(*args));
677 if (IS_ERR(args_buff))
678 return PTR_ERR(args_buff);
682 aw_info.num_watch_points = *((uint32_t *)(&args_buff[args_idx]));
683 args_idx += sizeof(aw_info.num_watch_points);
685 aw_info.watch_mode = (enum HSA_DBG_WATCH_MODE *) &args_buff[args_idx];
686 args_idx += sizeof(enum HSA_DBG_WATCH_MODE) * aw_info.num_watch_points;
689 * set watch address base pointer to point on the array base
692 aw_info.watch_address = (uint64_t *) &args_buff[args_idx];
694 /* skip over the addresses buffer */
695 args_idx += sizeof(aw_info.watch_address) * aw_info.num_watch_points;
697 if (args_idx >= args->buf_size_in_bytes - sizeof(*args)) {
702 watch_mask_value = (uint64_t) args_buff[args_idx];
704 if (watch_mask_value > 0) {
706 * There is an array of masks.
707 * set watch mask base pointer to point on the array base
710 aw_info.watch_mask = (uint64_t *) &args_buff[args_idx];
712 /* skip over the masks buffer */
713 args_idx += sizeof(aw_info.watch_mask) *
714 aw_info.num_watch_points;
716 /* just the NULL mask, set to NULL and skip over it */
717 aw_info.watch_mask = NULL;
718 args_idx += sizeof(aw_info.watch_mask);
721 if (args_idx >= args->buf_size_in_bytes - sizeof(args)) {
726 /* Currently HSA Event is not supported for DBG */
727 aw_info.watch_event = NULL;
729 mutex_lock(kfd_get_dbgmgr_mutex());
731 status = kfd_dbgmgr_address_watch(dev->dbgmgr, &aw_info);
733 mutex_unlock(kfd_get_dbgmgr_mutex());
741 /* Parse and generate fixed size data structure for wave control */
742 static int kfd_ioctl_dbg_wave_control(struct file *filep,
743 struct kfd_process *p, void *data)
745 struct kfd_ioctl_dbg_wave_control_args *args = data;
747 struct dbg_wave_control_info wac_info;
748 unsigned char *args_buff;
749 uint32_t computed_buff_size;
751 void __user *cmd_from_user;
752 unsigned int args_idx = 0;
754 memset((void *) &wac_info, 0, sizeof(struct dbg_wave_control_info));
756 /* we use compact form, independent of the packing attribute value */
757 computed_buff_size = sizeof(*args) +
758 sizeof(wac_info.mode) +
759 sizeof(wac_info.operand) +
760 sizeof(wac_info.dbgWave_msg.DbgWaveMsg) +
761 sizeof(wac_info.dbgWave_msg.MemoryVA) +
762 sizeof(wac_info.trapId);
764 dev = kfd_device_by_id(args->gpu_id);
768 if (dev->device_info->asic_family == CHIP_CARRIZO) {
769 pr_debug("kfd_ioctl_dbg_wave_control not supported on CZ\n");
773 /* input size must match the computed "compact" size */
774 if (args->buf_size_in_bytes != computed_buff_size) {
775 pr_debug("size mismatch, computed : actual %u : %u\n",
776 args->buf_size_in_bytes, computed_buff_size);
780 cmd_from_user = (void __user *) args->content_ptr;
782 if (cmd_from_user == NULL)
785 /* copy the entire buffer from user */
787 args_buff = memdup_user(cmd_from_user,
788 args->buf_size_in_bytes - sizeof(*args));
789 if (IS_ERR(args_buff))
790 return PTR_ERR(args_buff);
792 /* move ptr to the start of the "pay-load" area */
793 wac_info.process = p;
795 wac_info.operand = *((enum HSA_DBG_WAVEOP *)(&args_buff[args_idx]));
796 args_idx += sizeof(wac_info.operand);
798 wac_info.mode = *((enum HSA_DBG_WAVEMODE *)(&args_buff[args_idx]));
799 args_idx += sizeof(wac_info.mode);
801 wac_info.trapId = *((uint32_t *)(&args_buff[args_idx]));
802 args_idx += sizeof(wac_info.trapId);
804 wac_info.dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value =
805 *((uint32_t *)(&args_buff[args_idx]));
806 wac_info.dbgWave_msg.MemoryVA = NULL;
808 mutex_lock(kfd_get_dbgmgr_mutex());
810 pr_debug("Calling dbg manager process %p, operand %u, mode %u, trapId %u, message %u\n",
811 wac_info.process, wac_info.operand,
812 wac_info.mode, wac_info.trapId,
813 wac_info.dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value);
815 status = kfd_dbgmgr_wave_control(dev->dbgmgr, &wac_info);
817 pr_debug("Returned status of dbg manager is %ld\n", status);
819 mutex_unlock(kfd_get_dbgmgr_mutex());
826 static int kfd_ioctl_get_clock_counters(struct file *filep,
827 struct kfd_process *p, void *data)
829 struct kfd_ioctl_get_clock_counters_args *args = data;
832 dev = kfd_device_by_id(args->gpu_id);
834 /* Reading GPU clock counter from KGD */
835 args->gpu_clock_counter = amdgpu_amdkfd_get_gpu_clock_counter(dev->kgd);
837 /* Node without GPU resource */
838 args->gpu_clock_counter = 0;
840 /* No access to rdtsc. Using raw monotonic time */
841 args->cpu_clock_counter = ktime_get_raw_ns();
842 args->system_clock_counter = ktime_get_boottime_ns();
844 /* Since the counter is in nano-seconds we use 1GHz frequency */
845 args->system_clock_freq = 1000000000;
851 static int kfd_ioctl_get_process_apertures(struct file *filp,
852 struct kfd_process *p, void *data)
854 struct kfd_ioctl_get_process_apertures_args *args = data;
855 struct kfd_process_device_apertures *pAperture;
856 struct kfd_process_device *pdd;
858 dev_dbg(kfd_device, "get apertures for PASID %d", p->pasid);
860 args->num_of_nodes = 0;
862 mutex_lock(&p->mutex);
864 /*if the process-device list isn't empty*/
865 if (kfd_has_process_device_data(p)) {
866 /* Run over all pdd of the process */
867 pdd = kfd_get_first_process_device_data(p);
870 &args->process_apertures[args->num_of_nodes];
871 pAperture->gpu_id = pdd->dev->id;
872 pAperture->lds_base = pdd->lds_base;
873 pAperture->lds_limit = pdd->lds_limit;
874 pAperture->gpuvm_base = pdd->gpuvm_base;
875 pAperture->gpuvm_limit = pdd->gpuvm_limit;
876 pAperture->scratch_base = pdd->scratch_base;
877 pAperture->scratch_limit = pdd->scratch_limit;
880 "node id %u\n", args->num_of_nodes);
882 "gpu id %u\n", pdd->dev->id);
884 "lds_base %llX\n", pdd->lds_base);
886 "lds_limit %llX\n", pdd->lds_limit);
888 "gpuvm_base %llX\n", pdd->gpuvm_base);
890 "gpuvm_limit %llX\n", pdd->gpuvm_limit);
892 "scratch_base %llX\n", pdd->scratch_base);
894 "scratch_limit %llX\n", pdd->scratch_limit);
896 args->num_of_nodes++;
898 pdd = kfd_get_next_process_device_data(p, pdd);
899 } while (pdd && (args->num_of_nodes < NUM_OF_SUPPORTED_GPUS));
902 mutex_unlock(&p->mutex);
907 static int kfd_ioctl_get_process_apertures_new(struct file *filp,
908 struct kfd_process *p, void *data)
910 struct kfd_ioctl_get_process_apertures_new_args *args = data;
911 struct kfd_process_device_apertures *pa;
912 struct kfd_process_device *pdd;
916 dev_dbg(kfd_device, "get apertures for PASID %d", p->pasid);
918 if (args->num_of_nodes == 0) {
919 /* Return number of nodes, so that user space can alloacate
922 mutex_lock(&p->mutex);
924 if (!kfd_has_process_device_data(p))
927 /* Run over all pdd of the process */
928 pdd = kfd_get_first_process_device_data(p);
930 args->num_of_nodes++;
931 pdd = kfd_get_next_process_device_data(p, pdd);
937 /* Fill in process-aperture information for all available
938 * nodes, but not more than args->num_of_nodes as that is
939 * the amount of memory allocated by user
941 pa = kzalloc((sizeof(struct kfd_process_device_apertures) *
942 args->num_of_nodes), GFP_KERNEL);
946 mutex_lock(&p->mutex);
948 if (!kfd_has_process_device_data(p)) {
949 args->num_of_nodes = 0;
954 /* Run over all pdd of the process */
955 pdd = kfd_get_first_process_device_data(p);
957 pa[nodes].gpu_id = pdd->dev->id;
958 pa[nodes].lds_base = pdd->lds_base;
959 pa[nodes].lds_limit = pdd->lds_limit;
960 pa[nodes].gpuvm_base = pdd->gpuvm_base;
961 pa[nodes].gpuvm_limit = pdd->gpuvm_limit;
962 pa[nodes].scratch_base = pdd->scratch_base;
963 pa[nodes].scratch_limit = pdd->scratch_limit;
966 "gpu id %u\n", pdd->dev->id);
968 "lds_base %llX\n", pdd->lds_base);
970 "lds_limit %llX\n", pdd->lds_limit);
972 "gpuvm_base %llX\n", pdd->gpuvm_base);
974 "gpuvm_limit %llX\n", pdd->gpuvm_limit);
976 "scratch_base %llX\n", pdd->scratch_base);
978 "scratch_limit %llX\n", pdd->scratch_limit);
981 pdd = kfd_get_next_process_device_data(p, pdd);
982 } while (pdd && (nodes < args->num_of_nodes));
983 mutex_unlock(&p->mutex);
985 args->num_of_nodes = nodes;
987 (void __user *)args->kfd_process_device_apertures_ptr,
989 (nodes * sizeof(struct kfd_process_device_apertures)));
991 return ret ? -EFAULT : 0;
994 mutex_unlock(&p->mutex);
998 static int kfd_ioctl_create_event(struct file *filp, struct kfd_process *p,
1001 struct kfd_ioctl_create_event_args *args = data;
1004 /* For dGPUs the event page is allocated in user mode. The
1005 * handle is passed to KFD with the first call to this IOCTL
1006 * through the event_page_offset field.
1008 if (args->event_page_offset) {
1009 struct kfd_dev *kfd;
1010 struct kfd_process_device *pdd;
1011 void *mem, *kern_addr;
1014 if (p->signal_page) {
1015 pr_err("Event page is already set\n");
1019 kfd = kfd_device_by_id(GET_GPU_ID(args->event_page_offset));
1021 pr_err("Getting device by id failed in %s\n", __func__);
1025 mutex_lock(&p->mutex);
1026 pdd = kfd_bind_process_to_device(kfd, p);
1032 mem = kfd_process_device_translate_handle(pdd,
1033 GET_IDR_HANDLE(args->event_page_offset));
1035 pr_err("Can't find BO, offset is 0x%llx\n",
1036 args->event_page_offset);
1040 mutex_unlock(&p->mutex);
1042 err = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(kfd->kgd,
1043 mem, &kern_addr, &size);
1045 pr_err("Failed to map event page to kernel\n");
1049 err = kfd_event_page_set(p, kern_addr, size);
1051 pr_err("Failed to set event page\n");
1056 err = kfd_event_create(filp, p, args->event_type,
1057 args->auto_reset != 0, args->node_id,
1058 &args->event_id, &args->event_trigger_data,
1059 &args->event_page_offset,
1060 &args->event_slot_index);
1065 mutex_unlock(&p->mutex);
1069 static int kfd_ioctl_destroy_event(struct file *filp, struct kfd_process *p,
1072 struct kfd_ioctl_destroy_event_args *args = data;
1074 return kfd_event_destroy(p, args->event_id);
1077 static int kfd_ioctl_set_event(struct file *filp, struct kfd_process *p,
1080 struct kfd_ioctl_set_event_args *args = data;
1082 return kfd_set_event(p, args->event_id);
1085 static int kfd_ioctl_reset_event(struct file *filp, struct kfd_process *p,
1088 struct kfd_ioctl_reset_event_args *args = data;
1090 return kfd_reset_event(p, args->event_id);
1093 static int kfd_ioctl_wait_events(struct file *filp, struct kfd_process *p,
1096 struct kfd_ioctl_wait_events_args *args = data;
1099 err = kfd_wait_on_events(p, args->num_events,
1100 (void __user *)args->events_ptr,
1101 (args->wait_for_all != 0),
1102 args->timeout, &args->wait_result);
1106 static int kfd_ioctl_set_scratch_backing_va(struct file *filep,
1107 struct kfd_process *p, void *data)
1109 struct kfd_ioctl_set_scratch_backing_va_args *args = data;
1110 struct kfd_process_device *pdd;
1111 struct kfd_dev *dev;
1114 dev = kfd_device_by_id(args->gpu_id);
1118 mutex_lock(&p->mutex);
1120 pdd = kfd_bind_process_to_device(dev, p);
1123 goto bind_process_to_device_fail;
1126 pdd->qpd.sh_hidden_private_base = args->va_addr;
1128 mutex_unlock(&p->mutex);
1130 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS &&
1132 dev->kfd2kgd->set_scratch_backing_va(
1133 dev->kgd, args->va_addr, pdd->qpd.vmid);
1137 bind_process_to_device_fail:
1138 mutex_unlock(&p->mutex);
1142 static int kfd_ioctl_get_tile_config(struct file *filep,
1143 struct kfd_process *p, void *data)
1145 struct kfd_ioctl_get_tile_config_args *args = data;
1146 struct kfd_dev *dev;
1147 struct tile_config config;
1150 dev = kfd_device_by_id(args->gpu_id);
1154 dev->kfd2kgd->get_tile_config(dev->kgd, &config);
1156 args->gb_addr_config = config.gb_addr_config;
1157 args->num_banks = config.num_banks;
1158 args->num_ranks = config.num_ranks;
1160 if (args->num_tile_configs > config.num_tile_configs)
1161 args->num_tile_configs = config.num_tile_configs;
1162 err = copy_to_user((void __user *)args->tile_config_ptr,
1163 config.tile_config_ptr,
1164 args->num_tile_configs * sizeof(uint32_t));
1166 args->num_tile_configs = 0;
1170 if (args->num_macro_tile_configs > config.num_macro_tile_configs)
1171 args->num_macro_tile_configs =
1172 config.num_macro_tile_configs;
1173 err = copy_to_user((void __user *)args->macro_tile_config_ptr,
1174 config.macro_tile_config_ptr,
1175 args->num_macro_tile_configs * sizeof(uint32_t));
1177 args->num_macro_tile_configs = 0;
1184 static int kfd_ioctl_acquire_vm(struct file *filep, struct kfd_process *p,
1187 struct kfd_ioctl_acquire_vm_args *args = data;
1188 struct kfd_process_device *pdd;
1189 struct kfd_dev *dev;
1190 struct file *drm_file;
1193 dev = kfd_device_by_id(args->gpu_id);
1197 drm_file = fget(args->drm_fd);
1201 mutex_lock(&p->mutex);
1203 pdd = kfd_get_process_device_data(dev, p);
1209 if (pdd->drm_file) {
1210 ret = pdd->drm_file == drm_file ? 0 : -EBUSY;
1214 ret = kfd_process_device_init_vm(pdd, drm_file);
1217 /* On success, the PDD keeps the drm_file reference */
1218 mutex_unlock(&p->mutex);
1223 mutex_unlock(&p->mutex);
1228 bool kfd_dev_is_large_bar(struct kfd_dev *dev)
1230 struct kfd_local_mem_info mem_info;
1232 if (debug_largebar) {
1233 pr_debug("Simulate large-bar allocation on non large-bar machine\n");
1237 if (dev->device_info->needs_iommu_device)
1240 amdgpu_amdkfd_get_local_mem_info(dev->kgd, &mem_info);
1241 if (mem_info.local_mem_size_private == 0 &&
1242 mem_info.local_mem_size_public > 0)
1247 static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep,
1248 struct kfd_process *p, void *data)
1250 struct kfd_ioctl_alloc_memory_of_gpu_args *args = data;
1251 struct kfd_process_device *pdd;
1253 struct kfd_dev *dev;
1256 uint64_t offset = args->mmap_offset;
1257 uint32_t flags = args->flags;
1259 if (args->size == 0)
1262 dev = kfd_device_by_id(args->gpu_id);
1266 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) &&
1267 (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) &&
1268 !kfd_dev_is_large_bar(dev)) {
1269 pr_err("Alloc host visible vram on small bar is not allowed\n");
1273 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) {
1274 if (args->size != kfd_doorbell_process_slice(dev))
1276 offset = kfd_get_process_doorbells(dev, p);
1277 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
1278 if (args->size != PAGE_SIZE)
1280 offset = amdgpu_amdkfd_get_mmio_remap_phys_addr(dev->kgd);
1285 mutex_lock(&p->mutex);
1287 pdd = kfd_bind_process_to_device(dev, p);
1293 err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1294 dev->kgd, args->va_addr, args->size,
1295 pdd->vm, (struct kgd_mem **) &mem, &offset,
1301 idr_handle = kfd_process_device_create_obj_handle(pdd, mem);
1302 if (idr_handle < 0) {
1307 mutex_unlock(&p->mutex);
1309 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle);
1310 args->mmap_offset = offset;
1312 /* MMIO is mapped through kfd device
1313 * Generate a kfd mmap offset
1315 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
1316 args->mmap_offset = KFD_MMAP_TYPE_MMIO | KFD_MMAP_GPU_ID(args->gpu_id);
1317 args->mmap_offset <<= PAGE_SHIFT;
1323 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem);
1325 mutex_unlock(&p->mutex);
1329 static int kfd_ioctl_free_memory_of_gpu(struct file *filep,
1330 struct kfd_process *p, void *data)
1332 struct kfd_ioctl_free_memory_of_gpu_args *args = data;
1333 struct kfd_process_device *pdd;
1335 struct kfd_dev *dev;
1338 dev = kfd_device_by_id(GET_GPU_ID(args->handle));
1342 mutex_lock(&p->mutex);
1344 pdd = kfd_get_process_device_data(dev, p);
1346 pr_err("Process device data doesn't exist\n");
1351 mem = kfd_process_device_translate_handle(
1352 pdd, GET_IDR_HANDLE(args->handle));
1358 ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd,
1359 (struct kgd_mem *)mem);
1361 /* If freeing the buffer failed, leave the handle in place for
1362 * clean-up during process tear-down.
1365 kfd_process_device_remove_obj_handle(
1366 pdd, GET_IDR_HANDLE(args->handle));
1369 mutex_unlock(&p->mutex);
1373 static int kfd_ioctl_map_memory_to_gpu(struct file *filep,
1374 struct kfd_process *p, void *data)
1376 struct kfd_ioctl_map_memory_to_gpu_args *args = data;
1377 struct kfd_process_device *pdd, *peer_pdd;
1379 struct kfd_dev *dev, *peer;
1382 uint32_t *devices_arr = NULL;
1384 dev = kfd_device_by_id(GET_GPU_ID(args->handle));
1388 if (!args->n_devices) {
1389 pr_debug("Device IDs array empty\n");
1392 if (args->n_success > args->n_devices) {
1393 pr_debug("n_success exceeds n_devices\n");
1397 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr),
1402 err = copy_from_user(devices_arr,
1403 (void __user *)args->device_ids_array_ptr,
1404 args->n_devices * sizeof(*devices_arr));
1407 goto copy_from_user_failed;
1410 mutex_lock(&p->mutex);
1412 pdd = kfd_bind_process_to_device(dev, p);
1415 goto bind_process_to_device_failed;
1418 mem = kfd_process_device_translate_handle(pdd,
1419 GET_IDR_HANDLE(args->handle));
1422 goto get_mem_obj_from_handle_failed;
1425 for (i = args->n_success; i < args->n_devices; i++) {
1426 peer = kfd_device_by_id(devices_arr[i]);
1428 pr_debug("Getting device by id failed for 0x%x\n",
1431 goto get_mem_obj_from_handle_failed;
1434 peer_pdd = kfd_bind_process_to_device(peer, p);
1435 if (IS_ERR(peer_pdd)) {
1436 err = PTR_ERR(peer_pdd);
1437 goto get_mem_obj_from_handle_failed;
1439 err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
1440 peer->kgd, (struct kgd_mem *)mem, peer_pdd->vm);
1442 pr_err("Failed to map to gpu %d/%d\n",
1443 i, args->n_devices);
1444 goto map_memory_to_gpu_failed;
1446 args->n_success = i+1;
1449 mutex_unlock(&p->mutex);
1451 err = amdgpu_amdkfd_gpuvm_sync_memory(dev->kgd, (struct kgd_mem *) mem, true);
1453 pr_debug("Sync memory failed, wait interrupted by user signal\n");
1454 goto sync_memory_failed;
1457 /* Flush TLBs after waiting for the page table updates to complete */
1458 for (i = 0; i < args->n_devices; i++) {
1459 peer = kfd_device_by_id(devices_arr[i]);
1460 if (WARN_ON_ONCE(!peer))
1462 peer_pdd = kfd_get_process_device_data(peer, p);
1463 if (WARN_ON_ONCE(!peer_pdd))
1465 kfd_flush_tlb(peer_pdd);
1472 bind_process_to_device_failed:
1473 get_mem_obj_from_handle_failed:
1474 map_memory_to_gpu_failed:
1475 mutex_unlock(&p->mutex);
1476 copy_from_user_failed:
1483 static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep,
1484 struct kfd_process *p, void *data)
1486 struct kfd_ioctl_unmap_memory_from_gpu_args *args = data;
1487 struct kfd_process_device *pdd, *peer_pdd;
1489 struct kfd_dev *dev, *peer;
1491 uint32_t *devices_arr = NULL, i;
1493 dev = kfd_device_by_id(GET_GPU_ID(args->handle));
1497 if (!args->n_devices) {
1498 pr_debug("Device IDs array empty\n");
1501 if (args->n_success > args->n_devices) {
1502 pr_debug("n_success exceeds n_devices\n");
1506 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr),
1511 err = copy_from_user(devices_arr,
1512 (void __user *)args->device_ids_array_ptr,
1513 args->n_devices * sizeof(*devices_arr));
1516 goto copy_from_user_failed;
1519 mutex_lock(&p->mutex);
1521 pdd = kfd_get_process_device_data(dev, p);
1524 goto bind_process_to_device_failed;
1527 mem = kfd_process_device_translate_handle(pdd,
1528 GET_IDR_HANDLE(args->handle));
1531 goto get_mem_obj_from_handle_failed;
1534 for (i = args->n_success; i < args->n_devices; i++) {
1535 peer = kfd_device_by_id(devices_arr[i]);
1538 goto get_mem_obj_from_handle_failed;
1541 peer_pdd = kfd_get_process_device_data(peer, p);
1544 goto get_mem_obj_from_handle_failed;
1546 err = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
1547 peer->kgd, (struct kgd_mem *)mem, peer_pdd->vm);
1549 pr_err("Failed to unmap from gpu %d/%d\n",
1550 i, args->n_devices);
1551 goto unmap_memory_from_gpu_failed;
1553 args->n_success = i+1;
1557 mutex_unlock(&p->mutex);
1561 bind_process_to_device_failed:
1562 get_mem_obj_from_handle_failed:
1563 unmap_memory_from_gpu_failed:
1564 mutex_unlock(&p->mutex);
1565 copy_from_user_failed:
1570 static int kfd_ioctl_get_dmabuf_info(struct file *filep,
1571 struct kfd_process *p, void *data)
1573 struct kfd_ioctl_get_dmabuf_info_args *args = data;
1574 struct kfd_dev *dev = NULL;
1575 struct kgd_dev *dma_buf_kgd;
1576 void *metadata_buffer = NULL;
1581 /* Find a KFD GPU device that supports the get_dmabuf_info query */
1582 for (i = 0; kfd_topology_enum_kfd_devices(i, &dev) == 0; i++)
1588 if (args->metadata_ptr) {
1589 metadata_buffer = kzalloc(args->metadata_size, GFP_KERNEL);
1590 if (!metadata_buffer)
1594 /* Get dmabuf info from KGD */
1595 r = amdgpu_amdkfd_get_dmabuf_info(dev->kgd, args->dmabuf_fd,
1596 &dma_buf_kgd, &args->size,
1597 metadata_buffer, args->metadata_size,
1598 &args->metadata_size, &flags);
1602 /* Reverse-lookup gpu_id from kgd pointer */
1603 dev = kfd_device_by_kgd(dma_buf_kgd);
1608 args->gpu_id = dev->id;
1609 args->flags = flags;
1611 /* Copy metadata buffer to user mode */
1612 if (metadata_buffer) {
1613 r = copy_to_user((void __user *)args->metadata_ptr,
1614 metadata_buffer, args->metadata_size);
1620 kfree(metadata_buffer);
1625 static int kfd_ioctl_import_dmabuf(struct file *filep,
1626 struct kfd_process *p, void *data)
1628 struct kfd_ioctl_import_dmabuf_args *args = data;
1629 struct kfd_process_device *pdd;
1630 struct dma_buf *dmabuf;
1631 struct kfd_dev *dev;
1637 dev = kfd_device_by_id(args->gpu_id);
1641 dmabuf = dma_buf_get(args->dmabuf_fd);
1643 return PTR_ERR(dmabuf);
1645 mutex_lock(&p->mutex);
1647 pdd = kfd_bind_process_to_device(dev, p);
1653 r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->kgd, dmabuf,
1654 args->va_addr, pdd->vm,
1655 (struct kgd_mem **)&mem, &size,
1660 idr_handle = kfd_process_device_create_obj_handle(pdd, mem);
1661 if (idr_handle < 0) {
1666 mutex_unlock(&p->mutex);
1668 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle);
1673 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem);
1675 mutex_unlock(&p->mutex);
1679 #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \
1680 [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \
1681 .cmd_drv = 0, .name = #ioctl}
1684 static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = {
1685 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_VERSION,
1686 kfd_ioctl_get_version, 0),
1688 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_QUEUE,
1689 kfd_ioctl_create_queue, 0),
1691 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_QUEUE,
1692 kfd_ioctl_destroy_queue, 0),
1694 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_MEMORY_POLICY,
1695 kfd_ioctl_set_memory_policy, 0),
1697 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_CLOCK_COUNTERS,
1698 kfd_ioctl_get_clock_counters, 0),
1700 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES,
1701 kfd_ioctl_get_process_apertures, 0),
1703 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UPDATE_QUEUE,
1704 kfd_ioctl_update_queue, 0),
1706 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_EVENT,
1707 kfd_ioctl_create_event, 0),
1709 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_EVENT,
1710 kfd_ioctl_destroy_event, 0),
1712 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_EVENT,
1713 kfd_ioctl_set_event, 0),
1715 AMDKFD_IOCTL_DEF(AMDKFD_IOC_RESET_EVENT,
1716 kfd_ioctl_reset_event, 0),
1718 AMDKFD_IOCTL_DEF(AMDKFD_IOC_WAIT_EVENTS,
1719 kfd_ioctl_wait_events, 0),
1721 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_REGISTER,
1722 kfd_ioctl_dbg_register, 0),
1724 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_UNREGISTER,
1725 kfd_ioctl_dbg_unregister, 0),
1727 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_ADDRESS_WATCH,
1728 kfd_ioctl_dbg_address_watch, 0),
1730 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_WAVE_CONTROL,
1731 kfd_ioctl_dbg_wave_control, 0),
1733 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_SCRATCH_BACKING_VA,
1734 kfd_ioctl_set_scratch_backing_va, 0),
1736 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_TILE_CONFIG,
1737 kfd_ioctl_get_tile_config, 0),
1739 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_TRAP_HANDLER,
1740 kfd_ioctl_set_trap_handler, 0),
1742 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES_NEW,
1743 kfd_ioctl_get_process_apertures_new, 0),
1745 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ACQUIRE_VM,
1746 kfd_ioctl_acquire_vm, 0),
1748 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_MEMORY_OF_GPU,
1749 kfd_ioctl_alloc_memory_of_gpu, 0),
1751 AMDKFD_IOCTL_DEF(AMDKFD_IOC_FREE_MEMORY_OF_GPU,
1752 kfd_ioctl_free_memory_of_gpu, 0),
1754 AMDKFD_IOCTL_DEF(AMDKFD_IOC_MAP_MEMORY_TO_GPU,
1755 kfd_ioctl_map_memory_to_gpu, 0),
1757 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU,
1758 kfd_ioctl_unmap_memory_from_gpu, 0),
1760 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_CU_MASK,
1761 kfd_ioctl_set_cu_mask, 0),
1763 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_QUEUE_WAVE_STATE,
1764 kfd_ioctl_get_queue_wave_state, 0),
1766 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_DMABUF_INFO,
1767 kfd_ioctl_get_dmabuf_info, 0),
1769 AMDKFD_IOCTL_DEF(AMDKFD_IOC_IMPORT_DMABUF,
1770 kfd_ioctl_import_dmabuf, 0),
1774 #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls)
1776 static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
1778 struct kfd_process *process;
1779 amdkfd_ioctl_t *func;
1780 const struct amdkfd_ioctl_desc *ioctl = NULL;
1781 unsigned int nr = _IOC_NR(cmd);
1782 char stack_kdata[128];
1784 unsigned int usize, asize;
1785 int retcode = -EINVAL;
1787 if (nr >= AMDKFD_CORE_IOCTL_COUNT)
1790 if ((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) {
1793 ioctl = &amdkfd_ioctls[nr];
1795 amdkfd_size = _IOC_SIZE(ioctl->cmd);
1796 usize = asize = _IOC_SIZE(cmd);
1797 if (amdkfd_size > asize)
1798 asize = amdkfd_size;
1804 dev_dbg(kfd_device, "ioctl cmd 0x%x (#%d), arg 0x%lx\n", cmd, nr, arg);
1806 process = kfd_get_process(current);
1807 if (IS_ERR(process)) {
1808 dev_dbg(kfd_device, "no process\n");
1812 /* Do not trust userspace, use our own definition */
1815 if (unlikely(!func)) {
1816 dev_dbg(kfd_device, "no function\n");
1821 if (cmd & (IOC_IN | IOC_OUT)) {
1822 if (asize <= sizeof(stack_kdata)) {
1823 kdata = stack_kdata;
1825 kdata = kmalloc(asize, GFP_KERNEL);
1832 memset(kdata + usize, 0, asize - usize);
1836 if (copy_from_user(kdata, (void __user *)arg, usize) != 0) {
1840 } else if (cmd & IOC_OUT) {
1841 memset(kdata, 0, usize);
1844 retcode = func(filep, process, kdata);
1847 if (copy_to_user((void __user *)arg, kdata, usize) != 0)
1852 dev_dbg(kfd_device, "invalid ioctl: pid=%d, cmd=0x%02x, nr=0x%02x\n",
1853 task_pid_nr(current), cmd, nr);
1855 if (kdata != stack_kdata)
1859 dev_dbg(kfd_device, "ret = %d\n", retcode);
1864 static int kfd_mmio_mmap(struct kfd_dev *dev, struct kfd_process *process,
1865 struct vm_area_struct *vma)
1867 phys_addr_t address;
1870 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1873 address = amdgpu_amdkfd_get_mmio_remap_phys_addr(dev->kgd);
1875 vma->vm_flags |= VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE |
1876 VM_DONTDUMP | VM_PFNMAP;
1878 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1880 pr_debug("Process %d mapping mmio page\n"
1881 " target user address == 0x%08llX\n"
1882 " physical address == 0x%08llX\n"
1883 " vm_flags == 0x%04lX\n"
1884 " size == 0x%04lX\n",
1885 process->pasid, (unsigned long long) vma->vm_start,
1886 address, vma->vm_flags, PAGE_SIZE);
1888 ret = io_remap_pfn_range(vma,
1890 address >> PAGE_SHIFT,
1897 static int kfd_mmap(struct file *filp, struct vm_area_struct *vma)
1899 struct kfd_process *process;
1900 struct kfd_dev *dev = NULL;
1901 unsigned long vm_pgoff;
1902 unsigned int gpu_id;
1904 process = kfd_get_process(current);
1905 if (IS_ERR(process))
1906 return PTR_ERR(process);
1908 vm_pgoff = vma->vm_pgoff;
1909 vma->vm_pgoff = KFD_MMAP_OFFSET_VALUE_GET(vm_pgoff);
1910 gpu_id = KFD_MMAP_GPU_ID_GET(vm_pgoff);
1912 dev = kfd_device_by_id(gpu_id);
1914 switch (vm_pgoff & KFD_MMAP_TYPE_MASK) {
1915 case KFD_MMAP_TYPE_DOORBELL:
1918 return kfd_doorbell_mmap(dev, process, vma);
1920 case KFD_MMAP_TYPE_EVENTS:
1921 return kfd_event_mmap(process, vma);
1923 case KFD_MMAP_TYPE_RESERVED_MEM:
1926 return kfd_reserved_mem_mmap(dev, process, vma);
1927 case KFD_MMAP_TYPE_MMIO:
1930 return kfd_mmio_mmap(dev, process, vma);