drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Christian König <christian.koenig@amd.com>
  23  */
  24
  25 #include <linux/firmware.h>
  26 #include <drm/drmP.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_uvd.h"
  29 #include "vid.h"
  30 #include "uvd/uvd_6_0_d.h"
  31 #include "uvd/uvd_6_0_sh_mask.h"
  32 #include "oss/oss_2_0_d.h"
  33 #include "oss/oss_2_0_sh_mask.h"
  34 #include "smu/smu_7_1_3_d.h"
  35 #include "smu/smu_7_1_3_sh_mask.h"
  36 #include "bif/bif_5_1_d.h"
  37 #include "gmc/gmc_8_1_d.h"
  38 #include "vi.h"
  39 #include "ivsrcid/ivsrcid_vislands30.h"
  40
  41 /* Polaris10/11/12 firmware version */
  42 #define FW_1_130_16 ((1 << 24) | (130 << 16) | (16 << 8))
  43
  44 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
  45 static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  46
  47 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  48 static int uvd_v6_0_start(struct amdgpu_device *adev);
  49 static void uvd_v6_0_stop(struct amdgpu_device *adev);
  50 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev);
  51 static int uvd_v6_0_set_clockgating_state(void *handle,
  52                                           enum amd_clockgating_state state);
  53 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
  54                                  bool enable);
  55
  56 /**
  57 * uvd_v6_0_enc_support - get encode support status
  58 *
  59 * @adev: amdgpu_device pointer
  60 *
  61 * Returns the current hardware encode support status
  62 */
  63 static inline bool uvd_v6_0_enc_support(struct amdgpu_device *adev)
  64 {
  65         return ((adev->asic_type >= CHIP_POLARIS10) &&
  66                         (adev->asic_type <= CHIP_VEGAM) &&
  67                         (!adev->uvd.fw_version || adev->uvd.fw_version >= FW_1_130_16));
  68 }
  69
  70 /**
  71  * uvd_v6_0_ring_get_rptr - get read pointer
  72  *
  73  * @ring: amdgpu_ring pointer
  74  *
  75  * Returns the current hardware read pointer
  76  */
  77 static uint64_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
  78 {
  79         struct amdgpu_device *adev = ring->adev;
  80
  81         return RREG32(mmUVD_RBC_RB_RPTR);
  82 }
  83
  84 /**
  85  * uvd_v6_0_enc_ring_get_rptr - get enc read pointer
  86  *
  87  * @ring: amdgpu_ring pointer
  88  *
  89  * Returns the current hardware enc read pointer
  90  */
  91 static uint64_t uvd_v6_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
  92 {
  93         struct amdgpu_device *adev = ring->adev;
  94
  95         if (ring == &adev->uvd.inst->ring_enc[0])
  96                 return RREG32(mmUVD_RB_RPTR);
  97         else
  98                 return RREG32(mmUVD_RB_RPTR2);
  99 }
 100 /**
 101  * uvd_v6_0_ring_get_wptr - get write pointer
 102  *
 103  * @ring: amdgpu_ring pointer
 104  *
 105  * Returns the current hardware write pointer
 106  */
 107 static uint64_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
 108 {
 109         struct amdgpu_device *adev = ring->adev;
 110
 111         return RREG32(mmUVD_RBC_RB_WPTR);
 112 }
 113
 114 /**
 115  * uvd_v6_0_enc_ring_get_wptr - get enc write pointer
 116  *
 117  * @ring: amdgpu_ring pointer
 118  *
 119  * Returns the current hardware enc write pointer
 120  */
 121 static uint64_t uvd_v6_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
 122 {
 123         struct amdgpu_device *adev = ring->adev;
 124
 125         if (ring == &adev->uvd.inst->ring_enc[0])
 126                 return RREG32(mmUVD_RB_WPTR);
 127         else
 128                 return RREG32(mmUVD_RB_WPTR2);
 129 }
 130
 131 /**
 132  * uvd_v6_0_ring_set_wptr - set write pointer
 133  *
 134  * @ring: amdgpu_ring pointer
 135  *
 136  * Commits the write pointer to the hardware
 137  */
 138 static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
 139 {
 140         struct amdgpu_device *adev = ring->adev;
 141
 142         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 143 }
 144
 145 /**
 146  * uvd_v6_0_enc_ring_set_wptr - set enc write pointer
 147  *
 148  * @ring: amdgpu_ring pointer
 149  *
 150  * Commits the enc write pointer to the hardware
 151  */
 152 static void uvd_v6_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
 153 {
 154         struct amdgpu_device *adev = ring->adev;
 155
 156         if (ring == &adev->uvd.inst->ring_enc[0])
 157                 WREG32(mmUVD_RB_WPTR,
 158                         lower_32_bits(ring->wptr));
 159         else
 160                 WREG32(mmUVD_RB_WPTR2,
 161                         lower_32_bits(ring->wptr));
 162 }
 163
 164 /**
 165  * uvd_v6_0_enc_ring_test_ring - test if UVD ENC ring is working
 166  *
 167  * @ring: the engine to test on
 168  *
 169  */
 170 static int uvd_v6_0_enc_ring_test_ring(struct amdgpu_ring *ring)
 171 {
 172         struct amdgpu_device *adev = ring->adev;
 173         uint32_t rptr = amdgpu_ring_get_rptr(ring);
 174         unsigned i;
 175         int r;
 176
 177         r = amdgpu_ring_alloc(ring, 16);
 178         if (r)
 179                 return r;
 180         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
 181         amdgpu_ring_commit(ring);
 182
 183         for (i = 0; i < adev->usec_timeout; i++) {
 184                 if (amdgpu_ring_get_rptr(ring) != rptr)
 185                         break;
 186                 DRM_UDELAY(1);
 187         }
 188
 189         if (i >= adev->usec_timeout)
 190                 r = -ETIMEDOUT;
 191
 192         return r;
 193 }
 194
 195 /**
 196  * uvd_v6_0_enc_get_create_msg - generate a UVD ENC create msg
 197  *
 198  * @adev: amdgpu_device pointer
 199  * @ring: ring we should submit the msg to
 200  * @handle: session handle to use
 201  * @fence: optional fence to return
 202  *
 203  * Open up a stream for HW test
 204  */
 205 static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 206                                        struct dma_fence **fence)
 207 {
 208         const unsigned ib_size_dw = 16;
 209         struct amdgpu_job *job;
 210         struct amdgpu_ib *ib;
 211         struct dma_fence *f = NULL;
 212         uint64_t dummy;
 213         int i, r;
 214
 215         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 216         if (r)
 217                 return r;
 218
 219         ib = &job->ibs[0];
 220         dummy = ib->gpu_addr + 1024;
 221
 222         ib->length_dw = 0;
 223         ib->ptr[ib->length_dw++] = 0x00000018;
 224         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 225         ib->ptr[ib->length_dw++] = handle;
 226         ib->ptr[ib->length_dw++] = 0x00010000;
 227         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 228         ib->ptr[ib->length_dw++] = dummy;
 229
 230         ib->ptr[ib->length_dw++] = 0x00000014;
 231         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 232         ib->ptr[ib->length_dw++] = 0x0000001c;
 233         ib->ptr[ib->length_dw++] = 0x00000001;
 234         ib->ptr[ib->length_dw++] = 0x00000000;
 235
 236         ib->ptr[ib->length_dw++] = 0x00000008;
 237         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
 238
 239         for (i = ib->length_dw; i < ib_size_dw; ++i)
 240                 ib->ptr[i] = 0x0;
 241
 242         r = amdgpu_job_submit_direct(job, ring, &f);
 243         if (r)
 244                 goto err;
 245
 246         if (fence)
 247                 *fence = dma_fence_get(f);
 248         dma_fence_put(f);
 249         return 0;
 250
 251 err:
 252         amdgpu_job_free(job);
 253         return r;
 254 }
 255
 256 /**
 257  * uvd_v6_0_enc_get_destroy_msg - generate a UVD ENC destroy msg
 258  *
 259  * @adev: amdgpu_device pointer
 260  * @ring: ring we should submit the msg to
 261  * @handle: session handle to use
 262  * @fence: optional fence to return
 263  *
 264  * Close up a stream for HW test or if userspace failed to do so
 265  */
 266 static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring,
 267                                         uint32_t handle,
 268                                         struct dma_fence **fence)
 269 {
 270         const unsigned ib_size_dw = 16;
 271         struct amdgpu_job *job;
 272         struct amdgpu_ib *ib;
 273         struct dma_fence *f = NULL;
 274         uint64_t dummy;
 275         int i, r;
 276
 277         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 278         if (r)
 279                 return r;
 280
 281         ib = &job->ibs[0];
 282         dummy = ib->gpu_addr + 1024;
 283
 284         ib->length_dw = 0;
 285         ib->ptr[ib->length_dw++] = 0x00000018;
 286         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 287         ib->ptr[ib->length_dw++] = handle;
 288         ib->ptr[ib->length_dw++] = 0x00010000;
 289         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 290         ib->ptr[ib->length_dw++] = dummy;
 291
 292         ib->ptr[ib->length_dw++] = 0x00000014;
 293         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 294         ib->ptr[ib->length_dw++] = 0x0000001c;
 295         ib->ptr[ib->length_dw++] = 0x00000001;
 296         ib->ptr[ib->length_dw++] = 0x00000000;
 297
 298         ib->ptr[ib->length_dw++] = 0x00000008;
 299         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
 300
 301         for (i = ib->length_dw; i < ib_size_dw; ++i)
 302                 ib->ptr[i] = 0x0;
 303
 304         r = amdgpu_job_submit_direct(job, ring, &f);
 305         if (r)
 306                 goto err;
 307
 308         if (fence)
 309                 *fence = dma_fence_get(f);
 310         dma_fence_put(f);
 311         return 0;
 312
 313 err:
 314         amdgpu_job_free(job);
 315         return r;
 316 }
 317
 318 /**
 319  * uvd_v6_0_enc_ring_test_ib - test if UVD ENC IBs are working
 320  *
 321  * @ring: the engine to test on
 322  *
 323  */
 324 static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 325 {
 326         struct dma_fence *fence = NULL;
 327         long r;
 328
 329         r = uvd_v6_0_enc_get_create_msg(ring, 1, NULL);
 330         if (r)
 331                 goto error;
 332
 333         r = uvd_v6_0_enc_get_destroy_msg(ring, 1, &fence);
 334         if (r)
 335                 goto error;
 336
 337         r = dma_fence_wait_timeout(fence, false, timeout);
 338         if (r == 0)
 339                 r = -ETIMEDOUT;
 340         else if (r > 0)
 341                 r = 0;
 342
 343 error:
 344         dma_fence_put(fence);
 345         return r;
 346 }
 347
 348 static int uvd_v6_0_early_init(void *handle)
 349 {
 350         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 351         adev->uvd.num_uvd_inst = 1;
 352
 353         if (!(adev->flags & AMD_IS_APU) &&
 354             (RREG32_SMC(ixCC_HARVEST_FUSES) & CC_HARVEST_FUSES__UVD_DISABLE_MASK))
 355                 return -ENOENT;
 356
 357         uvd_v6_0_set_ring_funcs(adev);
 358
 359         if (uvd_v6_0_enc_support(adev)) {
 360                 adev->uvd.num_enc_rings = 2;
 361                 uvd_v6_0_set_enc_ring_funcs(adev);
 362         }
 363
 364         uvd_v6_0_set_irq_funcs(adev);
 365
 366         return 0;
 367 }
 368
 369 static int uvd_v6_0_sw_init(void *handle)
 370 {
 371         struct amdgpu_ring *ring;
 372         int i, r;
 373         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 374
 375         /* UVD TRAP */
 376         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
 377         if (r)
 378                 return r;
 379
 380         /* UVD ENC TRAP */
 381         if (uvd_v6_0_enc_support(adev)) {
 382                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 383                         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP, &adev->uvd.inst->irq);
 384                         if (r)
 385                                 return r;
 386                 }
 387         }
 388
 389         r = amdgpu_uvd_sw_init(adev);
 390         if (r)
 391                 return r;
 392
 393         if (!uvd_v6_0_enc_support(adev)) {
 394                 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
 395                         adev->uvd.inst->ring_enc[i].funcs = NULL;
 396
 397                 adev->uvd.inst->irq.num_types = 1;
 398                 adev->uvd.num_enc_rings = 0;
 399
 400                 DRM_INFO("UVD ENC is disabled\n");
 401         }
 402
 403         ring = &adev->uvd.inst->ring;
 404         sprintf(ring->name, "uvd");
 405         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);
 406         if (r)
 407                 return r;
 408
 409         r = amdgpu_uvd_resume(adev);
 410         if (r)
 411                 return r;
 412
 413         if (uvd_v6_0_enc_support(adev)) {
 414                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 415                         ring = &adev->uvd.inst->ring_enc[i];
 416                         sprintf(ring->name, "uvd_enc%d", i);
 417                         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);
 418                         if (r)
 419                                 return r;
 420                 }
 421         }
 422
 423         r = amdgpu_uvd_entity_init(adev);
 424
 425         return r;
 426 }
 427
 428 static int uvd_v6_0_sw_fini(void *handle)
 429 {
 430         int i, r;
 431         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 432
 433         r = amdgpu_uvd_suspend(adev);
 434         if (r)
 435                 return r;
 436
 437         if (uvd_v6_0_enc_support(adev)) {
 438                 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
 439                         amdgpu_ring_fini(&adev->uvd.inst->ring_enc[i]);
 440         }
 441
 442         return amdgpu_uvd_sw_fini(adev);
 443 }
 444
 445 /**
 446  * uvd_v6_0_hw_init - start and test UVD block
 447  *
 448  * @adev: amdgpu_device pointer
 449  *
 450  * Initialize the hardware, boot up the VCPU and do some testing
 451  */
 452 static int uvd_v6_0_hw_init(void *handle)
 453 {
 454         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 455         struct amdgpu_ring *ring = &adev->uvd.inst->ring;
 456         uint32_t tmp;
 457         int i, r;
 458
 459         amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
 460         uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
 461         uvd_v6_0_enable_mgcg(adev, true);
 462
 463         r = amdgpu_ring_test_helper(ring);
 464         if (r)
 465                 goto done;
 466
 467         r = amdgpu_ring_alloc(ring, 10);
 468         if (r) {
 469                 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
 470                 goto done;
 471         }
 472
 473         tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
 474         amdgpu_ring_write(ring, tmp);
 475         amdgpu_ring_write(ring, 0xFFFFF);
 476
 477         tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
 478         amdgpu_ring_write(ring, tmp);
 479         amdgpu_ring_write(ring, 0xFFFFF);
 480
 481         tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
 482         amdgpu_ring_write(ring, tmp);
 483         amdgpu_ring_write(ring, 0xFFFFF);
 484
 485         /* Clear timeout status bits */
 486         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
 487         amdgpu_ring_write(ring, 0x8);
 488
 489         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
 490         amdgpu_ring_write(ring, 3);
 491
 492         amdgpu_ring_commit(ring);
 493
 494         if (uvd_v6_0_enc_support(adev)) {
 495                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 496                         ring = &adev->uvd.inst->ring_enc[i];
 497                         r = amdgpu_ring_test_helper(ring);
 498                         if (r)
 499                                 goto done;
 500                 }
 501         }
 502
 503 done:
 504         if (!r) {
 505                 if (uvd_v6_0_enc_support(adev))
 506                         DRM_INFO("UVD and UVD ENC initialized successfully.\n");
 507                 else
 508                         DRM_INFO("UVD initialized successfully.\n");
 509         }
 510
 511         return r;
 512 }
 513
 514 /**
 515  * uvd_v6_0_hw_fini - stop the hardware block
 516  *
 517  * @adev: amdgpu_device pointer
 518  *
 519  * Stop the UVD block, mark ring as not ready any more
 520  */
 521 static int uvd_v6_0_hw_fini(void *handle)
 522 {
 523         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 524         struct amdgpu_ring *ring = &adev->uvd.inst->ring;
 525
 526         if (RREG32(mmUVD_STATUS) != 0)
 527                 uvd_v6_0_stop(adev);
 528
 529         ring->sched.ready = false;
 530
 531         return 0;
 532 }
 533
 534 static int uvd_v6_0_suspend(void *handle)
 535 {
 536         int r;
 537         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 538
 539         r = uvd_v6_0_hw_fini(adev);
 540         if (r)
 541                 return r;
 542
 543         return amdgpu_uvd_suspend(adev);
 544 }
 545
 546 static int uvd_v6_0_resume(void *handle)
 547 {
 548         int r;
 549         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 550
 551         r = amdgpu_uvd_resume(adev);
 552         if (r)
 553                 return r;
 554
 555         return uvd_v6_0_hw_init(adev);
 556 }
 557
 558 /**
 559  * uvd_v6_0_mc_resume - memory controller programming
 560  *
 561  * @adev: amdgpu_device pointer
 562  *
 563  * Let the UVD memory controller know it's offsets
 564  */
 565 static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
 566 {
 567         uint64_t offset;
 568         uint32_t size;
 569
 570         /* programm memory controller bits 0-27 */
 571         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 572                         lower_32_bits(adev->uvd.inst->gpu_addr));
 573         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 574                         upper_32_bits(adev->uvd.inst->gpu_addr));
 575
 576         offset = AMDGPU_UVD_FIRMWARE_OFFSET;
 577         size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
 578         WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
 579         WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
 580
 581         offset += size;
 582         size = AMDGPU_UVD_HEAP_SIZE;
 583         WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
 584         WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
 585
 586         offset += size;
 587         size = AMDGPU_UVD_STACK_SIZE +
 588                (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles);
 589         WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
 590         WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
 591
 592         WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 593         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 594         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 595
 596         WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
 597 }
 598
 599 #if 0
 600 static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
 601                 bool enable)
 602 {
 603         u32 data, data1;
 604
 605         data = RREG32(mmUVD_CGC_GATE);
 606         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 607         if (enable) {
 608                 data |= UVD_CGC_GATE__SYS_MASK |
 609                                 UVD_CGC_GATE__UDEC_MASK |
 610                                 UVD_CGC_GATE__MPEG2_MASK |
 611                                 UVD_CGC_GATE__RBC_MASK |
 612                                 UVD_CGC_GATE__LMI_MC_MASK |
 613                                 UVD_CGC_GATE__IDCT_MASK |
 614                                 UVD_CGC_GATE__MPRD_MASK |
 615                                 UVD_CGC_GATE__MPC_MASK |
 616                                 UVD_CGC_GATE__LBSI_MASK |
 617                                 UVD_CGC_GATE__LRBBM_MASK |
 618                                 UVD_CGC_GATE__UDEC_RE_MASK |
 619                                 UVD_CGC_GATE__UDEC_CM_MASK |
 620                                 UVD_CGC_GATE__UDEC_IT_MASK |
 621                                 UVD_CGC_GATE__UDEC_DB_MASK |
 622                                 UVD_CGC_GATE__UDEC_MP_MASK |
 623                                 UVD_CGC_GATE__WCB_MASK |
 624                                 UVD_CGC_GATE__VCPU_MASK |
 625                                 UVD_CGC_GATE__SCPU_MASK;
 626                 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
 627                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 628                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 629                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 630                                 UVD_SUVD_CGC_GATE__SDB_MASK |
 631                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
 632                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
 633                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
 634                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
 635                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
 636                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
 637                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
 638                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
 639         } else {
 640                 data &= ~(UVD_CGC_GATE__SYS_MASK |
 641                                 UVD_CGC_GATE__UDEC_MASK |
 642                                 UVD_CGC_GATE__MPEG2_MASK |
 643                                 UVD_CGC_GATE__RBC_MASK |
 644                                 UVD_CGC_GATE__LMI_MC_MASK |
 645                                 UVD_CGC_GATE__LMI_UMC_MASK |
 646                                 UVD_CGC_GATE__IDCT_MASK |
 647                                 UVD_CGC_GATE__MPRD_MASK |
 648                                 UVD_CGC_GATE__MPC_MASK |
 649                                 UVD_CGC_GATE__LBSI_MASK |
 650                                 UVD_CGC_GATE__LRBBM_MASK |
 651                                 UVD_CGC_GATE__UDEC_RE_MASK |
 652                                 UVD_CGC_GATE__UDEC_CM_MASK |
 653                                 UVD_CGC_GATE__UDEC_IT_MASK |
 654                                 UVD_CGC_GATE__UDEC_DB_MASK |
 655                                 UVD_CGC_GATE__UDEC_MP_MASK |
 656                                 UVD_CGC_GATE__WCB_MASK |
 657                                 UVD_CGC_GATE__VCPU_MASK |
 658                                 UVD_CGC_GATE__SCPU_MASK);
 659                 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK |
 660                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 661                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 662                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 663                                 UVD_SUVD_CGC_GATE__SDB_MASK |
 664                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
 665                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
 666                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
 667                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
 668                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
 669                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
 670                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
 671                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK);
 672         }
 673         WREG32(mmUVD_CGC_GATE, data);
 674         WREG32(mmUVD_SUVD_CGC_GATE, data1);
 675 }
 676 #endif
 677
 678 /**
 679  * uvd_v6_0_start - start UVD block
 680  *
 681  * @adev: amdgpu_device pointer
 682  *
 683  * Setup and start the UVD block
 684  */
 685 static int uvd_v6_0_start(struct amdgpu_device *adev)
 686 {
 687         struct amdgpu_ring *ring = &adev->uvd.inst->ring;
 688         uint32_t rb_bufsz, tmp;
 689         uint32_t lmi_swap_cntl;
 690         uint32_t mp_swap_cntl;
 691         int i, j, r;
 692
 693         /* disable DPG */
 694         WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
 695
 696         /* disable byte swapping */
 697         lmi_swap_cntl = 0;
 698         mp_swap_cntl = 0;
 699
 700         uvd_v6_0_mc_resume(adev);
 701
 702         /* disable interupt */
 703         WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0);
 704
 705         /* stall UMC and register bus before resetting VCPU */
 706         WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 1);
 707         mdelay(1);
 708
 709         /* put LMI, VCPU, RBC etc... into reset */
 710         WREG32(mmUVD_SOFT_RESET,
 711                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 712                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 713                 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 714                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 715                 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 716                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 717                 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 718                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 719         mdelay(5);
 720
 721         /* take UVD block out of reset */
 722         WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_UVD, 0);
 723         mdelay(5);
 724
 725         /* initialize UVD memory controller */
 726         WREG32(mmUVD_LMI_CTRL,
 727                 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 728                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 729                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 730                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 731                 UVD_LMI_CTRL__REQ_MODE_MASK |
 732                 UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK);
 733
 734 #ifdef __BIG_ENDIAN
 735         /* swap (8 in 32) RB and IB */
 736         lmi_swap_cntl = 0xa;
 737         mp_swap_cntl = 0;
 738 #endif
 739         WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 740         WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 741
 742         WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
 743         WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
 744         WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
 745         WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
 746         WREG32(mmUVD_MPC_SET_ALU, 0);
 747         WREG32(mmUVD_MPC_SET_MUX, 0x88);
 748
 749         /* take all subblocks out of reset, except VCPU */
 750         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 751         mdelay(5);
 752
 753         /* enable VCPU clock */
 754         WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
 755
 756         /* enable UMC */
 757         WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 0);
 758
 759         /* boot up the VCPU */
 760         WREG32(mmUVD_SOFT_RESET, 0);
 761         mdelay(10);
 762
 763         for (i = 0; i < 10; ++i) {
 764                 uint32_t status;
 765
 766                 for (j = 0; j < 100; ++j) {
 767                         status = RREG32(mmUVD_STATUS);
 768                         if (status & 2)
 769                                 break;
 770                         mdelay(10);
 771                 }
 772                 r = 0;
 773                 if (status & 2)
 774                         break;
 775
 776                 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
 777                 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 1);
 778                 mdelay(10);
 779                 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 0);
 780                 mdelay(10);
 781                 r = -1;
 782         }
 783
 784         if (r) {
 785                 DRM_ERROR("UVD not responding, giving up!!!\n");
 786                 return r;
 787         }
 788         /* enable master interrupt */
 789         WREG32_P(mmUVD_MASTINT_EN,
 790                 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
 791                 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
 792
 793         /* clear the bit 4 of UVD_STATUS */
 794         WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
 795
 796         /* force RBC into idle state */
 797         rb_bufsz = order_base_2(ring->ring_size);
 798         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 799         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 800         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 801         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
 802         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 803         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 804         WREG32(mmUVD_RBC_RB_CNTL, tmp);
 805
 806         /* set the write pointer delay */
 807         WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
 808
 809         /* set the wb address */
 810         WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
 811
 812         /* programm the RB_BASE for ring buffer */
 813         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 814                         lower_32_bits(ring->gpu_addr));
 815         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 816                         upper_32_bits(ring->gpu_addr));
 817
 818         /* Initialize the ring buffer's read and write pointers */
 819         WREG32(mmUVD_RBC_RB_RPTR, 0);
 820
 821         ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
 822         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 823
 824         WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);
 825
 826         if (uvd_v6_0_enc_support(adev)) {
 827                 ring = &adev->uvd.inst->ring_enc[0];
 828                 WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
 829                 WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
 830                 WREG32(mmUVD_RB_BASE_LO, ring->gpu_addr);
 831                 WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
 832                 WREG32(mmUVD_RB_SIZE, ring->ring_size / 4);
 833
 834                 ring = &adev->uvd.inst->ring_enc[1];
 835                 WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
 836                 WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
 837                 WREG32(mmUVD_RB_BASE_LO2, ring->gpu_addr);
 838                 WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
 839                 WREG32(mmUVD_RB_SIZE2, ring->ring_size / 4);
 840         }
 841
 842         return 0;
 843 }
 844
 845 /**
 846  * uvd_v6_0_stop - stop UVD block
 847  *
 848  * @adev: amdgpu_device pointer
 849  *
 850  * stop the UVD block
 851  */
 852 static void uvd_v6_0_stop(struct amdgpu_device *adev)
 853 {
 854         /* force RBC into idle state */
 855         WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
 856
 857         /* Stall UMC and register bus before resetting VCPU */
 858         WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
 859         mdelay(1);
 860
 861         /* put VCPU into reset */
 862         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 863         mdelay(5);
 864
 865         /* disable VCPU clock */
 866         WREG32(mmUVD_VCPU_CNTL, 0x0);
 867
 868         /* Unstall UMC and register bus */
 869         WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
 870
 871         WREG32(mmUVD_STATUS, 0);
 872 }
 873
 874 /**
 875  * uvd_v6_0_ring_emit_fence - emit an fence & trap command
 876  *
 877  * @ring: amdgpu_ring pointer
 878  * @fence: fence to emit
 879  *
 880  * Write a fence and a trap command to the ring.
 881  */
 882 static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 883                                      unsigned flags)
 884 {
 885         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 886
 887         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 888         amdgpu_ring_write(ring, seq);
 889         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 890         amdgpu_ring_write(ring, addr & 0xffffffff);
 891         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 892         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
 893         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 894         amdgpu_ring_write(ring, 0);
 895
 896         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 897         amdgpu_ring_write(ring, 0);
 898         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 899         amdgpu_ring_write(ring, 0);
 900         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 901         amdgpu_ring_write(ring, 2);
 902 }
 903
 904 /**
 905  * uvd_v6_0_enc_ring_emit_fence - emit an enc fence & trap command
 906  *
 907  * @ring: amdgpu_ring pointer
 908  * @fence: fence to emit
 909  *
 910  * Write enc a fence and a trap command to the ring.
 911  */
 912 static void uvd_v6_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
 913                         u64 seq, unsigned flags)
 914 {
 915         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 916
 917         amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
 918         amdgpu_ring_write(ring, addr);
 919         amdgpu_ring_write(ring, upper_32_bits(addr));
 920         amdgpu_ring_write(ring, seq);
 921         amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
 922 }
 923
 924 /**
 925  * uvd_v6_0_ring_emit_hdp_flush - skip HDP flushing
 926  *
 927  * @ring: amdgpu_ring pointer
 928  */
 929 static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 930 {
 931         /* The firmware doesn't seem to like touching registers at this point. */
 932 }
 933
 934 /**
 935  * uvd_v6_0_ring_test_ring - register write test
 936  *
 937  * @ring: amdgpu_ring pointer
 938  *
 939  * Test if we can successfully write to the context register
 940  */
 941 static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring)
 942 {
 943         struct amdgpu_device *adev = ring->adev;
 944         uint32_t tmp = 0;
 945         unsigned i;
 946         int r;
 947
 948         WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
 949         r = amdgpu_ring_alloc(ring, 3);
 950         if (r)
 951                 return r;
 952
 953         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 954         amdgpu_ring_write(ring, 0xDEADBEEF);
 955         amdgpu_ring_commit(ring);
 956         for (i = 0; i < adev->usec_timeout; i++) {
 957                 tmp = RREG32(mmUVD_CONTEXT_ID);
 958                 if (tmp == 0xDEADBEEF)
 959                         break;
 960                 DRM_UDELAY(1);
 961         }
 962
 963         if (i >= adev->usec_timeout)
 964                 r = -ETIMEDOUT;
 965
 966         return r;
 967 }
 968
 969 /**
 970  * uvd_v6_0_ring_emit_ib - execute indirect buffer
 971  *
 972  * @ring: amdgpu_ring pointer
 973  * @ib: indirect buffer to execute
 974  *
 975  * Write ring commands to execute the indirect buffer
 976  */
 977 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
 978                                   struct amdgpu_job *job,
 979                                   struct amdgpu_ib *ib,
 980                                   uint32_t flags)
 981 {
 982         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 983
 984         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0));
 985         amdgpu_ring_write(ring, vmid);
 986
 987         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
 988         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
 989         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
 990         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 991         amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
 992         amdgpu_ring_write(ring, ib->length_dw);
 993 }
 994
 995 /**
 996  * uvd_v6_0_enc_ring_emit_ib - enc execute indirect buffer
 997  *
 998  * @ring: amdgpu_ring pointer
 999  * @ib: indirect buffer to execute
1000  *
1001  * Write enc ring commands to execute the indirect buffer
1002  */
1003 static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1004                                         struct amdgpu_job *job,
1005                                         struct amdgpu_ib *ib,
1006                                         uint32_t flags)
1007 {
1008         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1009
1010         amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
1011         amdgpu_ring_write(ring, vmid);
1012         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1013         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1014         amdgpu_ring_write(ring, ib->length_dw);
1015 }
1016
1017 static void uvd_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
1018                                     uint32_t reg, uint32_t val)
1019 {
1020         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1021         amdgpu_ring_write(ring, reg << 2);
1022         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1023         amdgpu_ring_write(ring, val);
1024         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1025         amdgpu_ring_write(ring, 0x8);
1026 }
1027
1028 static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1029                                         unsigned vmid, uint64_t pd_addr)
1030 {
1031         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1032
1033         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1034         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1035         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1036         amdgpu_ring_write(ring, 0);
1037         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
1038         amdgpu_ring_write(ring, 1 << vmid); /* mask */
1039         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1040         amdgpu_ring_write(ring, 0xC);
1041 }
1042
1043 static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1044 {
1045         uint32_t seq = ring->fence_drv.sync_seq;
1046         uint64_t addr = ring->fence_drv.gpu_addr;
1047
1048         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1049         amdgpu_ring_write(ring, lower_32_bits(addr));
1050         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1051         amdgpu_ring_write(ring, upper_32_bits(addr));
1052         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
1053         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1054         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH9, 0));
1055         amdgpu_ring_write(ring, seq);
1056         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1057         amdgpu_ring_write(ring, 0xE);
1058 }
1059
1060 static void uvd_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1061 {
1062         int i;
1063
1064         WARN_ON(ring->wptr % 2 || count % 2);
1065
1066         for (i = 0; i < count / 2; i++) {
1067                 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0));
1068                 amdgpu_ring_write(ring, 0);
1069         }
1070 }
1071
1072 static void uvd_v6_0_enc_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1073 {
1074         uint32_t seq = ring->fence_drv.sync_seq;
1075         uint64_t addr = ring->fence_drv.gpu_addr;
1076
1077         amdgpu_ring_write(ring, HEVC_ENC_CMD_WAIT_GE);
1078         amdgpu_ring_write(ring, lower_32_bits(addr));
1079         amdgpu_ring_write(ring, upper_32_bits(addr));
1080         amdgpu_ring_write(ring, seq);
1081 }
1082
1083 static void uvd_v6_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1084 {
1085         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
1086 }
1087
1088 static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1089                                             unsigned int vmid, uint64_t pd_addr)
1090 {
1091         amdgpu_ring_write(ring, HEVC_ENC_CMD_UPDATE_PTB);
1092         amdgpu_ring_write(ring, vmid);
1093         amdgpu_ring_write(ring, pd_addr >> 12);
1094
1095         amdgpu_ring_write(ring, HEVC_ENC_CMD_FLUSH_TLB);
1096         amdgpu_ring_write(ring, vmid);
1097 }
1098
1099 static bool uvd_v6_0_is_idle(void *handle)
1100 {
1101         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1102
1103         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
1104 }
1105
1106 static int uvd_v6_0_wait_for_idle(void *handle)
1107 {
1108         unsigned i;
1109         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1110
1111         for (i = 0; i < adev->usec_timeout; i++) {
1112                 if (uvd_v6_0_is_idle(handle))
1113                         return 0;
1114         }
1115         return -ETIMEDOUT;
1116 }
1117
1118 #define AMDGPU_UVD_STATUS_BUSY_MASK    0xfd
1119 static bool uvd_v6_0_check_soft_reset(void *handle)
1120 {
1121         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1122         u32 srbm_soft_reset = 0;
1123         u32 tmp = RREG32(mmSRBM_STATUS);
1124
1125         if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
1126             REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
1127             (RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK))
1128                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
1129
1130         if (srbm_soft_reset) {
1131                 adev->uvd.inst->srbm_soft_reset = srbm_soft_reset;
1132                 return true;
1133         } else {
1134                 adev->uvd.inst->srbm_soft_reset = 0;
1135                 return false;
1136         }
1137 }
1138
1139 static int uvd_v6_0_pre_soft_reset(void *handle)
1140 {
1141         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1142
1143         if (!adev->uvd.inst->srbm_soft_reset)
1144                 return 0;
1145
1146         uvd_v6_0_stop(adev);
1147         return 0;
1148 }
1149
1150 static int uvd_v6_0_soft_reset(void *handle)
1151 {
1152         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1153         u32 srbm_soft_reset;
1154
1155         if (!adev->uvd.inst->srbm_soft_reset)
1156                 return 0;
1157         srbm_soft_reset = adev->uvd.inst->srbm_soft_reset;
1158
1159         if (srbm_soft_reset) {
1160                 u32 tmp;
1161
1162                 tmp = RREG32(mmSRBM_SOFT_RESET);
1163                 tmp |= srbm_soft_reset;
1164                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1165                 WREG32(mmSRBM_SOFT_RESET, tmp);
1166                 tmp = RREG32(mmSRBM_SOFT_RESET);
1167
1168                 udelay(50);
1169
1170                 tmp &= ~srbm_soft_reset;
1171                 WREG32(mmSRBM_SOFT_RESET, tmp);
1172                 tmp = RREG32(mmSRBM_SOFT_RESET);
1173
1174                 /* Wait a little for things to settle down */
1175                 udelay(50);
1176         }
1177
1178         return 0;
1179 }
1180
1181 static int uvd_v6_0_post_soft_reset(void *handle)
1182 {
1183         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1184
1185         if (!adev->uvd.inst->srbm_soft_reset)
1186                 return 0;
1187
1188         mdelay(5);
1189
1190         return uvd_v6_0_start(adev);
1191 }
1192
1193 static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev,
1194                                         struct amdgpu_irq_src *source,
1195                                         unsigned type,
1196                                         enum amdgpu_interrupt_state state)
1197 {
1198         // TODO
1199         return 0;
1200 }
1201
1202 static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
1203                                       struct amdgpu_irq_src *source,
1204                                       struct amdgpu_iv_entry *entry)
1205 {
1206         bool int_handled = true;
1207         DRM_DEBUG("IH: UVD TRAP\n");
1208
1209         switch (entry->src_id) {
1210         case 124:
1211                 amdgpu_fence_process(&adev->uvd.inst->ring);
1212                 break;
1213         case 119:
1214                 if (likely(uvd_v6_0_enc_support(adev)))
1215                         amdgpu_fence_process(&adev->uvd.inst->ring_enc[0]);
1216                 else
1217                         int_handled = false;
1218                 break;
1219         case 120:
1220                 if (likely(uvd_v6_0_enc_support(adev)))
1221                         amdgpu_fence_process(&adev->uvd.inst->ring_enc[1]);
1222                 else
1223                         int_handled = false;
1224                 break;
1225         }
1226
1227         if (false == int_handled)
1228                         DRM_ERROR("Unhandled interrupt: %d %d\n",
1229                           entry->src_id, entry->src_data[0]);
1230
1231         return 0;
1232 }
1233
1234 static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
1235 {
1236         uint32_t data1, data3;
1237
1238         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1239         data3 = RREG32(mmUVD_CGC_GATE);
1240
1241         data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
1242                      UVD_SUVD_CGC_GATE__SIT_MASK |
1243                      UVD_SUVD_CGC_GATE__SMP_MASK |
1244                      UVD_SUVD_CGC_GATE__SCM_MASK |
1245                      UVD_SUVD_CGC_GATE__SDB_MASK |
1246                      UVD_SUVD_CGC_GATE__SRE_H264_MASK |
1247                      UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
1248                      UVD_SUVD_CGC_GATE__SIT_H264_MASK |
1249                      UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
1250                      UVD_SUVD_CGC_GATE__SCM_H264_MASK |
1251                      UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
1252                      UVD_SUVD_CGC_GATE__SDB_H264_MASK |
1253                      UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
1254
1255         if (enable) {
1256                 data3 |= (UVD_CGC_GATE__SYS_MASK       |
1257                         UVD_CGC_GATE__UDEC_MASK      |
1258                         UVD_CGC_GATE__MPEG2_MASK     |
1259                         UVD_CGC_GATE__RBC_MASK       |
1260                         UVD_CGC_GATE__LMI_MC_MASK    |
1261                         UVD_CGC_GATE__LMI_UMC_MASK   |
1262                         UVD_CGC_GATE__IDCT_MASK      |
1263                         UVD_CGC_GATE__MPRD_MASK      |
1264                         UVD_CGC_GATE__MPC_MASK       |
1265                         UVD_CGC_GATE__LBSI_MASK      |
1266                         UVD_CGC_GATE__LRBBM_MASK     |
1267                         UVD_CGC_GATE__UDEC_RE_MASK   |
1268                         UVD_CGC_GATE__UDEC_CM_MASK   |
1269                         UVD_CGC_GATE__UDEC_IT_MASK   |
1270                         UVD_CGC_GATE__UDEC_DB_MASK   |
1271                         UVD_CGC_GATE__UDEC_MP_MASK   |
1272                         UVD_CGC_GATE__WCB_MASK       |
1273                         UVD_CGC_GATE__JPEG_MASK      |
1274                         UVD_CGC_GATE__SCPU_MASK      |
1275                         UVD_CGC_GATE__JPEG2_MASK);
1276                 /* only in pg enabled, we can gate clock to vcpu*/
1277                 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
1278                         data3 |= UVD_CGC_GATE__VCPU_MASK;
1279
1280                 data3 &= ~UVD_CGC_GATE__REGS_MASK;
1281         } else {
1282                 data3 = 0;
1283         }
1284
1285         WREG32(mmUVD_SUVD_CGC_GATE, data1);
1286         WREG32(mmUVD_CGC_GATE, data3);
1287 }
1288
1289 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev)
1290 {
1291         uint32_t data, data2;
1292
1293         data = RREG32(mmUVD_CGC_CTRL);
1294         data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
1295
1296
1297         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
1298                   UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
1299
1300
1301         data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
1302                 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1303                 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
1304
1305         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
1306                         UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
1307                         UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
1308                         UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
1309                         UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
1310                         UVD_CGC_CTRL__SYS_MODE_MASK |
1311                         UVD_CGC_CTRL__UDEC_MODE_MASK |
1312                         UVD_CGC_CTRL__MPEG2_MODE_MASK |
1313                         UVD_CGC_CTRL__REGS_MODE_MASK |
1314                         UVD_CGC_CTRL__RBC_MODE_MASK |
1315                         UVD_CGC_CTRL__LMI_MC_MODE_MASK |
1316                         UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
1317                         UVD_CGC_CTRL__IDCT_MODE_MASK |
1318                         UVD_CGC_CTRL__MPRD_MODE_MASK |
1319                         UVD_CGC_CTRL__MPC_MODE_MASK |
1320                         UVD_CGC_CTRL__LBSI_MODE_MASK |
1321                         UVD_CGC_CTRL__LRBBM_MODE_MASK |
1322                         UVD_CGC_CTRL__WCB_MODE_MASK |
1323                         UVD_CGC_CTRL__VCPU_MODE_MASK |
1324                         UVD_CGC_CTRL__JPEG_MODE_MASK |
1325                         UVD_CGC_CTRL__SCPU_MODE_MASK |
1326                         UVD_CGC_CTRL__JPEG2_MODE_MASK);
1327         data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
1328                         UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
1329                         UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
1330                         UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
1331                         UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
1332
1333         WREG32(mmUVD_CGC_CTRL, data);
1334         WREG32(mmUVD_SUVD_CGC_CTRL, data2);
1335 }
1336
1337 #if 0
1338 static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev)
1339 {
1340         uint32_t data, data1, cgc_flags, suvd_flags;
1341
1342         data = RREG32(mmUVD_CGC_GATE);
1343         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1344
1345         cgc_flags = UVD_CGC_GATE__SYS_MASK |
1346                 UVD_CGC_GATE__UDEC_MASK |
1347                 UVD_CGC_GATE__MPEG2_MASK |
1348                 UVD_CGC_GATE__RBC_MASK |
1349                 UVD_CGC_GATE__LMI_MC_MASK |
1350                 UVD_CGC_GATE__IDCT_MASK |
1351                 UVD_CGC_GATE__MPRD_MASK |
1352                 UVD_CGC_GATE__MPC_MASK |
1353                 UVD_CGC_GATE__LBSI_MASK |
1354                 UVD_CGC_GATE__LRBBM_MASK |
1355                 UVD_CGC_GATE__UDEC_RE_MASK |
1356                 UVD_CGC_GATE__UDEC_CM_MASK |
1357                 UVD_CGC_GATE__UDEC_IT_MASK |
1358                 UVD_CGC_GATE__UDEC_DB_MASK |
1359                 UVD_CGC_GATE__UDEC_MP_MASK |
1360                 UVD_CGC_GATE__WCB_MASK |
1361                 UVD_CGC_GATE__VCPU_MASK |
1362                 UVD_CGC_GATE__SCPU_MASK |
1363                 UVD_CGC_GATE__JPEG_MASK |
1364                 UVD_CGC_GATE__JPEG2_MASK;
1365
1366         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1367                                 UVD_SUVD_CGC_GATE__SIT_MASK |
1368                                 UVD_SUVD_CGC_GATE__SMP_MASK |
1369                                 UVD_SUVD_CGC_GATE__SCM_MASK |
1370                                 UVD_SUVD_CGC_GATE__SDB_MASK;
1371
1372         data |= cgc_flags;
1373         data1 |= suvd_flags;
1374
1375         WREG32(mmUVD_CGC_GATE, data);
1376         WREG32(mmUVD_SUVD_CGC_GATE, data1);
1377 }
1378 #endif
1379
1380 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
1381                                  bool enable)
1382 {
1383         u32 orig, data;
1384
1385         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
1386                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
1387                 data |= 0xfff;
1388                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
1389
1390                 orig = data = RREG32(mmUVD_CGC_CTRL);
1391                 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
1392                 if (orig != data)
1393                         WREG32(mmUVD_CGC_CTRL, data);
1394         } else {
1395                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
1396                 data &= ~0xfff;
1397                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
1398
1399                 orig = data = RREG32(mmUVD_CGC_CTRL);
1400                 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
1401                 if (orig != data)
1402                         WREG32(mmUVD_CGC_CTRL, data);
1403         }
1404 }
1405
1406 static int uvd_v6_0_set_clockgating_state(void *handle,
1407                                           enum amd_clockgating_state state)
1408 {
1409         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1410         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1411
1412         if (enable) {
1413                 /* wait for STATUS to clear */
1414                 if (uvd_v6_0_wait_for_idle(handle))
1415                         return -EBUSY;
1416                 uvd_v6_0_enable_clock_gating(adev, true);
1417                 /* enable HW gates because UVD is idle */
1418 /*              uvd_v6_0_set_hw_clock_gating(adev); */
1419         } else {
1420                 /* disable HW gating and enable Sw gating */
1421                 uvd_v6_0_enable_clock_gating(adev, false);
1422         }
1423         uvd_v6_0_set_sw_clock_gating(adev);
1424         return 0;
1425 }
1426
1427 static int uvd_v6_0_set_powergating_state(void *handle,
1428                                           enum amd_powergating_state state)
1429 {
1430         /* This doesn't actually powergate the UVD block.
1431          * That's done in the dpm code via the SMC.  This
1432          * just re-inits the block as necessary.  The actual
1433          * gating still happens in the dpm code.  We should
1434          * revisit this when there is a cleaner line between
1435          * the smc and the hw blocks
1436          */
1437         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1438         int ret = 0;
1439
1440         WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1441
1442         if (state == AMD_PG_STATE_GATE) {
1443                 uvd_v6_0_stop(adev);
1444         } else {
1445                 ret = uvd_v6_0_start(adev);
1446                 if (ret)
1447                         goto out;
1448         }
1449
1450 out:
1451         return ret;
1452 }
1453
1454 static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags)
1455 {
1456         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1457         int data;
1458
1459         mutex_lock(&adev->pm.mutex);
1460
1461         if (adev->flags & AMD_IS_APU)
1462                 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU);
1463         else
1464                 data = RREG32_SMC(ixCURRENT_PG_STATUS);
1465
1466         if (data & CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
1467                 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
1468                 goto out;
1469         }
1470
1471         /* AMD_CG_SUPPORT_UVD_MGCG */
1472         data = RREG32(mmUVD_CGC_CTRL);
1473         if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
1474                 *flags |= AMD_CG_SUPPORT_UVD_MGCG;
1475
1476 out:
1477         mutex_unlock(&adev->pm.mutex);
1478 }
1479
1480 static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
1481         .name = "uvd_v6_0",
1482         .early_init = uvd_v6_0_early_init,
1483         .late_init = NULL,
1484         .sw_init = uvd_v6_0_sw_init,
1485         .sw_fini = uvd_v6_0_sw_fini,
1486         .hw_init = uvd_v6_0_hw_init,
1487         .hw_fini = uvd_v6_0_hw_fini,
1488         .suspend = uvd_v6_0_suspend,
1489         .resume = uvd_v6_0_resume,
1490         .is_idle = uvd_v6_0_is_idle,
1491         .wait_for_idle = uvd_v6_0_wait_for_idle,
1492         .check_soft_reset = uvd_v6_0_check_soft_reset,
1493         .pre_soft_reset = uvd_v6_0_pre_soft_reset,
1494         .soft_reset = uvd_v6_0_soft_reset,
1495         .post_soft_reset = uvd_v6_0_post_soft_reset,
1496         .set_clockgating_state = uvd_v6_0_set_clockgating_state,
1497         .set_powergating_state = uvd_v6_0_set_powergating_state,
1498         .get_clockgating_state = uvd_v6_0_get_clockgating_state,
1499 };
1500
1501 static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
1502         .type = AMDGPU_RING_TYPE_UVD,
1503         .align_mask = 0xf,
1504         .support_64bit_ptrs = false,
1505         .get_rptr = uvd_v6_0_ring_get_rptr,
1506         .get_wptr = uvd_v6_0_ring_get_wptr,
1507         .set_wptr = uvd_v6_0_ring_set_wptr,
1508         .parse_cs = amdgpu_uvd_ring_parse_cs,
1509         .emit_frame_size =
1510                 6 + /* hdp invalidate */
1511                 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
1512                 14, /* uvd_v6_0_ring_emit_fence x1 no user fence */
1513         .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
1514         .emit_ib = uvd_v6_0_ring_emit_ib,
1515         .emit_fence = uvd_v6_0_ring_emit_fence,
1516         .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1517         .test_ring = uvd_v6_0_ring_test_ring,
1518         .test_ib = amdgpu_uvd_ring_test_ib,
1519         .insert_nop = uvd_v6_0_ring_insert_nop,
1520         .pad_ib = amdgpu_ring_generic_pad_ib,
1521         .begin_use = amdgpu_uvd_ring_begin_use,
1522         .end_use = amdgpu_uvd_ring_end_use,
1523         .emit_wreg = uvd_v6_0_ring_emit_wreg,
1524 };
1525
1526 static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
1527         .type = AMDGPU_RING_TYPE_UVD,
1528         .align_mask = 0xf,
1529         .support_64bit_ptrs = false,
1530         .get_rptr = uvd_v6_0_ring_get_rptr,
1531         .get_wptr = uvd_v6_0_ring_get_wptr,
1532         .set_wptr = uvd_v6_0_ring_set_wptr,
1533         .emit_frame_size =
1534                 6 + /* hdp invalidate */
1535                 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
1536                 VI_FLUSH_GPU_TLB_NUM_WREG * 6 + 8 + /* uvd_v6_0_ring_emit_vm_flush */
1537                 14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
1538         .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
1539         .emit_ib = uvd_v6_0_ring_emit_ib,
1540         .emit_fence = uvd_v6_0_ring_emit_fence,
1541         .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
1542         .emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync,
1543         .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1544         .test_ring = uvd_v6_0_ring_test_ring,
1545         .test_ib = amdgpu_uvd_ring_test_ib,
1546         .insert_nop = uvd_v6_0_ring_insert_nop,
1547         .pad_ib = amdgpu_ring_generic_pad_ib,
1548         .begin_use = amdgpu_uvd_ring_begin_use,
1549         .end_use = amdgpu_uvd_ring_end_use,
1550         .emit_wreg = uvd_v6_0_ring_emit_wreg,
1551 };
1552
1553 static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = {
1554         .type = AMDGPU_RING_TYPE_UVD_ENC,
1555         .align_mask = 0x3f,
1556         .nop = HEVC_ENC_CMD_NO_OP,
1557         .support_64bit_ptrs = false,
1558         .get_rptr = uvd_v6_0_enc_ring_get_rptr,
1559         .get_wptr = uvd_v6_0_enc_ring_get_wptr,
1560         .set_wptr = uvd_v6_0_enc_ring_set_wptr,
1561         .emit_frame_size =
1562                 4 + /* uvd_v6_0_enc_ring_emit_pipeline_sync */
1563                 5 + /* uvd_v6_0_enc_ring_emit_vm_flush */
1564                 5 + 5 + /* uvd_v6_0_enc_ring_emit_fence x2 vm fence */
1565                 1, /* uvd_v6_0_enc_ring_insert_end */
1566         .emit_ib_size = 5, /* uvd_v6_0_enc_ring_emit_ib */
1567         .emit_ib = uvd_v6_0_enc_ring_emit_ib,
1568         .emit_fence = uvd_v6_0_enc_ring_emit_fence,
1569         .emit_vm_flush = uvd_v6_0_enc_ring_emit_vm_flush,
1570         .emit_pipeline_sync = uvd_v6_0_enc_ring_emit_pipeline_sync,
1571         .test_ring = uvd_v6_0_enc_ring_test_ring,
1572         .test_ib = uvd_v6_0_enc_ring_test_ib,
1573         .insert_nop = amdgpu_ring_insert_nop,
1574         .insert_end = uvd_v6_0_enc_ring_insert_end,
1575         .pad_ib = amdgpu_ring_generic_pad_ib,
1576         .begin_use = amdgpu_uvd_ring_begin_use,
1577         .end_use = amdgpu_uvd_ring_end_use,
1578 };
1579
1580 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev)
1581 {
1582         if (adev->asic_type >= CHIP_POLARIS10) {
1583                 adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_vm_funcs;
1584                 DRM_INFO("UVD is enabled in VM mode\n");
1585         } else {
1586                 adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_phys_funcs;
1587                 DRM_INFO("UVD is enabled in physical mode\n");
1588         }
1589 }
1590
1591 static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1592 {
1593         int i;
1594
1595         for (i = 0; i < adev->uvd.num_enc_rings; ++i)
1596                 adev->uvd.inst->ring_enc[i].funcs = &uvd_v6_0_enc_ring_vm_funcs;
1597
1598         DRM_INFO("UVD ENC is enabled in VM mode\n");
1599 }
1600
1601 static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
1602         .set = uvd_v6_0_set_interrupt_state,
1603         .process = uvd_v6_0_process_interrupt,
1604 };
1605
1606 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1607 {
1608         if (uvd_v6_0_enc_support(adev))
1609                 adev->uvd.inst->irq.num_types = adev->uvd.num_enc_rings + 1;
1610         else
1611                 adev->uvd.inst->irq.num_types = 1;
1612
1613         adev->uvd.inst->irq.funcs = &uvd_v6_0_irq_funcs;
1614 }
1615
1616 const struct amdgpu_ip_block_version uvd_v6_0_ip_block =
1617 {
1618                 .type = AMD_IP_BLOCK_TYPE_UVD,
1619                 .major = 6,
1620                 .minor = 0,
1621                 .rev = 0,
1622                 .funcs = &uvd_v6_0_ip_funcs,
1623 };
1624
1625 const struct amdgpu_ip_block_version uvd_v6_2_ip_block =
1626 {
1627                 .type = AMD_IP_BLOCK_TYPE_UVD,
1628                 .major = 6,
1629                 .minor = 2,
1630                 .rev = 0,
1631                 .funcs = &uvd_v6_0_ip_funcs,
1632 };
1633
1634 const struct amdgpu_ip_block_version uvd_v6_3_ip_block =
1635 {
1636                 .type = AMD_IP_BLOCK_TYPE_UVD,
1637                 .major = 6,
1638                 .minor = 3,
1639                 .rev = 0,
1640                 .funcs = &uvd_v6_0_ip_funcs,
1641 };