drivers/gpu/drm/amd/amdgpu/soc15.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include "drmP.h"
  27 #include "amdgpu.h"
  28 #include "amdgpu_atomfirmware.h"
  29 #include "amdgpu_ih.h"
  30 #include "amdgpu_uvd.h"
  31 #include "amdgpu_vce.h"
  32 #include "amdgpu_ucode.h"
  33 #include "amdgpu_psp.h"
  34 #include "atom.h"
  35 #include "amd_pcie.h"
  36
  37 #include "vega10/soc15ip.h"
  38 #include "vega10/UVD/uvd_7_0_offset.h"
  39 #include "vega10/GC/gc_9_0_offset.h"
  40 #include "vega10/GC/gc_9_0_sh_mask.h"
  41 #include "vega10/SDMA0/sdma0_4_0_offset.h"
  42 #include "vega10/SDMA1/sdma1_4_0_offset.h"
  43 #include "vega10/HDP/hdp_4_0_offset.h"
  44 #include "vega10/HDP/hdp_4_0_sh_mask.h"
  45 #include "vega10/MP/mp_9_0_offset.h"
  46 #include "vega10/MP/mp_9_0_sh_mask.h"
  47 #include "vega10/SMUIO/smuio_9_0_offset.h"
  48 #include "vega10/SMUIO/smuio_9_0_sh_mask.h"
  49
  50 #include "soc15.h"
  51 #include "soc15_common.h"
  52 #include "gfx_v9_0.h"
  53 #include "gmc_v9_0.h"
  54 #include "gfxhub_v1_0.h"
  55 #include "mmhub_v1_0.h"
  56 #include "vega10_ih.h"
  57 #include "sdma_v4_0.h"
  58 #include "uvd_v7_0.h"
  59 #include "vce_v4_0.h"
  60 #include "amdgpu_powerplay.h"
  61 #include "dce_virtual.h"
  62 #include "mxgpu_ai.h"
  63
  64 MODULE_FIRMWARE("amdgpu/vega10_smc.bin");
  65
  66 #define mmFabricConfigAccessControl                                                                    0x0410
  67 #define mmFabricConfigAccessControl_BASE_IDX                                                           0
  68 #define mmFabricConfigAccessControl_DEFAULT                                      0x00000000
  69 //FabricConfigAccessControl
  70 #define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT                                                     0x0
  71 #define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT                                                0x1
  72 #define FabricConfigAccessControl__CfgRegInstID__SHIFT                                                        0x10
  73 #define FabricConfigAccessControl__CfgRegInstAccEn_MASK                                                       0x00000001L
  74 #define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK                                                  0x00000002L
  75 #define FabricConfigAccessControl__CfgRegInstID_MASK                                                          0x00FF0000L
  76
  77
  78 #define mmDF_PIE_AON0_DfGlobalClkGater                                                                 0x00fc
  79 #define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX                                                        0
  80 //DF_PIE_AON0_DfGlobalClkGater
  81 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT                                                         0x0
  82 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK                                                           0x0000000FL
  83
  84 enum {
  85         DF_MGCG_DISABLE = 0,
  86         DF_MGCG_ENABLE_00_CYCLE_DELAY =1,
  87         DF_MGCG_ENABLE_01_CYCLE_DELAY =2,
  88         DF_MGCG_ENABLE_15_CYCLE_DELAY =13,
  89         DF_MGCG_ENABLE_31_CYCLE_DELAY =14,
  90         DF_MGCG_ENABLE_63_CYCLE_DELAY =15
  91 };
  92
  93 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
  94 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
  95 #define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba
  96 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX                                                    0
  97
  98 /*
  99  * Indirect registers accessor
 100  */
 101 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 102 {
 103         unsigned long flags, address, data;
 104         u32 r;
 105         struct nbio_pcie_index_data *nbio_pcie_id;
 106
 107         if (adev->asic_type == CHIP_VEGA10)
 108                 nbio_pcie_id = &nbio_v6_1_pcie_index_data;
 109         else
 110                 BUG();
 111
 112         address = nbio_pcie_id->index_offset;
 113         data = nbio_pcie_id->data_offset;
 114
 115         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 116         WREG32(address, reg);
 117         (void)RREG32(address);
 118         r = RREG32(data);
 119         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 120         return r;
 121 }
 122
 123 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 124 {
 125         unsigned long flags, address, data;
 126         struct nbio_pcie_index_data *nbio_pcie_id;
 127
 128         if (adev->asic_type == CHIP_VEGA10)
 129                 nbio_pcie_id = &nbio_v6_1_pcie_index_data;
 130         else
 131                 BUG();
 132
 133         address = nbio_pcie_id->index_offset;
 134         data = nbio_pcie_id->data_offset;
 135
 136         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 137         WREG32(address, reg);
 138         (void)RREG32(address);
 139         WREG32(data, v);
 140         (void)RREG32(data);
 141         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 142 }
 143
 144 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 145 {
 146         unsigned long flags, address, data;
 147         u32 r;
 148
 149         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 150         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 151
 152         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 153         WREG32(address, ((reg) & 0x1ff));
 154         r = RREG32(data);
 155         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 156         return r;
 157 }
 158
 159 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 160 {
 161         unsigned long flags, address, data;
 162
 163         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 164         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 165
 166         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 167         WREG32(address, ((reg) & 0x1ff));
 168         WREG32(data, (v));
 169         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 170 }
 171
 172 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
 173 {
 174         unsigned long flags, address, data;
 175         u32 r;
 176
 177         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 178         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 179
 180         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 181         WREG32(address, (reg));
 182         r = RREG32(data);
 183         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 184         return r;
 185 }
 186
 187 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 188 {
 189         unsigned long flags, address, data;
 190
 191         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 192         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 193
 194         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 195         WREG32(address, (reg));
 196         WREG32(data, (v));
 197         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 198 }
 199
 200 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
 201 {
 202         return nbio_v6_1_get_memsize(adev);
 203 }
 204
 205 static const u32 vega10_golden_init[] =
 206 {
 207 };
 208
 209 static void soc15_init_golden_registers(struct amdgpu_device *adev)
 210 {
 211         /* Some of the registers might be dependent on GRBM_GFX_INDEX */
 212         mutex_lock(&adev->grbm_idx_mutex);
 213
 214         switch (adev->asic_type) {
 215         case CHIP_VEGA10:
 216                 amdgpu_program_register_sequence(adev,
 217                                                  vega10_golden_init,
 218                                                  (const u32)ARRAY_SIZE(vega10_golden_init));
 219                 break;
 220         default:
 221                 break;
 222         }
 223         mutex_unlock(&adev->grbm_idx_mutex);
 224 }
 225 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 226 {
 227         if (adev->asic_type == CHIP_VEGA10)
 228                 return adev->clock.spll.reference_freq/4;
 229         else
 230                 return adev->clock.spll.reference_freq;
 231 }
 232
 233
 234 void soc15_grbm_select(struct amdgpu_device *adev,
 235                      u32 me, u32 pipe, u32 queue, u32 vmid)
 236 {
 237         u32 grbm_gfx_cntl = 0;
 238         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 239         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 240         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 241         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 242
 243         WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
 244 }
 245
 246 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
 247 {
 248         /* todo */
 249 }
 250
 251 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
 252 {
 253         /* todo */
 254         return false;
 255 }
 256
 257 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
 258                                      u8 *bios, u32 length_bytes)
 259 {
 260         u32 *dw_ptr;
 261         u32 i, length_dw;
 262
 263         if (bios == NULL)
 264                 return false;
 265         if (length_bytes == 0)
 266                 return false;
 267         /* APU vbios image is part of sbios image */
 268         if (adev->flags & AMD_IS_APU)
 269                 return false;
 270
 271         dw_ptr = (u32 *)bios;
 272         length_dw = ALIGN(length_bytes, 4) / 4;
 273
 274         /* set rom index to 0 */
 275         WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
 276         /* read out the rom data */
 277         for (i = 0; i < length_dw; i++)
 278                 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
 279
 280         return true;
 281 }
 282
 283 static struct amdgpu_allowed_register_entry vega10_allowed_read_registers[] = {
 284         /* todo */
 285 };
 286
 287 static struct amdgpu_allowed_register_entry soc15_allowed_read_registers[] = {
 288         { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS), false},
 289         { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2), false},
 290         { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE0), false},
 291         { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE1), false},
 292         { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE2), false},
 293         { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE3), false},
 294         { SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_STATUS_REG), false},
 295         { SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_STATUS_REG), false},
 296         { SOC15_REG_OFFSET(GC, 0, mmCP_STAT), false},
 297         { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT1), false},
 298         { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT2), false},
 299         { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT3), false},
 300         { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT), false},
 301         { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1), false},
 302         { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS), false},
 303         { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1), false},
 304         { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS), false},
 305         { SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), false},
 306 };
 307
 308 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 309                                          u32 sh_num, u32 reg_offset)
 310 {
 311         uint32_t val;
 312
 313         mutex_lock(&adev->grbm_idx_mutex);
 314         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 315                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 316
 317         val = RREG32(reg_offset);
 318
 319         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 320                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 321         mutex_unlock(&adev->grbm_idx_mutex);
 322         return val;
 323 }
 324
 325 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
 326                                          bool indexed, u32 se_num,
 327                                          u32 sh_num, u32 reg_offset)
 328 {
 329         if (indexed) {
 330                 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
 331         } else {
 332                 switch (reg_offset) {
 333                 case SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG):
 334                         return adev->gfx.config.gb_addr_config;
 335                 default:
 336                         return RREG32(reg_offset);
 337                 }
 338         }
 339 }
 340
 341 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
 342                             u32 sh_num, u32 reg_offset, u32 *value)
 343 {
 344         struct amdgpu_allowed_register_entry *asic_register_table = NULL;
 345         struct amdgpu_allowed_register_entry *asic_register_entry;
 346         uint32_t size, i;
 347
 348         *value = 0;
 349         switch (adev->asic_type) {
 350         case CHIP_VEGA10:
 351                 asic_register_table = vega10_allowed_read_registers;
 352                 size = ARRAY_SIZE(vega10_allowed_read_registers);
 353                 break;
 354         default:
 355                 return -EINVAL;
 356         }
 357
 358         if (asic_register_table) {
 359                 for (i = 0; i < size; i++) {
 360                         asic_register_entry = asic_register_table + i;
 361                         if (reg_offset != asic_register_entry->reg_offset)
 362                                 continue;
 363                         if (!asic_register_entry->untouched)
 364                                 *value = soc15_get_register_value(adev,
 365                                                                   asic_register_entry->grbm_indexed,
 366                                                                   se_num, sh_num, reg_offset);
 367                         return 0;
 368                 }
 369         }
 370
 371         for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
 372                 if (reg_offset != soc15_allowed_read_registers[i].reg_offset)
 373                         continue;
 374
 375                 if (!soc15_allowed_read_registers[i].untouched)
 376                         *value = soc15_get_register_value(adev,
 377                                                           soc15_allowed_read_registers[i].grbm_indexed,
 378                                                           se_num, sh_num, reg_offset);
 379                 return 0;
 380         }
 381         return -EINVAL;
 382 }
 383
 384 static void soc15_gpu_pci_config_reset(struct amdgpu_device *adev)
 385 {
 386         u32 i;
 387
 388         dev_info(adev->dev, "GPU pci config reset\n");
 389
 390         /* disable BM */
 391         pci_clear_master(adev->pdev);
 392         /* reset */
 393         amdgpu_pci_config_reset(adev);
 394
 395         udelay(100);
 396
 397         /* wait for asic to come out of reset */
 398         for (i = 0; i < adev->usec_timeout; i++) {
 399                 if (nbio_v6_1_get_memsize(adev) != 0xffffffff)
 400                         break;
 401                 udelay(1);
 402         }
 403
 404 }
 405
 406 static int soc15_asic_reset(struct amdgpu_device *adev)
 407 {
 408         amdgpu_atomfirmware_scratch_regs_engine_hung(adev, true);
 409
 410         soc15_gpu_pci_config_reset(adev);
 411
 412         amdgpu_atomfirmware_scratch_regs_engine_hung(adev, false);
 413
 414         return 0;
 415 }
 416
 417 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 418                         u32 cntl_reg, u32 status_reg)
 419 {
 420         return 0;
 421 }*/
 422
 423 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 424 {
 425         /*int r;
 426
 427         r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
 428         if (r)
 429                 return r;
 430
 431         r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
 432         */
 433         return 0;
 434 }
 435
 436 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 437 {
 438         /* todo */
 439
 440         return 0;
 441 }
 442
 443 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
 444 {
 445         if (pci_is_root_bus(adev->pdev->bus))
 446                 return;
 447
 448         if (amdgpu_pcie_gen2 == 0)
 449                 return;
 450
 451         if (adev->flags & AMD_IS_APU)
 452                 return;
 453
 454         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 455                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 456                 return;
 457
 458         /* todo */
 459 }
 460
 461 static void soc15_program_aspm(struct amdgpu_device *adev)
 462 {
 463
 464         if (amdgpu_aspm == 0)
 465                 return;
 466
 467         /* todo */
 468 }
 469
 470 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
 471                                         bool enable)
 472 {
 473         nbio_v6_1_enable_doorbell_aperture(adev, enable);
 474         nbio_v6_1_enable_doorbell_selfring_aperture(adev, enable);
 475 }
 476
 477 static const struct amdgpu_ip_block_version vega10_common_ip_block =
 478 {
 479         .type = AMD_IP_BLOCK_TYPE_COMMON,
 480         .major = 2,
 481         .minor = 0,
 482         .rev = 0,
 483         .funcs = &soc15_common_ip_funcs,
 484 };
 485
 486 int soc15_set_ip_blocks(struct amdgpu_device *adev)
 487 {
 488         nbio_v6_1_detect_hw_virt(adev);
 489
 490         if (amdgpu_sriov_vf(adev))
 491                 adev->virt.ops = &xgpu_ai_virt_ops;
 492
 493         switch (adev->asic_type) {
 494         case CHIP_VEGA10:
 495                 amdgpu_ip_block_add(adev, &vega10_common_ip_block);
 496                 amdgpu_ip_block_add(adev, &gfxhub_v1_0_ip_block);
 497                 amdgpu_ip_block_add(adev, &mmhub_v1_0_ip_block);
 498                 amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block);
 499                 amdgpu_ip_block_add(adev, &vega10_ih_ip_block);
 500                 if (amdgpu_fw_load_type == 2 || amdgpu_fw_load_type == -1)
 501                         amdgpu_ip_block_add(adev, &psp_v3_1_ip_block);
 502                 if (!amdgpu_sriov_vf(adev))
 503                         amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
 504                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 505                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
 506                 amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block);
 507                 amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block);
 508                 amdgpu_ip_block_add(adev, &uvd_v7_0_ip_block);
 509                 amdgpu_ip_block_add(adev, &vce_v4_0_ip_block);
 510                 break;
 511         default:
 512                 return -EINVAL;
 513         }
 514
 515         return 0;
 516 }
 517
 518 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
 519 {
 520         return nbio_v6_1_get_rev_id(adev);
 521 }
 522
 523
 524 int gmc_v9_0_mc_wait_for_idle(struct amdgpu_device *adev)
 525 {
 526         /* to be implemented in MC IP*/
 527         return 0;
 528 }
 529
 530 static const struct amdgpu_asic_funcs soc15_asic_funcs =
 531 {
 532         .read_disabled_bios = &soc15_read_disabled_bios,
 533         .read_bios_from_rom = &soc15_read_bios_from_rom,
 534         .read_register = &soc15_read_register,
 535         .reset = &soc15_asic_reset,
 536         .set_vga_state = &soc15_vga_set_state,
 537         .get_xclk = &soc15_get_xclk,
 538         .set_uvd_clocks = &soc15_set_uvd_clocks,
 539         .set_vce_clocks = &soc15_set_vce_clocks,
 540         .get_config_memsize = &soc15_get_config_memsize,
 541 };
 542
 543 static int soc15_common_early_init(void *handle)
 544 {
 545         bool psp_enabled = false;
 546         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 547
 548         adev->smc_rreg = NULL;
 549         adev->smc_wreg = NULL;
 550         adev->pcie_rreg = &soc15_pcie_rreg;
 551         adev->pcie_wreg = &soc15_pcie_wreg;
 552         adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
 553         adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
 554         adev->didt_rreg = &soc15_didt_rreg;
 555         adev->didt_wreg = &soc15_didt_wreg;
 556
 557         adev->asic_funcs = &soc15_asic_funcs;
 558
 559         if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) &&
 560                 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP)))
 561                 psp_enabled = true;
 562
 563         if (amdgpu_sriov_vf(adev)) {
 564                 amdgpu_virt_init_setting(adev);
 565                 xgpu_ai_mailbox_set_irq_funcs(adev);
 566         }
 567
 568         /*
 569          * nbio need be used for both sdma and gfx9, but only
 570          * initializes once
 571          */
 572         switch(adev->asic_type) {
 573         case CHIP_VEGA10:
 574                 nbio_v6_1_init(adev);
 575                 break;
 576         default:
 577                 return -EINVAL;
 578         }
 579
 580         adev->rev_id = soc15_get_rev_id(adev);
 581         adev->external_rev_id = 0xFF;
 582         switch (adev->asic_type) {
 583         case CHIP_VEGA10:
 584                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 585                         AMD_CG_SUPPORT_GFX_MGLS |
 586                         AMD_CG_SUPPORT_GFX_RLC_LS |
 587                         AMD_CG_SUPPORT_GFX_CP_LS |
 588                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 589                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 590                         AMD_CG_SUPPORT_GFX_CGCG |
 591                         AMD_CG_SUPPORT_GFX_CGLS |
 592                         AMD_CG_SUPPORT_BIF_MGCG |
 593                         AMD_CG_SUPPORT_BIF_LS |
 594                         AMD_CG_SUPPORT_HDP_LS |
 595                         AMD_CG_SUPPORT_DRM_MGCG |
 596                         AMD_CG_SUPPORT_DRM_LS |
 597                         AMD_CG_SUPPORT_ROM_MGCG |
 598                         AMD_CG_SUPPORT_DF_MGCG |
 599                         AMD_CG_SUPPORT_SDMA_MGCG |
 600                         AMD_CG_SUPPORT_SDMA_LS |
 601                         AMD_CG_SUPPORT_MC_MGCG |
 602                         AMD_CG_SUPPORT_MC_LS;
 603                 adev->pg_flags = 0;
 604                 adev->external_rev_id = 0x1;
 605                 break;
 606         default:
 607                 /* FIXME: not supported yet */
 608                 return -EINVAL;
 609         }
 610
 611         adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
 612
 613         amdgpu_get_pcie_info(adev);
 614
 615         return 0;
 616 }
 617
 618 static int soc15_common_late_init(void *handle)
 619 {
 620         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 621
 622         if (amdgpu_sriov_vf(adev))
 623                 xgpu_ai_mailbox_get_irq(adev);
 624
 625         return 0;
 626 }
 627
 628 static int soc15_common_sw_init(void *handle)
 629 {
 630         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 631
 632         if (amdgpu_sriov_vf(adev))
 633                 xgpu_ai_mailbox_add_irq_id(adev);
 634
 635         return 0;
 636 }
 637
 638 static int soc15_common_sw_fini(void *handle)
 639 {
 640         return 0;
 641 }
 642
 643 static int soc15_common_hw_init(void *handle)
 644 {
 645         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 646
 647         /* move the golden regs per IP block */
 648         soc15_init_golden_registers(adev);
 649         /* enable pcie gen2/3 link */
 650         soc15_pcie_gen3_enable(adev);
 651         /* enable aspm */
 652         soc15_program_aspm(adev);
 653         /* enable the doorbell aperture */
 654         soc15_enable_doorbell_aperture(adev, true);
 655
 656         return 0;
 657 }
 658
 659 static int soc15_common_hw_fini(void *handle)
 660 {
 661         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 662
 663         /* disable the doorbell aperture */
 664         soc15_enable_doorbell_aperture(adev, false);
 665         if (amdgpu_sriov_vf(adev))
 666                 xgpu_ai_mailbox_put_irq(adev);
 667
 668         return 0;
 669 }
 670
 671 static int soc15_common_suspend(void *handle)
 672 {
 673         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 674
 675         return soc15_common_hw_fini(adev);
 676 }
 677
 678 static int soc15_common_resume(void *handle)
 679 {
 680         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 681
 682         return soc15_common_hw_init(adev);
 683 }
 684
 685 static bool soc15_common_is_idle(void *handle)
 686 {
 687         return true;
 688 }
 689
 690 static int soc15_common_wait_for_idle(void *handle)
 691 {
 692         return 0;
 693 }
 694
 695 static int soc15_common_soft_reset(void *handle)
 696 {
 697         return 0;
 698 }
 699
 700 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
 701 {
 702         uint32_t def, data;
 703
 704         def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
 705
 706         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
 707                 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
 708         else
 709                 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
 710
 711         if (def != data)
 712                 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
 713 }
 714
 715 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
 716 {
 717         uint32_t def, data;
 718
 719         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
 720
 721         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
 722                 data &= ~(0x01000000 |
 723                           0x02000000 |
 724                           0x04000000 |
 725                           0x08000000 |
 726                           0x10000000 |
 727                           0x20000000 |
 728                           0x40000000 |
 729                           0x80000000);
 730         else
 731                 data |= (0x01000000 |
 732                          0x02000000 |
 733                          0x04000000 |
 734                          0x08000000 |
 735                          0x10000000 |
 736                          0x20000000 |
 737                          0x40000000 |
 738                          0x80000000);
 739
 740         if (def != data)
 741                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
 742 }
 743
 744 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
 745 {
 746         uint32_t def, data;
 747
 748         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
 749
 750         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
 751                 data |= 1;
 752         else
 753                 data &= ~1;
 754
 755         if (def != data)
 756                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
 757 }
 758
 759 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
 760                                                        bool enable)
 761 {
 762         uint32_t def, data;
 763
 764         def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
 765
 766         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
 767                 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
 768                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
 769         else
 770                 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
 771                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
 772
 773         if (def != data)
 774                 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
 775 }
 776
 777 static void soc15_update_df_medium_grain_clock_gating(struct amdgpu_device *adev,
 778                                                        bool enable)
 779 {
 780         uint32_t data;
 781
 782         /* Put DF on broadcast mode */
 783         data = RREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl));
 784         data &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
 785         WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl), data);
 786
 787         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
 788                 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
 789                 data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
 790                 data |= DF_MGCG_ENABLE_15_CYCLE_DELAY;
 791                 WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
 792         } else {
 793                 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
 794                 data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
 795                 data |= DF_MGCG_DISABLE;
 796                 WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
 797         }
 798
 799         WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl),
 800                mmFabricConfigAccessControl_DEFAULT);
 801 }
 802
 803 static int soc15_common_set_clockgating_state(void *handle,
 804                                             enum amd_clockgating_state state)
 805 {
 806         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 807
 808         if (amdgpu_sriov_vf(adev))
 809                 return 0;
 810
 811         switch (adev->asic_type) {
 812         case CHIP_VEGA10:
 813                 nbio_v6_1_update_medium_grain_clock_gating(adev,
 814                                 state == AMD_CG_STATE_GATE ? true : false);
 815                 nbio_v6_1_update_medium_grain_light_sleep(adev,
 816                                 state == AMD_CG_STATE_GATE ? true : false);
 817                 soc15_update_hdp_light_sleep(adev,
 818                                 state == AMD_CG_STATE_GATE ? true : false);
 819                 soc15_update_drm_clock_gating(adev,
 820                                 state == AMD_CG_STATE_GATE ? true : false);
 821                 soc15_update_drm_light_sleep(adev,
 822                                 state == AMD_CG_STATE_GATE ? true : false);
 823                 soc15_update_rom_medium_grain_clock_gating(adev,
 824                                 state == AMD_CG_STATE_GATE ? true : false);
 825                 soc15_update_df_medium_grain_clock_gating(adev,
 826                                 state == AMD_CG_STATE_GATE ? true : false);
 827                 break;
 828         default:
 829                 break;
 830         }
 831         return 0;
 832 }
 833
 834 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
 835 {
 836         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 837         int data;
 838
 839         if (amdgpu_sriov_vf(adev))
 840                 *flags = 0;
 841
 842         nbio_v6_1_get_clockgating_state(adev, flags);
 843
 844         /* AMD_CG_SUPPORT_HDP_LS */
 845         data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
 846         if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
 847                 *flags |= AMD_CG_SUPPORT_HDP_LS;
 848
 849         /* AMD_CG_SUPPORT_DRM_MGCG */
 850         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
 851         if (!(data & 0x01000000))
 852                 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
 853
 854         /* AMD_CG_SUPPORT_DRM_LS */
 855         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
 856         if (data & 0x1)
 857                 *flags |= AMD_CG_SUPPORT_DRM_LS;
 858
 859         /* AMD_CG_SUPPORT_ROM_MGCG */
 860         data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
 861         if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
 862                 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
 863
 864         /* AMD_CG_SUPPORT_DF_MGCG */
 865         data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
 866         if (data & DF_MGCG_ENABLE_15_CYCLE_DELAY)
 867                 *flags |= AMD_CG_SUPPORT_DF_MGCG;
 868 }
 869
 870 static int soc15_common_set_powergating_state(void *handle,
 871                                             enum amd_powergating_state state)
 872 {
 873         /* todo */
 874         return 0;
 875 }
 876
 877 const struct amd_ip_funcs soc15_common_ip_funcs = {
 878         .name = "soc15_common",
 879         .early_init = soc15_common_early_init,
 880         .late_init = soc15_common_late_init,
 881         .sw_init = soc15_common_sw_init,
 882         .sw_fini = soc15_common_sw_fini,
 883         .hw_init = soc15_common_hw_init,
 884         .hw_fini = soc15_common_hw_fini,
 885         .suspend = soc15_common_suspend,
 886         .resume = soc15_common_resume,
 887         .is_idle = soc15_common_is_idle,
 888         .wait_for_idle = soc15_common_wait_for_idle,
 889         .soft_reset = soc15_common_soft_reset,
 890         .set_clockgating_state = soc15_common_set_clockgating_state,
 891         .set_powergating_state = soc15_common_set_powergating_state,
 892         .get_clockgating_state= soc15_common_get_clockgating_state,
 893 };