drivers/gpu/drm/amd/amdgpu/si_enums.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef SI_ENUMS_H
  24 #define SI_ENUMS_H
  25
  26 #define VBLANK_INT_MASK                (1 << 0)
  27 #define DC_HPDx_INT_EN                 (1 << 16)
  28 #define VBLANK_ACK                     (1 << 4)
  29 #define VLINE_ACK                      (1 << 4)
  30
  31 #define CURSOR_WIDTH 64
  32 #define CURSOR_HEIGHT 64
  33
  34 #define VGA_VSTATUS_CNTL               0xFFFCFFFF
  35 #define PRIORITY_MARK_MASK             0x7fff
  36 #define PRIORITY_OFF                   (1 << 16)
  37 #define PRIORITY_ALWAYS_ON             (1 << 20)
  38 #define INTERLEAVE_EN                  (1 << 0)
  39
  40 #define LATENCY_WATERMARK_MASK(x)      ((x) << 16)
  41 #define DC_LB_MEMORY_CONFIG(x)         ((x) << 20)
  42 #define ICON_DEGAMMA_MODE(x)           (((x) & 0x3) << 8)
  43
  44 #define GRPH_ENDIAN_SWAP(x)            (((x) & 0x3) << 0)
  45 #define GRPH_ENDIAN_NONE               0
  46 #define GRPH_ENDIAN_8IN16              1
  47 #define GRPH_ENDIAN_8IN32              2
  48 #define GRPH_ENDIAN_8IN64              3
  49
  50 #define GRPH_DEPTH(x)                  (((x) & 0x3) << 0)
  51 #define GRPH_DEPTH_8BPP                0
  52 #define GRPH_DEPTH_16BPP               1
  53 #define GRPH_DEPTH_32BPP               2
  54
  55 #define GRPH_FORMAT(x)                 (((x) & 0x7) << 8)
  56 #define GRPH_FORMAT_INDEXED            0
  57 #define GRPH_FORMAT_ARGB1555           0
  58 #define GRPH_FORMAT_ARGB565            1
  59 #define GRPH_FORMAT_ARGB4444           2
  60 #define GRPH_FORMAT_AI88               3
  61 #define GRPH_FORMAT_MONO16             4
  62 #define GRPH_FORMAT_BGRA5551           5
  63 #define GRPH_FORMAT_ARGB8888           0
  64 #define GRPH_FORMAT_ARGB2101010        1
  65 #define GRPH_FORMAT_32BPP_DIG          2
  66 #define GRPH_FORMAT_8B_ARGB2101010     3
  67 #define GRPH_FORMAT_BGRA1010102        4
  68 #define GRPH_FORMAT_8B_BGRA1010102     5
  69 #define GRPH_FORMAT_RGB111110          6
  70 #define GRPH_FORMAT_BGR101111          7
  71
  72 #define GRPH_NUM_BANKS(x)              (((x) & 0x3) << 2)
  73 #define GRPH_ARRAY_MODE(x)             (((x) & 0x7) << 20)
  74 #define GRPH_ARRAY_LINEAR_GENERAL      0
  75 #define GRPH_ARRAY_LINEAR_ALIGNED      1
  76 #define GRPH_ARRAY_1D_TILED_THIN1      2
  77 #define GRPH_ARRAY_2D_TILED_THIN1      4
  78 #define GRPH_TILE_SPLIT(x)             (((x) & 0x7) << 13)
  79 #define GRPH_BANK_WIDTH(x)             (((x) & 0x3) << 6)
  80 #define GRPH_BANK_HEIGHT(x)            (((x) & 0x3) << 11)
  81 #define GRPH_MACRO_TILE_ASPECT(x)      (((x) & 0x3) << 18)
  82 #define GRPH_ARRAY_MODE(x)             (((x) & 0x7) << 20)
  83 #define GRPH_PIPE_CONFIG(x)                   (((x) & 0x1f) << 24)
  84
  85 #define CURSOR_EN                      (1 << 0)
  86 #define CURSOR_MODE(x)                 (((x) & 0x3) << 8)
  87 #define CURSOR_MONO                    0
  88 #define CURSOR_24_1                    1
  89 #define CURSOR_24_8_PRE_MULT           2
  90 #define CURSOR_24_8_UNPRE_MULT         3
  91 #define CURSOR_2X_MAGNIFY              (1 << 16)
  92 #define CURSOR_FORCE_MC_ON             (1 << 20)
  93 #define CURSOR_URGENT_CONTROL(x)       (((x) & 0x7) << 24)
  94 #define CURSOR_URGENT_ALWAYS           0
  95 #define CURSOR_URGENT_1_8              1
  96 #define CURSOR_URGENT_1_4              2
  97 #define CURSOR_URGENT_3_8              3
  98 #define CURSOR_URGENT_1_2              4
  99 #define CURSOR_UPDATE_PENDING          (1 << 0)
 100 #define CURSOR_UPDATE_TAKEN            (1 << 1)
 101 #define CURSOR_UPDATE_LOCK             (1 << 16)
 102 #define CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)
 103
 104 #define AMDGPU_NUM_OF_VMIDS                     8
 105 #define SI_CRTC0_REGISTER_OFFSET                0
 106 #define SI_CRTC1_REGISTER_OFFSET                0x300
 107 #define SI_CRTC2_REGISTER_OFFSET                0x2600
 108 #define SI_CRTC3_REGISTER_OFFSET                0x2900
 109 #define SI_CRTC4_REGISTER_OFFSET                0x2c00
 110 #define SI_CRTC5_REGISTER_OFFSET                0x2f00
 111
 112 #define DMA0_REGISTER_OFFSET 0x000
 113 #define DMA1_REGISTER_OFFSET 0x200
 114 #define ES_AND_GS_AUTO       3
 115 #define RADEON_PACKET_TYPE3  3
 116 #define CE_PARTITION_BASE    3
 117 #define BUF_SWAP_32BIT       (2 << 16)
 118
 119 #define GFX_POWER_STATUS                           (1 << 1)
 120 #define GFX_CLOCK_STATUS                           (1 << 2)
 121 #define GFX_LS_STATUS                              (1 << 3)
 122 #define RLC_BUSY_STATUS                            (1 << 0)
 123
 124 #define RLC_PUD(x)                               ((x) << 0)
 125 #define RLC_PUD_MASK                             (0xff << 0)
 126 #define RLC_PDD(x)                               ((x) << 8)
 127 #define RLC_PDD_MASK                             (0xff << 8)
 128 #define RLC_TTPD(x)                              ((x) << 16)
 129 #define RLC_TTPD_MASK                            (0xff << 16)
 130 #define RLC_MSD(x)                               ((x) << 24)
 131 #define RLC_MSD_MASK                             (0xff << 24)
 132 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
 133 #define WRITE_DATA_DST_SEL(x) ((x) << 8)
 134 #define EVENT_TYPE(x) ((x) << 0)
 135 #define EVENT_INDEX(x) ((x) << 8)
 136 #define WAIT_REG_MEM_MEM_SPACE(x)               ((x) << 4)
 137 #define WAIT_REG_MEM_FUNCTION(x)                ((x) << 0)
 138 #define WAIT_REG_MEM_ENGINE(x)                  ((x) << 8)
 139
 140 #define GFX6_NUM_GFX_RINGS     1
 141 #define GFX6_NUM_COMPUTE_RINGS 2
 142 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
 143 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET    0x3D
 144
 145 #define TAHITI_GB_ADDR_CONFIG_GOLDEN        0x12011003
 146 #define VERDE_GB_ADDR_CONFIG_GOLDEN         0x02010002
 147 #define HAINAN_GB_ADDR_CONFIG_GOLDEN        0x02011003
 148
 149 #define PACKET3(op, n)  ((RADEON_PACKET_TYPE3 << 30) |                  \
 150                          (((op) & 0xFF) << 8) |                         \
 151                          ((n) & 0x3FFF) << 16)
 152 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
 153 #define PACKET3_NOP                                     0x10
 154 #define PACKET3_SET_BASE                                0x11
 155 #define         PACKET3_BASE_INDEX(x)                  ((x) << 0)
 156 #define PACKET3_CLEAR_STATE                             0x12
 157 #define PACKET3_INDEX_BUFFER_SIZE                       0x13
 158 #define PACKET3_DISPATCH_DIRECT                         0x15
 159 #define PACKET3_DISPATCH_INDIRECT                       0x16
 160 #define PACKET3_ALLOC_GDS                               0x1B
 161 #define PACKET3_WRITE_GDS_RAM                           0x1C
 162 #define PACKET3_ATOMIC_GDS                              0x1D
 163 #define PACKET3_ATOMIC                                  0x1E
 164 #define PACKET3_OCCLUSION_QUERY                         0x1F
 165 #define PACKET3_SET_PREDICATION                         0x20
 166 #define PACKET3_REG_RMW                                 0x21
 167 #define PACKET3_COND_EXEC                               0x22
 168 #define PACKET3_PRED_EXEC                               0x23
 169 #define PACKET3_DRAW_INDIRECT                           0x24
 170 #define PACKET3_DRAW_INDEX_INDIRECT                     0x25
 171 #define PACKET3_INDEX_BASE                              0x26
 172 #define PACKET3_DRAW_INDEX_2                            0x27
 173 #define PACKET3_CONTEXT_CONTROL                         0x28
 174 #define PACKET3_INDEX_TYPE                              0x2A
 175 #define PACKET3_DRAW_INDIRECT_MULTI                     0x2C
 176 #define PACKET3_DRAW_INDEX_AUTO                         0x2D
 177 #define PACKET3_DRAW_INDEX_IMMD                         0x2E
 178 #define PACKET3_NUM_INSTANCES                           0x2F
 179 #define PACKET3_DRAW_INDEX_MULTI_AUTO                   0x30
 180 #define PACKET3_INDIRECT_BUFFER_CONST                   0x31
 181 #define PACKET3_INDIRECT_BUFFER                         0x3F
 182 #define PACKET3_STRMOUT_BUFFER_UPDATE                   0x34
 183 #define PACKET3_DRAW_INDEX_OFFSET_2                     0x35
 184 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT                0x36
 185 #define PACKET3_WRITE_DATA                              0x37
 186 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI               0x38
 187 #define PACKET3_MEM_SEMAPHORE                           0x39
 188 #define PACKET3_MPEG_INDEX                              0x3A
 189 #define PACKET3_COPY_DW                                 0x3B
 190 #define PACKET3_WAIT_REG_MEM                            0x3C
 191 #define PACKET3_MEM_WRITE                               0x3D
 192 #define PACKET3_COPY_DATA                               0x40
 193 #define PACKET3_CP_DMA                                  0x41
 194 #              define PACKET3_CP_DMA_DST_SEL(x)    ((x) << 20)
 195 #              define PACKET3_CP_DMA_ENGINE(x)     ((x) << 27)
 196 #              define PACKET3_CP_DMA_SRC_SEL(x)    ((x) << 29)
 197 #              define PACKET3_CP_DMA_CP_SYNC       (1 << 31)
 198 #              define PACKET3_CP_DMA_DIS_WC        (1 << 21)
 199 #              define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
 200 #              define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
 201 #              define PACKET3_CP_DMA_CMD_SAS       (1 << 26)
 202 #              define PACKET3_CP_DMA_CMD_DAS       (1 << 27)
 203 #              define PACKET3_CP_DMA_CMD_SAIC      (1 << 28)
 204 #              define PACKET3_CP_DMA_CMD_DAIC      (1 << 29)
 205 #              define PACKET3_CP_DMA_CMD_RAW_WAIT  (1 << 30)
 206 #define PACKET3_PFP_SYNC_ME                             0x42
 207 #define PACKET3_SURFACE_SYNC                            0x43
 208 #              define PACKET3_DEST_BASE_0_ENA      (1 << 0)
 209 #              define PACKET3_DEST_BASE_1_ENA      (1 << 1)
 210 #              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)
 211 #              define PACKET3_CB1_DEST_BASE_ENA    (1 << 7)
 212 #              define PACKET3_CB2_DEST_BASE_ENA    (1 << 8)
 213 #              define PACKET3_CB3_DEST_BASE_ENA    (1 << 9)
 214 #              define PACKET3_CB4_DEST_BASE_ENA    (1 << 10)
 215 #              define PACKET3_CB5_DEST_BASE_ENA    (1 << 11)
 216 #              define PACKET3_CB6_DEST_BASE_ENA    (1 << 12)
 217 #              define PACKET3_CB7_DEST_BASE_ENA    (1 << 13)
 218 #              define PACKET3_DB_DEST_BASE_ENA     (1 << 14)
 219 #              define PACKET3_DEST_BASE_2_ENA      (1 << 19)
 220 #              define PACKET3_DEST_BASE_3_ENA      (1 << 21)
 221 #              define PACKET3_TCL1_ACTION_ENA      (1 << 22)
 222 #              define PACKET3_TC_ACTION_ENA        (1 << 23)
 223 #              define PACKET3_CB_ACTION_ENA        (1 << 25)
 224 #              define PACKET3_DB_ACTION_ENA        (1 << 26)
 225 #              define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
 226 #              define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
 227 #define PACKET3_ME_INITIALIZE                           0x44
 228 #define         PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
 229 #define PACKET3_COND_WRITE                              0x45
 230 #define PACKET3_EVENT_WRITE                             0x46
 231 #define PACKET3_EVENT_WRITE_EOP                         0x47
 232 #define PACKET3_EVENT_WRITE_EOS                         0x48
 233 #define PACKET3_PREAMBLE_CNTL                           0x4A
 234 #              define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE     (2 << 28)
 235 #              define PACKET3_PREAMBLE_END_CLEAR_STATE       (3 << 28)
 236 #define PACKET3_ONE_REG_WRITE                           0x57
 237 #define PACKET3_LOAD_CONFIG_REG                         0x5F
 238 #define PACKET3_LOAD_CONTEXT_REG                        0x60
 239 #define PACKET3_LOAD_SH_REG                             0x61
 240 #define PACKET3_SET_CONFIG_REG                          0x68
 241 #define         PACKET3_SET_CONFIG_REG_START                    0x00002000
 242 #define         PACKET3_SET_CONFIG_REG_END                      0x00002c00
 243 #define PACKET3_SET_CONTEXT_REG                         0x69
 244 #define         PACKET3_SET_CONTEXT_REG_START                   0x000a000
 245 #define         PACKET3_SET_CONTEXT_REG_END                     0x000a400
 246 #define PACKET3_SET_CONTEXT_REG_INDIRECT                0x73
 247 #define PACKET3_SET_RESOURCE_INDIRECT                   0x74
 248 #define PACKET3_SET_SH_REG                              0x76
 249 #define         PACKET3_SET_SH_REG_START                        0x00002c00
 250 #define         PACKET3_SET_SH_REG_END                          0x00003000
 251 #define PACKET3_SET_SH_REG_OFFSET                       0x77
 252 #define PACKET3_ME_WRITE                                0x7A
 253 #define PACKET3_SCRATCH_RAM_WRITE                       0x7D
 254 #define PACKET3_SCRATCH_RAM_READ                        0x7E
 255 #define PACKET3_CE_WRITE                                0x7F
 256 #define PACKET3_LOAD_CONST_RAM                          0x80
 257 #define PACKET3_WRITE_CONST_RAM                         0x81
 258 #define PACKET3_WRITE_CONST_RAM_OFFSET                  0x82
 259 #define PACKET3_DUMP_CONST_RAM                          0x83
 260 #define PACKET3_INCREMENT_CE_COUNTER                    0x84
 261 #define PACKET3_INCREMENT_DE_COUNTER                    0x85
 262 #define PACKET3_WAIT_ON_CE_COUNTER                      0x86
 263 #define PACKET3_WAIT_ON_DE_COUNTER                      0x87
 264 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF                 0x88
 265 #define PACKET3_SET_CE_DE_COUNTERS                      0x89
 266 #define PACKET3_WAIT_ON_AVAIL_BUFFER                    0x8A
 267 #define PACKET3_SWITCH_BUFFER                           0x8B
 268 #define PACKET3_SEM_WAIT_ON_SIGNAL    (0x1 << 12)
 269 #define PACKET3_SEM_SEL_SIGNAL      (0x6 << 29)
 270 #define PACKET3_SEM_SEL_WAIT        (0x7 << 29)
 271
 272 #endif